EZMod3D

EZMod3D is a 3D multi-domain physics simulation

software tool primarily developed to address Integrated Circuits (IC) and Printed Circuit Boards (PCB) design.

Why a new tool?

EZMod3D is the first tool addressing designers concerns for advanced nodes and complex designs (System/ICs) :

Ease of Use

Intuitive GUI: no training needed

Simple tech files: only material properties and layers thickness.

Import / export from / to electronics industry standards GDS2, Gerber, Spice

Accuracy

Field solver: only simple physical data, no complex rules

Can handle a very large number of meshes

Low Cost

License fees << saved costs on a single project

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1. Some concerns are poorly addressed by existing tools.

Substrate parasitic coupling

Existing tool usually require difficult to create tech files and generate hard to use results

EZMod3D requires only materials properties and layers thickness.

EZMod3D generates an equivalent netlist interconnecting declared pins, making it possible to

simulate actual coupling.

Thermal coupling (static and dynamic)

Only few (expensive) tools actually do that.

EZMod3D can display frequency dependent magnitude and phase of temperature variations in a

chip. Here at 1 Hz:

EZMod3D brings an efficient and easy to use solution to these concerns, limiting the number of runs

and drastically cutting costs and delays.

No need to define complicated tech files or coupling rules. Just define materials properties and layers

thickness.

TEMP MAGNITUDE

8°C

0.8°C

0°

-4.5°

1Hz 10Hz 100Hz 1KHz 10KHz 100KHz 1MHz 10MHz 100MHz 1GHz 10GHz

-66dB

-60dB

-54dB

-48dB

-42dB

-36dB

-30dB

-24dB

-18dB

-12dB

-6dB

0dB

6dBV(a1gnd) V(a2gnd) V(dgnd)

TEMP PHASE

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2. Rule based extractors definitely lack accuracy (for advanced nodes or high-performance designs)

3ML MOM cap (active and parasitic)

EZMod3D uses a 3D finite elements analysis that can reach the required accuracy. Thanks to its unique

solving algorithm, it can address relatively large designs. The Record so far was:

683 million nodes, then

2.5 billion nodes, and now …

11 billion nodes

Again, no need to define complicated tech files or coupling rules. Just define materials properties and

layers thickness.

EZMod3D : 493 fF Active / 14.3 fF parasitic.

Calibre : 476 fF Active / 113.7 Ff . parasitic

Difference : -4.8% useful / . + 695 % . parasitic Calibre/EZMod3D

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3. The design flow in use for about 40 years reaches its limits.

Classic Design Flow

It is only at the end of the loop that one can realize there is an issue. Then iterations are required

generating delays and costs.

EZMod3D allows parasitic extraction all along the flow from floor plan to leaf cells and even down to

components or just only routing, minimizing iterations, saving time and money.

No need for LVS correct to perform an extraction. A GDS defining geometry and pins is sufficient.

For instance, a bus equivalent schematic can be extracted and used for driver design...

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4. EZMod3D Limitations

EZMod3D is a stationary solver

that does not take into account propagation

This is also the case for all localized constants extraction tools (R, C, CC, RCC) …

… But EZMod3D has a distributed frequency domain mode to model dynamic behavior.

And EZMod3D can model transmission lines by separating R, C, L and K on a short enough line

segment.

EZMod3D is a true 3D Finite Elements solver that cannot extract an entire SOC

Few tools actually do that, most use random walk and do not achieve the same accuracy.

5. How does EZMod3D compare to other tools ?

Tool Method Size capability Accuracy Speed Cost

Calibre Rule based +++ - +++

Assura Rule based? +++ - +++

Quantus Random walk ++ + +

Ansys Method of moments + ++ -

EZMod3D Finite elements ++ ++ + 2k/year

6. EZMod3D is a multi-domain tool

Thanks to the analogy of diffusion equations in different domains, EZMod3D engine can address the

following domains:

Resistive : Analysis of resistance, parasitic resistance, IR drop

Capacitive : Analysis of capacitance, parasitic capacitance, full capacitive coupling

Thermal : Analysis of self heating, thermal transfer

Magnetic : Analysis of magnetic fields

Chemical : Analysis of chemical species diffusion in a solution

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7. Application examples

Here are just some actual use cases from the huge list of problems tackled by EZMod3D.

These examples mainly come from two fields, PCB design and IC design, but two other

examples from thermal system design and multi-conductor modeling have been added to

show EZMod3D capabilities.

1. PCB use cases: Data were imported through Gerber files

LED lighting board thermal path optimization

LED lighting board overheating analysis and layout optimization

Large digital board IR drop and thermal simulation

2. IC use cases: Data were imported through GDS files

Full 3D parasitic C extraction of a switched cap integrator (XFAB 180 nm)

Thermal feedback in an audio amplifier (XFAB 180 nm)

LDO pass device IR drop (TSMC 28 HPC)

Integral non linearity of a capacitive DAC (XFAB 180 nm)

Substrate coupling in a sensor conditioning IC (XFAB 0.35 um)

Substrate coupling in a sensor conditioning IC (undiclosed)

3. System design cases: Data were created using built in graphic editor

Sizing a Peltier modules stack. Aviation application.

4. Miscellaneous cases: Data were created using built in graphic editor

Multi-conductor cable modeling: 5 + 1 wires, 200 um overall diameter 2 meters long. Medical

application.

THERMAL DOMAIN

THERMAL DOMAIN

RESISTIVE DOMAIN

RESISTIVE & THERMAL DOMAIN

CAPACITIVE DOMAIN

THERMAL DOMAIN

CAPACITIVE DOMAIN

RESISTIVE DOMAIN

THERMAL DOMAIN

RESISTIVE, CAPACITIVE & MAGNETIC DOMAINS

RESISTIVE DOMAIN

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Applications examples

1. PCB use cases: Data were imported through Gerber files

1. LED lighting board thermal path optimization

Context Developing a new LED lighting board optimizing BOM and reliability while meeting tight schedule

constraints

Goal Minimize LEDs and Driver temperature for reliability and keeping cost low. This implies comparing design

options (materials, layout…) but this takes time and comes at a cost.

Strategy Using thermal simulation on each design option instead of building prototypes, saving both NRE costs and

manufacturing delays.

Outcome

Copper design could be optimized and saved 10°C on LEDs temperature with respect to initial design,

more than doubling lamp lifetime and optimizing heat sink cost.

This could be done before the first prototype, reducing both development costs and time to market.

PCB was first time right

View in Altium PCB design tool:

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3D View in EZMod3D after importing Gerber files (0.5 day for creating tech file and 2 hours for processing data)

Components temperature map as simulated by EZMod3D

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2. LED lighting board overheating analysis and layout optimization

Context A customer had developed a large LED lighting board and faced over-heating problems causing driver

thermal shutdown on prototypes.

Goal Reduce Driver temperature to prevent shutdown and improve reliability while keeping BOM cost low and

staying in a very tight schedule since production was delayed

Strategy Using thermal simulation to understand where the thermal path causes significant temperature difference

and address that point

Outcome

Redesigning some copper shapes around the drivers (switching to isolation cut technique)

Adding a plain, unconnected copper plane on the rear side.

This reduced peak temperature by more than 20°C, increasing lamp lifetime by a factor of 4 and fixing

the thermal shutdown issue.

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Final design. Data were imported from Gerber files (0.5 days for creating tech file and 3 hours for processing data)

And here is the simulated temperature map Meshing generated 165 million nodes. Simulation took just 8 hours

EZMod3D clearly shows hot spots. After optimization, the hottest component is a 1206 SMD resistor that can

withstand that temperature. The driver ICs are much cooler than in initial design.

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3. IR drop in a parallel processing board (1V 150 A supply)

Context Development of a large digital board (10 copper layers, 28 x 24 cm2, 28000 vias, 192 ASICs, 3000 passives)

with a very tight schedule.

Goal

Size the PCB stackup for IR drop to maintain ASICs supply voltage within 1V+/- 5% at full steam (150 A)

while staying in the manufacturer’s capabilities.

Define location for connecting the sense feedback to 6 phases buck regulator.

Optimize tradeoff between thermal path and supply path: The more thermal vias are added the lower

the thermal resistance to backside heat sink but the less copper left to supply and ground planes so the

more IR drop.

Strategy Thanks to symmetry, simulate IR drop on half board with 96 ASICs 1 V 150 A. For thermal, analyze only one

“tile”

Outcome

Simulation predicted about 4.5 mV maximum drop with respect to DC-DC converter output on ground

planes, and 6 mV on supply planes, very good values.

Simulation defined where feedback should be connected to the converter to properly balance overall

drop so that half the ASICS are 5 mV above supply and half 5 mV below supply.

Measured values confirmed simulation results and the board appeared fully functional and running at

the expected performances at the first cut, suppressing the need for a second cut.

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Design as imported in EZMod3D through Gerber files (1 week for creating tech file, processing the data, 1 week for simulation)

Meshing generated 2.5 billion nodes.

ZOOM

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IC use cases: Data were imported through GDS files

1. Full 3D parasitic C extraction of a differential switched cap integrator

Context During the design of a differential switched capacitors integrator in a Sigma-Delta modulator, the potential

effect of layout parasitic capacitance was questioned.

Goal Detect offset caused by layout dissymmetry if any and improve layout if required.

Strategy Extract all layout parasitic capacitors and simulate integrator with these additional components to check

performance. Modify design if required.

Outcome

Initial layout looked pretty symmetrical but simulation with extracted parasitic capacitors showed 14

mV offset that impaired integrator operation

Differential integrator schematic was redrawn as two single ended paths with bridges to implement the

differential behavior. Only one path has been implemented and then two instances were used, one

being flipped. This way, the layout went symmetrical by construction.

Extraction and simulation of modified design showed offset dropped to less than 1 mV, probably caused

by EZMod3D accuracy setting that were not set to a very tight value.

This potential layout issue could be highlighted at an early stage and that saved a silicon run, hundreds

of k€ NRE and 4 months of time to market.

Layout view in à gds editor (Glade):

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3D View in EZMod3D (4 hours to create tech file and import data)

Netlist (partial) of same cell as extracted by EZMod3D (C + CC):

* dscr2 20461980 Nodes .SUBCKT EQUIVC0 + vdda + phi1n +phi21n + inp + net96 + vrefp + vrefm + net97 + inm + phi1 + phi21 + gnda + phi20 + phi20n + phi2n + outp + net102 + vcm + net104 + outm + phi21n0 CC010 gnda vdda 7.72E-15 CC163 net96 net102 2.65E-15 CC186 net97 net104 2.58E-15 CC208 phi1 phi21n0 2.45E-15 CC20 phi1n phi21n 2.42E-15 CC140 phi1n phi2n 2.14E-15 CC108 phi1 phi21 2.13E-15 CC1412 phi20n phi2n 1.97E-15 CC128 phi1 phi20 1.97E-15 CC118 phi1 gnda 1.55E-15 CC00 phi1n vdda 1.49E-15 CC174 vrefp vcm 1.45E-15 CC175 vrefm vcm 1.44E-15 CC126 net97 phi20 9.59E-16 CC123 net96 phi20 9.41E-16 CC113 net96 gnda 9.27E-16 …

A total of 210 capacitors have been extracted each net connecting to all the other nets. Signal names as defined in layout have been kept, greatly simplifying identification of parasitic capacitance values.

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2. Thermal Feedback in audio amplifier

Context During first silicon evaluation of a customer designed high end audio power amplifier, Total Harmonic

Distortion (<-130 dB @ 1 kHz) unexpectedly raised to -100 dB @ 20 Hz.

Goal Propose a design modification to fix the issue and validate the fix before running silicon

Strategy Build a thermal model of the chip to validate the coupling mechanism. Understand the effect of disturber,

coupling and victim

Outcome

EZMod3D could extract a thermal coupling model between output stage and a temperature sensitive

section in the design. At “high” frequencies, the coupling path could filter out the temperature changes,

but at low frequencies, temperature changes of sensitive section appeared large enough to cause

distortion.

Simulation of that model showed very strong correlation with measurements.

Once the coupling mechanism understood, a solution could be found (increasing distances between

disturber and sensitive function, reducing temperature sensitivity and putting P and N output

transistors closer to each other)

EZMod3D could validate the fix before launching a second run.

Modified design kept distortion level within specification down to the lowest frequencies without need

for a third run.

Would EZMod3D have been used at the first run, the design would have been first time right saving

months of investigations, hundreds of k€ NRE costs and months of manufacturing.

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Magnitude of temperature variations at 1 Hz (left) and 1 kHz (right) from 0.8 °C (outer shape) to 8°C (inner shape):

One can clearly see that at low frequency, temperature “wave” diffuses further.

Phase of temperature variation at 1 Hz (left) and 1 kHz (right). Ranges are 0 to -4.5° at 1 Hz, -180° to +180° at 1 kHz.

Thick lines at 1 kHz indicate a -180°/+180° phase step: Overall phase takes 4 turns to cover the entire chip.

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3. LDO pass device IR drop (50 mA 28 nm node)

Context Design of a fully integrated LiFi transceiver. Floorplan did constrain pass device form factor and pins

position making it uneasy to optimize

Goal Check proper current distribution over 4000 parallel PMOS devices and overall minimum voltage dropout.

Strategy Extract tentative layout equivalent resistance and check VDS differences throughout the 4000 devices.

Iterate if required

Outcome

EZMod3D predicted equivalent series resistance of 74 milli-ohm and could plot IR drop color maps.

EZMod3D could validate pass device layout long before tape out and not only did it extract parasitic R

equivalent value but also could it display IR drop values showing a good current distribution in the

complex power routing indicating a clever layout

.

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Design as imported in EZMod3D through gds2 file:

10 metal layers, 9 via layers, 6 million polygons. Meshing generated 11 billion nodes…

IR drop color map (here in metal 10):

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4. Integral non linearity of a 10 bits DAC

Context Design of a 10 bits capacitive DAC

Goal

Check effect of layout on integral non linearity

Strategy Run extraction with Calibre and EZMod3D and simulate with extracted parasitics

Outcome

EZMod3D full 3D extraction gives much more realistic simulation results than rule based Calibre

o It predicts the step at mid-range that Calibre does not show.

o It shows a much more significant dissymmetry than Calibre.

o Calibre hardly reveals the steps every 1/32 th full scale.

o Calibre shows a positive slope on the leftmost 1/16 th scale segments.

EZMod3D accuracy greatly increases confidence in post layout simulations and can save silicon runs in

ADC / DAC design.

Integral non linearity as simulated with Calibre parasitic extraction:

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As simulated with EZMod3D parasitic extraction:

As measured on silicon:

-4,000

-3,000

-2,000

-1,000

0,000

1,000

2,000

3,000

0 200 400 600 800 1000 1200

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5. Substrate coupling in a sensor conditioning ASIC

Context Development of a sensor conditioning ASIC with a high current section (200 mA) and a high accuracy

section (< 1mV)

Goal Define floor plan and substrate connection strategy to provide sufficient isolation between noisy and quiet regions

Strategy First, consider each top-level cell as a constant voltage area and extract substrate equivalent schematic

reduced to one access per cell

Outcome EZMod3D showed that substrate coupling even with a simple model would kill design performance. It was decided to create two substrate areas, each connected by separate pins. Predicted resistance between pins was 6 Ω, measured value was 7 Ω. Parasitic coupling could be improved by 40 dB making it low enough to meet design specifications.

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Chip 3D View in EZMod3D

Extracted SPICE substrate equivalent Netlist:

* SubLEAF_42 2046528 Nodes .SUBCKT EQUIVR0 + Port1 + Port2 + Port3 + Port4 + Port5 + Port6 + Port7 + Port8 + Port9 + Port10 + Port11 * Run 1 RR00 Port2 Port1 1.00089877656713977e+01 RR20 Port2 Port3 1.42339878855168891e+01 RR30 Port2 Port4 1.06238894656360099e+01 RR40 Port2 Port5 7.67391835192174465e+00 RR50 Port2 Port6 1.96759879102190602e+01 RR60 Port2 Port7 1.86885828837821037e+01 RR70 Port2 Port8 5.96714477096950304e+01 RR80 Port2 Port9 9.62114936419411215e+00 RR90 Port2 Port10 2.53883766087227443e+01 RR100 Port2 Port11 1.90912441822667418e+01 * Run 2 RR01 Port3 Port1 2.16156867572003755e+01 RR31 Port3 Port4 1.38461597984208531e+01 RR41 Port3 Port5 1.28505245222790716e+01 RR51 Port3 Port6 2.63074664488792926e+01 RR61 Port3 Port7 2.50772351198250014e+01 RR71 Port3 Port8 9.95075255333911173e+01 RR81 Port3 Port9 1.52201618370221841e+01 RR91 Port3 Port10 3.55861681055412049e+01 RR101 Port3 Port11 2.71647451201394006e+01 * Run 3 RR02 Port4 Port1 1.58294365750045181e+01 RR42 Port4 Port5 9.08810830350310539e+00 RR52 Port4 Port6 1.60125850698144703e+01 RR62 Port4 Port7 1.29312703681024033e+01 RR72 Port4 Port8 6.83046772695680744e+01

RR82 Port4 Port9 9.97313295356698148e+00 RR92 Port4 Port10 2.04449854361164114e+01 RR102 Port4 Port11 1.56944369985126073e+01 * Run 4 RR03 Port5 Port1 8.73376521320312271e+00 RR53 Port5 Port6 1.23105036817725573e+01 RR63 Port5 Port7 1.25262938186477424e+01 RR73 Port5 Port8 2.77621142465253143e+01 RR83 Port5 Port9 4.74574881505522761e+00 RR93 Port5 Port10 1.49738886808259526e+01 RR103 Port5 Port11 1.10056380792872126e+01 * Run 5 RR04 Port6 Port1 2.69516877244696182e+01 RR64 Port6 Port7 1.91299783482284873e+01 RR74 Port6 Port8 9.10583442206676921e+01 RR84 Port6 Port9 1.27196546725247472e+01 RR94 Port6 Port10 2.52221638271501085e+01 RR104 Port6 Port11 2.00807267722784886e+01 * Run 6 RR05 Port7 Port1 2.59462630436467592e+01 RR75 Port7 Port8 8.84304105584212721e+01 RR85 Port7 Port9 1.17576576591658739e+01 RR95 Port7 Port10 1.89319933440942343e+01 RR105 Port7 Port11 1.47655332088415516e+01 * Run 7 RR06 Port8 Port1 6.78001128657335244e+01 RR86 Port8 Port9 2.50649145862052336e+01 RR96 Port8 Port10 1.00180175838729525e+02 RR106 Port8 Port11 7.07807174976416178e+01 * Run 8 RR07 Port9 Port1 1.14070762795934630e+01 RR97 Port9 Port10 1.25513725335351083e+01 RR107 Port9 Port11 8.39838771487940150e+00 * Run 9 RR08 Port10 Port1 3.36802268473390072e+01 RR108 Port10 Port11 1.51438291179655913e+01 * Run 10 RR09 Port11 Port1 2.49686178664098435e+01 .ENDS EQUIVR0

Ready to be included in top schematic to interconnect substrate pins of all top-level cells.

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6. Substrate coupling in a sensor conditioning ASIC

Context Development of a sensor conditioning ASIC with a high dynamic range. Process with deep trench and N+

pockets everywhere.

Goal Extract substrate model to check isolation between noisy and quiet signals Strategy Consider all the pockets connected to pads and extract substrate equivalent schematic reduced to one

access per pad. Check that all other pockets are floating.

Outcome EZMod3D could extract the full substrate model. Plugged into the Top-Level schematic simulation, this substrate model could show the influence of digital I/Os on sensitive analog inputs.

Chip 3D View in EZMod3D

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Extracted SPICE substrate equivalent Netlist (partial):

.SUBCKT EQUIVR0_FAST + sub n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15 n16 n17…

n20 n21 n22 n23 n24 n25 n26 n27 n28 n29 n30 n31 n32 n33 n34 n35 n36 n37 n38 n39 n40 n41 n42

RR00 n1 sub 5,43E-02 RR01 n2 sub 1,14E-01 RR02 n3 sub 1,57E-01 RR03 n4 sub 1,57E-01 RR04 n5 sub 2,85E-01 RR20 n1 n2 2,86E+00 RR30 n1 n3 3,29E+00 RR025 n26 sub 3,54E+00 RR40 n1 n4 3,66E+00 RR018 n19 sub 5,01E+00 RR033 n34 sub 5,01E+00 RR50 n1 n5 5,19E+00 RR031 n32 sub 7,17E+00 RR06 n7 sub 8,01E+00 RR023 n24 sub 1,84E+01 RR08 n9 sub 2,37E+01 RR029 n30 sub 2,42E+01 RR019 n20 sub 2,42E+01 RR035 n36 sub 2,42E+01 RR034 n35 sub 2,42E+01 RR015 n16 sub 2,44E+01 RR041 n42 sub 2,46E+01 RR014 n15 sub 2,48E+01 RR016 n17 sub 2,48E+01 RR07 n8 sub 2,48E+01 RR039 n40 sub 2,49E+01 RR032 n33 sub 2,49E+01 RR027 n28 sub 2,49E+01 RR028 n29 sub 2,50E+01 RR09 n10 sub 2,50E+01 RR024 n25 sub 2,50E+01 …

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3. System design cases: Data were created using built in graphic editor

1. Sizing a Peltier modules stack

Context Development of a system with an IR image sensor to be kept cool in a hot environment with predefined

mechanical constraints

Goal Size properly Peltier modules and stacking hardware to meet requirements before building a prototype Strategy Create the stack assembly and simulate operation to check design margin

Outcome System could be sized properly and showed first time good performance saving months of machining and

assembly and tens of k€ NRE costs

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3D view of Peltier modules stack with temperature profile

View of temperature gradient (log color scale)

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4. Miscellaneous cases: Data were created using built in graphic editor

1. Modeling a multiconductor cable

Context Development of a medical diagnostic ASIC fitted at the end of 2 meters long 200 µm diameter catheter.

Concerns were IR drop and parasitic coupling between signals.

Goal Put numbers on our concerns and define mitigation techniques to ensure proper ASIC operation and performances in this very particular environment

Strategy Create a cable model (RLCK) and simulate ASIC at the end of that model

Outcome Model showed strong interactions between signals. Proper cable signals assignment, smoothing signal

edges and adding Schmidt triggers allowed proper operation in simulation. Measurements fully confirmed

predicted behavior and effectiveness of mitigation techniques, saving one run, hundreds of k€ NRE costs

and months of time to market.

View of cable geometry as created using EZMod3D built in graphic editor

Extracted capacitance values for a 1mm long section

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EZMod3D Materials library:

EZMod3D comes with a comprehensive library of common materials. This library can easily be extended by adding new materials as required.

When materials and layers are defined, they can be saved in a tech file to be reused even more easily.

EZMod3D manages non isotropic material properties.

EZMod3D Tech Files library:

Through times, EZMod3D has been used to simulate hundreds of designs. For each design, materials and layers have

to be defined. Once done, these data can be saved as a Tech File if to be reused as such or as templates for a similar

technology.

Tens of tech files have been created for various PCB stackup or IC process nodes. Some of these data are covered by

NDAs but some are freely available and are supplied with EZMod3D.

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9 0 , a v e n u e L e o n B l u m 3 8 1 0 0 G r e n o b le

F r a n c e w w w . e a s i i – i c . c o m