Consider you are working on a network system. The memory is directly connected to your system through a 32 bit bus clocked at 233 MHz. Your application requires read requests of 64 -byte packets (organized in 32-bit words) from an arbitrary memory location. What are the minimum and maximum transfer rates, if you used:

Synchronous DRAM with a Row Access Signal (RAS) latency of 12 cycles and a maximum burst length of 16?

1.

SRAM with a RAS latency of two cycles and a maximum burst length of 16?2.and d) like a) and b), but with a maximum burst length of four words?3.

Exercise 4: SDRAM vs. SRAM Performance

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Given the parameters in the table below of a typical two input standard cell NAND gate for different technologies, system frequencies and high end die sizes for that technology.

How 'far' can you compute without having more than one data wave between two registers, in fractions of half-chip perimeters? Let the typical delay include the wiring delay.

a.

Exercise 1: Computational Radius

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Long wires are bad from a delay perspective if no repeaters (=buffers or inverters) are inserted.

Why? What is the influence of the wire length on signal delay without repeaters?a.

The table above gives typical scaling values of the input pin capacitance of different technology nodes. Compare the reduction of the gate delays to the change in wire delay caused by the sidewall-capacitances. Suppose that all wire dimensions scale with the same factor as the technology.

For short wires (in the range of standard cell dimensions)?b.

For long wires without repeaters (in the range of chip dimensions)?c.

Exercise 2: Wires

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You are designing a Voice-over-IP transponder operating in a geostationary orbit 35000km above sea level. The idea is to be able to have 1000 customers communicating simultaneously.

The voice is going to be sent in 20ms chunks. What is the packet size if the senders digitize their analog speech signals at 8KHz / 8bit / mono, deploy an audio-codec with an average compression of typically 1:8, pack it into an IP header (overhead 44 bytes), and add 7:4 Hamming ECC before sending it?

a.

What is the data rate that is seen by the receiver?b.

What is the minimum data rate required for the bus in the suggested target architecture if the signal latency must not exceed 250ms in any connection? Assume that the CPU must process half of each packet on average (read half the packet from memory, process it, then write it back to memory).

c.

Exercise 3: Bus

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What if 300ms of latency could be tolerated?d.

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