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1 Concord ia Universi ty Excitati on Vectors Input Combinational Logic Memory Output State s

Excitation Vectors

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Input. Combinational Logic. Output. Excitation Vectors. States. Memory. RS Latch Q+ = S + R’ Q. Two Problems: R=S= 1 Not allowed, Data is transparent. Q. D. CLK. The D Latch. Q + = D. Problem: Level sensitive. JK Latch : Universal, Level sensitive, - PowerPoint PPT Presentation

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Page 1: Excitation Vectors

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Concordia University

Excitation Vectors

InputCombinational Logic

Memory

Output

States

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Concordia University

R S Qt+1 0 0 tq

0 1 1 1 0 0 1 1 —

R

SQ

Q

RS Latch

Q+ = S + R’ Q

Two Problems:

R=S= 1 Not allowed, Data is transparent

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Concordia University

Q

D

C

Q

QC

D

RS Flip Flop

The D Latch

Problem: Level sensitive

D Q+

0 0

1 1

Q+ = D

DLatch

D

CLK

Q

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Concordia University

QKQJQ 1t tt

JK Flip Flop:

S

R

J

K

Q

Q

JK Latch : Universal, Level sensitive,

Timing Constraints due to feed back.

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Concordia University

DLatch

DLatch

Q

QD

C

QD

C

D

C

Q

Master Slave

Master and Slave Flip Flop :

A D Flip Flop with a falling-edge trigger.

Q

D

C

Master Slave Flip Flop Edge sensitive,Set up and Hold time

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Concordia UniversityMaster Slave Flip Flop Edge sensitive,-Falling Edge

Path to setup data

Path to hold data

DLatch

DLatch

Q

QD

C

QD

C

D

C

Q

Master Slave

Set Up and Hold Time constraints

Q

D

C

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Concordia University

S

R

Clk

Q

Q

`

Edge triggered Flip Flop:

Set up and Hold time Constraints

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Concordia University

D Flip-Flop

clkreset

D Q

Edge Triggered, D Flip Flop,

With Reset

clk

D

reset

Q

NAND1

NAND2

NAND3

NAND4

NAND5

NAND6

S

R

Active Low

Reset C D Q Q’

0 X X 0 1

1 0 0 1

1 1 1 0

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Concordia University

D Flip-Flop

clkreset

D Q

Edge Triggered, D Flip Flop When CLK=0

Clk=0

D

reset

Q

NAND1

NAND2

NAND3

NAND4

NAND5

NAND6

S 1

R 1

Active Low

0

0

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Concordia University

clk

D

reset

Q

NAND1

NAND2

NAND3

NAND4

NAND5

NAND6

S

R

When CLK changes from 0 to 1

Case1, D=0: tsetup= t4, thold=t3

Path for set up

Path for hold

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Concordia University

clk

D

reset

Q

NAND1

NAND2

NAND3

NAND4

NAND5

NAND6

S

R

When CLK changes from 0 to 1

Case2, D=1 tsetup=t4 + t1 thold= t2

Path to set up

Path to hold

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Concordia University

clk

D

reset

Q

NAND1

NAND2

NAND3

NAND4

NAND5

NAND6

S

R

When CLK changes from 0 to 1

Case1, D=0: tsetup= t4, thold=t3

Case2, D=1 tsetup=t4 + t1 thold= t2

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Concordia UniversityD Flip Flop

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Concordia University

JK Flip Flop with a rising-edge :

C

J

K

J

K

Q

Q

JK FFJ

K

Q

Q

C

Q+ = JQ’ + K’Q

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Concordia University

JK FFJ

K

Q

Q

C

Q+ = JQ’ + K’Q

J=K=T

Q+ =TQ’ + T’ Q

T=1 Q+ = Q’

T=0 Q+ = Q

QK

J

CLK

T

T-Flip Flop

T

CLK

Q

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Concordia University

Q+ = JQ’ + K’Q

J=K=T

Q+ =TQ’ + T’ Q

T=1 Q+ = Q’

T=0 Q+ = Q

T-Flip Flop

QD

CLK

T

D

CLK

Q

T

CLK

Q