Exceptions and Interrupts on Cortex-M

CS/ECE 5780/6780Embedded Systems Design

Lecture 7, part 2: Exceptions and Interrupts

Thomas [email protected] February 5, 2013

Tuesday, February 5, 13

Announcements

• Are we using C, or ARM or Thumb?• What’s the difference between ARM & Thumb?

–ARM (assembly): always 32-bit–Thumb (assembly): always 16-bit–Thumb-2 (assembly): Mixed 16 and 32-bit

• Who clears interrupt, software or hardware? How to find out?–Read the datasheet.

2Tuesday, February 5, 13

System Timer Register Map

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SmartFusion Microcontroller Subsystem User’s Guide

Revision 3 309

System Timer Register Map The System Timer base address resides at 0x40005000 and extends to address 0x40005FFF in theCortex-M3 memory map.

Table 17-1 • System Timer Register Map

Register Name Address R/WReset Value Description

TIM1_VAL (TIMx_VAL) 0x40005000 R 0x0 Current value of Timer 1

TIM1_LOADVAL (TIMx_LOADVAL) 0x40005004 R/W 0x0 Load value for Timer 1

TIM1_BGLOADVAL (TIMx_BGLOADVAL) 0x40005008 R/W 0x0 Background load value for Timer 1

TIM1_CTRL (TIMx_CTRL) 0x4000500C R/W 0x0 Timer 1 Control register

TIM1_RIS (TIMx_RIS) 0x40005010 R/W 0x0 Timer 1 raw interrupt status

TIM1_MIS (TIMx_MIS) 0x40005014 R 0x0 Timer 1 masked interrupt status

TIM2_VAL (TIMx_VAL) 0x40005018 R 0x0 Current value of Timer 2

TIM2_LOADVAL (TIMx_LOADVAL) 0x4000501C R/W 0x0 Load value for Timer 2

TIM2_BGLOADVAL (TIMx_BGLOADVAL) 0x40005020 R/W 0x0 Background load value for Timer 2

TIM2_CTRL (TIMx_CTRL) 0x40005024 R/W 0x0 Timer 2 Control register

TIM2_RIS (TIMx_RIS) 0x40005028 R/W 0x0 Timer 2 raw interrupt status

TIM2_MIS (TIMx_MIS) 0x4000502C R 0x0 Timer 2 masked interrupt status

TIM64_VAL_U 0x40005030 R 0x0 Upper 32-bit word in 64-bit mode

TIM64_VAL_L 0x40005034 R 0x0 Lower 32-bit word in 64-bit mode

TIM64_LOADVAL_U 0x40005038 R/W 0x0 Upper 32-bit load value word in 64-bitmode

TITM64_LOADVAL_L 0x4000503C R/W 0x0 Lower 32-bit load value word in 64-bitmode

TIM64_BGLOADVAL_U 0x40005040 R/W 0x0 Upper 32-bit background load value in 64-bit mode

TIM64_BGLOADVAL_L 0x40005044 R/W 0x0 Lower 32-bit background load value in 64-bit mode

TIM64_CTRL 0x40005048 R/W 0x0 Control register in 64-bit mode

TIM64_RIS 0x4000504C R/W 0x0 Raw interrupt status in 64-bit mode

TIM64_MIS 0x40005050 R 0x0 Masked interrupt status in 64-bit mode

TIM64_MODE 0x40005054 R/W 0x0 System Timer dual 32-bit or 64-bit mode


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SmartFusion Microcontroller Subsystem User’s Guide

Revision 3 311

Timer x Control RegisterTable 17-5 • TIMx_CTRL

Bit Number Name R/W

Reset Value Description

31:3 Reserved R/W 0x0 Software should not rely on the value of a reserved bit. To providecompatibility with future products, the value of a reserved bit should bepreserved across a read-modify-write operation.

2 TIMxINTEN R/W 0x0 Timer x Interrupt Enable. When the counter reaches zero, an interrupt issignaled to the Cortex-M3 Nested Vectored Interrupt Controller; IRQ20for Timer x, IRQ21 for Timer 2.0 = Timer x interrupt disabled1 = Timer x interrupt enabledWriting this register while the System Timer is set to 64-bit mode has noeffect. Reading this register while the System Timer is set to 64-bit modereturns the reset value.

1 TIMxMODE R/W 0x0 Timer x Mode. 0 = Timer x in Periodic Mode. If TIMxENABLE = 1 when the counterreaches zero the counter is reloaded from the value in theTIMxLOADVAL register and begins counting down immediately.1 = Timer x in One-Shot mode. If TIMxENABLE = 1 when the counterreaches zero the counter stops counting. To start the counter again, theuser must load TIMxLOADVAL with a non-zero value or set the Timer toPeriodic mode by clearing TIMxMODE to 0.Writing this register while the System Timer is set to 64-bit mode has noeffect. Reading this register while the System Timer is set to 64-bit modereturns the reset value.

0 TIMxENABLE R/W 0x0 Timer x Enable0 = Timer x disabled1 = Timer x enabledSetting to 1 enables the timer and starts it counting from the currentvalue in TIMx_VAL unless TIMx_VAL is 0, in which case TIMx_VAL isloaded from TIMx_LOADVAL.Writing this register while the System Timer is set to 64-bit mode has noeffect. Reading this register while the System Timer is set to 64-bit modereturns the reset value.


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System Timer

312 Revision 3

Timer x Raw Interrupt Status Register

Timer x Masked Interrupt Status Register

Timer 64 Value Upper Register

Timer 64 Value Lower Register

Table 17-6 • TIMx_RIS

Bit Number Name R/W


31:1 Reserved R/W 0x0 Software should not rely on the value of a reserved bit. To providecompatibility with future products, the value of a reserved bit should bepreserved across a read-modify-write operation.

0 TIMx_RIS R/W 0x0 Timer x Raw Interrupt Status0 = Timer x has not reached zero1 = Timer x has reached zero at least once since this bit was last cleared(by a reset or by writing 1 to this bit).Writing a 1 to this bit clears the bit and the interrupt, writing a zero has noeffect.

Table 17-7 • TIMx_MIS

Bit Number Name R/W


31:1 Reserved R 0x0 Software should not rely on the value of a reserved bit. To providecompatibility with future products, the value of a reserved bit shouldbe preserved across a read-modify-write operation.

0 TIMx_MIS R 0x0 Timer x masked interrupt statusThis read only bit is a logical AND of the TIMxRIS and TIMxINTENbits. The TIMERxINT output from the timer has the same value as thisbit. Writing to this bit has no effect.

Table 17-8 • TIM64_VAL_U

Bit Number Name R/W


31:0 TIM64_VAL_U R 0x0 This register holds the current value of the upper 32 bits of the 64-bitcount value for the System Timer. This register is read only; writeshave no effect. Reading this register while the System Timer is set to32-bit mode returns the reset value.

Table 17-9 • TIM64_VAL_L

Bit Number Name R/W


31:0 TIM64_VAL_L R 0x0 This register holds the current value of the lower 32 bits of the 64-bitcount value for the System Timer. This register is read only; writes haveno effect. When reading from this register, the upper 32 bits of the 64-bit counter is stored into TIM64_VAL_U. To properly read the 64-bitcounter value, the user must read from this register first; then theTIM64_VAL_U. Reading this register while the System Timer is set to32-bit mode returns the reset value.


6

Minute Quiz


Minute Quiz

7

What is the first interrupt that fires on a Cortex-M3?


Exercise: How many preemption priorities and subpriority levels do we get on the Smart Fusion if we set Priority Group to 5?

8

ProgrammableExceptions

-3-2-1

0x00

ResetNMI

Hard Fault

Preempt levels with priority

group set to 5

Subpriority levels

0x080x100x180x200x280x300x380x400x48

0xe00xe80xf00xf8

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0PreemptPreempt SubSubSub

0x40

0xc0

0x00

0x80

0x080x100x180x200x280x300x38

0x00

0xe00xe80xf00xf8

0xc00xc80xd00xd8


PRIMASK, FAULTMASK, and BASEPRI

• What if we quickly want to disable all interrupts?

• Write 1 into PRIMASK to disable all interrupt except NMI– MOV R0, #1– MSR PRIMASK, R0

• Write 0 into PRIMASK to enable all interrupts• FAULTMASK is the same as PRIMASK, but also blocks

hard fault (priority -1)

• What if we want to disable all interrupts below a certain priority?

• Write priority into BASEPRI– MOV R0, #0x60– MSR BASEPRI, R09


Question

10

Assume BASE_PRIO_REG is set to the programmable interrupt priority register,

and the following code runs:movw r0, #:lower16:INT_PRIO_REGmovt r0, #:upper16:INT_PRIO_REGmov r1, #61strb r, [r0, #31]MOV R0, #0x60MSR BASEPRI, R0

Will interrupt 31 still interrupt your code?


Outline• Minute quiz• Finish up interrupts• Graduate student presentations• Final projects


What exactly is an interrupt handler?


Vector Table

• Upon an interrupt, the Cortex-M3 needs to know the address of the interrupt handler (function pointer)

• After powerup, vector table is located at 0x00000000

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Exceptions

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Since the address 0x0 should be boot code, usually it will either be Flash memory or ROM devices, and the value cannot be changed at run time. However, the vector table can be relocated to other memory locations in the Code or RAM region where the RAM is so that we can change the handlers during run time. This is done by setting a register in the NVIC called the vector table offset register (address 0xE000ED08). The address offset should be aligned to the vector table size, extended to the power of 2. For example, if there are 32 IRQ inputs, the total number of exceptions will be 32 ! 16 (system exceptions) " 48. Extending it to the power of 2 makes it 64. Multiplying it by 4 makes it 256 (0x100). Therefore, the vector table offset can be programmed as 0x0, 0x100, 0x200, and so on. The vector table offset register contains the items shown in Table 7.7.

In applications where you want to allow dynamic changing of exception handlers, in the beginning of the boot image you need to have these (at a minimum):

• Initial Main Stack Pointer value

• Reset vector

Figure 7.8 Defi nition of Priority Fields in an 8-bit Priority Level Register with Priority Group Set to 0

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Preempt priority Subpriority

Address Exception Number Value (Word Size)0x00000000 – MSP initial value

0x00000004 1 Reset vector (program counter initial value)

0x00000008 2 NMI handler starting address

0x0000000C 3 Hard fault handler starting address

… … Other handler starting address

Table 7.6 Exception Vector Table After Power Up

Bits Name Type Reset Value Description29 TBLBASE R/W 0 Table base in Code (0) or RAM (1)

28:7 TBLOFF R/W 0 Table offset value from Code region or RAM region

Table 7.7 Vector Table Offset Register (Address 0xE000ED08)

Vector Tables

When an exception takes place and is being handled by the Cortex-M3, the processor will need to locate the starting address of the exception handler. This information is stored in the vector table. By default, the vector table starts at address zero, and the vector address is arranged according to the exception number times 4 (see Table 7.6).

CH07-H8534.indd 123CH07-H8534.indd 123 7/19/07 1:32:07 PM7/19/07 1:32:07 PM

• Can be relocated to change interrupt handlers at runtime (vector table offset register)


Vector Table in SoftConsole• Located in startup_a2fxxxm3.s

• Put at 0x00000000 in linker script


Interrupt Handlers


Interrupt Handler in GNU C

• We can overwrite the predefined interrupt handlers

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__attribute__((__interrupt__)) void Timer1_IRQHandler(){ MSS_TIM1_disable_irq(); MSS_TIM1_clear_irq(); … NVIC_ClearPendingIRQ( Timer1_IRQn );}

int main(){ … MSS_TIM1_enable_irq(); NVIC_EnableIRQ( Timer1_IRQn ); … while(1){}}


Interrupt Service Routines

1. Automatic saving of registers upon exception• PC, PSR, R0-R3, R12, LR pushed on the stack

2. While bus busy, fetch exception vector3. Update SP to new location4. Update IPSR (low part of PSR) with new exception

number5. Set PC to vector handler6. Update LR to special value EXC_RETURN

• Several other NVIC registers get updated• Latency: as short as 12 cycles


Interrupt Stacking

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Chapter 9

150

The values of PC and PSR are stacked fi rst so that instruction fetch can be started early (which requires modifi cation of PC) and the IPSR can be updated early. After stacking, SP will be updated to N-32 (0 ! 20), and the stacked data arrangement in the stack memory will look like Table 9.1.

N-8Address(HADDR)

PC

N-4

PSR

N-32

R0

N-28

R1

N-24

R2

N-20

R3

N-16

R12

N-12

LRData

(HWDATA)

Time

Figure 9.1 Stacking Sequence

Address Data Push OrderOld SP (N) -" (Previously pushed data) –

(N-4) PSR 2

(N-8) PC 1

(N-12) LR 8

(N-16) R12 7

(N-20) R3 6

(N-24) R2 5

(N-28) R1 4

New SP (N-32) -" R0 3

Table 9.1 Stack Memory Content After Stacking and Stacking Order

The reason the registers R0–R3, R12, LR, PC, and PSR are stacked is that these are caller saved registers, according to C standards (C/C## standard Procedure Call Standard for the ARM Architecture, AAPCS, Ref 5). This arrangement allows the interrupt handler to be a normal C function, because registers that could be changed by the exception handler are saved in the stack.

The general registers (R0–R3, R12) are located at the end of the stack frame so that they can be easily accessed using SP-related addressing. As a result, it’s easy to pass parameters to software interrupts using stacked registers.

Vector Fetches

While the data bus is busy stacking the registers, the instruction bus carries out another important task of the interrupt sequence: It fetches the exception vector (the starting address of the exception handler) from the vector table. Since the stacking and vector fetch are performed on separate bus interfaces, they can be carried out at the same time.


Chapter 3

34

You can read the program status registers using the MRS instruction. You can also change the APSR using the MSR instruction, but EPSR and IPSR are read-only. For example:

MRS r0, APSR ; Read Flag state into R0MRS r0, IPSR ; Read Exception/Interrupt stateMRS r0, EPSR ; Read Execution stateMSR APSR, r0 ; Write Flag state

In ARM assembler, when accessing xPSR (all three program status registers as one), the symbol PSR is used:

MRS r0, PSR ; Read the combined program status wordMSR PSR, r0 ; Write combined program state word

The descriptions for the bit fi elds in PSR are shown in Table 3.1.

31 30 29 28 27 26:25 24 23:20 19:16 15:10 9 8 7 6 5 4:0

APSR N Z C V Q

IPSR Exception Number

EPSR ICI/IT T ICI/IT

Figure 3.3 Program Status Registers (PSRs) in the Cortex-M3

31 30 29 28 27 26:25 24 23:20 19:16 15:10 9 8 7 6 5 4:0

xPSR N Z C V Q ICI/IT T ICI/IT Exception Number

Figure 3.4 Combined Program Status Registers (xPSR) in the Cortex-M3

Bit DescriptionN Negative

Z Zero

C Carry/borrow

V Overfl ow

Q Sticky saturation fl ag

ICI/IT Interrupt-Continuable Instruction (ICI) bits, IF-THEN instruction status bit

T Thumb state, always 1; trying to clear this bit will cause a fault exception

Exception Indicates which exception the processor is handlingNumber

Table 3.1 Bit Fields in Cortex-M3 Program Status Registers


From: The Definitive Guide to the ARM Cortex-M3


Return from ISR

• 3 ways to return from an ISR

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Interrupt Behavior

151

Register Updates

After the stacking and vector fetch are completed, the exception vector will start to execute. On entry of the exception handler, a number of registers will be updated:

• SP: The Stack Pointer (either the MSP or the PSP) will be updated to the new location during stacking. During execution of the interrupt service routine, the MSP will be used if the stack is accessed.

• PSR: The IPSR (the lowest part of the PSR) will be updated to the new exception number.

• PC: This will change to the vector handler as the vector fetch completes and starts fetching instructions from the exception vector.

• LR: The LR will be updated to a special value called EXC_RETURN.1 This special value drives the interrupt return operation. The last 4 bits of the LR have a special meaning, which is covered later in this chapter.

A number of other NVIC registers will also be updated. For example, the pending status of the exception will be cleared and the active bit of the exception will be set.

Exception Exits

At the end of the exception handler, an exception exit (known as an interrupt return in some processors) is required to restore the system status so that the interrupted program can resume normal execution. There are three ways to trigger the interrupt return sequence; all of them use the special value stored in the LR in the beginning of the handler (see Table 9.2).

1 EXC_RETURN has values with bit[31:4] and are all 1 (i.e., 0xFFFFFFFX); the last 4 bits defi ne the return information. More information on the EXC_RETURN value is covered later in this chapter.

Return Instruction DescriptionBX !reg" If the EXC_RETURN value is still in LR, we can use the BX LR instruction to perform the interrupt return.

POP {PC}, or Very often the value of LR is pushed to the stack after entering the exceptionPOP {...., PC} handler. We can use the POP instruction, either a single POP or multiple POPs, to put the EXC_RETURN value to the program counter. This will cause the processor to perform the interrupt return.

LDR, or LDM It is possible to produce an interrupt return using the LDR instruction with PC as the destination register.

Table 9.2 Instructions that Can be Used for Triggering Exception Return


• Unstack and reset SP• Update NVIC registers


Nested Interrupts

• Built into the Cortex-M3 (not every MCU has this)• Make sure main stack is large enough!

• Three methods:–Tail Chaining–Late Arrival–Preemption


Tail Chaining

• If first interrupt has same or higher priority• Skip stacking/unstacking for efficiency

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Interrupt Behavior

153

Late Arrivals

Another feature that improves interrupt performance is late arrival exception handling. When an exception takes place and the processor has started the stacking process, and if during this delay a new exception arrives with higher preemption priority, the late arrival exception will be processed fi rst.

For example, if Exception #1 (lower priority) takes place a few cycles before Exception #2 (higher priority), the processor will behave as shown in Figure 9.3, such that Handler #2 is executed as soon as the stacking completes.

Interrupt #1

Interrupt #2

Main Program

ProcessorState

Interrupt ServiceRoutine #1


Main Program

InterruptEvent #1

Interrupt exits Interrupt exits

Stacking Unstacking

Thread Mode Handler Mode Handler Mode Thread Mode

Figure 9.2 Tail Chaining of Exceptions

Interrupt #1(Low Priority)

Interrupt #2(High Priority)

ProcessorState Thread Handler #2Exception Sequence

Data Bus

InstructionBus Thread

Vector Fetch

Handler Instruction Fetch

Stacking

Figure 9.3 Late Arrival Exception Behavior

More on the Exception Return Value

When entering an exception handler, the LR is updated to a special value called EXC_RETURN, with the upper 28 bits all set to 1. This value, when loaded into the PC at the end of the




Late Arrival

• Main stack must be able to hold maximum number of preemptions!

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Interrupt Behavior

153

Late Arrivals

Another feature that improves interrupt performance is late arrival exception handling. When an exception takes place and the processor has started the stacking process, and if during this delay a new exception arrives with higher preemption priority, the late arrival exception will be processed fi rst.

For example, if Exception #1 (lower priority) takes place a few cycles before Exception #2 (higher priority), the processor will behave as shown in Figure 9.3, such that Handler #2 is executed as soon as the stacking completes.

Interrupt #1

Interrupt #2

Main Program

ProcessorState



Main Program

InterruptEvent #1

Interrupt exits Interrupt exits

Stacking Unstacking

Thread Mode Handler Mode Handler Mode Thread Mode

Figure 9.2 Tail Chaining of Exceptions

Interrupt #1(Low Priority)

Interrupt #2(High Priority)

ProcessorState Thread Handler #2Exception Sequence

Data Bus

InstructionBus Thread

Vector Fetch

Handler Instruction Fetch

Stacking

Figure 9.3 Late Arrival Exception Behavior

More on the Exception Return Value

When entering an exception handler, the LR is updated to a special value called EXC_RETURN, with the upper 28 bits all set to 1. This value, when loaded into the PC at the end of the




EXC_RETURN

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150 CHAPTER 9 Interrupt Behavior

Bit 0 indicates the process state being used after the exception return. Since the Cortex-M3 supports only the Thumb® state, bit 0 must be 1. The valid values (for the Cortex-M3) are shown in Table 9.3.

If the thread is using the MSP (main stack), the value of LR will be set to 0xFFFFFFF9 when it enters an exception, and 0xFFFFFFF1 when a nested exception is entered, as shown in Figure 9.5. If the thread is using PSP (process stack), the value of LR would be 0xFFFFFFFD when entering the first exception and 0xFFFFFFF1 for entering a nested exception, as shown in Figure 9.6.

As a result of the EXC_RETURN number format, you cannot perform interrupt returns to an address in the 0xFFFFFFF0–0xFFFFFFFF memory range. However, since this address is in a nonexecutable region anyway, it is not a problem.

Table 9.2 Description of Bit Fields in EXC_RETURN Value

Bits 31:4 3 2 1 0

Descriptions 0xFFFFFFF Return mode (thread/handler)

Return stack Reserved; must be 0

Process state (Thumb/ARM)

Table 9.3 Allowed EXC_RETURN Values on Cortex-M3

Value Condition

0xFFFFFFF1 Return to handler mode0xFFFFFFF9 Return to thread mode and on return use the main stack0xFFFFFFFD Return to thread mode and on return use the process stack

FIGURE 9.4Late Arrival Exception Behavior.

Interrupt #1(Low priority)

Interrupt #2(High priority)

Processorstate Thread Handler #2Exception sequence

Data bus Stacking

Instructionbus Thread

Vector fetch

Handler instruction fetch

150 CHAPTER 9 Interrupt Behavior

Bit 0 indicates the process state being used after the exception return. Since the Cortex-M3 supports only the Thumb® state, bit 0 must be 1. The valid values (for the Cortex-M3) are shown in Table 9.3.

If the thread is using the MSP (main stack), the value of LR will be set to 0xFFFFFFF9 when it enters an exception, and 0xFFFFFFF1 when a nested exception is entered, as shown in Figure 9.5. If the thread is using PSP (process stack), the value of LR would be 0xFFFFFFFD when entering the first exception and 0xFFFFFFF1 for entering a nested exception, as shown in Figure 9.6.

As a result of the EXC_RETURN number format, you cannot perform interrupt returns to an address in the 0xFFFFFFF0–0xFFFFFFFF memory range. However, since this address is in a nonexecutable region anyway, it is not a problem.

Table 9.2 Description of Bit Fields in EXC_RETURN Value

Bits 31:4 3 2 1 0

Descriptions 0xFFFFFFF Return mode (thread/handler)

Return stack Reserved; must be 0

Process state (Thumb/ARM)

Table 9.3 Allowed EXC_RETURN Values on Cortex-M3

Value Condition

0xFFFFFFF1 Return to handler mode0xFFFFFFF9 Return to thread mode and on return use the main stack0xFFFFFFFD Return to thread mode and on return use the process stack

FIGURE 9.4Late Arrival Exception Behavior.



Processorstate Thread Handler #2Exception sequence

Data bus Stacking

Instructionbus Thread

Vector fetch

Handler instruction fetch


Allowed values on the ARM Cortex-M3


Preemption (Thread with Main Stack)

24

1519.6 More on the Exception Return Value

FIGURE 9.5LR Set to EXC_RETURN at Exception (Main Stack Used in Thread Mode).



Main program

Interrupt exit

Interruptexit

Unstacking

Interrupt serviceroutine #2


Stacking

Executionstatus

Interruptevent #1

Thread modeHandlermode

Handlermode

Handlermode Thread mode

LR 5 0xFFFFFFF9 LR 5 0xFFFFFFF1

Main stackMain stack Main stack

FIGURE 9.6LR Set to EXC_RETURN at Exception (Process Stack Used in Thread Mode).



Main program

Interrupt exit

Interruptexit

Unstacking



Stacking

Executionstatus

Interruptevent #1

Thread mode Handlermode

Handlermode

Handlermode Thread mode

LR 5 0xFFFFFFFD LR 5 0xFFFFFFF1

Main stackProcess stack Process stack


Different Concepts of Interrupt Sharing

• Number of potential interrupts usually larger than interrupt lines availability on Core

• One peripheral often only has one interrupt• Different types of events are stored in a status register

• Example, UART– IIR, 0x40000008

25

Universal Asynchronous Receiver/Transmitter (UART) Peripherals

278 Revision 1

Interrupt Identification Register (IIR)Table 15-8 • IIR

Bit Number Name R/W Reset Value Description

7:6 Mode R 0b11 Always 0b11. Enables FIFO mode.

5:4 Reserved R 0 Software should not rely on the value of a reserved bit. Toprovide compatibility with future products, the value of areserved bit should be preserved across a read-modify-writeoperation.

3:0 Interrupt identification

bits

R 0b0001 0b0110 = Highest priority. Receiver line status interrupt dueto overrun error, parity error, framing error or breakinterrupt. Reading the Line Status Register resets thisinterrupt.0b0100 = Second priority. Receive data available interruptmodem status interrupt. Reading the Receiver BufferRegister (RBR) or the FIFO drops below the trigger levelresets this interrupt.

0b1100 = Second priority. Character timeout indicationinterrupt occurs when no characters have been read from theRX FIFO during the last four character times and there was atleast one character in it during this time. Reading the ReceiveBuffer Register (RBR) resets this interrupt.0b0010 = Third priority. Transmit Holding Register Emptyinterrupt. Reading the IIR or writing to the Transmit HoldingRegister (THR) resets the interrupt.0b0000 = Fourth priority. Modem status interrupt due toClear to Send, Data Set Ready, Ring Indicator, or Data CarrierDetect being asserted. Reading the Modem Status Registerresets this interrupt.

This register is read only; writing has no effect. Also seeTable 15-9.

Table 15-9 • Interrupt Identification Bit Values

IIR ValuePriority Level Interrupt Type Interrupt Source Interrupt Reset Control

0b0110 Highest Receiver line status Overrun error, parity error, or break interrupt

Reading the Line Status Register

0b0100 Second Received data available

Receiver data available Reading the Receiver Buffer register or the FIFO drops below the trigger level

0b1100 Second Character timeout indication

No characters have been read from the RX FIFO during the last four character times and there was at least one character in it during this time.

Reading the Receiver Buffer register

0b0010 Third Transmitter Holding register empty

Transmitter Holding Register empty Reading the IRR or writing into the Transmitter Holding register

0b0000 Fourth Modem status Clear to Send, Data Set Ready, Ring Indicator, or Data Carrier Detect

Reading the Modem Status register


ISR Sharing, i.e., Callbacks in C• There is only one interrupt handler• Functions have to “subscribe” for events• Callbacks

–Driver provides function to register a function pointer–Driver stores function pointers in list–Upon interrupt, each registered function gets called

26

typedef void (*radioalarm_handler_t)(void);radioalarm_handler_t radio_alarm_fired;

void RadioAlarm_init(radioalarm_handler_t handler){ radio_alarm_fired = handler;}

__attribute__((__interrupt__)) void Timer1_IRQHandler(){ alarm_state = FREE; MSS_TIM1_disable_irq(); MSS_TIM1_clear_irq(); NVIC_ClearPendingIRQ( Timer1_IRQn ); (*(radio_alarm_fired))(); // call the callback function}


Common Problems and Pit-Falls

• Too many interrupts–Your core can’t keep up with handling interrupts

• Concurrency issues–One interrupt handler modifies global variables–Can be avoided using atomic sections protected through

PRIMASK

• Lost interrupts–It can happen that an interrupt doesn’t get treated by the

Core–State machine and peripheral has to be aware of this

possibility–Danger for deadlocks


Summary• Overwrite default Interrupt Handler

• Initialization–Enable interrupt in NVIC–Enable interrupt in Peripheral

• Upon Interrupt–Clear interrupt in Peripheral–Clear pending bit in NVIC–Potentially disable interrupts temporarily


29

Graduate Student Presentations


Graduate Student Presentations• Graduate students will present one embedded system

–Processor and system architecture–Tools and software for programming, hackability–Platforms–Why does this system exist–Demo it

• 19 graduate students• 5 Lectures between Spring Break & Open House• 4 students per lecture (~15 min)• You can pick your platform

• Sign up: http://goo.gl/HUAXN30


http://goo.gl/HUAXN

http://goo.gl/HUAXN

31

You propose a platform!

Selection due by Feb 21st

Talk to me about the platform you want to choose (Office Hours or by appointment)


32

Projects


Start Thinking about Projects!

33

Picking a Project Idea: Think BIG to StartPicking a Project Idea: Think BIG to

StartThinking Big: Segway Example Simplified 373 Project

Problems•Scale: To Big…Accommodates adults!•Power: Large Power Source and Actuators•Complex Control

Solution•Scale: Scale Down 1’ High•Power: Low Power, Hobby Servo Actuators•Simple ControlComplex Control

•Gyro Stabilized•High Center of Gravity

•Simple Control•“Tail” controls variable resistor•Low Center of Gravity

Slides from Matt SmithTuesday, February 5, 13

34

Types Of Projects: MusicAir Guitar

Touch key matrix to emulate fret board of guitar. Fabricate with PC board.

Guitar Pick air action is modeled with 3 axis

Music created by sending MIDI codes with 3 axis

accelerometer. to MIDI synthesizer.


35

Types Of Projects: ConceptlAuto Balancing Teeter Totter

Angle position controlled by propeller speedpropeller speed

Infrared distance sensor to measure height

Angle is maintained with feedback control.

Construction by KnexConstruction by Knex


36

Types Of Projects: Robotich dKnight Ryder

• Featured gyros and accelerometers for inertial guidance (really).• Spoiler was added to maintain traction and stability at high speeds! (probably cosmetic).(probably cosmetic).

GraphicsGraphics display indicating heading and positionSlides from Matt Smith


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Types Of Projects: GamingSpace InvadersSpace Invaders

I t iIntense gaming in the 373 lab! Classic game

controllers: N64 and N8

GraphicsGraphics display indicating the t i titermination of Earth!

Slides from Matt Smith


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Types Of Projects: MeasurementdRadar

IR and Ultrasonic Sensor for Ranging

Servo provided angular sweep. p

Reflections plotted as function of angle and distance

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Types Of Projects: ResearchWireless Power Monitoring

Objectives• Contained in 1 cubic inch•Wireless transmitting info to

Processor (LPC1114)

AC thru plugPCB Design!

central monitor and control• Low power• Low cost (in quantity)

RadioRadio (CC2520)

Power Monitor Circuit(ADE7753)

Interconnect Points Fold to Connect Cube Sides

(ADE7753)


3D PCB and Conductive Ink


Quadcopter


Idea, Starting Points• Review Last Year ECE/CS 5780/6780 Projects

• h6p://wiesel.ece.utah.edu/redmine/projects/ece5780-‐s12-‐groups• Review Past UM 373 Projects

• h6p://www.eecs.umich.edu/courses/eecs373/Labs/Web/projects.html

• Search YouTube 373 projects

• Provides Sense of Scale • Review Cornel Projects Web Site

• h6p://instruct1.cit.cornell.edu/courses/ee476/FinalProjects/

• Feedback control oriented, but lots of applicaQons

•More devices to consider • Research Oriented Projects

• Prof Schmid will provide a list soon• YOU!• Have a big cup of coffee and dream • Pick something you want to do!! • Think about all the embedded applicaQons around you • Consider variants • Consider improvements

• Research the applicaQon (know something about it!) • Discuss your ideas with potenQal partners and friends • Discuss your ideas with staff 42


http://wiesel.ece.utah.edu/redmine/projects/ece5780-s12-groups

http://wiesel.ece.utah.edu/redmine/projects/ece5780-s12-groups

http://www.eecs.umich.edu/courses/eecs373/Labs/Web/projects.html

http://www.eecs.umich.edu/courses/eecs373/Labs/Web/projects.html

http://instruct1.cit.cornell.edu/courses/ee476/FinalProjects/

http://instruct1.cit.cornell.edu/courses/ee476/FinalProjects/

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Forming GroupsForming Groups

• Group sizes: 2 – 4p• Larger Groups– Advantages: Do more complex projects– Disadvantages: Challenging group management,

unknown relationships• Smaller GroupsSmaller Groups– Advantages: Group dynamic is simpler, task

management, known relationship, etcDi d t P ibl li it j t l it– Disadvantages: Possibly limits project complexity

• Start with existing Lab Partner or form new groupsgroups


Proposal• Due: 3/5, Tuesday in Lecture• Contents–List of group members–Goal Statement: In general terms describe your project–Functional Specification

List and describe high level functionshigh level functional diagram

–Preliminary Component List• Proposal Reviews–March 6th (Wednesday) & 7th (Thursday)


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Proposal Example

Goal StatementFor our project we intend to build a sound level

meter. Sound level meters are used in applications ranging from environmental noise management to balancing sound systems in concert halls.

Our meter will approximate the Extech Model 407764 We will attempt emulate some the meter’s basic407764. We will attempt emulate some the meter s basic functionality, but with out the same precision or reference accuracy.

h ll h h f ll b fThe meter will have the following basic functions:1. Sound level measurement with A and C frequency

weighting2. Time weighting from 1 – 100 secondsg g3. Linear and logarithmic display of sounds level4. Manual (4 ranges) and auto ranging5. Data logging for 1 hour6 PC i t f t h t i l f ASCII fil ti i fil6. PC interface to hyper terminal for ASCII file time series file

storage of data log.


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Functional Description• Sound MeasurementSound Measurement

– Microphone: Commercial sound meters use expensive microphones. We will use a simple audio mic that will not have the same sensitivity, but can be frequency compensated. Signal Conditioning: An audio amplifier will have to be provided to provide– Signal Conditioning: An audio amplifier will have to be provided to provide gain to the ADC.

– Signal Conditioning: An antiͲaliasing filter will have to be provided to for audio frequencies. We will use an active filter.

• Data Acquision– The ACE will be setup to acquire data with 10 bit resolution and sample

frequency of 40khz.

• Frequency Measurement• Frequency Measurement– An FFT over the audio range will be performed using SmartFusion FFT

core.

• Displayp y– Display sound level digitally, simply analog meter graphic, measurement

modes, etc.

• Key PadU i t t d di l ti t– User input: measurement modes, display options, etc


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Functional DiagramFunctional Diagram

Audio

SmartFusion KitU I t f

Audio Microphone,

Amplifier,AntiͲalias Filter

Serial Interface to Computer

User InterfaceADCFFT

Log Memoryd DisplayKeypad Display


Questions?

Comments?

Discussion?

Write on a paper:

- One point that really sticks out about this lecture- One point that was unclear about this lecture


Documents

Exceptions and Interrupts on Cortex-M