Example Target - MVME2604read.pudn.com/downloads27/sourcecode/embed/86350/Tornado...Set processor to supervisor mode by clearing PR bit. Conﬁgure for big-endian mode by clearing

Wind River SystemsTornado BSP Training Workshop © Copyright Wind River Systems A-1

Appendix

A

Example Target -MVME2604

Overview A-2

Power On and romInit() A-13

sysHwInit() A-20

Memory Maps A-33

Interrupts A-37

Timers A-59

LAN Integration A-63


Example Target - MVME2604

Overview

Power On and romInit()

sysHwInit()

Memory Maps

Interrupts

Timers

LAN Integration


Overview

• This appendix provides support material for

understanding BSP issues associated with the

MVME2604.

• MVME2604 BSP illustrates many of the practical issues

a BSP developer will need to resolve:

● Managing interrupts via interrupt controller.● Managing multiple busses.● Supporting standard embedded devices (LAN,

serial, SCSI, etc.)● Programming for a modern architecture.● Building a WRS compliant BSP for a complex

environment.


MVME2604 Environment

• CPU:

● PowerPC 604.

• Buses:

● MPC604 Processor bus.● PCI● ISA● External VME bus.

• Bus controllers:

● MPC604/PCI bus bridge controller (Raven ASIC).● VME/PCI bus bridge controller (Universe ASIC).● PCI/ISA bus bridge controller (Winbond ASIC - PIB)● Memory controller (Falcon ASIC).

• PIB - PCI to ISA Bridge.

• Board has support for (stacking) a PCI Mezzanine Card (PMC).

Provides I/O expansion:

● FDDI.● ATM.● Graphics● Additional Ethernet and/or SCSI.

• Board also has a PCI expansion slot for connecting to a carrier board.

• PMC and carrier board connected to expansion slot require PCI bridge

controllers.


MVME2604 Environment - cont.

• Memory:

● 1 MB socketed EEPROM/Flash on MPC604 bus.● 256 KB L2 cache on MPC604 bus.● 4 MB (or 8 MB) solderedFlash (RAM200 Mezzanine).● 16 MB to 256 MB ECC DRAM (RAM200 Mezzanine).● 8 KB NVRAM (with RTC).

• Devices accessed via local PCI bus:

● DEC 21140 Ethernet controller.● NCR 53C825A SCSI controller.● PCI expansion slot devices (mezzanine & expansion)● ISA bus devices via Winbond PIB.● VME bus devices via Universe chip.

• Additional devices may be supported via the local PCI bus by using the

two on-board PCI expansion slots.

• RTC - Real-Time Clock.


MVME2604 Environment - cont.

• Devices accessed via local ISA bus:

● Zilog 85230 ESCC.● Zilog Z8536 CIO - Support for modem control lines

not supported by Z85230 SCC. Used for auxilaryclock by VxWorks.

● Super I/O ASIC - Controller for keyboard, mouse,floppy disk drive via front panel connectors; andasynchronous serial and parallel ports throughtransition module.

• Transition Module:

● MVME761 or MVME712M - Provides front panelinterface for ethernet, 2 ESCC ports, and super I/Oserial/parallel ports. Separate board which plugsinto VME backplane.

• Note, there are two varieties of the MVME761 transition module:

● The MVME761-001 with conventional 3-row P2 adapter.● The MVME761-011 with a 5-row P2 adapter.

• The Winbond ISA/PCI bridge controller also provides ISA bus

arbitration for DMA devices.


MVME2604

PPC604

EthernetSCSI

L2 Cache

PCI-EPCM

Raven

Falcon

ROM/Flash

Flash4/8MB

DRAM

PIB NVRAM

SCC CIO SIO

Universe

• Processor bus -

• PCI bus -

• ISA bus -

• PCM - PCI Mezzanine Card slot.

• PCI-E - PCI Expansion slot.

• The socketed ROM/Flash supports 1 MB of firmware.


Busses And Endianness

• On-board busses:

● Processor bus: big-endian.● Memory bus: big-endian.● PCI bus: little-endian.● ISA bus: little-endian.● VME bus: big-endian.

• Bridge controllers and endianness:

● Raven ASIC provides endian translation betweenhost and PCI busses. No issues for Ethernet and SCSIdata, however, big-endian software needs to performbyte-swapping when accessing control registers.

● Universe ASIC manages endian translation betweenPCI and VME bus.

• Falcon and PIB controllers bridge busses with the same endianness, and

have no endian issues.


Example Target

• Example BSP supports the following features:

● 33 and 66 MHz MPC bus clock.● L2 cache, write-through only.● 1 MB socketed EEPROM/Flash.● 4 or 8 MB (64-bit wide) soldered flash. (Used for

VxWorks images.)● DRAM - 16, 32, 64, 128, 256 MB. Interleaved with

fixed size or auto-sized.● PCI bus - 32-bit address and 32-bit data transfers.

Revision 2.1 compliant (Local Bus Specification).● ISA interface - 64 KB memory and 64 KB I/O space.● A32/A24/A16 and D32/D16/D08 VME bus master/

slave support. Full system controller support. 2location monitor/signal registers.


Example Target - cont.

• Supported peripheral devices:

● 10baseT/100baseTX Ethernet controller (DEC 21140).● Single-ended fast SCSI-2 controller(NCR 53C825A).● 2 serial ports for Z85230 ESCC.● 2 serial ports (COM1 /COM2) for Super I/O ASIC.

• Unsupported features and devices:

● ECC protection for DRAM.● 64-bit extensions for PCI bus.● ISA interface - RTC and DMA controllers.● VME bus - D64 transfers and programmable DMA.● Modem control lines for Z8536 CIO.● Super I/O except for serial ports.

• Some device features are partially supported:

● MK48T59/559 chip supplies a RTC and NVRAM. NVRAM issupported but the RTC is not.

● The Z8536 CIO chip is supported as an auxilary clock for VxWorks,but modem features are not supported.

• ECC - Error Correction Code.


Example Target - Device Support

• To support target devices the following BSP libraries are

required:

● pciIomapLib.c - PCI configuration library.● ravenMpic.c - Library for Raven host bridge. Also

includes support for Winbond PIB.● universe.c - Library for Universe VME/PCI bridge.● ppcDecTimer.c - PowerPC decrementer timer library

(system clock).● ppcZ8536Timer.c - Z8536 CIO timer library

(auxiliary clock).● byteNvRam.c - Library for non-volatile RAM.

• Note device libraries which are not BSP specific:

● Ethernet, serial, SCSI, and Falcon chip.


MVME2600 Board Labels

• The MVME2600 family of boards are differentiated by

series part numbers. The format is:

● MVME260p-tcmm

• Format parameters are:

● p = processor type (3 = 603e, 4 = 604ev)● t = transition module (1 = MVME761, 2 = MVME712)● c = processor clock freq. (0 = 167 MHz, 1 = 200 MHz)● mm = ECC DRAM size (21 = 16 MB, 31 = 32 MB, ...)

• A MVME2604-1131 will use a PowerPC 604ev

processor, with clock speed of 200 MHz, 32 MB of ECC

DRAM, and require a MVME761 transition module.

• See target.txt for more infomation.

• The complete set of ECC DRAM size options are:

● mm = 21 16 MB● mm = 31 32 MB● mm = 41 64 MB● mm = 51 128 MB● mm = 61 256 MB● mm = 91 96 MB



Overview


sysHwInit()

Memory Maps

Interrupts

Timers

LAN Integration


MVME2604 Power On

• Hardware properly configured prior to power on.

• BSP is responsible for partial initialization of the

following items at power on:

● Some CPU registers.● Disable on processor cache.● Disable L2 cache.● Host bridge controller (Raven chip). *● PCI bus. *● DRAM memory controller (Falcon chip).● DRAM.● Super I/O ASIC. *

• Initializations performed by code in romInit.s.

• * - Should be done later in sysHwInit().


Hardware Configuration

• See target.txt and hardware documentation for

instructions on configuring particular options.

• Jumper configuration options:

● Configure board as system controller (VME).● Boot from either socketed EEPROM/Flash or

soldered flash (ROM controller).● L2 cache controller (automatic write through mode).

• If booting VxWorks from socketed Flash, “burn”

VxWorks into ROM and swap manufacturer’s ROM.

• If booting VxWorks from soldered Flash, follow

instructions in target.txt to download VxWorks to

socketed Flash with aid of bug ROM.

• The socketed EEPROM/Flash can be used with the native PowerPC bug

ROM or VxWorks boot ROM.

● If VxWorks is loaded into soldered Flash, developer can then set theROM jumper to either boot the PowerPC bug ROM code or VxWorks.


CPU Register Configuration

• romInit() configures appropriate CPU registers to:

● Initialize processor to a known state via the MSR.● Initialize cache.● Saving and passing boot type (warm/cold).● Initializing stack pointer for romStart().

• The processor is intialized to known state using MSR.

For example:

● Disable interrupts by clearing the EE bit.● Disable the floating point unit by clearing the FP bit.● Set processor to supervisor mode by clearing PR bit.● Configure for big-endian mode by clearing LE bit.

• All MSR bits are cleared.

• See PowerPC documents for definitions of MSR bits.

• In addition to initializing the FP bit of the MSR, the FPU is also

intialized. So the FPU is switched on, configured, and then switched off.

• MSR - Machine State Register.

• See Appendix B for romInit.s source code.


CPU Register Configuration - cont.

• All caches are first disabled (default for all VxWorks

images).

● For PowerPC 603/604 a check is performed to see ifinstruction cache should be enabled for faster FlashROM boots.

● If USER_I_CACHE_ENABLE is defined in configAll.hcache is enabled by writing to the processordependent HID0 (hardware implementation)register.

• The boot type is saved and passed to romStart() using a

general purpose register.

• The stack pointer for romStart() is intialized to

STACK_ADRS and then aligned by FRAMEBASESZ.

• The off-processor L2 cache (GLANCE) is also disabled.

• FRAMEBASESZ is defined as the minimum stack size (16 bytes) in ../h/arch/ppc/toolPpc.h.


DRAM Configuration

• Bridge/memory controller between processor bus and

memory bus (Falcon chip) must be intialized:

● Probe for correct memory size.● Probe for memory bus speed.● Initialize Falcon registers.

• Each possible memory bank size is tested.

• DRAM speed is obtained by probing, and processor bus

speed is set accordingly. Possible values: 50, 60, or 70 ns.

• Control register addresses for Falcon chip initialized in

mv2600.h

• RAM begins at address 0x00000000.


DRAM Configuration - cont.

• Table is used to provide data for size probing:

● Memory bank size.● Probe addresses.● Data patterns for probe addresses.

• There are four DRAM banks, each is probed and

intialized:

● Probes and intialization of DRAM attribute registersare done in a loop.

● Attributes are then loaded using intialized attributeregisters.

• After Falcon chip is intialized, stack is intialized and

processor jumps to romStart().

• If no DRAM present in bank, attribute register for that bank will be

intialized to zero.



Overview


sysHwInit()

Memory Maps

Interrupts

Timers

LAN Integration


Example Target - sysHwInit()

• sysHwInit() will prepare the hardware environment for

kernel activation:

● Checks CPU type.● Initializes PCI I/O space support library.● Configure bridge chips and devices on PCI bus.● Initialize some VME facilities.● Initialize two serial ports.● Access NVRAM for ethernet address and to disable

hardware watchdog.● Check for memory autosizing.

• sysHwInit() will #include driver code for board.

● Both BSP specific and generic drivers.

• Board parameters are supplied by config.h and mv2600.h.


Checking CPU Type

void sysCpuCheck (void)

• mv2600 BSP specific routine which validates CPU type.

• If appropriate CPU type is not found:

● Serial interface is initialized.● Error message is printed to console channel in polled

mode.● System is restarted.

• CPU type is set in mv2600.h:

#define CPU_TYPE ((vxPvrGet() >> 16) & 0xffff)

• vxPvrGet() reads the processor type from the PowerPC

Processor Version Register.

• CPU types checked:

● 604, 604E, 604R● 603, 603E, 603P

• System restart is performed with sysToMonitor() with

BOOT_NO_AUTOBOOT.

• Example sysHwInit() in Appendix B.


Initialization Of PCI Library

• PCI library to manage I/O mapped bus addresses must

be initialized.

• This is necessary to initialize PCI headers for all

potential PCI bus masters:

● DEC 21140 network device.● NEC 53C825 SCSI device.● Winbond PIB chip.● Raven host bridge.● Universe chip.● PMC span bridge and mezzanine card if present.

• Routine will also check for secondary instances of

devices on the PMC and initialize if present.

• Secondary instances of PCI devices defined in config.h if present:

● INCLUDE_SECONDARY_ENET● INCLUDE_SECONDARY_SCSI

• There are no secondary PCI devices for our example target.

• For discussion of PCI bus see Appendix K.


Configuration of PCI Headers -Example Target

• Standard PCI header configuration for:

● DEC 21140 Ethernet controller.● NCR 53C825 SCSI controller.● Universe PCI/VME bridge controller.

• Raven and Winbond ASICs power-up with correct

Standard PCI header values.

• Extended PCI header configuration for:

● Raven ASIC.● Winbond PIB.

• No secondary PCI devices (on PMC).

• Raven and Winbond ASICs power-up with correct Standard PCI header

values.


Initializing PCI Headers

• Initializing Standard PCI headers:

● Verify device is on bus - pciFindDevice().● Write to configuration header for device -

pciDevConfig().

• Configuration parameters for pciFindDevice() and

pciDevConfig() defined in mv2600.h.

• Initialization of extended PCI headers:

● Verify device is on bus if not previously done -pciFindDevice().

● Write to configuration header for device using BSPspecific routine.

● Configuration parameters in BSP device specificheader file.


Additional Initialization Of BridgeControllers

• Initialization of non-PCI configuration space registers is

performed for on-board bridge controllers:

● Raven ASIC.● Winbond PIB.● Universe ASIC.

• Raven ASIC - Initialize interrupt management facilities.

• Winbond PIB - Initalize interrupt management

registers.

• Universe ASIC - Map access to VMEbus space, and

intialize registers.

• Details of interrupt management will be discussed in an upcomming

section of this Appendix.


Configuration For Second PCI BusSegment Access

• Second PCI bus segment accessed through PCM Span

bridge controller.

• PCM Span bridge controller configured using

sysPciSpanConfig():

● Initializes brigde configuration header with staticparameter set using a configuration parameter arraydefined in sysLib.c

• Configuration parameters defined in config.h:

● I/O and memory base addresses.● I/O and memory space sizes.● etc.

• Note, if duplicate devices exist on primary and secondary bus segments

same driver can be used:

● Different bus segment numbers.● Use appropriate memory and I/O addresses in device driver.


VMEbus Initialization

STATUS sysUniverseInit (void)

• BSP specific routine which:

● Resets Universe chip - clears interrupts and errors.● Maps slave image windows on the Universe chip.● Initializes VMEbus latancy timer.● Clears board SYSFAIL signal.

•In addition, a routine to clear a TAS operation over the

VME bus is hooked into the VxWorks shared memory

utility library.

•Universe driver code in universe.c.

• The remainder of VME intialization occurs after kernel activation.


Bus Probe Initializtion

STATUS sysBusProbe (adrs, mode,length, pVal)

routine Address to be probed. Variable type:char *.

mode Read/write. Variable type: int.

length 1, 2, or 4 byte probe. Variable type: int.

pVal Adress of value to write or location toplace vlaue read. Variable type: char *.

• This routine is hooked to vxMemProbe():

● For PCI bus calls sysPciProbe().● For VME bus calls sysVmeProbe().● For local bus returns ERROR, native routine used.

• Code for sysPciProbe() and sysVmeProbe() are in sysLib.c.

• vxMemProbe() will be discussed in an upcomming chapter.


Serial Interface InitialIzation

void sysSerialHwInit (void)

• This routine initializes both hardware and software

control structures for on-board serial interfaces:

● Loops through intialization of device controlstructures for each channel.

● Calls routine to initialize hardware registers.

• This routine must be called before using Tornado tools

in system mode.

• This routine, as well as using a serial channel for system

level debugging is discussed in detail in an upcomming

chapter.

• sysSerialHwInit() performs intialization for:

● Z85230 SCC - 2 channels.● Super I/O - 2 channels.


NVRAM And Initialization

• On-board M48T59 chip provies:

● NVRAM● Watchdog timer.● Real-time clock (RTC).

• The six byte ethernet address for board is initilaized

using value stored in NVRAM:

● Known three byte manufacturer code intializedwhen global ethernet address variable is declared insysLib.c.

● Three byte station specific code initialized byreading NVRAM using sysNvRamGet().

• Hardware watchdog timer disabled using

sysNvRamWrite().

• sysNvRamGet() is part of the NVRAM driver code in ../src/drv/mem/byteNvRam.c.

• sysNvRamWrite() code is in sysLib.c.

• NVRAM management will be discussed in an upcomming section.


Checking For Memory Autosizing

char * sysPhysMemTop (void)

• Routine returns the size of physical memory.

• This routine will provide dynamic memory sizing if

LOCAL_MEM_AUTOSIZE is defined in config.h.

• Since Falcon chip is initialized by romInit(), this routine

will simply read and interpret its DRAM atrributes

register(s) in a loop.

● Obtain DRAM size for all four banks.● Update total physical memory size.

• If autosizing is not configured, routine returns default.

• Default physical memory size is LOCAL_MEM_SIZE.



Overview


sysHwInit()

Memory Maps

Interrupts

Timers

LAN Integration


MMU Memory Map

• sysPhysMemDesc[] specifies memory maps using:

● End-user configurable addresses and mappinglengths in config.h.

● Non-configurable map parameters in mv2600.h.

• Memory mappings are for the Extended VME memory

model (default map):

● Define EXTENDED_VME in config.h.

• End-user configurable parameters in config.h:

● LOCAL_MEM_LOCAL_ADRS● RAM_LOW_ADRS● LOCAL_MEM_SIZE● CPU_VME_WINDOW_[A32,A24,A16,REG]_SIZE

• BSP also supports a pseudo-PReP configuration (undefine

EXTENDED_VMEin config.h).

• sysPhysMemDesc[] is provided in Appendix L (diagram not to scale).


Memory Access Caveat

• PowerPC architecture limits its relative addressing to 26

bit signed offsets (+/- 32 MB):

● EABI (Embedded Application Binary Interface)standard.

● C function calls relative to the current address arerestricted to +/- 32 MB (supported by GNU).

• VxWorks images should be contained in a single 32 MB

RAM block.

• Potential issues:

● Target based loader if system memory pool largerthan 32 MB.

● ROM-resident VxWorks images.

• Note calls to C functions using a function pointer access the function

through a 32 bit register making 4GB of memory space accessible.


Bus Probes

• BSP supports hook for vxMemProbe() which allows the

following buses to be probed:

● PCI● VME● Processor

• Routine is sysBusProbe() in sysLib.c.

● Support routines which it calls also in sysLib.c.

• sysBusProbe():

● Checks address to find appropriate bus to probe.● Probes bus providing bus controller management.● If exception occurs, determine type and return error

on bus error.

• See Appendix L for sysBusProbe() routine.



Overview


sysHwInit()

Memory Maps

Interrupts

Timers

LAN Integration


Example Target - Interrupts

• Hardware management of interrupts pertormed by

interrupt controllers.

● Interrupt controllers are cascaded.

• Raven ASIC controls interrupts for:

● Primary PCI bus devices (Ethernet, SCSI)).● Secondary PCI bus devices. (Ethernet, SCSI)● Winbond PIB ASIC.● Universe chip.● Raven self generated (timer, transfer error, etc.).

• Windbond PIB controls interrupts for ISA devices:

● Z85230 SCC (COM3 and COM4).● Z8536 CIO (auxilary clock).

• The example target does not contain secondary Ethernet or SCSI

devices.

• The secondary PCI bus is accessed through the PCI Mezzanine Card

(PMC).


Example Target - Interrupts cont.

● Super I/O chip serial ports (COM1 and COM2).● Abort switch interrupt which returns control to ROM

or Flash.

• Universe chip controls VMEbus interrupts.

• The Falcon chip set handles memory interrupts.

• Processor handles self-generated interrupts

(exceptions).

• The following interrupt controllers are cascaded

through the Raven ASIC:

● Winbond PIB.● Universe.


Primary PCI Bus Interrupts

Ethernet Universe Winbond PIB SCSI

ISAInterrupts

VMEInterrupts

Raven ASIC

To PowerPCExternel Interrupt

• The four interrupt lines going into the Raven ASIC are the four PCI bus

interrupts.


Raven Interrupt Controller

• For this BSP, Raven ASIC controls all external

interrupts:

● Four primary PCI bus interrupts.● Four secondary PCI bus interrupts.● One VME mailbox interrupt.

• Raven ASIC is capable of supporting sixteen distinct

external interrupts (seven are not assigned for this BSP).

• ASIC supports 16 interrupt levels:

● Interrupt request lines: IRQ15 - IRQ0.● Levels have priorities 15 (highest) to 0 (lowest).● Priority zero disables interrupt.


Raven Interrupt Controller - cont.

• Supported IRQs and relative priorities:

IRQ Priority Source

IRQ0 8 Winbond PIB (ISA)

IRQ2 14 Ethernet

IRQ3 3 SCSI

IRQ5 10 Universe (VME)

IRQ9 7 PCI PMC INTA

IRQ10 6 (13) PCI PMC INTB

IRQ11 5 (2) PCI PMC INTC

IRQ12 4 (2) PCI PMC INTD

IRQ14 15 VME mailbox 1

• See Motorola documentation for remaining IRQ assignments.


Raven Interrupt Controller - cont.

• Manufacturer assigned interrupt numbers:

Interrupt Number Source

0x10 Winbond PIB (ISA)

0x12 PCI Ethernet

0x13 PCI SCSI

0x15 Universe ASIC (VME)

0x19 PCI PMC INTA

0x1a PCI PMC INTB

0x1b PCI PMC INTC

0x1c PCI PMC INTD

0x1e VME mailbox 1

• See Motorola documentation for remaining (unsupported) interrupt

number assignments.


Winbond Interrupt Controller

• Handles all on-board ISA interrupts. Unit consist of two

coupled Intel 82C59A interrupt controllers providing 15

distinct IRQ lines:

● First Intel 82C59A provides interrupt numbers 0 - 7,with interrupt number 2 as the cascaded interrupt tothe second Intel 82C59A.

● Second 82C59A provides interrupt numbers 8 - 15.● 15 interrupt priority levels. Due to cascading priority

levels map to vector numbers as follows (from highto low): 0x00, 0x01, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d,0x0e, 0x0f, 0x03, 0x04, 00x05, 0x06, and 0x07.

• Winbond can generate four PCI interrupts, only one is

used to request service via the Raven ASIC.


Winbond Interrupt Controller - cont.

• Winbond interrupt numbers and relative priorities:

• Interrupt priorities range from 15 (highest) to 0 (lowest).

• Devices assigned to interrupt number 0x09 will need to

be demultiplexed in software:

● System interrupt table and serial ISR will handle this.

Interrupt Number Priority Source

0x02 - ISA cascade interrupt

0x03 4 Super I/O COM1

0x04 3 Super I/O COM2

0x09 12 Auxiliary clock, serialports 3 and 4 (Z85230)


Universe Chip

• The Universe chip handles all VME interrupts.

● Configured as system arbiter via on-board jumper.

• Decouples VMEbus and PCI bus interrupters:

● Resolves timing issues - VME bus is asynchronous,PCI bus has maximum clock cycle limit forresponding to IACK transaction.

• If mv2604 board requests service from another VME

backplane card:

● Universe chip will complete IACK cycle and placeSTATUS/ID on VMEbus.

● Manage PCI bus ACK for software generatedinterrupts (configurable).


Universe Chip - cont.

• If mv2604 board receives an interrupt request:

● Universe chip completes IACK cycle and storesSTATUS/ID in dedicated register.

● Asserts PCI interrupt via the Raven chip.

• One constraint, all STATUS/IDs must be even numbers.

Least significant bit is masked for both requested and

requesting interrupt service.

● Universe will only transmit and respond to the sevenmost significant bits of a STATUS/ID.

• Note, VMEbus interrupt priority scheme cannot be

maintained as only one PCI interrupt line is connected

to the Raven chip.

• In addition to VMEbus cards, Universe chip also manages interrupts for

SYSFAIL, ACFAIL, PCI bus error, etc. See manufacturer documentation

for more details.

• Note, board can be configured to provide up to four VMEbus interrupt

levels by mapping all four PCI interrupt levels to the Universe chip.

• VME STATUS/ID is an interrupt vector number.


System Interrupt Table

• System interrupt table will support up to 256 interrupt

service routines. Interrupt number assignments:

Interrupt Numbers Source

0x00 - 0x0f ISA IRQ numbers (Winbond)

0x10 - 0x1f Raven interrupts - external devices.

0x20 - 0x23 Raven timers.

0x24 - 0x27 Raven interprocessor dispatch.

0x28 Raven dectected internal errors.

0x29 - 0x55 User defined.

0x56 - 0x5f Universe interrupts.

0x60 - 0xff User defined.


System Interrupt Table - cont.

• System interrupt table managed by Raven chip driver:

● Provides system demultiplexer on exception table.● Provides hooks for intConnect(), intEnable(), and

intDisable().

• Each interrupt controller has its own demultiplexer

routine on the system interrupt table.

• Table is an array of linked lists:

● Each array element corresponds to an interruptnumber.

● If multiple interrupt services routines are connectedto the same interrupt number, they are stored on alinked list associated with that interrupt table arrayelement.

• Interrupt numbers defined in mv2600.h.

• INUM_TO_IVEC(intNum) is defined in ../h/arch/ppc/ivPpc.h as intNum .

This is insures that the system interrupt table array elements are

interrupt numbers.


System Interrupt Table - cont.

• System interrupt table declared as:

INT_HANDLER_DESC * sysIntTbl [256];

• INT_HANDLER_DESC structure declared in ravenMpic.h:

typedef struct intHandlerDesc { VOIDFUNCPTR vec; int arg; struct intHandlerDesc * next; } INT_HANDLER_DESC;

• Structure members:

● vec - Interrupt service routine.● arg - Optional argument for ISR.● next - Link list pointer to next INT_HANDLER_DESC

for interrupt numbers with multiple ISRs.


System Interrupt Table Initialization

• System interrupt table is initialized by sysMpicInit()called by sysHwInit().

• Initializes elements of table to NULL.

• Connects system demultiplexer routine to the exception

table using excIntConnect():

● Routine is sysMpicIntHandler().

• Initializes hook routines for intArchLib:

● sysMpicIntConnect()● sysMpicIntEnable()● sysMpicIntDisable()

• Initialization and demultiplexer code in ravenMpic.c.

• MPIC - Multi-Processor Interrupt Controller. Interrupt controller on the

Raven chip.

• sysMpicInit() also initializes Raven chip interrupt controller registers.


Connecting Interrupts

• After the Wind kernel is activated intConnect() will call

sysMpicIntConnect(). Both take the same arguments.

• sysMpicIntConnect() will:

● First time it is called, connect the Winbond PIB PCIinterrupt.

● Allocate memory for an INT_HANDLER_DESCstructure, and initialize structure.

● Add element to interrupt table array. If element(s)currently exist for this interrupt number, add newlinked list node.

● Check if interrupt is for the MPIC itself, if so convertto MPIC vector and store in appropriate MPIC vectorregister.

• See Appendix H for example target code.


Connecting Interrupts - cont.

• The PCI Winbond PIB interrupt handler is the interrupt

demultiplexer for ISA interrupts managed by the

Winbond ASIC.

● Handler is installed by routine sysIbcMpicConnect()which calls intConnect() to put ISA demultiplexer onsystem interrupt table.

● Handler routine is sysIbcIntHandler().● Both handler and installation routines are in

ravenMpic.c.

• For this BSP the Universe chip VME demultiplexer

routine is placed on the system interrupt table by the

first call to intConnect():

● ISA and VME demultiplexers are installed together.

• Winbond and Universe demultiplexer routines are installed when the

system clock is connected. This will be discussed in an upcoming

chapter.

• The VME demultiplexer routine is sysUnivVmeIntr(), code is in

universe.c

• Devices with drivers (Ethernet, SCSI, SCC, etc.) will install their

interrupt routines when device is initialized.


System Interrupt Demultiplexer

• System interrupt demultipler routine,

sysMpicIntHandler(), is connect to the PowerPC’s

single external interrupt (exception 0x500).

• After WRS supplied PowerPC interrupt dispatch code

executes, system demultiplexer will:

● Read interrupt number from Raven MPIC.● Set EE bit of PowerPC MSR (allow nesting).● Call all routines from the system interrupt table

associated with interrupt number from MPIC.● Issue End Of Interrupt (EOI) code to MPIC.● Lock interrupts.

• WRS PowerPC exception code restores environment.

• Interrupts are locked by clearing EE bit in MSR to mask further

interrupts while exception code restores environment,

• The Raven MPIC will mask lower priority interrupts until EOI code is

written to MPIC.


Example Interrupt

• As and example, consider series of events when Z85230

SCC interrupt is generated:

● SCC requests interrupt service by asserting interruptnumber 0x09 on Winbond ASIC.

● Winbond registers interrupt (interrupt number 0x09),masks out lower priority interrupts (ISA level 12),and asserts PCI interrupt.

● Raven MPIC responds to PCI interrupt and masksout its lower priority interrupts (level 8 and lower).

● Raven MPIC asserts PowerPC external interrupt line.● PowerPC begins execution of WRS handler for

exception 0x500.


Example Interrupt - cont.

● WRS exception handler saves context, incrementsintCnt variable, and jumps to system interruptdemultiplexer routine.

● Demultiplexer reads interrupt number from MPIC.● Demultiplexer sets EE bit of PowerPC MSR.● Using interrupt number obtained from Raven MPIC

demultiplexer calls ISA interrupt demultiplexerroutine.

● ISA demultiplexer jumps to (first) ISR on systeminterrupt table element (interrupt number) 0x09.

● This routine is the Z8536CIO timer (auxiliary clock),which checks device and returns because devicestatus indicates it is not requesting service.

● Demultiplexer jumps to second link list element attable array element 0x09. This is the Z85230 ISR.

• For this BSP intConnect() is called for the Z8536CIO before it is called

for the Z85230 SCC.


Example Interrupt - cont.

● Z85230 ISR determines which of its two channels arerequesting service, provides service, resets Z85230,and returns.

● ISA demultiplexer re-enables Winbond interrupt andreturns.

● No more ISRs for this interrupt number, so systemdemultiplexer issues EOI code to re-enable theWinbond PCI interrupt.

● System demultiplexer locks interrupts at theprocessor level (intLock()) before returning to WRSexception handler (restore state of system).

● Return to exception handler which decrementsintCnt variable, resets MSR, and restores savedcontext.

• Demultiplexer ISR was called by exception handler with interrupts

locked, so before completing demultiplexer must lock interrupts.


Interrupt Enable and Disable

• Raven MPIC supplies hook code for intEnable()/intDisable():

● sysMpicIntEnable()/sysMpicIntDisable().● Routines take interrupt level as sole argument, and

return STATUS.

• Routines first check for legal interrupt level, and then:

● Check if level corresponds to a ISA interrupt, if soWinbond interrupt enable/disable routine is called.

● For Raven MPIC interrupt, appropriate controlregister is obtained from interrupt level, and registeris written to enable/disable interrupt.

• For enable/disable of ISA interrupts, Winbond code

determines appropriate PIC and masks interrupt.

• Code for enabling/disabling interrupts for Raven MPIC and Winbond

PIB is in ravenMpic.c.



Overview


sysHwInit()

Memory Maps

Interrupts

Timers

LAN Integration


System Clock

• Example target uses on-processor timer for the system

clock.

● Uses PowerPC 604 decrementer timer.

• Decrement register is 64 bit counter driven from main

processor clock:

● Generates exception at rollover (counts down).● System clock period set by loading appropriate

decrement count value to count register.● Decrementer does not reload period count after

exception.● Driven by processor clock.● Decrementer exception disabled by setting EE bit of

MSR.

• BSP uses lower 32 bits of decrement register.


System Clock - cont.

• System clock timer library ../src/drv/timer/ppcDecTimer.c follows template. Notes:

● System clock “ISR” installed on system exceptiontable (excectption 0x900) not system interrupt table.

● Decrementer count value computed insysClkRateSet(), but reloaded to decrementer bytimer exception handler.

● Decrementer exception handler corrects for driftbetween exception generation and reload ofdecrementer count register.

● sysClkDisable() routine prevents system clockroutine from executing by setting sysClkRunning toFALSE. Does not disable decrement exception.

● Setting EE bit in MSR (external interrupts) disablesdecrementer exception.

• Example target system clock code in Appendix I.

• Decrementer also has a timestamp driver. Follows template timestamp

driver.


Auxiliary Clock

• Target uses a Z8536CIO timer as auxiliary clock:

● Chip supports three 16 bit counter/timers.● Timer 2 used for auxiliary clock.● Driven by 5 MHz clock input.

• Auxiliary clock driver follows template:

● Code in ../src/drv/timer/ppcZ8536Timer.c● Macro INCLUDE_Z8536_AUXCLK must be defined

in config.h to identify Z8536CIO as auxiliary clock.

• If INCLUDE_Z8536_AUXCLK is defined, Z8536

initialized and ISR installed in sysHwInit2():

● Routine name sysClkIntCIO().● Routine calls sysAuxClkInt().

• Z8536CIO also has a timestamp driver. Follows template timestamp

driver.



Overview


sysHwInit()

Memory Maps

Interrupts

Timers

LAN Integration


DEC 21140 Ethernet Interface

• Environment:

● Device sits on PCI bus.● Controller is little endian.

• Software interface divided into four parts:

● Initialization of PCI configuration registers.● Providing interrupt support.● Management of I/O control registers.● Management of device and network buffers.

• BSP handles PCI configuration and interrupt support:

● Driver provides device ISRs.

• Ethernet driver handles the remaining portions of the

device software interface.

• For this example target only the primary ethernet interface (0) will be

considered.


BSP Device Support

• PCI configuration and interrupt support established in

sysHwInit().

• Call to pciDevConfig():

● Intializes device I/O space base address toPCI_IO_LN_ADRS (defined in mv2600.h).

● Enables controllers I/O facilities.

• Call to sysMpicInit():

● Initialized Raven interrupt controller.● Configures interrupt level priority (level 14 - IRQ2).● Configures interrupt number (0x12).

• Interrupt level and number (vector) defined in

mv2600.h.


Driver Initialization

• LAN device initialization activated by call to

usrNetInit() by tUsrRoot:

● All initialization performed by an driver attachroutine dcattach().

• Attach routine obtains configuration information

through its arguement list and uses it to initialize a

network interface structure.

• Fixed BSP relevant parameters in mv2600.h:

● LAN device address.● Memory base seen from PCI bus.● Device interrupt vector (number).● Device interrupt level.

• Routine usrNetInit() in ../src/config/usrNetwork.c.

• Routine dcattach() in ../config/mv2604/dec21140/dec21140.h.

• dcattach() adds initialized network interface to system list. This allows

network protocol stack and network driver to communicate.

• dcattach() routine appears in Appendix B.


Driver Initialization - cont.

• User configurable BSP relevant parameters in config.h:

● Network memory pool address (malloc option).● Network memory pool size.● Byte with for data.● Mode of operation for device.

• Attach routine also:

● Connects (demultiplexer) ISR for LAN device bycalling intConnect() initialized by BSP.

● Configures cache strategy (DMA coherency).● Initializes device link layer buffers.● Initializes device control and status registers

(including imterrupt mask registers).● Enables interrupts.

• Interrupts are enabled with a call to sysLanIntEnable() (in sysLib.c)

which simply calls the intEnable() routine intialized by BSP with the

appropriate interrupt level for the device.


Device Access

• Driver provides its own access to device registers over

PCI bus:

● Command Status Register (CSR).● Receive transmit descriptor reads and writes.

• CSR example:

#define READ_CSR(base,x) (PCISWAP(*((ULONG *)CSR((base),(x)))))

• Driver uses memory to PCI bus address translation

macro routines supplied by BSP to access memory and

I/O space:

#define PCI_TO_MEM_PHYS(pciAdrs) \ ((pciAdrs) - (pDrvCtrl->pciMemBase))

• Driver macro access routines defined in ../mv2604/dec21140/dec21140.h.

• BSP macro access routines defined in mv2600.h.

Documents

Example Target - MVME2604read.pudn.com/downloads27/sourcecode/embed/86350/Tornado...Set processor to supervisor mode by clearing PR bit. Conﬁgure for big-endian mode by clearing