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1.  Draw the schematic of the following combinational logic circuit using CMOS technology:

=   +  

Choose NMOS and PMOS widths for equal worst case rise time and fall time equal to a unit

inverter with NMOS width = 240n PMOS width = 480n (assuming  = 2).

2.  Simulate the circuit in ADE L and show waveforms to verify that it functions accordingly.

3. 

Draw the layout of your designed circuit.4.  Clear all DRC errors.

5.  Match the layout with schematic using LVS.

6.  Make an extracted view from the layout.

7.  Simulate the extracted view in ADE L and show waveforms to verify that it functions

accordingly.

Solution:

Pull Down Network (PDN):

 NMOS’s with input B and C will be in series and this brunch will be in parallel with the NMOS with

input A.

In the worst case, only one of these two paths will be ON.

If the brunch with NMOS with input A is ON, then it should have the same current carrying

capability or on-resistance as the NMOS of the unit inverter. So, it can have a width of 240n.

If the brunch with two NMOS in series is ON, then as they are in series, they have to have double the

width of NMOS of unit inverter to have same pull-down on-resistance as the NMOS of unit inverter.

So, their widths will be 480n.

(Increasing width decreases on resistance and vice versa. Doubling the width will decrease the on-

resistance and to ½ of its previous value and two of them in series will provide the same pull-down

on-resistance as unit inverter).

Pull Up Network (PUN):

PMOS’s with input B and C will be in parallel and this will be in series with the NMOS with input A.

In the worst case, only one of these two parallel paths (through A and B or through A and C) will be

ON.

For the PUN, PMOS with input A has to be ON for PUN to be ON. But either PMOS with input B or

input C will be on in the worst case.

So, in the worst case, there will be two series PMOS. So, both of them should have half the on-

resistance of the PMOS of unit inverter. We can do that by selecting PMOS widths to be double of

that of the PMOS of unit inverter, i.e., 960n. So, all the PMOS’s will have a width of 960n.

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1. 

Schematic of the circuit:

Draw Schematic as you did in Experiment 1.

2.  Simulate the circuit using appropriate stimuli and using model library gpdk090_mos.scs for

TT_s1v section.

Simulated waveforms:

3. 

 Now draw the layout of the circuit using Virtuoso Layout Editor L as you did in experiment 7.

In the Schematic Editor window, go to Launch> Layout XL. ‘Startup Option’ form will open.

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Click OK .

‘New File’ form will open. Click OK .

Virtuoso Layout Suite XL Editor window will open. First, fix the display as shown (Press E):

Take care while putting snap spacing value. For gpdk090, a snap spacing smaller than .005 will

lead to off-grid error while performing DRC.

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 Now, go to Connectivity>Generate>All From Source. ‘Generate Layout’ form will open. Go

to ‘I/O pins’ tab. Select ‘Metal1 (drw)’ in ‘Specify Default Values for all pins’ option. Click

‘Apply’. You should notice all the pin layers to change to Metal1.

Click OK . Now you will see the Layout Editor window having NMOS, PMOS and PR

Boundary.

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You may delete the bounding box (PR boundary, the blue rectangle) for now.

You must be comfortable with shortcut keys in Layout Editor window.

 K > ruler

O > Via

 P > Path R > Rectangle

Q > Edit Object Properties

 M > Move

C > Copy

U > Undo

S > Stretch

 F > Fit Display

 E > Display Options

etc.

In the Layout Editor  window, you will find pins and MOSFETs with specified width in

Schematic Editor. When you route, you will also see connections being displayed. While

routing, keep ‘DRD Notify ON’. This will display most of the errors while routing or drawing.

Use skills learned in Experiment 2 and 7 to draw a successful layout.

Layout of the circuit:

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4. 

DRC Errors Cleared:

Check and Clear DRC Errors as you did in Experiment 3.

5. 

LVS matched:

Check and Clear LVS Errors as you did in Experiment 3.

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 6.  Make an extracted view of the cell as you did in Experiment 3.

av_extracted view:

7. 

Simulated waveforms of extracted view from ADE L: