EX3 DIGITAL ELECTRONICS G________

After completing the task and studying Unit 1.6, students will be able to: (check all that apply):

Explain the concept of logic family to build digital circuits and the obsolescence curve associated to a given logic family

Explain the evolution of integrated circuits, the scales of integration (SSI, MSI, LSI, etc.) and the Moore Law

Calculate the electrical characteristics of classic digital integrated circuits, such as: logic voltage levels, noise margins, propagation delays and transition times, power dissipation; maximum frequency of operation of a digital circuit; three-state gates

Use chronograms or timing diagrams to verify circuit operation

Explain the basics of CMOS technology for realizing basic gates

Capture a diagram schematic in Proteus-VSM and run the simulation

Use the (SPICE based) virtual laboratory software Proteus-VSM1 to calculate electrical characteristics

Produce a written solution for the exercise using the instructions from:

http://epsc.upc.edu/projectes/ed/unitats/unitat_1_1/Criteris_Correccio_Exercici.pdf

Work cooperatively in a team of 3 members using the method described in:

http://epsc.upc.edu/projectes/ed/problemes/metode_resolucio_cooperativa_recomanat.pdf

Write down the most significative doubts or questions you have had while or after completing the task:

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STATEMENT:

My signature below indicates that I have (1) made equitable contribution to EX3 as a member of the group, (2) read and fully agree with the contents (i.e., results, conclusions, analyses,

1 Proteus-VSM is the proprietary software in use for the whole course: http://www.labcenter.com for having effectively a “digital circuits’ laboratory in the classroom”

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simulations) of this document, and (3) acknowledged by name anyone outside this group who assisted this learning team or any individual member in completing this document.

Today’s date: __________________

Active members Roles: (reporter, simulator, etc.)

(1) ___________________________ _______________

(2) ___________________________ _______________

(3) ___________________________ _______________

Acknowledgement of individual(s) who assisted this group in completing this document:

(1) _______________________

(2) _______________________

Study time

(in hours)

Group work

Sessions TGA, TGB

Sessions TGC

Individual Student 1

Student 2

Student 3

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Which is the internal electronic circuit of a logic gate? How is possible to integrate millions of transistors into a single chip?

(2)

Mixed signal integrated circuit which includes a built-in sensor for DIDDQ testing and a standard cell DSP with 250000 transistors as Circuit Under Test.

Technology: CMOS 0.18 m, size: 0.9 mm2

Designed by DEE engineers and fabricated by Philips

DIDDQ testing is a method able to detect defects producing small increases in leakage current on top of high background

Fig. 1 From page photograph and explanation of the Department of Electronic Engineering web site at http://www-eel.upc.edu/. You can gather more information about microelectronics through the power point presentation from Prof. Salvador Manich referenced in Unit 1.6 (http://tec.upc.es/SetCiencies/NanoElectronics.ppt )

a) Explain how the CMOS3 logic gates4 represented in Fig. 2 work. And determine which their equivalent logic symbols are. Invent a CMOS circuit for the tri-state inverter in Fig. 2d

a)

b)

2 Department of Electronic Engineering, UPC, http://www-eel.upc.edu/

3 http://www.opamp-electronics.com/tutorials/digital_theory_ch_003.htm

4 Here you can find Java aplets that will simulate the gate’s operation http://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/05-switched/40-cmos/chapter.html (HADES)

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CMOS gate

c)

d)

Fig. 2 Some internal circuitry for CMOS logic gates

Circuit shown Fig. 3 represents the internal structure of the chip MC14560 as presented by Motorola in its datasheet. Let us to use it for understanding concepts as: power dissipation; number of gate levels and transmission delays; transfer function and voltage levels; timing diagrams (a graphical representation that shows the propagation of the signals as a function of time); and other important electrical characteristics of digital circuits.

b) Find the chip datasheet somewhere in the internet and print only the 2 or 3 most significative pages which contain the circuit description and electrical characteristics. Explain the chip’s features in half a sheet.

c) With respect to the output S1, analyse the internal circuit in Fig. 3: deduce the algebraic equation, apply Boole Algebra, and obtain its truth table as a function of B1, A1 and Cin

(nothing new but copying the same EX2’s methodology).

d) Deduce the timing diagram when applying the waveforms of Fig. 4 (evidently applying results from above).

e) Redesign the function S1 = f(B1, A1, Cin) and implement a 3 level-of-gates circuit (for instance, only NAND, only NOR, NOT-AND-OR, or NOT-OR-AND)

f) Simulate both, the circuit for S1 in Fig. 3 and the one designed in e) and compare if they both have the same truth table.

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g) Apply an up-to-the-limit square waveform to determine through a graphical digital simulation the maximum frequency of operation for the S1 function in both circuits (the one in Fig. 3 and the one designed in e)).

h) Find in the internet another datasheet of a logic gate of the same CMOS 4000B family (for example the hex 4069UB inverter) and obtain the characteristics of a single gate of this technology when powered at VCC = 5V and VCC = 15V: quiescent current IDD, propagation delay time tPLH and tPHL, input voltage VIH and VIL, output voltage VOH and VOL.

i) Draw the input-output transfer function and obtain the noise margins for both supply voltages: 5V and 15V.

j) Determine the static power consumption of the MC14560 circuit represented in Fig. 3 for both supply voltages: 5V and 15V.

k) Deduce the number of gate levels of each output function of the chip: S1, S2, S3, S4, COUT

l) Using values from k) calculate the maximum frequency of operation for both supply voltages: 5V and 15V for the MC14560 chip.

m) If such an integrated circuit, the MC14560, is employed as a building block for the design of a 4-bit BCD adder and subtractor, calculate its maximum frequency of operation.

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Fig. 3 Gate network and input and output signals

Fig. 4 Gate network and input and output signals

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Fig. 5 Chip details

And, what to do, when a chip is no longer available in the market?

n) (demonstrative) The MC14560 is obsolete, thus, it is not manufactured and can not be found in the marketplace. Implement the MC14560 chip functionality into a simple programmable logic device (sPLD) GAL22V10 like the one partially reproduced in Fig. 6. See Units 1.14 and 1.15.

o) (demonstrative) Implement the MC14560 chip functionality into a ROM memory. See Unit 2.11.

Fig. 6 Partial details of the GAL22V10 simple programmable logic device (sPLD)7

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DIGITAL ELECTRONICS G________

Working plan5 for solving the exercise EX____

Explain succinctly how the cooperative group has organize the realization of the exercise: i.e., which has been your working plan; in which way has you divided the task fairly so that more or less all of you are doing a similar amount of work; how have you learned each other’s materials; what has been worked out in class time (sessions A and B) and what has been resolved in sessions C; and so on... white down also your impressions or opinions about the subject and how your group work is going6 ...

5 This document, filled before delivering the exercise, will be included in the group learning portfolio

6 Check similar documents in http://epsc.upc.edu/projectes/ed/unitats/ED_05-06_Q1_Autoavaluacio_Grup_Base.pdf, and http://epsc.upc.edu/projectes/ed/unitats/que_va_malament_al_grup.pdf

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Active members’ signatures

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