Evolution, Challenge, And Outlook of TSV 3D IC -ICEP April 2011 Keynote

Keynote at IEEE Japan ICEP, April 13-15, 2011

Evolution, Challenge, and Outlook of TSV (Through-Silicon Via) and 3D IC/Si Integration

John H. Lau Electronics & Optoelectronics Laboratory Industrial Technology Research Institute

886-3591-3390, [email protected]

ABSTRACT

3D integration consists of 3D IC packaging, 3D IC integration, and 3D Si integration. They are different and in general the TSV (through-silicon via) separates 3D IC packaging from 3D IC/Si integrations since the latter two use TSV but 3D IC packaging does not. TSV (with a new concept that every chip or interposer could have two surfaces with circuits) is the heart of 3D IC/Si integrations and is the focus of this investigation. The origin of 3D integration is presented. Also, the evolution, challenges, and outlook of 3D IC/Si integrations are discussed as well as their road maps are presented. Finally, a few generic, low-cost, and thermal-enhanced 3D IC integration system-in-packages (SiPs) with various passive TSV interposers are proposed for high performance applications.

1. INTRODUCTION The Electronics Industry has been the largest

industry since 1996 and may well reach 1.5 trillion dollars (i.e., $1.5x1012) by the end of 2011 [1, 2]. The most important invention of the Electronics Industry is, arguably the transistor (1947), which earned John Bardeen, Walter Brattain, and William Shockley the 1956 Nobel Prize in Physics. The invention of the integrated circuit (IC) by Jack Kilby in 1958 (which earned him the 2000 Nobel Prize in Physics), and six months later by Robert Noyce (who didn't share the Nobel Prize with Jack Kilby because he passed away in 1990) excited the generations of IC integrations [1]. The proposal of doubling the number of transistors on an IC chip (for minimum costs and innovations) every 24 months by Gordon Moore in 1965 (also called Moore’s law) [3] has been the most powerful driver for the development of the microelectronics industry in the past 45 years. This law emphasizes lithography scaling and integration (in 2D) of all functions on a single chip, perhaps through system-on-chip (SoC) as schematically shown in the left-hand side of Figure 1. On the other hand, the integration of all these functions can be achieved through 3D integrations such as 3D IC packaging [1], 3D IC integration [1], [2], [4] – [68], [92] – [125] and 3D Si integration [1], [2], [69] – [91], [92] – [125] as shown in Figure 2. Since 3D IC packaging is a mature technology and does not use TSVs, it is not included in this study. The 3D IC integration and 3D Si integration are shown in the right-hand side of Figure 1 and are some of the more-than-Moore. TSV is the heart of 3D Si integration and 3D IC integration [124]. Though the 1956 Nobel Laureate in Physics, William Shockley (yes, the same William Shockley who co-invented the transistor) invented TSVs more than 50 years ago [125] (Figure 3), but it was not intended for 3D Si/IC integration.

Fig. 1 Moore’s law vs. more-than-Moore [1, 2] For commercial products, even HP’s coplanar

GaAs RF MMIC (monolithic microwave integrated circuit) has been using via hole grounding technology since 1975 (Figure 4), but it was not for 3D integration. Generally, the industry consider Toshiba’s CMOS image sensor with TCVs (through chip vias) [37] as the first high-volume 3D integration product (2008), Figure 5. Straightly speaking, however, it is not a 3D integration product neither; at most it is a 2.5D IC integration product [1].

Fig. 2 Maturity of 3D integration technologies [1, 2]

MEMORY

PROCESSOR, ASIC, MCU, etc.

MEMS

OPTO

DSP

DISPLAY

Long Wiring (from A to B) in 2D SoC

A

B

Moore’s Law

PROCESSOR. ASIC, MCU, etc.

MEMORY

DISPLAYDSP

MEMS

OPTO

A

B

TSVMicro

Bumps

Thin Chip

For both cases, Thermal Management

is a big issue!

More-than-Moore

3D IC Integration 3D Si Integration2D SoC

TSV

Thin Wafers

Wafer-to-wafer bonding (Bumpless)

Very short wiring in 3D Si integration with very tiny

TSVs, thin wafers, and bumpless (no bumps!)Thermal management

is a huge problem!

TSV

Solder Bump

Chip #1

Technology

Mat

uri

ty

Basic R&D

Applied R&D

Mass Production

Commercia-lization

Die Stacking with wire

bonds

Package on

PackageStacking

(PoP)

C2C, C2W, W2W

Stacking

W2WStacking

Full swing production for memories.

Testing and yield challenges give way for package stacking

Active applied R&D is undertaken by Research Institutes. System level challenges are key. In the

phase of industrialization.

Still in upstream research, technological challenges such as yield & device architecture

are key issues.

3D IC Packaging 3D IC Integration 3D Si Integration


Fig. 3 TSV invented by William Shockley, US Patent #3,044,909, filed on October 23, 1958 and granted on July 17, 1962 In this study, TSV (with a new concept that every chip or interposer could have two surfaces with circuits) is the focus. Emphasis is placed on the 3D IC integration, especially the interposer (both active and passive) technologies and their roadmaps. The origin of 3D integration is also briefly presented.

Fig. 4 HP’s high volume product (MMIC) with via through IC chip (1975)

Fig. 5 Toshiba’s CMOS image sensor with TCV (converted from wire bond to flip chip) (2008) [37, 38]

Fig. 6 The evolution of 3D integration (excluding 3D IC Packaging) [1] 2. THE ORIGIN OF 3D INTEGRATION Again, since the focus of this study is TSV, thus 3D IC packaging is out of the scope and will not be discussed. 3D integration is a very old idea [1] which consists of two or more layers of active electronic components that are integrated vertically through TSV (it used to be called vertical interconnection) into a single circuit. It was trigged by the advance of the silicon-on-insulator (SOI) technology first reported by Gat and his colleagues more than 30 years ago [126], when semiconductor people thought Moore’s law could be hitting the wall by the 1990s. Of course, the fact showed otherwise.

Figure 6 shows the evolution of 3D integration. In the early 80s, there were two schools of thought [69, 70]. One is to stack up the chips with TSV and flip-chip [127, 128] solder bumps (3D IC integration), and the other is to stack up the wafers with TSV alone, i.e., bumpless (3D Si integration), as shown in Figure 1. The advantages of 3D Si integration over 3D IC integration are: (1) better electrical performance, (2) less power, (3) lower profile, (4) less weight, and (5) higher throughput. In general, industry favored the 3D Si integration. 3. OVERVIEW, CHANLLEGES, AND OUTLOOK OF 3D Si INTEGRATION

Fig. 7 Japan 3D Si integration roadmap [69] In the early 80s, the Japan MITI (Ministry of International Trade and Industry) funded and directed

Co-planar GaAs RF MMIC (monolithic microwave IC)

Via through IC chip

Via through IC chip

Via-hole grounding Technology

Optical Lens

Wire Bonds

IR Cut Filter

Sensor Chip

IR Cut Filter

Lens Holder

Glass

Through Chip Via (TCV)

Board

Solder Balls

Lens Holder

Sensor Chip

Optical Lens

Through Chip Via (TCV)

3D IC Integration with microbumps and thin chips

(has been favored since 2000)

The origin of 3D Integration (1980)3D integration was trigged by the silicon-on-insulator (SOI) technology 30 years

ago, when people thought Moore’s law could be hitting the wall by the 1990s.

3D Si Integration(was favored in 1980)

Long way to go!

No sight in Volume Production in the

next 10 years

Stacking up wafers with TSVs for electrical feed through. Bumpless!

Need Ecosystem, EDA, Technology

The right way to go and compete with Moore’s law

Memory-chips

Stacking

Active Interposers (Memory/Logic +

CPU/Logic)

Passive Interposers (2.5D & 3D)

Need Ecosystem, EDA, and Business models

Cost issues and Competing technology

Will be used the most in the next

10 years

Because of the disappointment of 3D Si Integration, and using thin chips and microbumps

3D IC Integration (was rejected in 1980)

Stacking up the chips with TSVs and solder bumps

The invention of TSV (1958)

Shockley's invention was

not meant for 3D integration

A boost (1985) by Richard Feynman

Go 3D instead of all on a surface of a chip!

Nu

mb

er o

f Ele

me

nts

X F

un

cti

on

/Ch

ip

Japan 3D Si Integration Roadmap

Basic Research

Volume Production

Year

3D

2D VLSI

1970 1980 1990 2000

100

102

10

4

10

6

10

8

10

10

Development for Application


Fig. 8 3D Si integration: (a) IBM/RPI’s Cu-to-Cu bonding; [71-73] (b) NIMS/AIST/Toshiba/ University of Tokyo’s Cu-to-Cu bonding [74-80] the 3D Research Committee of the 3D Si integration project. Their roadmap is shown in Figure 7 [69]. It was announced that: (1) functional models have been fabricated in stacked double or triple active layers demonstrating the concept of a future 3D structure; (2) the basic technology for stacking active layers will be developed before 1990; and (3) with this technology, various kinds of circuits such as high-packing density memory, high-speed logic or image processors are expected to be designed and realized in a 3D single chip between 1990 and 2000. History showed that the technology did not materialize within the timeframe stated by the Project.

Basically, wafer-to-wafer (W2W) is the only way to perform the bonding operation for 3D Si integration and yield is a big issue (e.g., some bad chips are forced to bond on the good chips). In addition, the absence of (or an infinitesimal) gap between wafers and thermal management is a huge problem. Furthermore, the requirements of the bonding conditions, such as the surface cleanness, surface flatness, and the class of clean room for 3D Si integration are very high.

There are at least two different W2W bonding methods for 3D Si integration, namely, Cu-to-Cu bonding and oxide-to-oxide bonding, as shown in Figures 8 and 9, respectively. Figure 8a shows a high-quality bonding interface by IBM and RPI [71 - 73]. Before bonding, the Cu interconnects (pads) are fabricated with the standard BEOL (back end of line) damascene process, followed by the oxide CMP (chemical mechanical polish) processed (oxide touch-up) to recess the oxide level to 40 nm lower than the Cu surface. The bonding temperature is ramped up to 400°C. Figure 8b shows a cross-section of the interface between the bumpless Cu-to-Cu electrodes (pads) given by the NIMS/AIST/Toshiba/University of Tokyo [74] – [80].

Figure 9a shows a cross section of MIT’s oxide-to-oxide bonding structure of three-layer 3D (ring oscillator) bonded at 275°C [81] – [87]. It can be seen that: (1) the layers are bonded and interconnected with W-plugs, (2) the conventional inter level connections are in the bottom two layers, and (3) the

Fig. 9 3D Si integration: (a) MIT’s oxide-to-oxide bonding; [81-87] (b) Leti/Freescale/ STMicroelectronics’ oxide-to-oxide bonding [88-90] 3D vias are located in the isolation (field) region between transistors. Figure 9b shows Leti/Freescale/ STMicroelectronics’ dielectric-to-dielectric bonding structure of two device layers bonded at ~400°C [88] - [90]. It can be seen that: (a) first, a metal level is formed on a 200 mm bulk wafer and SOI wafer; next, these wafers are bonded face to face, and then the bulk silicon of the SOI wafer is removed down to the BOX layer; (b) the ~1.5µm interstrata vias (ISVs) are formed, which make contact from upper strata to lower strata; (c) a metal layer is formed at the top of the back side of the SOI wafer, and (d) this ISV makes contact with both the top and bottom metal layers.

Tremendous of work still need to be done before products can be manufactured using the 3D Si integration technology. Besides thermal management, vias formation, thin-wafer handling, more research and development efforts should also be placed on areas such as: cost reduction, design and process parameter optimization, bonding environment, W2W bonding alignment, wafer distortion, wafer bow (warpage), inspection and testing, contact performance, contact integrality, contact reliability, and manufacturing yield issues. In addition, packaging the 3D Si integration module systematically and reliably to the next level of interconnect pose another great challenge.

Besides technology issues, the EDA (electronic design automation), which is the soul of 3D Si integration [124] is far from ready. Urgently, the industry needs an ecosystem (e.g., standard and infrastructure) for 3D Si integration. Then, the EDA can write the design, simulation, analysis & verification, manufacturing preparation, and test software with the following guidelines.

1. Design automation from high level description to layout generation/optimization.

2. Verification all dedicated and tuned to 3D integration.

(a)

(b)

(b)

(a)


3. Addressing the 3rd dimension not like a packaging bumping.

4. Addressing the true 3rd dimension, with partitioning, floor planning, automatic placing and routing.

5. Full extraction with the 3rd dimension, full 3D DRC (design rule checks), 3D LVS (layout vs. schematic) with all tiers together in a same database.

6. The 3D integrations have then to be seen as a whole system distributed in several tiers, and not just a stack of predefined chips.

In the next 10 years, the industry will be hard-pressed for high volume products with the 3D Si integration technology, except for very niche applications (Figure 6). However, it should be noted and emphasized that 3D Si integration is the right way to go and compete with Moore’s law. The industry should stride to make this happens! 4. OVERVIEW, CHALLENGES, AND OUTLOOK OF 3D IC INTEGRATION Unlike 3D Si integration, 3D IC Integration (as shown in Figure 1) stacks up whatever Moore law’s IC chips in the 3rd dimension with TSVs, thin chips and microbumps [1] to achieve performance, small form factor, and eventually low cost. Today, unlike 30 years ago, most people favor 3D IC integration. Basically, there are two groups of 3D IC integrations. One is memory-chip stacking and the other is interposers (active and passive) as shown in Figures 6 and 10.

Fig. 10 3D IC integration: Memory-chip stacking (L), Active Interposer (M), Passive Interposer (R) 4A. Memory-Chip Stacking (3D IC Integration) [1]

The left-hand photo of Figure 10 (provided by Samsung) shows the simplest example of memory-chip stacking. It can be seen that even with eight chips, their total thickness (560μm) is still less than the thickness of an ordinary chip. Figure 11 shows another example, a 32-chip stacked by Samsung. It can be seen that 32 memory chips, each 20 µm thick, are stacked up with microbumps and communicated with Cu-filled TSVs. Unfortunately, due to cost issue and competing technologies, e.g., Au/Cu wire bonding, memory-chip stacking is not in volume production today.

Fig. 11 Samsung’s 32-memory chips stacking with microbumps (each chip is 20μm thick) [50] It should be pointed out that for this kind of high-volume products, 3D Si integration would be the perfect technology for its manufacturing. Hopefully, 10 years from now, when the ecosystem (e.g., standards and infrastructures), EDA, technology, testing, and the reliability of 3D Si integration are ready, then memory-chip stacking could be produced at higher throughputs and lower costs. 4B. Active Interposers (3D IC Integration)

(a)

(b)

(c) Fig. 12 Active interposers: (a) Wide I/O Memory/ Logic + CPU/Logic [14]; (b) Wide I/O DRAM by Samsung [50]; (c) Wide I/O DRAM by Micron.

3D IC IntegrationActive Interposer

(TSVs in active chips)Passive Interposer

(No TSVs in active chips)

PROCESSOR. ASIC, MCU, etc.

MEMORY

DISPLAY

DSP

MEMS

OPTO

A

B

TSV

Micro Bump

Thin Chip

TSV/RDL/IPD Passive Interposer

Micro Bump

TSV

8@50μm thick 2Gb Chips (16Gb)

Micro bump

TSV

Memory-Chip Stacking (TSVs in active chips)

TSV/RDL/IPD Passive Interposer

3D IC Integration with Passive Interposer

2.5D IC Integration with Passive Interposer

560μ

m

CPU/Logic

Memory

TSV

PCB

Cu filled TSV

Microbumpsbetween

Memory and Logic

Memory Si chip on top

Logic Si chip at the bottom

Active Interposer

Active Interposer


TSVs, in addition to being used for stacking just memory chips, they can also be used as an active interposers (the mid-schematic of Figure 10) such as logics, microprocessors, wide I/O memory [14], and wide I/O DRAM (dynamic random access memory) [50]. Figure 12(a) demonstrates the ultimate goal of a high power, pin-count and fine-pitch CPU/Logic and a maximum bandwidth with low power memory stacked together to address the memory bandwidth challenge [14, 129]. In this case, the CPU (or Logic) with TSVs acts like an active TSV interposer. Figure 12(b) shows a wide I/O DRAM (8X) proposed by Samsung [50]. In this case, the Master chip is the active interposer. Figure 12(c) shows a wide I/O DRAM (20X) proposed by Micron, where the Logic is the active interposer [http://news.cnet.com/8301-13924_3-20031380-64.html (February 10, 2011 1:51 PM PST)].

Due to the very high device density and the complexity of the circuits (see Figure 13 for example) [130] on the CPU and memory, however, finding places/spaces to “drill” holes (TSVs) either by via-middle or via-last processes are very difficult.

Fig. 13 The cross section of a 65nm Cu/low-k chip with 11,000 I/Os by Chartered Semiconductor (2006) [10] Additionally, the CPU and memory chip sizes and number of pin-outs may differ. Forcing them to attach reduces design freedom and could compromise functionality. Longer routings may be needed in the TSVed CPU and memory chip, which affects performance. Most importantly, the required TSV manufacturing yield is too high (>99.99%) for the CPU to bear additional costs due to yield loss [9].

Also, the yield lost due to front/back-side metallization, wafer temporary bonding and de-bonding, and wafer thinning of the CPU wafer increases the hidden costs [9]. Thus, a passive TSV interposer connecting the memory and CPU (without any TSVs) in certain 3D configurations could be cost-effective in resolving these issues, which will be

discussed in Sections (4C) and (4D). Thermal management is critical to 3D IC

integration (with active interposer) because 3D circuits increase the total power generated per unit surface area; chips in the 3D stack may overheat if proper and adequate cooling is not provided; the space between the 3D stack may be too small for cooling channels; and thin chips may create extreme conditions for on-chip hot spots. For example, Figure 14 shows the temperature maps on a chip for various chip thicknesses. It can be seen that the heat on the chip surface is well dissipated for typical chip thicknesses of 200μm subjected to a generated power of 0.2W. For the 200-μm-thick chip, the temperature distribution is almost uniform and equal to 35°C. However, the hot-spot temperature on the chip increases to 69°C (0.2W power) if the chip thickness is reduced to 10μm and the hot-spot area is clearly shown. Thus, low-cost and effective thermal management solutions are desperately needed for widespread use of 3D IC integration SiPs [1, 2, 4, 8, 15, 16, 19, 20, 24, 31]. Again, with a passive TSV interposer, the thermal

Fig. 14 Effect of chip thickness on temperature distribution: - hot spot temperature [8] management of memory/logic + CPU/logic is easier and more effective, which will be discussed in Sections (4C) and (4D). Why not dig holes on the active chips now? Besides the technology issues mentioned in Section (4B), the EDA and testing tools for 3D IC integration are not ready. Because the ecosystem such as standards and infrastructures of 3D IC integration does not yet exist, this area cannot be worked on seriously and with full-force. It should be noted that, besides they are different, the EDA for 3D IC integration is much simpler and easier to build and qualify than for 3D Si integration. However, it should be emphasized that the EDA for 3D Si integration (once it is ready) should be more attractive, useful, and acceptable because it is built for the true 3rd dimension right from the very beginning as shown in Section (3) and not from the predefined chips like 3D IC integration.

Actually, the biggest issue for system houses on 3D IC integration with the active interposer is their

65nm Cu/low-k Chip by Chartered Semiconductor (2006) to show the tiny vias.

Many tiny vias filled with W or Cu.

Besides the tiny devices such as transistors (which cannot beseen in this SEM image), there are many tiny vias on a chip.They are connected to devices (e.g., 4 vias for each transistor)to build the first metal (M1) layer. Today, the number of thesetiny vias, for many chips, already exceeds the world populationof over 7 billion. One of the core competences and majorbusinesses of foundries is to make these tiny vias. They arenot the same TSV for 3D IC integration.

9 low-k layers

Cu-structure

Low-k layers, closest to

chip surface

Low-k material

t=10µm t=25µm t=50µm

t=100µm t=200µm Chip Size: 5mmx5mm

Chip Power: 0.2W/Chip

Chip Heat Source Area:

0.2mmx0.2mm


“business model”. Most of these companies buy the chips from different sources and want them to be “bullet-proved” before they were shipped to SATS (semiconductor assembly and test services). Forcing two chips from different sources together into “one chip” is not acceptable to the system houses because if something wrong, they don’t know who is responsible for finding the root causes and fixing the problem so they can continue shipping their products.

By using a passive interposer to integrate a few “bullet-proved” chips together (like a multichip module) is what the system houses want and used to. Thus, passive interposer becomes the most effective 3D IC integrator! It could be very low cost because we don’t have to dig and fill the holes on the active dies. Also, we don’t have to thin and metalize the active dies. Furthermore, we don’t have to temporary bonding and de-bonding of a supporting wafer to the active wafers. Let the passive interposer be the workhorse of our 3D IC integration SiP before the 3D Si integration time comes!

Fig. 15 (a) Conventional face-down PBGA; (b) Face-down PBGA with a passive TSV interposer (2.5D IC integration) [10, 11] 4C. Passive Interposers (2.5D IC Integration)

TSVs can also be used in a passive interposer to support ultra-fine pitch, high pin-count, wide bandwidth, and high-density Moore’s law IC chips as shown in the right-hand side of Figure 10. For example, Figure 15a shows a conventional face-down plastic ball grid array (PBGA) package, in which the chip is supported by a high-density organic-substrate with build-up layers connected through microvias [131]. As the chip gets bigger and its pitch gets smaller, the organic-substrate can no longer support the chip. Hence, an intermediate substrate is needed (e.g., the passive TSV interposer) to redistribute the array of fine-pitch pads on the chip to fewer and relatively larger pitch pads on a simpler and thinner organic substrate (Figure 15b) to achieve a smaller footprint with better performance. The packaging system in

Fig. 16 Xilinx’s stacked silicon interconnection technology for Wide I/O Interface FPGA (2.5D IC integration with sample) [66] Figure 15b is called 2.5D IC integration SiPs.

In the past few years, many significant 2.5D IC integration papers have been published by, e.g., IBM, IMEC, Fraunhofer IZM, Leti, AIST, KAIST, ALLVIA, Technical Univ. of Berlin, Nokia, ASE, NEC-Schott, STATSChipPAC, UTAC, IPDiA, DNP, Shinko, GIT, IME, Xilinx, etc. For example, Figure 16 [66] shows Xilinx’s stacked silicon interconnection technology, which provides breakthrough field-programmable gate array (FPGA) capacity, bandwidth, and power efficiency. It can be seen that the four 28nm FPGA die slices are supported by a coarse-pitch TSV interposer with 4 redistribution layers (RDLs), which provides the connections between the package substrate and the FPGA for the parallel and serial I/O, power/ground, clocking, configuration signals, etc. According to Xilinx, this stacked silicon interconnect technology provides multi-Terabit-per-second die-to-die bandwidth through more than 10,000 device-scale connections. It should be emphasized that there are no TSVs in the active FPGA device chips! The passive TSV interposer is the workhorse of the system.

Fig. 17 TSV filled with carbon nanotube (CNT) [118, 119]

Solder balls

Heat spreader

Ordinary solder bumps

Ordinary underfill

Adhesive

Stiffener

Thermal interface material (TIM)

Chip

BT substrate with RDL

(a)

TSV Interposer with Redistribution layer (RDL) & integrated

passive devices (IPD)

Simple organic

substrate

Stiffenerring

AdhesiveTIMHeat Spreader

Chip

Ordinary solder bumps

Special underfill

(b)

Solder balls

Microbumps

Ordinary underfill PCB

PCB

FPGA Die Slices

Silicon Interposer

Package

Signal Line

SiSiSi

TSVTSV Signal Line

SiO2SiO2

SW-CNT bundle


Most passive interposers reported are made by silicon and filled with copper. However, glass interposers have been reported by IZM [61] and GIT [54, 55] for potential niche applications. Also, other filling materials such as tungsten, polymer, solder, and carbon nanotube (CNT) have been report. Figure 17 [118, 119] schematically shows TSVs filled with CNT. 4D. Passive Interposers (3D IC Integration)

Most passive interposers reported in the literatures are 2.5D IC integration SiPs, i.e., the interposer supports chips (without TSVs) only on its top surface as schematically shown in the upper right-hand side of Figure 10. The 3D IC integration with passive interposer is shown in the lower right-hand side of Figure 10, which supports chips on its top and bottom surfaces. In this study, a few low-cost and thermal enhanced 3D IC integration SiPs with a passive TSV interposer are presented for high pin-count and/or high-performance applications. There are no TSVs in any of the active IC chips. 4D.1 Design Philosophy

The present design philosophy addresses the electronic packaging of 3D IC integration with a passive TSV interposer with RDLs and/or IPDs (integrated passive devices) for high-power, high-performance, high pin-count, ultra fine-pitch, small real-estate, and low-cost applications. To achieve this, the design uses chip-to-chip interconnections through a passive TSV interposer in a 3D IC integration SiP format. Rather than “digging holes” (TSVs) on active (devices) chips, existing Moore’s law chips are stacked with a passive TSV interposer to:

a) Provide vertical (as well as horizontal) electrical feed through interconnections.

b) Perform redistributions (to fan out high pin-out and ultra fine-pitch circuitries).

c) Provide decoupling (to enhance the electrical performance).

d) Connect to the next level of interconnects (e.g., the package substrate with fewer pin-outs and coarse pitches).

e) Construct a cost-effective thermal management system (e.g., heat spreader/sink).

4D.2 Example No. 1 The 3D IC integration SiP shown in Figure 12 can be redesigned with a TSV/RDL/IPD passive interposer as shown in Figure 18. In this case; (1) no new EDA is needed; (2) there are no TSVs in the chips; and (3) the heat from the high power chips can be removed from their back sides. ; and (4) the solder joint reliability is not an issue because it is a standard package and has been used for more than 15 years. The outlook (package) of this proposed 3D IC integration SiP is very attractive to integrated device manufactures (IDMs), original equipment manufacturers (OEMs), and electronics manufacturing services (EMS) because

it is a standard face-down PBGA package and has been used by the electronic industry for more than 15 years.

Fig. 18 TSV passive interposer supporting high-power chips (e.g., microprocessor and logic) on its top side and low-power chips (e.g., memory) on its bottom side. Modified from [11, 34] 4D.3 Example No. 2 If the memory chips are too thick to fit in the space between the interposer and organic substrate and back-grinding is too expensive for active chips, then the design shown in Figure 19 could be a solution. The interposer consists of a cavity in its bottom-side, which can be easily fabricated by either lasers or wet anisotropic etches, for example the KOH (potassium hydroxide) solution as report in [7].

Fig. 19 TSV interposer supporting high-power chips on its top side and low-power chips on its bottom side with a cavity. Modified from [11, 34] 4D.4 Example No. 3

The 3D IC integration SiP as shown in Figure 20) features a silicon interposer with high-density TSVs, RDLs, and IPDs that connect various Moore’s chips with pads that have different pitches, sizes, and locations. A simple, organic substrate (either full or with cavity) with standard (in size and pitch) solder balls for PCB assembly supports the passive interposer. All the high-power chips such as the micro-processor unit (MPU), graphic processor unit (GPU), application specific IC (ASIC), digital signal processor (DSP), micro-controller unit (MCU), radio frequency (RF),

Microprocessor/ ASIC

TSV Interposer with RDL & IPD Simple

organic substrate

Stiffener ring

Adhesive

TIM

Heat Spreader + Sink (if needed)Microbumps

Ordinary solder bumps Solder balls

PCBMemory

Special underfills are needed between the Cu-filled interposer and all the chips. Ordinary underfills are needed between the interposer and the organic substrate.

Microprocessor/ ASIC

Stiffener ring

Adhesive

TIM

Heat Spreader + Sink (if needed)

Microbumps

TSV /RDL/IPD interposer

with a cavity Simple organic

substrate

Ordinary solder bumps Solder balls

PCBSpecial underfills are needed between the Cu-filled interposer and all the chips. Ordinary underfills are needed between the interposer and the organic substrate.


Fig. 20 Passive TSV interposer with RDL and IPD supporting high-power chips on its top-side and low-power chips at its bottom-side. The organic substrate is with a cavity [11, 34] and high-power memory chips are on top of the TSV interposer in a flip-chip format [127, 128] so that the backside of these chips can be attached to a heat spreader via a thermal interface material (TIM). Just like Examples 1, 2, and 3, most of the heat from the high-power chips can be dissipated through the heat spreader (with a heat sink if it is necessary). All low-power chips — MEMS, OMEMS, CMOS image sensors, and memory chips are at the bottom-side of the interposer with either flip-chip or wire-bond formats or both. Just like Examples 1, 2, and 3, a ring-stiffener connecting the organic substrate and the heat spreader provides adequate standoff for 3D IC integration with the passive interposer and to support the heat spreader with or without the heat sink. Underfill encapsulants are needed between the TSV interposer and the high- and low-power flip chips, and between the TSV interposer and the organic substrate. However, underfill is not needed between the 3D IC integration SiP and the PCB. For wire bonding chips, encapsulants may be needed.

The outlook (package) of this proposed 3D IC integration SiP has been used by the electronic industry for more than 15 years [132]. It’s not only effective in thermal management [133] – [139], but its solder joints are very reliable [140] – [143]. Therefore, in conjunction with the proper design of the high-power and low-power chips above/below the passive TSV/RDL/IPD interposer inside the package, a cost-effective, 3D IC integration SiP that displays high electrical and thermal performance can be achieved and manufactured.

The thickness of the proposed TSV/RDL/IPD passive interposer should be ≤ 200µm, however, the thinner the better. Thus thin-wafer handling methods, e.g., [22, 30, 104, 105, 107, 109] are required for the passivation, metallization and/or wafer bumping processes. Fortunately, by using the passive interposer, thin-wafer handling is not necessary for the TSV-less

high- and low-power IC chips. It should be noted that, recently, in order to eliminate thin-wafer handling (save manufacturing cost), interposer thicknesses ≧ 300µm are used provided the electrical requirements are met.

Fig. 21 3D IC integration SiP consists of a series of TSV/RDL/IPD interposers with embedded fluidic channels to support multiple Moore’s law chips without any TSVs 4D.5 Example No. 4

The 3D IC integration SiP shown in Figure 20 cannot be stacked into 3D because of the heat sink. Also, there may not be the luxury to separate all the high-power chips (on top) from the low-power chips (at the bottom) of the interposer. Figures 21 and 22 show a new 3D IC integration SiP design which is able to be stacked up in 3D and the chips can be randomly arranged on top or bottom of the interposer.

Fig. 22 TSV/RDL/IPD interposer with embedded fluidic channels supporting all kinds of chips on its top and bottom sides

The basic unit is shown in Figure 21, which consists of the TSV/RDL/IPD interposer with embedded fluidic channels. This interposer is fabricated by bonding two silicon wafers together by wafer-to-wafer (W2W) bonding, and an optimized liquid cooling channel structure is embedded in between the chips, as shown in Figure 23. Silicon is chosen as interposer material because it is a suitable material for the integration of both electrical and fluidic structures in the same substrate with microfabrication process. The difference between these

TSV/RDL/IPD Interposer with

embedded fluidic channels to

support multiple Moore’s law

chips without any TSVs

Substrate

PCB

MicrobumpsMicro-channelsTSVs

Solder bumps

IPD RDL

Moore’s law chips

TSV/RDL/IPD interposer with embedded fluidic channels to support Moore’s law chips with no TSVs


Fig. 23 Interposer (carrier) with TSVs for electrical feed through and fluidic microchannels for thermal management [1, 2]

Fig. 24 Fabricated TSV and embedded fluidic microchannel carrier (interposer). The TSV, sealing ring for TSVs, sealing ring for micochannels. Au20Sn solder bumps and Ti/Cu/Ni/Au UBMs [1,2] two chips is that the bottom Si chip does not have any outlets. TSVs can be designed along the periphery of the carrier (interposer). After W2W bonding, electrical interconnection through the carrier is made by the TSV with on-wall metallization (in this case, the copper filling may not be necessary). The fluidic channels are connected out through the inlet and outlet. There are sealing rings (the solder is Au20Sn and the UBM is TiCuNiAu) around both the fluidic path and the individual TSV to isolate the fluid from the electrical interconnection as shown in Figure 24 [15, 16, 24]. 5. SUMMARY AND RECOMMENDATIONS

A few generic, low-cost and thermal-enhanced 3D IC integration SiPs with various passive interposers have been presented for high performance applications. Also, the origin of 3D integration and the overview, challenges, and outlook of 3D Si/IC integrations have been presented and discussed. Some important results

Fig. 25 3D IC/Si integration roadmap (excluding memory chips stacking) modified from [11] and recommendation are summarized here. (1) A roadmap for the passive and active interposers is

shown in Figure 25. In the next 10 years, most TSVs will be fabricated on passive interposers. For active interposers, we have to wait for the ecosystem and EDA, except for niche applications such as CMOS image sensor (CIS) [37], 3D MEMS [2, 6] and 3D LED [1, 7]. Even for these products, some (e.g., CIS) are going to be replaced by the passive interposer, e.g., [39, 40].

(2) Because of System Houses’ business model, it would be hard-pressed for them to use the active interposers, e.g., memory/logic + CPU/logic. An “architect + broker” system helps!

(3) Passive interposer is the most cost-effective 3D IC integrator. It is not only for substrates, carriers, but also thermal management tools. Let the passive interposer be the workhorse of 3D IC integration SiPs!

(4) With the passive interposer, it is not necessary to ‘dig’ holes on the active chips. In fact, try to avoid making TSVs in the active chips.

(5) The passive interposer provides flexible coupling for whatever Moore’s law chips are available and/or necessary, and enhances the functionality and possibly the routings.

(6) With the passive interposer, wafer thinning and thin-wafer handling costs (for the interposer) are lower because these are not needed for the active chips and thus adds no cost due to yield loss.

(7) For many products, their passive interposers can be ≧300μm and still meet the electrical requirements. In these cases, thin wafer handling is not needed.

(8) With the passive interposer, just about all the thermal problems of 3D IC integration can be managed. A few examples have been proposed in Section 4D.

(9) With the passive interposer, the TSV manufacturing cost is lower because the requirement of TSV manufacturing yield is too high (>99.99%) for the active chips to bear additional costs due to TSV manufacturing yield loss.

(10) With the passive interposer, large SoC dies can be replaced by a few smaller pieces of dies (like

Fluidic inlet

Fluidic outlet TSV Fluidic

channel

TSV

Fluidic inlet

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Top-side Bottom-side

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CIS with TSV (2.5D)

CIS with TSV and DSP

2020201420122008 2016 2018

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MEMS on ASIC with TSV

Memory/Logic + CPU/Logic with TSV

Chip on TSV/RDL/IPD

interposer (2.5D)

2.5D IC integration (with TSV/RDL/IPD interposer),

Multichip

3D IC integration (with TSV/RDL/IPD interposer),

Multichip

Multi-LEDs on driver chip with TSV

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Xilinx’s FPGA) with much higher manufacturing yield and save cost!

(11) With passive interposers, leaning from Xilinx: (a) the state-of-the-art technology (≦28nm) is only focused/applied on the device chips with billions of tiny vias, which Foundries can do best; (b) all the TSVs and RDLs are fabricated on a piece of “dummy” silicon with the most mature technology (≧65nm), which can be done by the backend (or a packaging assembly and test house) with much less expensive materials, processes, equipments and personals; and (c) these lead to substantial cost saving.

(12) 3D Si integration is the right way to go and compete with Moore’s law. However, it is still a long way to go. Some technology R&D topics have been proposed in Section 3. Also, some guidelines on building the EDA have been recommended. The industry should immediately build an ecosystem incorporating standards and infrastructures so that EDA vendors can create and qualify the software for design, simulation, analysis & verification, manufacturing preparation, and test for 3D Si integration and stride to make it happens! Hopefully, (a) 10 years from now (Figure 25), at least the memory chips stacking could be manufactured at lower costs and higher throughputs by using the 3D Si integration technology, i.e., there are no bumps between the memory chips, and (b) 15 years from now, the wide I/O heterogeneous structures such as wide I/O DRAM, wide I/O interface, and wide I/O memory could be manufactured at high volume with the 3D Si integration technology. These will be performed by Foundries. The backend or packaging assembly and test houses receive the stacked wafers (without any bumps) and will go through the routine tasks such as dicing, packaging, and testing. In that case 100X is possible!.

6. ACKNOWLEDGEMENTS The author would like to thank Dr. Ian Yi-Jen Chan

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