Evidences for vertical charge dipole formation in charge-trapping memories and itsimpact on reliabilityAndrea Padovani, Antonio Arreghini, Luca Vandelli, Luca Larcher, Geert Van den bosch, and Jan Van Houdt Citation: Applied Physics Letters 101, 053505 (2012); doi: 10.1063/1.4740255 View online: http://dx.doi.org/10.1063/1.4740255 View Table of Contents: http://scitation.aip.org/content/aip/journal/apl/101/5?ver=pdfcov Published by the AIP Publishing Articles you may be interested in Charge trapping in alumina and its impact on the operation of metal-alumina-nitride-oxide-silicon memories:Experiments and simulations J. Appl. Phys. 110, 014505 (2011); 10.1063/1.3602999 Highly scaled charge-trapping layer of ZrON nonvolatile memory device with good retention Appl. Phys. Lett. 97, 213504 (2010); 10.1063/1.3522890 Device characteristics of HfON charge-trap layer nonvolatile memory J. Vac. Sci. Technol. B 28, 1005 (2010); 10.1116/1.3481140 Charge-trapping memory cell of SiO 2 ∕ SiN ∕ high k dielectric Al 2 O 3 with TaN metal gate for suppressingbackward-tunneling effect Appl. Phys. Lett. 87, 073510 (2005); 10.1063/1.2010607 Reliability of metal–oxide–semiconductor capacitors on nitrogen implanted 4H -silicon carbide J. Appl. Phys. 84, 2943 (1998); 10.1063/1.368399

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Evidences for vertical charge dipole formation in charge-trapping memoriesand its impact on reliability

Andrea Padovani,1,2 Antonio Arreghini,3 Luca Vandelli,1 Luca Larcher,1

Geert Van den bosch,3 and Jan Van Houdt31DISMI, Universit�a di Modena e Reggio Emilia, 42122 Reggio Emilia, Italy2INTERMECH Center, Reggio Emilia (RE), Italy3IMEC, 3001 Leuven, Belgium

(Received 16 January 2012; accepted 17 July 2012; published online 1 August 2012)

We demonstrate the formation of a vertical charge dipole in the nitride layer of TaN/Al2O3/Si3N4/

SiO2/Si memories and use dedicated experiments and device simulations to investigate its

dependence on program and erase conditions. We show that the polarity of the dipole depends on

the program/erase operation sequence and demonstrate that it is at the origin of the charge losses

observed during retention. This dipole severely affects the retention of mildly programmed and

erased states, representing a serious reliability concern especially for multi-level applications.VC 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.4740255]

Among the many innovative memory concepts that have

been proposed to replace the conventional floating gate tech-

nology, charge-trapping devices, and especially their 3D

implementation,1,2 are considered attractive due to their

compatibility with complementary metal-oxide-semiconduc-

tor technology and immunity to stress-induced leakage cur-

rents. Despite the significant progresses made in the last

years in understanding the physics governing the operation

of these devices,2–10 some major factors affecting their reli-

ability have still to be fully understood. In particular, the

injection of both electrons (e�) and holes (hþ) during pro-

gram and erase operations9 may lead to the formation of a

charge dipole in the nitride,11,12 which has been associated

to severe reliability issues13–15 not thoroughly investigated

until now.

In this work, we demonstrate the formation of a vertical

charge dipole in the nitride layer of charge-trapping devices

and investigate its dependencies on program (P) and erase

(E) conditions by means of dedicated experiments and

physics-based device simulations. We show that polarity and

entity of the dipole depend on the P/E operation sequence

and that the dipole is directly related to the retention degra-

dation of mildly programmed or erased states, thus represent-

ing a serious reliability concern especially for multi-level

memory applications.

The devices used in this work are large area

(50� 50 lm2) planar TaN/Al2O3/Si3N4/SiO2/Si (TANOS)

p-type metal-oxide-semiconductor capacitors with a gate

stack comprised of 4 nm of SiO2 tunnel oxide, 6 nm of next-

to-stoichiometric SiN, 12 nm of Al2O3, and 10 nm of TaN

metal gate. Numerical device simulations have been per-

formed by using the model in Refs. 8 and 16, where the e�/

hþ transport in the nitride is described through the self-

consistent solution of drift-diffusion, current continuity, and

Poisson equations. Charge trapping is described by Shock-

ley-Read-Hall process, whereas thermal emission and trap-

to-band tunneling mechanisms are considered for e�/hþ

emission.8,16 Simulations performed in this work neglect the

charge trapping in the alumina layer, since we verified that

this phenomena is negligible for the considered operating

conditions, as expected from the high nitride to alumina

thickness ratio of our devices.8 The complete list of simula-

tion parameters can be found in Table I of Ref. 9.

In our previous study,9 we demonstrated that both elec-

trons and holes are injected in the nitride layer during pro-

gram and erase operations, respectively. In order to

investigate and quantify the potential reliability issues asso-

ciated to their concurrent presence in the nitride layer of the

charge-trap memory device, we performed retention experi-

ments on devices whose VFB was brought back to its fresh

value after a sequence of PþE or Eþ P operations (from

now on we will refer to this state as reset state and to devices

in this conditions as reset devices). The results in Fig. 1

show that the fresh device exhibits a stable flat band voltage

(VFB), as expected. Conversely, devices in the reset state ex-

hibit significant flat band voltage shifts (DVFB) whose polar-

ity depends on the applied reset sequence, being positive

after PþE reset and negative after EþP reset. Note that the

same behavior is observed at both 200 �C and 25 �C, thus

proving that the retention degradation in Fig. 1, although

accelerated by the temperature, cannot be explained only by

the physical mechanisms responsible for the retention charge

losses observed in the “conventional” case of programmed

devices.3,6,17 Instead, these results indicate that a significant

amount of e� and hþ charges (that produce a null electro-

static effect) is still present in the nitride when the cell is

brought back to its fresh VFB after a given P/E sequence.

Moreover, the opposite DVFB polarities observed after oppo-

site P/E sequences (see Fig. 1) strongly suggest that this

charge is not distributed uniformly across the nitride, but

forms a vertical charge dipole.18

In order to further confirm these data and exclude other

physical mechanisms as the possible origin of the observed

VFB shifts, we performed additional high temperature reten-

tion experiments on slightly programmed and erased devices,

see Fig. 2. As expected, no VFB shifts are observed when

only either e� or hþ is present in the nitride layer of the de-

vice. On one hand, this proves that the charge loss during

retention is negligible in these conditions. More importantly,

it further confirms that the retention degradation shown in

0003-6951/2012/101(5)/053505/4/$30.00 VC 2012 American Institute of Physics101, 053505-1

APPLIED PHYSICS LETTERS 101, 053505 (2012)

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Fig. 1 for reset devices is related to the concurrent presence

of the two carrier species, fully supporting the idea of a

recombination of nitride e� and hþ,18 whose orientation

depends on the last operation performed. This behavior can

be understood by considering the simple model illustrated in

Fig. 3 for the two opposite P/E sequences. When an erase

operation is performed on a previously programmed device

[see the PþE sequence in Figs. 3(b)–3(d)], only the e�

charge trapped close to the SiO2 layer is emitted efficiently

during the operation.9 At the same time, the holes that are

injected from the substrate9 accumulate in the electron-

depleted region close to the SiN/SiO2 interface and partially

recombine with the electrons stored close to the Al2O3 layer.

These concurrent processes lead to the formation of physi-

cally separated e� and hþ distributions near the SiN/Al2O3

and SiN/SiO2 interfaces, respectively [see Fig. 3(c)]. During

retention, this charge recombines, thus reducing the net

amount of e� and hþ in the nitride [see Fig. 3(d)]. Since the

charge close to the SiN/SiO2 interface [i.e., hþ, see Fig. 3(d)]

has the highest impact on the VFB, the overall effect of the

recombination is an increase of the flat band voltage, coher-

ently to what observed in Fig. 1. The same explanation

applies to the case of the Eþ P sequence, where the opposite

dipole orientation originates a VFB shift of the opposite po-

larity [see Figs. 3(e)–3(g)].

We also investigated the dependence of the dipole mag-

nitude on the voltages used during P/E sequences. Fig. 4

shows the retention experiments after PþE (Eþ P) reset

performed using the same program (erase) voltage,

VP¼þ16 V (VE¼ –18 V), while varying the voltage of the

subsequent erase (program) operation. As can be seen, in

both cases the magnitude of the flat band voltage shift

observed during retention increases with the voltage applied

during the last operation, i.e., the one determining the dipole

orientation.

In order to verify the simple model illustrated in Fig. 3

and to better understand the dependence of the retention

DVFB shifts on the voltage of the last operation (see Fig. 4),

we used our charge-trapping device model8,16 to simulated

the P/E sequences in Figs. 1 and 4 and derive the net nitride

charge distribution in the reset state. Results are shown in

Figs. 5(a) and 5(b) for PþE sequences performed at VP/

FIG. 1. Threshold voltage shifts measured during retention experiments per-

formed at (open symbols) room temperature and (filled symbols) 200 �C on

fresh and reset devices after (red circles) VG¼þ16 V/�20 V PþE and

(blue squares) VG¼�18 V/þ14 V EþP sequences.

FIG. 2. Flat band voltage shifts measured during high temperature (200 �C)

retention experiments on (red circles) fresh, (green squares) slightly pro-

grammed, and (black diamonds) slightly erased devices.

FIG. 3. Schematic representation of the forma-

tion of the charge dipole in the TANOS nitride

layer after PþE (b)–(d) and EþP (e)–(g) oper-

ation sequences. The well-known equation used

to compute the DVFB induced by a charge Q is

also reported.

053505-2 Padovani et al. Appl. Phys. Lett. 101, 053505 (2012)

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VE¼þ16/�20 and VP/VE¼þ16/�16, respectively, and

Figs. 5(c) and 5(d) for Eþ P sequences performed at VE/VP

¼ �18/þ14 and VE/VP¼�18/þ13, respectively. Simula-

tions confirm that after a reset operation physically separated

e� and hþ distributions coexist in the nitride layer of the de-

vice, generating a vertical charge dipole with an orientation

that depends on the last operation performed. Moreover, the

simulation results shown in Fig. 5 agree with the simplified

model in Fig. 3, fully supporting the recombination of nitride

e� and hþ charges as the root cause of the VFB shifts

observed during retention. In addition, the distributions

simulated for devices reset using different P/E voltages are

fully consistent with the results shown in Fig. 4. For the case

of the PþE sequence illustrated in Figs. 5(a) and 5(b), it can

be seen that the hole distribution close to the SiO2/SiN inter-

face is much smaller when the device is reset using a lower

erase voltage. As a consequence, a lower VFB shift is

expected during retention, due to the smaller amount of

charge that recombines under the action of the internal

dipole, in full agreement with the experimental data in Fig.

4. The same reasoning applies to the case of the Eþ P

sequence shown in Figs. 5(c) and 5(d).

Previous results clearly demonstrate that subsequent P/E

operations create a vertical nitride charge dipole that signifi-

cantly affects the retention of charge-trapping devices. This

degradation is not limited to the case of reset devices, but

extends also to devices mildly programmed (mildly erased)

after an initial erase (program) operation. In order to better

understand this aspect and quantify the DVFB range in which

the dipole influences the retention of the device, we com-

pared retention transients measured on devices brought to a

certain program or erase level either through single-pulse

operations (i.e., injecting only one carrier species) or double-

pulse operations (i.e., injecting both e� and hþ). The results

are shown in Figs. 6(a) and 6(b) for PþE and Eþ P sequen-

ces, respectively. In both cases, the retention VFB shift is

much higher when the initial state is reached through the

double-pulse operation (see Fig. 6), thus confirming that the

presence of the electron-hole dipole strongly degrades de-

vice retention. Moreover, the dipole formed after PþE

sequences lead to positive VFB variations (in agreement with

Figs. 1 and 3) that severely worsen the retention of mildly

erased states causing shifts up to 0.5 V as in the case of the

initial DVFB¼�1.5 V, see Fig. 6(a). Conversely, in mildly

programmed states, this effect partially compensates the loss

due to conventional charge leakage, slightly improving the

device retention as in the case shown in Fig. 6(a) for the ini-

tial DVFB¼þ1.7 V. Vice versa, the dipole formed after

Eþ P operations causes negative VFB variations, worsening

the retention in the whole DVFB range considered, see

Fig. 6(b). These results demonstrate that the negative influ-

ence of the charge dipole on device retention extends to a

wide VFB window (from �1.5 V to þ2 V in Fig. 6), thus rep-

resenting a critical reliability concern especially for the case

FIG. 4. Flat band voltage shifts measured during retention experiments per-

formed at 200 �C on reset devices after (red circles) PþE and (blue squares)

EþP sequences performed using different P/E voltages (corresponding P/E

times have been adjusted in order to reset the device).

FIG. 5. Net nitride charge distributions

simulated for the (a) and (b) PþE and (c)

and (d) EþP reset sequences as in Fig. 3.

053505-3 Padovani et al. Appl. Phys. Lett. 101, 053505 (2012)

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of multi-level application, where erased and programmed

states such as DVFB¼�1.5 V in Fig. 6(a) and DVFB¼þ2 V

in Fig. 6(b) are used as logic states of the device. This

demands for an optimization of program/erase pulses in

order to minimize this effect.

We demonstrated that subsequent program and erase

operation of a charge-trapping memory cell lead to the for-

mation of a vertical charge dipole in the nitride layer of

the device, whose polarity has been correlated to the last

operation of P/E sequence applied to the cell. This charge

severely affects device retention, thus representing a seri-

ous reliability concern especially for multi-level NAND

applications.

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FIG. 6. Comparison of retention characteristics measured at 200 �C on devi-

ces brought to a certain program or erase level either through single-pulse

(red squares) or (a) PþE (blue triangles) and (b) EþP (green circles)

double-pulse operations.

053505-4 Padovani et al. Appl. Phys. Lett. 101, 053505 (2012)

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