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Information furnished by Analog Devices is believed to be accurate andreliable. However, no responsibility is assumed by Analog Devices for itsuse, nor for any infringements of patents or other rights of third parties thatmay result from its use. No license is granted by implication or otherwiseunder any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2002
EVAL-AD1953EB
SigmaDSP™
Evaluation Board
FUNCTIONAL BLOCK DIAGRAM
U9AOP275
604 SUBJ5
U8BOP275
604 RIGHTJ4
U8AOP275
604 LEFTJ3
U7
AD1953SIGMADSP
U13
M4A5-128/64INTERFACE
PLD
U1574AC244
DATAOUTPUT
J13
SW1RESET
J12-SPIINTERFACE
U12ADM811
SW2 SW3
MCLK0
MCLK1
MCLK2
D3ZERO
S2MUTEU3
74HC04
J14 J15 J16EXT. INPUTS
D1VERF
D2EMP
U374HC04
U2S/PDIF
RECEIVER
U4S/PDIF
TRANSMITTER
INPUTJ1
OUTPUTJ2
U1TORX173
U5TOTX173
U6
J17CODEC
INTERFACE
SigmaDSP is a trademark of Analog Devices, Inc.
OVERVIEWThe AD1953 evaluation board (EVAL-AD1953EB) permitstesting and demonstration of the AD1953 3-channel, 24-bitSigmaDSP audio processor. An input signal is required ineither optical or coaxial S/PDIF format, or directly via oneof three 10-pin headers in I2S, left-justified, right-justified, orDSP modes. The internal signal processing program andparameters of the AD1953 can be controlled by a 25-lead SPIinterface to a computer’s parallel port.
Power requirements are a ±9 V to +12 V dc source for boththe analog and digital sections. On-board regulators driveseparate “clean” 5 V dc supplies for the digital and analogsections. Three analog RCA phone jacks provide analogaudio output. Digital output comes from optical and RCAjacks in S/PDIF format.
AD1953 OVERVIEWThe AD1953 is a complete 26-bit, single-chip, 3-channeldigital audio playback system with built-in DSP functionalityfor speaker equalization, dual-band dynamics processing(compressor/expander/limiter/noise gate), delay compensation,and spatial enhancement. These algorithms can be used tocompensate for real-world limitations of speakers, amplifiers,and listening environments, resulting in a dramatic improvementof perceived audio quality.
The signal processing used in the AD1953 is comparable to thatfound in high end studio equipment. Most of the processing isdone in full 48-bit double-precision mode, resulting in very goodlow level signal performance and the absence of limit cycles or idletones. The compressor/limiter uses a sophisticated two-bandalgorithm often found in high end broadcast compressors.
An extensive SPI port allows click-free parameter updates, alongwith readback capability from any point in the algorithm flow.
The AD1953 also includes ADI’s patented multibit sigma-deltaDAC architecture that provides 112 dB SNR and dynamic rangeand THD+N of –100 dB. These specifications allow the AD1953 tobe used in applications ranging from low end boom boxes to highend professional mixing/editing systems.
The AD1953 also has a digital output that allows it to be usedpurely as a DSP. This digital output can be used to drive anexternal DAC to extend the number of channels beyond thethree that are provided on the chip.
The AD1953 operates from a single 5 V power supply. It isfabricated on a single monolithic integrated circuit and is housedin a 48-lead LQFP package for operation over the temperaturerange –40°C to +105°C.
REV. 0–2–
EVAL-AD1953EBsary clocks to the AD1953 evaluation board, as well as to sendthe serial data to the external DACs.
Headers J6 and J7 are for future expansion and functionality ofthe evaluation board.
EXTERNAL SPI CONTROL PORTThe AD1953 evaluation board includes a 25-lead header thatinterfaces the chip’s SPI input with a computer’s parallel port.This port is capable of full read/write operation for all of the memories(program and parameter) and some of the SPI registers. Mostsignal processing parameters are controlled by writing new valuesto the parameter RAM using the SPI port. Other functions, suchas volume and de-emphasis filtering, are programmed by writingto SPI control registers. Details of signal format and timing canbe found in the AD1953 data sheet.
AUDIO SIGNAL OUTPUTSRCA jacks J3, J4, and J5 provide left, right, and sub outputs,respectively. The output is low-pass filtered with an anti-imagefilter and converted from a differential voltage output to single-ended voltage by op amps U8 and U9. The left and right channelfilters’ –3 dB cutoff frequency is 100 kHz and has an approximatethird order Bessel (linear phase) response. The subwoofer chan-nel uses the same filter but with a –3 dB cutoff at 10 kHz. Theoutput impedance is approximately 600 Ω. The full-scale outputsignal is 2.0 Vrms for all channels.
SWITCH AND JUMPER FUNCTIONSA quick reference for the default switch and jumper positions isshown in Table I. These settings should be used for a first-timeuse of the evaluation board. All directional references assume thatthe board is facing with the digital connections on the left and theanalog connections on the right. A more detailed description ofeach switch and jumper follows.
Table I. Default Switch/Jumper Positions
Jumper/Switch Position Setting
S1 Down RCA InputS2 Right Mute OffS4 Don’t Care For Future FunctionalityS5 Don’t Care For Future FunctionalitySW2 0 See Tables II and IIISW3 0 See Table IVLK2 B (Right) 5 VLK5 On (Down) AVDD ReferenceLK6 Off (Up) XREF OffLK9 C (Bottom) DIR_MCLKLK10 B (Right) MCLK1_INTFLK11 B (Right) MCLK2_INTF
Slide switch S1 selects between the RCA S/PDIF input and theTOSLINK input.
Push-button switch SW1 provides a RESET function via resetgenerator U12 (ADM811) and a “clean” 240 ms delay after release.U12 also provides a 240 ms reset pulse at power-up.
A 16-position rotary switch (SW2) controls the signal routing onthe evaluation board. The source of the SDATA, BCLK, andLRCLK signals for each of the three MUXes is indicated in Table II.Table III shows the source of signals driving the CS8404A (U4,S/PDIF digital output transmitter). In each of these two tables,
PERFORMANCE SPECIFICATIONSThe typical evaluation board performance is tabulated below.
1. SNR 112 dB ± 1 dB
2. DR, A-Weighted 112 dB ± 1 dB
3. THD + N –100 dB ± 2 dB
4. Frequency Response ±0.2 dB, 20 Hz to 20 kHz (0 dBFS)
5. Noise Floor –145 dB
6. Full-Scale Audio Output 2.0 Vrms
FUNCTIONAL DESCRIPTIONThe AD1953 evaluation board presents a reference design thatcan be used as a suggested layout and circuit implementationthat will deliver optimal performance from the SigmaDSP audioprocessor. As far as is possible, current assembly methods andcomponents are used on the evaluation board. Most componentsare surface-mount devices, although there is a version of theevaluation board that uses through-hole components in theoutput filters, and a four-layer printed circuit board is used withfull internal power and ground planes for superior noise perfor-mance. A schematic, bill of materials, and PCB plots areincluded for guidance.
POWER SUPPLIESThe board is divided into analog and digital sections, with commonpower supplies.
The power supply is input via binding posts J8, J9, and J10. Therecommended supply settings are +12 V dc with a maximumcurrent of +350 mA and –12 V dc with a maximum current of–50 mA. An on-board, low noise voltage regulator (U11) provides5 V dc, ±5% to the evaluation board circuit.
DIGITAL SIGNAL INPUTS AND OUTPUTSRCA phone jack J1 and optical TOSLINK input U1 may be usedfor standard consumer mode S/PDIF input signals. J1 is terminatedwith a 75 Ω resistor. Switch S1 selects between J1 and U1 inputsand feeds the selected signal to the digital interface receiver (U2).
The EXT DATA INTF 1/2/3 (J14, J15, and J16) inputs permitaccess, buffered via U13, to the BCLK, LRCLK, SDATA, andMCLK inputs of the AD1953. This permits testing with left-justified, I2S, or right-justified serial input modes. Note that switchSW3 must be set to correspond to the input data format. Whenusing the direct input header, it is necessary to provide all foursignals: MCLK, BCLK, LRCLK, and SDATA. A terminationnetwork consisting of a series-connected 100 Ω resistor and a 47 pFcapacitor is shunted across each signal line to reduce line reflections.
Digital audio signals are output through the RCA phone jack J2or TOSLINK output U5. Both output jacks are always “on,” sono switch is needed to select between the two. The transformer(U6) on the output buffers the external connection from the restof the evaluation board to prevent a ground loop.
Header J13 is for the serial data output from the input MUXand the data capture serial output. Either of these two signals,coupled with the left/right clock and bit clock signals, form avalid 3-wire output. This header can be used to connect an externalDAC to the AD1953 evaluation board.
Twenty-lead header J17 is for interfacing to an Analog Devicescodec evaluation board. This connection can be used to supplytwo serial data lines from external ADCs and all of the neces-
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EVAL-AD1953EB
–3–
the column entries are the signal sources and the headings are thesignal destinations for a given switch position.
Note: Switch position F is not used.
Table II. SW2 Settings—Signal Sources
SW2Pos. MUX 0 MUX 1 MUX 2 AUXDATA
0 8414 Ext. port 1 Ext. port 2 Ext. port 01 Ext. port 0 8414 Ext. port 2 Ext. port 12 Ext. port 0 Ext. port 1 8414 Ext. port 23 Ext. port 0 Ext. port 1 Ext. port 2 84144 8414 Ext. port 1 Ext. port 2 Ext. port 05 Ext. port 0 8414 Ext. port 2 Ext. port 16 Ext. port 0 Ext. port 1 8414 Ext. port 27 Ext. port 0 Ext. port 1 Ext. port 2 84148 8414 Ext. port 1 Ext. port 2 Ext. port 09 Ext. port 0 8414 Ext. port 2 Ext. port 1A Ext. port 0 Ext. port 1 8414 Ext. port 2B ASDATA1 ASDATA1 ASDATA1 ASDATA2C ASDATA2 ASDATA2 ASDATA2 ASDATA1D ASDATA1 ASDATA1 ASDATA1 ASDATA2E ASDATA2 ASDATA2 ASDATA2 ASDATA1
Table III. SW2 Settings—CS8404A Signal Sources
SW2 8404 8404 8404Pos. SDI LRCLK/BCLK MCLK (128 fS)*
0 DCSOUT 8414 8414 (* 1/2)1 DCSOUT 8414 8414 (* 1/2)2 DCSOUT 8414 8414 (* 1/2)3 DCSOUT MUX OUT MCLKOUT (* 1/2)4 SDATAOUT MUX OUT 8414 (* 1/2)5 SDATAOUT MUX OUT 8414 (* 1/2)6 SDATAOUT MUX OUT 8414 (* 1/2)7 SDATAOUT MUX OUT 8414 (* 1/2)8 DCSOUT MUX OUT MCLKOUT (* 1/2)9 DCSOUT MUX OUT MCLKOUT (* 1/2)A DCSOUT MUX OUT MCLKOUT (* 1/2)B DCSOUT MUX OUT Ext. CODEC (* 1/2)C DCSOUT MUX OUT Ext. CODEC (* 1/2)D SDATAOUT MUX OUT Ext. CODEC (* 1/2)E SDATAOUT MUX OUT Ext. CODEC (* 1/2)*MCLK input signals to the CS8404 are divided by two in the PLD becausethis part runs on 128 fS, while the rest of the board runs on a 256 fS MCLK.
Rotary switch SW3 determines which serial interface format isselected. Table IV shows the different modes.
Note: Switch positions 6–F are not used.
Table IV. SW3 Settings
SW3 Position Serial Data Format
0 I2S1 Right Justified — 24-bit2 DSP3 Left Justified4 Right Justified — 20-bit5 Right Justified — 16-bit
Switch S2 enables the AD1953 mute function.
Push-button switch SW4 and switches S4 and S5 are not currentlyfunctional but will be used in future evaluation board revisions.
Jumper LK2 selects between an external supply (Position A) ora 5 V input (Position B) to the AD1953’s ODVDD pin. ODVDDis the supply for the digital output pins. Using an external supplyat 3 V allows the outputs to be 3.3 V compatible. The switchshould be left in the 5 V position if no external power supply isconnected to the EXT side of the jumper.
Jumper LK9, LK10, and LK11 select between internal and exter-nal MCLK inputs to the MCLK MUX for MCLK0, MCLK1, andMCLK2, respectively. For LK9, Position A selects theMCLK0_INTF from External Data Interface 0 (J14), Position Bselects the MCLK from the codec interface header (J17), andPosition C selects the recovered DIR_MCLK from the S/PDIFreceiver (U2). For LK10 and LK11, in the left Position (A), theDIR_MCLK signal from U2 is selected. Position B selects theMCLKx_INTF signal from external data header J15 and J16.
Jumpers LK5 and LK6 connect the reference voltage to theVREF_IN pin. If LK5 is on, then the voltage will come fromAVDD. With LK6 on, the reference voltage will be taken fromthe external reference Test Point 1 (TP1).
INDICATOR DISPLAY LEDSFive LED indicators are provided for status indication.
• Display LED D1, VERF, indicates that the S/PDIF digitalinterface receiver has detected an error condition in thereceived signal. When not illuminated, this LED is a goodindicator that there is a signal present on the S/PDIF input.
• Display LED D2, EMP, indicates that the incoming signalhas had pre-emphasis added.
• Display LED D3, ZERO, is provided to show that theAD1953 is detecting a zero input in one of the two inputchannels.
• Display LEDs D6 and D11, DVDD and AVDD, show thepresence of 5 V dc on the digital and analog 5 V powersupplies, respectively.
INTEGRATED CIRCUIT FUNCTIONSThere are 16 active devices on the AD1953 evaluation board.Following is a brief description of the function of each part.
• U1 (TORX173) is the Toshiba digital audio optical receiver.It accepts the visible red S/PDIF modulated signal andconverts it to a standard TTL digital signal suitable forinput to the digital audio receiver (U2).
• U2 (CS8414-CS) receives the serial S/PDIF digital audioencoded signal and decodes the audio information. TheCS8414 decodes four digital signals from the serial inputstream: the serial data SDATA, the master clock MCLK,the left/right frame clock LRCLK, and the serial bit clockBCLK at 64 Fs. The output interface mode of U2 must becompatible with the input to the AD1953 (U7). This modeis selected at the same time for both U2 and U7 via switch SW3.
• U3 (74HC04) is a quad input logic inverter that providesmiscellaneous buffering and interface functions.
• U4 (CS8404A-CS) is the S/PDIF transmitter that takes inthe serial data SDATA, master clock MCLK, the left/right
REV. 0–4–
EVAL-AD1953EBframe clock LRCLK, and the serial bit clock BCLK, andoutputs the S/PDIF signal to the TOSLINK transmitter andthe RCA output jack.
• U5 (TOTX173) is the Toshiba digital audio optical transmitter.It creates a visible red S/PDIF modulated signal from thestandard TTL digital signal output of the digital audiotransmitter (U4).
• U6 (SC937-02) is a digital audio transformer with low jitterand high CMRR that provides buffering between the evalu-ation board and the external circuit, preventing ground loops.
• U7 (AD1953) is the SigmaDSP digital audio processorand converter.
• U8 and U9 (OP275) are low noise and distortion audioop amps. U8 provides differential-to-single-ended conversionfor the left and right channel outputs, while U9 does thesame for the sub channel. A third order low-pass Besselfilter response is implemented with a –3 dB corner frequencyof 100 kHz on the left and right channels, 10 kHz onthe subchannel, and a 60 dB/decade (18 dB/octave) roll-off.This type of filter is characterized by a linear phase responseand fast transient response without overshoot.
• U10 (LM317) provides 5 V dc low voltage regulation forthe digital section of the evaluation board.
• U11 (ADP3303-5) is a low noise 5 V dc regulator for theanalog section of the AD1953.
• U12 (ADM811) is a RESET generator that provides adebounced reset signal from the push-button (SW1) or a240 ms reset pulse on power-up.
• U13 (M4A5-128/64) provides decoding, buffering, andselection functions between the different modes of operation.
• U14 (74HC243) is a quad three-state noninverting buffer.
• U15 (74AC244) is an octal noninverting buffer/line driverwith three-state outputs.
• U16 (NC7S14) is a high performance inverter with Schmitttrigger input.
SOFTWAREThe AD1953 evaluation board comes with software that can beused to control all of the part’s functions. The evaluation boardinterfaces with this software via the 25-lead header (J12), whichconnects to a computer’s parallel port.
Custom programming tools are available for the AD1953. AGraphical Compiler, in conjunction with OrCAD, can be usedto design custom signal processing algorithms using any of theAD1953’s processing blocks. All settings can be programmedwith this Graphical Compiler, which writes to the program andparameter RAMs through the SPI port of the AD1953.
More in-depth documentation is available for all software.
FURTHER INFORMATIONOrdering information: order number is EVAL-AD1953EB.
For application questions, please contact our Central Applica-tions Department at 1-781-937-1428.
REV. 0
EVAL-AD1953EB
–5–
Figure 1. Silkscreen – Top Overlay
REV. 0–6–
EVAL-AD1953EB
Figure 2. Component – Top Layer
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EVAL-AD1953EB
–7–
Figure 3. Internal Plane 2 – Ground Planes
REV. 0–8–
EVAL-AD1953EB
Figure 4. Internal Plane 3 – Power Planes
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EVAL-AD1953EB
–9–
Figure 5. Bottom Layer – Solder Side
REV. 0–10–
EVAL-AD1953EBBill of Materials
Qty.Used Designator Description Part Decal Value
27 C1, C5–C11, Multilayer Ceramic 50 V X7R SMD 0805 Case 0.1 µFC13, C51–C54, C56,C58, C61, C64,C66–C71, C87–C90
4 C2, C3, C63, C91 Multilayer Ceramic 50 V X7R SMD 0805 Case 10 nF1 C4 Multilayer Ceramic 50 V X7R SMD 0805 Case 68 nF2 C12, C57 SMD Aluminum Electrolytic Capacitor (Case B) 16 V CAP\ELEK_SMD_B 10 µF3 C14, C59, C65 SMD Aluminum Electrolytic Capacitor (Case D) 16 V CAP\ELEK_SMD_D 47 µF3 C15, C27, C39 Ceramic Chip Capacitor, 5%, 50 V, NPO SMD 0805 Case 100 pF3 C16, C28, C40 P-Series Polypropylene Capacitor CAP-5 mm 100 pF2 C17, C29 Ceramic Chip Capacitor, 5%, 50 V, NPO SMD 0805 Case 1 nF2 C18, C30 Film Chip Capacitor, 5%, 50 V, PPS SMD 0805 Case 2 n7F2 C19, C31 P-Series Polypropylene Capacitor CAP-5 mm 1 nF2 C20, C32 P-Series Polypropylene Capacitor CAP-5 mm 2 n7F2 C21, C33 Ceramic Chip Capacitor, 5%, 50 V, NPO SMD 0805 Case 270 pF2 C22, C34 P-Series Polypropylene Capacitor CAP-5 mm 270 pF2 C23, C35 Ceramic Chip Capacitor, 5%, 50 V, NPO SMD 0805 Case 820 pF2 C24, C36 P-Series Polypropylene Capacitor CAP-5 mm 820 pF2 C25, C37 Film Chip Capacitor, 5%, 50 V, PPS SMD 0805 Case 2n2F2 C26, C38 P-Series Polypropylene Capacitor CAP-5 mm 2n2F1 C41 Ceramic Chip Capacitor, 5%, 50 V, NPO SMD 0805 Case 270 pF1 C42 Panasonic PPS (ECHS) Series Capacitor CAP-5 mm 27 nF1 C43 Ceramic Chip Capacitor, 5%, 50 V, NPO SMD 0805 Case 560 pF1 C44 Panasonic PPS (ECHS) Series Capacitor CAP-5 mm 56 nF1 C45 Ceramic Chip Capacitor, 5%, 50 V, NPO SMD 0805 Case 68 pF1 C46 Panasonic PPS (ECHS) Series Capacitor CAP-5 mm 6n8F1 C47 Ceramic Chip Capacitor, 5%, 50 V, NPO SMD 0805 Case 150 pF1 C48 Panasonic PPS (ECHS) Series Capacitor CAP-5 mm 15 nF1 C49 Film Chip Capacitor, 5%, 50 V, PPS SMD 0805 Case 2n2F1 C50 Panasonic PPS (ECHS) Series Capacitor CAP-5 mm 220 nF3 C55, C60, C62 SMD Electrolytic Capacitor (Case D) 25 V CAP\ELEK_SMD_E 47 µF20 C72–C86, C92–C96 Ceramic Chip Capacitor, 5%, 50 V, NPO SMD 0805 Case 47 pF2 D1, D6 Red Light Emitting Diode LED_SMT Red2 D2, D3 Yellow Light Emitting Diode LED_SMT Yellow1 D11 Green Light Emitting Diode LED_SMT Green2 D7–D8 SMD Aluminum Rectifier Diode, 50 V, 1 A, SOD-87 MELF13 D5, D9–D10 15 V Zener Diode DIODE-SMB 15 V5 J1–J5 Audio Connector—RCA Female Right Angle PHONO1 J8 Connector, Binding Post (Uninsulated Base) BINDING-POST Yellow1 J9 Connector, Binding Post (Uninsulated Base) BINDING-POST Green1 J10 Connector, Binding Post (Uninsulated Base) BINDING-POST Blue6 J7, J11, J13–J16 10-Way (5 × 2) IDC Header—Shrouded HEADER10-POL1 J12 CON\DB25HM DB25-HM
J17 20-Way (10 × 2) IDC Header—Shrouded6 L1–L4, L8–L9 Chip Ferrite Bead 600 Ω @ 100 MHz SMD 0805 Case1 L5 Chip Ferrite Bead 600 Ω @ 100 MHz SMD 0805 Case2 L6, L7 Do Not Insert SMD 0805 Case2 LK5–LK6 Jumper Block, 2 PINS 0.1" SPACING SIP-2P7 LK1, LK3–LK4, LK7– Do Not Insert SIP-2P
LK8, LK12–LK136 LK2, LK10–LK11, Jumper Changeover × 1 LINK-3P
S2, S4, S51 LK9 6-Pin Square Pin Header (3 × 2) 0.1" Pitch
REV. 0
EVAL-AD1953EB
–11–
Bill of Materials (continued)
Qty.Used Designator Description Part Decal Value
27 R1, R9, R12–R14, R43, Chip Resistor 1% 100 mW Thick Film SMD 0805 Case 10.0 kΩR47, R49–R51, R56–R59,R64–R67, R72–R75, R81,R82, R83, R85, R86
1 R2 Chip Resistor 1% 100 mW Thick Film SMD 0805 Case 75 Ω1 R3 Chip Resistor 1% 100 mW Thick Film SMD 0805 Case 475 Ω5 R4–R5, R11, R41–R42 Chip Resistor 1% 100 mW Thick Film SMD 0805 Case 649 Ω1 R6 Chip Resistor 1% 100 mW Thick Film SMD 0805 Case 374 Ω1 R7 Chip Resistor 1% 100 mW Thick Film SMD 0805 Case 90.9 kΩ1 R8 Chip Resistor 1% 100 mW Thick Film SMD 0805 Case 8.25 kΩ2 R15, R23 Chip Resistor 1% 100 mW Thick Film SMD 0805 Case 2.80 kΩ2 R16, R24 Chip Resistor 1% 100 mW Thick Film SMD 0805 Case 806 Ω3 R17, R25, R34 Chip Resistor 1% 100 mW Thick Film SMD 0805 Case 3.01 kΩ3 R18, R26, R36 Chip Resistor 1% 100 mW Thick Film SMD 0805 Case 1.50 kΩ2 R19, R27 Chip Resistor 1% 100 mW Thick Film SMD 0805 Case 1.00 kΩ2 R20, R28 Chip Resistor 1% 100 mW Thick Film SMD 0805 Case 499 Ω2 R21, R29 Chip Resistor 1% 100 mW Thick Film SMD 0805 Case 549 Ω3 R22, R30, R38 Resistor SMD 0805 Case OPEN2 R31, R33 Chip Resistor 1% 100 mW Thick Film SMD 0805 Case 11.0 kΩ2 R32, R35 Chip Resistor 1% 100 mW Thick Film SMD 0805 Case 5.62 kΩ1 R37 Chip Resistor 1% 100 mW Thick Film SMD 0805 Case 604 Ω1 R39 Chip Resistor 1% 100 mW Thick Film SMD 0805 Case 243 Ω1 R40 Chip Resistor 1% 100 mW Thick Film SMD 0805 Case 715 Ω20 R44–R46, R52–R55, Chip Resistor 1% 100 mW Thick Film SMD 0805 Case 100 Ω
R60–R63, R68–R71,R87–R91
6 R48, R76–80 Chip Resistor 1% 100 mW Thick Film SMD 0805 Case 22.1 Ω1 R84 Chip Resistor 1% 100 mW Thick Film SMD 0805 Case 100 kΩ1 RP1 RES-PACK8 SIP-9P 10 kΩ1 S1 DPDT PCB Switch (Top Actuator) SW-DPDT-SLIDE2 SW1, SW4 SMD Push-Button Switch (Sealed 6 mm × 6 mm) SW\PB-SMALL2 SW2–3 HEX Rotary Switch SW-ROTARY-HEX17 TP1–17 Testpoint TESTPOINT1 U1 Fiber Optic Receiving Module for Digital Audio TORX173 TORX1731 U2 96 kHz Digital Audio Receiver SO28WB DIR-CS8414-CS1 U3 HEX INV SO14NB 74HC041 U4 96 kHz Digital Audio Transmitter SO24WB CS8404A-CS1 U5 Fiber Optic Transmitting Module for Digital Audio TORX173 TOTX1731 U6 Digital Audio Signal Transformer (AES/EBU) TRAFFO-SC937-02 TRAFFO-SC937-021 U7 AD1953 – SigmaDSP LQFP48 AD1953YST2 U8–9 Dual Bipolar/JFET Audio Op Amp SO8NB OP275GP1 U10 Three Terminal Adjustable Regulator D-PAK LM3171 U11 Precision Low Dropout Voltage Regulator SO8NB ADP3303AR-51 U12 Voltage Monitor SOT143 ADM811R-ART1 U13 CPLD QFP100-3 CPLD-M4A5-
128/64-10YC1 U14 Quad Bus Transciever Three-State Noninverting SO14NB 74HC2431 U15 Octal Buffer/Line Driver Three-State Outputs SO20WB 74AC2441 U16 NC7S14 SOT23-5 NC7S144 PCB Standoffs
REV. 0–12–
EVAL-AD1953EB
J2
U6
1 4
5 8 6T
RA
FF
O-S
C93
7-02
LO
HI
2
SC
KL
RC
KS
DAT
A
CB
LR
ST
MC
LK
V C U M0
M1
M2
PR
0C
7/C
3C
1/F
C0
C6/
C2
CR
E/F
C1
C9/
C15
EM
1/C
8E
M0/
C9
TX
P
TX
N
VD
+
GN
D
U4
CS
8404
6 7 8
15 16
5 910 11 21 22 23
8404
_BC
LK
8404
_LR
CL
K84
04_S
DI
RE
SE
TB
DIT
_MC
LK
8404
_M0
8404
_M1
8404
_M2
18
20 17141312244312
DV
DD
19
DV
DD
C7
0.1
F
CA
SE
1C
AS
E2
RL
IMIT
DG
ND
INP
UT
5 6 2 1
U5
TOT
X17
34
R6
374
R7
90.9
R8
8.25
k
DV
DD360
0ZL
4
DV
DD
C8
0.1
F
SD
ATA
FS
YN
CS
CK
MC
K
M0
M1
M2
M3 C U
CB
LV
ER
FE
RF
CO
/E0
CA
/E1
CB
/E2
CC
/F0
CD
/F1
CE
/F2
SE
LC
S12
/FC
K
26 11 12 19 23 24 18 17 1 14 15 28 25 6 5 4 3 2 27 16 13
8414
_SD
O84
14_L
RC
LK
8414
_BC
LK
8414
_MC
LK
8414
_M0
8414
_M1
8414
_M2
8414
_M3
RX
P
RX
N
FIL
T
AG
ND
DG
ND
9
10 20 21
8
C5
0.1
F
VA+
VD
+722
U2
DIR
-CS
8414
U3-
A74
HC
04
R4
649
R5
649 U3-
B74
HC
04
4 3
2 1
8 9
U3-
D74
HC
04
D2
P/E
MP
YE
LL
OW
D1
RE
DV
ER
F
DV
DD
C6
0.1
F
R3
475 C
468
nFC
210
nF
C3
10n
F
600Z L
260
0ZL
3
LK
1DV
DD
R2
75
J1
SH
LD
1
SH
LD
2
DG
ND
1D
GN
D2
U1
TOR
X17
3
OU
T
DV
DD
5 6 2 4
3
C1
0.1
FR
110
.0k
600Z
L1
DV
DD
S1
Figure 6. Evaluation Board, S/PDIF Interfaces
REV. 0
EVAL-AD1953EB
–13–
Figure 7. Evaluation Board, DUT
MCLK22MCLK2MCLK13MCLK1MCLK04MCLK0
SDATA28SDATA2_DUTBCLK29BCLK2_DUTLRCLK210LRCLK2_DUT
SDATA111SDATA1_DUTBCLK112BCLK1_DUTLRCLK114LRCLK1_DUT
SDATA015SDATA0_DUTBCLK016BCLK0_DUTLRCLK017LRCLK0_DUT
DMUXO/TDMO41SDATAOUTBMUXO/TDMBC42BCLKOUTLRMUXO/TDMFS43LRCLKOUTDCSOUT45SCOUT_TRAPMCLKOUT47MCLKOUT
CDATACDATA_DUTCCLK19CCLK_DUTCLATCH20CLATCH_DUTCOUT46COUT_DUT
ZEROFLAGRESETB21RESETBMUTE6
AUXDATA5AUXDATA
18
40
VOUTL+ 33 VOUTL+
VOUTL– 34 VOUTL–
VOUTR+ 29 VOUTR+
VOUTR– 28 VOUTR–
VOUTS+ 26 VOUTS+
VOUTS– 25 VOUTS–
VREF_IN 38
FILTCAP 39
U7AD1953
ODVDD DVDD AVDD AVDD AVDD
DGND DGND AGND AGND AGND AGND13 48 23 27 31 35
C1210F
+ C130.1F
R1210k
R1310k
R1410k
C1447F
+
LK5 LK6
XREF
AVDD
44 7 32 22 30
C110.1F
LK4
600ZL8
AVDD
C100.1F
C90.1F
LK3
DVDD
ODVDD
A BLK2
ODVDD_EXTEXT 5V
R11649
6
5
U3-C74HC04
D3ZERO
YELLOW
DVDDTP1
R910k
DVDD
S2
MUTE
600ZL5
600ZL6
REV. 0–14–
EVAL-AD1953EB
R15
2.80
k
C15
100p
FN
PO
C16
100p
FP
P-M
F
C17
1nF
NP
O
C18
2n7F
PP
S
R16
806
VOU
TL
+
VOU
TL
–
C19
1nF
PP
-MF
C20
2n7F
PP
-MF
R18
1.50
k
R20
499
R19
1.00
k
R17
3.01
k
C23
820p
FN
PO
C21
270p
FN
PO
C24
820p
FP
P-M
F
C22
270p
FP
P-M
F
6 57
U8-
B OP
275
R21
549
C25
2n2F
PP
S
C26
2n2F
PP
-MF
R22
OP
EN
J3
LO
UT
TP
12
R23
2.80
k
C27
100p
FN
PO
C28
100p
FP
P-M
F
C29
1nF
NP
O
C30
2n7F
PP
S
R24
806
VOU
TR
+
VOU
TR
–
C31
1nF
PP
-MF
C32
2n7F
PP
-MF
R26
1.50
k
R28
499
R27
1.00
k
R25
3.01
k
C35
820p
FN
PO
C33
270p
FN
PO
C36
820p
FP
P-M
F
C34
270p
FP
P-M
F
2 31
U8-
A OP
275
R29
549
C37
2n2F
PP
S
C38
2n2F
PP
-MF
R30
OP
EN
J4
RO
UT
TP
13
R31
11.0
k
C39
100p
FN
PO
C40
100p
FP
P-M
F
C41
270p
FN
PO
C43
560p
FN
PO
R32
5.62
k
VOU
TS
+
VOU
TS
–
C42
27n
FE
CH
S
C44
56n
FE
CH
S
R34
3.01
k
R36
1.50
kR
355.
62k
R33
11.0
k
C47
150p
FN
PO
C45
68p
FN
PO
C48
15n
FE
CH
S
C46
6.8n
FE
CH
S
2 31
U9-
A OP
275
R37
604
C49
2n2F
PP
S
C50
220n
FE
CH
S
R38
OP
EN
J5
SU
B
TP
14
U9-
BO
P27
5
6 5+–
LK
13
LK
12
V+
V–U9-
CO
P27
5
+12V
–12V
C53
0.1
F
C54
0.1
F
8 4
V+
V–
U8-
CO
P27
5
+12V
–12V
C51
0.1
F
C52
0.1
F
8 4
7
NO
TE
: ON
LY O
NE
CA
PAC
ITO
R IN
EA
CH
OF
TH
E P
AR
AL
LE
L P
AIR
S N
UM
BE
RE
D C
15-C
40A
RE
PR
ES
EN
T O
N E
AC
H E
VAL
UAT
ION
BO
AR
D.
Figure 8. Evaluation Board, Analog Output Section
REV. 0
EVAL-AD1953EB
–15–
YELLOW
GREEN
BLUE
+
R39243
TP3
R41649
TP6
TP5
TP4
TP7
R42649
DGND
DVDDLK7
+C5947F
C580.1F
R40715
+C5710F
1
23
U10LM317
IN OUTADJ/GND
C560.1F
C5547F25V
D5
L7600Z
L9600Z
D7
D8
VIN+
VIN–
COM
D9
D10
C6047F25V
C6247F
–12V
875
12
63
4AGND
C6310nF
C640.1F
C6547F
+
D6REDDVDD
D11GREENAVDD
AVDDU11ADP3303-5
IN1
IN2SD GND
NRERROR
OUT2
OUT1
J10
J9
J8
1SMB15AT315V
1SMB15AT315V
1SMB15AT315V
+ RESETB
R4310.0k
DVDD
2RESET
GND1
VCC
MR3
4
SW1
C660.1F
DVDD
LK8
+12V
+
C610.1F
Figure 9. Evaluation Board, Power Supply and Reset Generator Sections
REV. 0–16–
EVAL-AD1953EB
B1
B2
B4
B8
CO
MC
OM S
W2
SW
-RO
TAR
Y-H
EX1 4 3 6
2 5
U13
CP
LD
-M4A
5-12
8/64
GN
D1
GN
D2
TD
I3
I54
I/O8
5
I/O9
6
I/O10
7
I/O11
8
I/O12
9
I/O13
10
I/O14
11
I/O15
12
IO/C
LK
013
VC
C14
VC
C15
GN
D16
GN
D17
I1/C
LK
118
I/O16
19
I/O17
20
I/O18
21
I/O19
22
I/O20
23
I/O21
24
I/O22
25
I/O23
26
TM
S27
TC
K28
GN
D29
GN
D30
TD
IA
SD
ATA
2U
CS
EL
184
14_S
DO
8414
_LR
CL
K84
14_B
CL
K84
14_M
384
14_M
284
14_M
184
14_M
0D
IR_M
CL
KD
VD
D C70
0.1
FA
LR
CL
KD
IT_M
CL
K84
04_B
CL
K84
04_L
RC
LK
8404
_M2
8404
_M1
8404
_M0
8404
_SD
IU
CS
EL
2T
MS
TC
K
I/O24 31
I/O25 32
I/O26 33
I/O27 34
I/O28 35
I/O29 36
I/O30 37
I/O31 38
VCC 39
GND 40
GND 41
VCC 42
I/O32 43
I/O33 44
I/O34 45
I/O35 46
I/O36 47
I/O37 48
I/O3849
I/O3950
GN
D80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
GN
DT
DO
TR
ST
I/O55
I/O54
I/O53
I/O52
I/O51
I/O50
I/O49
I/O48
I4/C
LK
3G
ND
GN
DV
CC
VC
CI3
/CL
K2
I/O47
I/O46
I/O45
I/O44
I/O43
I/O42
I/O41
I/O40 I2
EN
AB
LE
GN
DG
ND
AS
DAT
A1
UC
SE
L3
SD
ATA
2_D
UT
BC
LK
2_D
UT
LR
CL
K2_
DU
TL
RC
LK
OU
TS
CO
UT
_TR
AP
SD
ATA
OU
TB
CL
KO
UT
MC
LK
OU
T
DV
DD
C68
0.1
F
AB
CL
KS
DAT
A1_
DU
TB
CL
K1_
DU
TL
RC
LK
1_D
UT
SD
ATA
0_D
UT
BC
LK
0_D
UT
LR
CL
K0_
DU
T
TP
15 LRCK0
TP
16T
P17
BCK0
SDO
UC
SE
L4
CO
UT-
UC
DV
DD
TD
O
I/O710099989796959493929190898887868584838281
RE
SE
TB
CL
ATC
H-U
CP
IN-8
3P
IN-8
4A
UX
DAT
A
TP
2
CC
LK
-UC
CD
ATA
-UC
C67
0.1
F
DV
DD
BC
LK
2_IN
TF
LR
CL
K2_
INT
F
SD
ATA
2_IN
TF
SD
ATA
1_IN
TF
BC
LK
1_IN
TF
LR
CL
K1_
INT
FS
DAT
A0_
INT
FB
CL
K0_
INT
FL
RC
LK
0_IN
TF
I/O6I/O5I/O4I/O3I/O2I/O1I/O0VCCGNDGNDVCC
I/O63I/O62I/O61I/O60I/O59I/O58I/O57I/O56
RP
1D
VD
D
B1
B2
B4
B8
CO
MC
OM
SW
2S
W-R
OTA
RY
-HE
X
1 4 3 6
2 5C
690.
1F
DV
DD
CL
ATC
H_D
UT
CD
ATA
_DU
TC
OU
T_D
UT
CC
LK
_DU
TC
LAT
CH
_IN
TF
CD
ATA
_IN
TF
CO
UT
_IN
TF
CC
LK
_IN
TF
10
U3-
E74
HC
04
11
1213
U3-
F74
HC
04
DV
DD C
710.
1F
MC
LK
0_IN
TF
A
TD
M_M
CL
KB
DIR
_MC
LK
C
INT
DIR
MC
LK
0
LK
9
MC
LK
1_IN
TF
B AL
K10
INT
DIR
MC
LK
1M
CL
K1
DIR
_MC
LK
MC
LK
2_IN
TF
B AL
K11
INT
DIR
MC
LK
2M
CL
K2
DIR
_MC
LK
J11-
1
J11-
2
J11-
3
J11-
4
J11-
5
J11-
6
J11-
7
J11-
8
J11-
9
J11-
10
TC
K
TM
S
TD
I
TD
O
DV
DD
Figure 10. Evaluation Board, CPLD Section
REV. 0
EVAL-AD1953EB
–17–
J13-
1
J13-
2
J13-
3
J13-
5
J13-
7
J13-
9
J13-
4
J13-
6
J13-
8
J13-
10
DS
CO
UT
TD
MS
DAT
A/S
DAT
AO
UT
TD
MF
S/L
RC
LK
OU
T
TD
MB
CL
K/B
CL
KO
UT
R78
22.1
R76
22.1
R77
22.1
R79
22.1
R80
22.1
A3
8
A2
5
A1
4
A0
2
Y3
12
Y2
14
Y1
16
Y0
181
OE
U15
-A74
AC
244 A3
17
A2
15
A1
13
A0
11
Y3
3
Y2
5
Y1
7
Y0
919
OE
U15
-B74
AC
244
SC
OU
T_T
RA
PS
DAT
AO
UT
LR
CL
KO
UT
BC
LK
OU
T
MC
LK
OU
T
OD
VD
D_E
XT
OD
VD
D C88
0.1
FU
15
20 10
J12-
1J1
2-2
J12-
3J1
2-4
J12-
5J1
2-6
J12-
7J1
2-8
J12-
9J1
2-10
J12-
11J1
2-12
J12-
13J1
2-14
J12-
15J1
2-16
J12-
17J1
2-18
J12-
19J1
2-20
J12-
21J1
2-22
J12-
23J1
2-24
J12-
25
B3
U14
74H
C24
3
8
B2
9
B1
10
B0
11
A3
6
A2
5
A1
4
A0
3
OE
BO
EA
113
TP
8T
P9
TP
10
CD
ATA
_IN
TF
CL
ATC
H_I
NT
FC
CL
K_I
NT
F
R48
22.1
R49
10.0
kR
5010
.0k
R51
10.0
k
DV
DD
C72
47p
F
R44
100
C73
47p
F
R45
100
C74
47p
F
R46
100
R47
10.0
k
TP
11
CO
UT
_IN
TF
DV
DD C
890.
1F
SP
I IN
TE
RFA
CE
(25
WAY
–D S
HE
LL
)
J14-
1J1
4-2
J14-
3J1
4-4
J14-
5J1
4-6
J14-
7J1
4-8
J14-
9J1
4-10
C75
47p
F
R52
100
R56
10.0
C76
47p
F
R53
100
R57
10.0
C77
47p
F
R54
100
R58
10.0
C78
47p
F
R55
100
R59
10.0
DV
DD
SD
ATA
0_IN
TF
LR
CL
K0_
INT
F
BC
LK
0_IN
TF
MC
LK
0_IN
TF
J15-
1J1
5-2
J15-
3J1
5-4
J15-
5J1
5-6
J15-
7J1
5-8
J15-
9J1
5-10
C79
47p
F
R60
100
R64
10.0
C80
47p
F
R61
100
R65
10.0
C81
47p
F
R62
100
R66
10.0
C82
47p
F
R63
100
R67
10.0
DV
DD
SD
ATA
1_IN
TF
LR
CL
K1_
INT
F
BC
LK
1_IN
TF
MC
LK
1_IN
TF
J16-
1J1
6-2
J16-
3J1
6-4
J16-
5J1
6-6
J16-
7J1
6-8
J16-
9J1
6-10
C83
47p
F
R68
100
R72
10.0
C84
47p
F
R69
100
R73
10.0
C85
47p
F
R70
100
R74
10.0
C86
47p
F
R71
100
R75
10.0
DV
DD
SD
ATA
2_IN
TF
LR
CL
K2_
INT
F
BC
LK
2_IN
TF
MC
LK
2_IN
TF
C87
0.1
F
Figure 11. Evaluation Board, External Digital Interface
REV. 0–18–
EVAL-AD1953EB
C9247pF
R87100
R8110.0k
J17-1
J17-2
J17-3
J17-4
J17-5
J17-6
J17-7
J17-8
J17-9
J17-10
J17-11
J17-12
J17-13
J17-14
J17-15
J17-16
J17-17
J17-18
J17-19
J17-20
ODVDD_EXT
BCLKOUT_HEADER
SDATAOUT_HEADER
DSCOUT
LRCLKOUT_HEADER
C9347pF
R88100
R8210.0k
C9447pF
R89100
R8310.0k
C9547pF
R90100
R8510.0k
C9647pF
R91100
R8610.0k
DVDD
CODEC_MCLK
ASDATA2
ASDATA1
ALRCLK
ABCLK
J6-13
J6-28
J6-29
DVDD
J6-1
J6-14
J6-15
J6-18
J6-6 UCSEL1J6-7 UCSEL2J6-8 UCSEL3J6-9 UCSEL4
J6-10 RESETB
J6-22 COUT-UCJ6-23 CLATCH-UCJ6-26 CCLK-UCJ6-27 CDATA-UC
PROGRAMSELECT
RESET
SPICONTROL
U16NC7S14
4 2J6-5C9110nF
R84100
SW4
INTERRUPTREQUEST
DVDD
J6-21 J7-3
J6-19 J7-4
J6-20 J7-5
J6-24 J7-6
J6-16 J7-7
J6-17 J7-8
ADC2
ADC3
ADC4
ADC5
CREF
VREF
J7-9
J7-10
DVDD
S5
S4
J6-12 ADC1
J6-11 ADC0
J7-2
J7-1
PIN-83
PIN-84TO CPLD
TO VOLUME/TONE CONTROLBOARD
C900.1F
Figure 12. Evaluation Board, ADuC812S Interface
–19–
C03
090–
0–8/
02(0
)P
RIN
TE
D IN
U.S
.A.
–20–