EV-OXU200 and EV-OXU200-PCI Evaluation Board User Guide · EV-OXU200-PCI EV-OXU200-PCI and EV-OXU200 Evaluation Board User Guide Figure 1-2 PCI104 Register Mappings The Base Address

Oxford Semiconductor, Inc.1900 McCarthy Boulevard, Suite 210Milpitas, CA 95035USA

http://www.oxsemi.com

UG-0038 Mar 07

EV-OXU200-PCI and EV-OXU200

Evaluation BoardUser Guide

ii External—Free Release UG-0038 Mar 07

EV-OXU200-PCI and EV-OXU200 Evaluation Board User Guide Oxford Semiconductor, Inc.

© Oxford Semiconductor, Inc. 2007

The content of this document is furnished for informational use only, is subject to change without notice, and should not be construed as a commitment by Oxford Semiconductor, Inc. Oxford Semiconductor, Inc. assumes no responsibility or liability for any errors or inaccuracies that may appear in this document.

PLX is a trademark of PLX TechnologyON Semiconductor is a register trademark of Semiconductor Components Industries, LLC.

All other trademarks are the property of their respective owners.

Contents

Preface ................................................................................................................ vRevision Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vTypographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vOrdering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vContacting Oxford Semiconductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v

Chapter 1 - EV-OXU200-PCI ............................................................................ 1-1Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1PCI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-2Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-3Serial EEPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-4

Chapter 2 - EV-OXU200 Evaluation Board .................................................... 2-1Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1Board Operation Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2Default Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2Power Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2Oscillator Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3OXU200 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3DP/DM Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3VBUS Over-Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-4LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-4Mounting Holes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-4Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-4

Chapter 3 - PCI104 Bridge Board ................................................................... 3-1Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1Power Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2Local Bus Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3Local Bus Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3Mounting Holes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3

Chapter 4 - Schematics ................................................................................... 4-1Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1

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Contents EV-OXU200-PCI and EV-OXU200 Evaluation Board User Guide

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Preface

This manual documents the EV‐OXU200‐PCI and EV‐OXU200 Evaluation Board hardware.

Revision Information

Table I documents the revisions of this manual

Typographic Conventions

In this manual, the conventions listed in Table II apply.

Ordering Information

The following boards are available:

EV‐OXU200‐PCI Evaluation Board (EV‐OXU200‐PCI‐120)

EV‐OXU200 Evaluation Board (EV‐OXU200‐120)

PCI104 Bridge Board (TDPCI104‐1000‐01)

Contacting Oxford Semi-conductor

See the Oxford Semiconductor website (http://www.oxsemi.com) for further details about Oxford Semiconductor devices, or email [email protected].

Table I Revision Information

Revision ModificationFeb 2007 First publicationMar 2007 Added the Certified USB logo to the cover page

Table II Typographic Conventions

Convention Meaning

Italic Letters With Initial Capital Letters A cross-reference to another publication

Courier Font Software code, or text typed in via a keyboard

1, 2, 3 A numbered list where the order of list items is significant

A list where the order of items is not significant

“Title” Cross-refers to another section within the document

Significant additional information

UG-0038 Mar 07 External—Free Release v

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EV-OXU200-PCI and EV-OXU200 Evaluation Board User Guide


vi External—Free Release UG-0038 Mar 07

Chapter 1

EV-OXU200-PCI

Overview The EV‐OXU200‐PCI Evaluation Board is a system for OXU200 customer evaluations and internal software development in the PC environment. The EV‐OXU200‐PCI Evaluation Board allows the user to install and use the EV‐OXU200 in any PCI‐based computer. Application software running on the system has access to the OXU200 via the PCI memory space.

The EV‐OXU200‐PCI Evaluation Board is a two‐board combination of the following:

An EV‐OXU200 Evaluation Board

A 33 MHz, 32‐bit PCI Bridge Board, the PCI104

The EV‐OXU200 Evaluation Board contains the OXU200 and all the USB‐specific hardware.

The PCI104 Bridge Board contains a PCI‐to‐local‐bus bridge chip that bridges the PCI bus to the OXU200. Power and control signals to the PCI bus are maintained by the PCI bridge chip, while initialization and configuration of the PCI bridge chip is maintained by the on‐board serial EEPROM.

Figure 1‐1 illustrates the orientation of the two boards. The combined boards are approximately one inch thick and require space for two PCI devices, but only one PCI slot. The OXU200 peripheral USB connector is accessible through the opening in the computer case.

Chapter 2 describes the EV‐OXU200 Evaluation Board. Chapter 3 describes the PCI104 Bridge Board. For complete information about the OXU200 device, see the OXU200 Hardware Reference Manual.

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EV-OXU200-PCI EV-OXU200-PCI and EV-OXU200 Evaluation Board User Guide

Figure 1-1 EV-OXU200-PCI System Board Orientation

PCI Operation

Every PCI implementation has a PCI configuration space, where the PCI configuration registers are found. PCI configuration registers are accessed with read/write to configuration space, which is separate from memory and I/O space. Table 1‐1 lists the standard PCI configuration register space for all PCI functions on the PCI bus.

EV-OXU200

PC104 Connectors

PCI Slot

PCI Connector PCI104

CPU Motherboard

Table 1-1 Standard PCI Configuration Register Space

Byte 3 Byte 2 Byte 1 Byte 0 OffsetDevice ID Vendor ID 00hStatus Register Command Register 04hClass Code Revision ID 08hBIST Header Type Latency Timer Cache Line Size 0ChBase Address Register 0 (BAR 0) 10hBase Address Register 1 (BAR 1) 14hBase Address Register 2 (BAR 2) 18hBase Address Register 3 (BAR 3) 1ChBase Address Register 4 (BAR 4) 20hBase Address Register 5 (BAR 5) 24hCardBus CIS Pointer 28hSubsystem ID Subsystem Vendor ID 2ChExpansion ROM Base Address 30hReserved Capabilities

Pointer34h

Reserved 38hMax Latency Min Grant Interrupt Pin Interrupt Line 3Ch

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EV-OXU200-PCI and EV-OXU200 Evaluation Board User Guide EV-OXU200-PCI

The PCI104 can be identified on the PCI bus during enumeration by the following PCI configuration registers:

Most operating systems provide functions for finding devices on the PCI bus. These functions typically key off the Vendor and Device IDs, or the Class Code. Because the Class Code for the PCI104 appears as a PCI Bridge with sub class code “other”, the search should be keyed to the Vendor and Device IDs.

Configuration The EV‐OXU200‐PCI has two memory mapped register spaces and one I/O mapped register space. The address locations of the various spaces are determined by the Base Address Registers of the PCI configuration registers. Base Address Register 0 (BAR0) of the PCI configuration registers contains the address of the memory mapped PCI bridge controller registers. BAR1 contains the I/O address for the same PCI bridge controller registers. The PCI bridge controller registers are mapped into both memory and I/O space, so that these registers can be accessed via memory accesses or I/O addressing. BAR3 contains the address of the memory mapped OXU200 registers. Figure 1‐2 illustrates the register mappings within a PCI system.

Table 1-2 PCI Configuration Registers

Register Power-On ValueVendor ID 192EhDevice ID 016BhRevision 0001hClass Code 0680hSubsystem ID 016BhSubsystem Vendor ID 192Eh



Figure 1-2 PCI104 Register Mappings

The Base Address Registers are typically initialized by the system BIOS or by the operating system. Software generally does not have to manually set the addresses of the mapped locations, however, this is system dependent. If these registers are not initialized, the three spaces should be manually mapped into system memory and I/O space accordingly. Care must be taken to ensure no conflicts exist between the mapped regions and other devices on the PCI bus.

Serial EEPROM Registers

The PCI9030 PCI bridge controller provides an interface to program the attached serial EEPROM. The serial EEPROM should be pre‐programmed with the default values in Table 1‐3. The table is for informational purposes only. If the default values are modified, the behavior of the PCI104 will change.

CPU

PCI9030

Offset 0x10 0x14 0x18 0x1C 0x20 0x24

Local Addr Space 0

Local Addr Space 1

Local Addr Space 2

Local Addr Space 3

Configuration Registers

Register BAR0 (mem) BAR1 (I/O) BAR2 (mem) BAR3 (mem) BAR4 (mem) BAR5 (mem)

Table 1-3 Serial EEPROM Registers

Serial EEPROM Offset Description Default00h PCI Device ID 016Bh02h PCI Vendor ID 192Eh04h PCI Status Register 0290h06h PCI Command Register 0003h08h PCI Class Code 0680h0Ah PCI Class Code / Revision Number 0001h0Ch PCI Subsystem ID 016Bh0Eh PCI Subsystem Vendor ID 192Eh10h MSB New Capability Pointer 0000h12h LSB New Capability Pointer 0040h


EV-OXU200-PCI and EV-OXU200 Evaluation Board User Guide EV-OXU200-PCI

14h (Maximum Latency and Minimum Grant are not loadable) 0000h16h Interrupt Pin (Interrupt Line Routing is not loadable) 0100h18h MSW of Power Management Capabilities 4801h1Ah LSW of Power Management Next Capability Pointer /

Power Management Capability ID4801h

1Ch MSW of Power Management Data /PMCSR Bridge Support Extension 0000h1Eh LSW of Power Management Control/Status 0000h20h MSW of Hot Swap Control/Status 0000h22h LSW of Hot Swap Next Capability Pointer / Hot Swap Control 4C06h24h PCI Vital Product Data Address 0000h26h PCI Vital Product Data Next Capability Pointer /

PCI Vital Protocol Data Control0003h

28h MSW of Local Address Space 0 Range 0000h2Ah LSW of Local Address Space 0 Range 0000h2Ch MSW of Local Address Space 1 Range FFFFh2Eh LSW of Local Address Space 1 Range 8000h30h MSW of Local Address Space 2 Range 0000h32h LSW of Local Address Space 2 Range 0000h34h MSW of Local Address Space 3 Range 0000h36h LSW of Local Address Space 3 Range 0000h38h MSW of Expansion ROM Range 0000h3Ah LSW of Expansion ROM Range 0000h3Ch MSW of Local Address Space 0 Local Base Address (Remap) 0000h3Eh LSW of Local Address Space 0 Local Base Address (Remap) 0000h40h MSW of Local Address Space 1 Local Base Address (Remap) 0000h42h LSW of Local Address Space 1 Local Base Address (Remap) 0001h44h MSW of Local Address Space 2 Local Base Address (Remap) 0000h46h LSW of Local Address Space 2 Local Base Address (Remap) 0000h48h MSW of Local Address Space 3 Local Base Address (Remap) 0000h4Ah LSW of Local Address Space 3 Local Base Address (Remap) 0000h4Ch MSW of Expansion ROM Local Base Address (Remap) 0010h4Eh LSW of Expansion ROM Local Base Address (Remap) 0000h50h MSW of Local Address Space 0 Bus Region Descriptor 0080h52h LSW of Local Address Space 0 Bus Region Descriptor 0000h54h MSW of Local Address Space 1 Bus Region Descriptor 4040h56h LSW of Local Address Space 1 Bus Region Descriptor A040h58h MSW of Local Address Space 2 Bus Region Descriptor 0000h5Ah LSW of Local Address Space 2 Bus Region Descriptor 0000h5Ch MSW of Local Address Space 3 Bus Region Descriptor 0080h5Eh LSW of Local Address Space 3 Bus Region Descriptor 0000h


Serial EEPROM Offset Description Default



60h MSW of Expansion ROM Bus Region Descriptor 0000h62h LSW of Expansion ROM Bus Region Descriptor 0000h64h MSW of Chip Select 0 Base Address 0BFFh66h LSW of Chip Select 0 Base Address FFC1h68h MSW of Chip Select 1 Base Address 0000h6Ah LSW of Chip Select 1 Base Address 4001h6Ch MSW of Chip Select 2 Base Address 0000h6Eh LSW of Chip Select 2 Base Address 0000h70h MSW of Chip Select 3 Base Address 0000h72h LSW of Chip Select 3 Base Address 0000h74h Serial EEPROM Write-Protected Address Boundary 0030h76h LSW of Interrupt Control/Status 0041h78h MSW of Target Response, Serial EEPROM, and initialization Control 0870h7Ah LSW of Target Response, Serial EEPROM, and initialization Control 0000h7Ch MSW of General Purpose I/O Control 0024h7Eh LSW of General Purpose I/O Control 9864h80h MSW of Hidden 1 Power Management Data Select 0000h82h LSW of Hidden 1 Power Management Data Select 0000h84h MSW of Hidden 2 Power Management Data Select 0000h86h LSW of Hidden 2 Power Management Data Select 0000h


Serial EEPROM Offset Description Default


Chapter 2

EV-OXU200 Evaluation Board

Overview This chapter describes the hardware operation and configuration options available for the EV‐OXU200 in stand‐alone mode. These options allow customers to directly connect the OXU200 to their embedded processor or CPU without going through a PCI bus. The use of this board without the PCI bridge card increases performance and allows driver development in real‐world applications of the product. Figure 2‐1 shows the EV‐OXU200 block diagram.

Figure 2-1 EV-OXU200 Block Diagram

5.0 V to 3.3 V

Converter 3.3 V

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Mictor Test

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(Optional)

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Crystal or

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EV-OXU200 Evaluation Board EV-OXU200-PCI and EV-OXU200 Evaluation Board User Guide

Board Operation Requirement

The EV‐OXU200 requires a DC power source capable of supplying 5 V ± 10% at 1.0 A through a power switch.

Default Configura-tions

Zero‐Ohm resistors are used to set the following factory default configurations:

R1, R3 (0 Ω) populated to route 5 V from the PC104 connectors

R30, R31 (0 Ω) populated, R29 (0 Ω) removed to use on‐board 12 MHz crystal

R28 (0 Ω) populated, R27 (0 Ω) removed to set VDDW to 3.3 V I/O

Power Distribution

In the default mode, the EV‐OXU200 receives all its power from the 5 V pins of the PC104 connector. The 5 V supply drives the 3.3 V DC regulator. Alternative power‐supply options are described below.

The power for the core voltage (VDD1.8 pins) comes from the OXU200’s internal regulator. This regulator can also be selected to drive the 1.8 V I/O option for VDDW.

5 V Power Supply

The EV‐OXU200 5 V power is supplied by one of two sources:

1. From the PC104 connector 5 V pins: J2.D16, J3.B29, J3.B3 (default setting).

2. From an external power supply connected to JP5.3. To enable this mode, remove R1 and R3 (0 Ω). Protection circuitry is not provided.

3.3 V Power Supply

The EV‐OXU200 3.3 V power is supplied by a 5 V‐to‐3.3 V DC regulator (U5).

1.8 V Core Power Supply

The EV‐OXU200 1.8 V power is supplied by the internal regulator via VREGOUT. No external power supply should be connected to drive 1.8 V or else chip damage will result.


EV-OXU200-PCI and EV-OXU200 Evaluation Board User Guide EV-OXU200 Evaluation Board

3.3/1.8 V VDDW Wide Range I/O Power Supply

The EV‐OXU200 provides either 1.8 V or 3.3 V for VDDW, the wide range power. The voltage is selected through the intallation or removal of resistors as described below. While the OXU200 allows any voltage in this range, any other value is customer specific and is not directly supported by this evaluation board. The EV‐OXU200 VDDW power is supplied by one of two sources:

1. From the 3.3 V power rail (default setting). Install R28 (0 Ω) and remove R27 (0 Ω).

2. From the OXU200’s 1.8 V internal regulator. Install R27 (0 Ω) and remove R28 (0 Ω).

Oscillator Input

The EV‐OXU200 uses a 12 MHz crystal at Y1 for the OXU200 OSC1/OSC2 clock source.

A 12 MHz oscillator can be soldered at the U6/U7 dual‐footprint by the customer and used as the OXU200 clock source. To enable this mode, install R29 (0 Ω) and remove R31 (0 Ω). Also, remove R30 (0 Ω)because the OSC2 pin must be floating in this configuration. Below are the oscillator part numbers that Oxford Semiconductor has used for internal design and testing. Other components meeting the OXU200 requirements may be used (see the OXU210HP, OXU140CM, OXU121HP, and OXU200 External Crystal Selection application note).

12 MHz crystal: Citizen America, HCM49‐12.000MABJUT, 18 pF internal load (RoHS compliant)

12 MHz oscillator: Ecliptek, EH1345HSTS‐12.000M, 50 ppm, 8‐pin DIP (RoHS compliant)

OXU200 Reset

The /RESET pin of the OXU200 is brought out to the PC104 connector to allow control of the /RESET through a CPU GPIO. /RESET can also be asserted manually using the S1 switch.

DP/DM Signals

Pads are provided for the DP/DM signals to enable use of an external ESD protection device. The pad locations are designated U2 on the schematic and circuit board. See the OXU200 External ESD Protection application note

These traces are impedance controlled to 90 Ω + 10%


EV-OXU200 Evaluation Board EV-OXU200-PCI and EV-OXU200 Evaluation Board User Guide

VBUS Over-Voltage Protection

Besides the ESD transient protection provided by the external ESD devices, the OXU200 VBUS pin is also protected against steady‐state voltages above 5.1 V (typical) by the voltage divider resistor (R32 = 390 Ω) and the Zener diode D2. When the OXU200 is connected to a host, the Zener diode protects the OXU200 from damage.

Zener diode: ON Semiconductor® BZX84C5V1LT1G, 225 mW, 5.1 V breakdown

LEDs The EV‐OXU200 has the following LEDs to enable monitoring of the normal operation of the board:

D5: 1.8 V Power Rail Indicator



D1: Peripheral Port VBUS Power Indicator

Mounting Holes

The EV‐OXU200 board has four un‐plated standoff holes, one near each corner of the board. Each hole is 0.146 inch in diameter. The placement matches the PCI104 PCI board which together make the EV‐OXU200‐PCI.

Test Points The following test points are furnished on the EV‐OXU200:

Ground test points JP1, JP2, JP6, and JP7

VBUS 5 V test point TP1

Power supplies 5 V (JP5), 3.3 V (JP4), 1.8 V (JP3), and VDDW test point TP2

All the microprocessor signals are routed to Mictor connector J1. The Mictor connectors are not installed but can be obtained from AMP/Tyco Electronics Part Number: 2‐5767004‐2 Description: Receptacle, 38 positions, .025 vertical


Chapter 3

PCI104 Bridge Board

Overview The PCI104 Bridge Board, measured at 5.55 in. (140.9 mm) by 3.00 in. (76.2 mm), can be employed to:

Evaluate the Oxford Semiconductor OXU200 USB peripheral controller

Run OXU200 demonstrations

Develop user software for OXU200‐based applications

Serve as a subassembly in an OEM product to provide USB OTG and host controller functionality

While the EV‐OXU200‐PCI can be used to evaluate the OXU200, it will not result in optimal performance due to the long access times of the PCI bus. For optimal performance evaluation, the OXU200 should be placed directly on the system bus using the EV‐OXU200 board as described in Chapter 2 .

The PCI104 board bridges between the PCI bus and the OXU200 local bus. The local bus is routed out to the standard PC104 connectors (J1 and J2). The EV‐OXU200 interfaces to the PCI104 Bridge Card via these three female connectors. Another proprietary, non‐PC104 connector (J3) was added to support a 32‐bit interface and additional signals not included in the PC104 signal definition. Figure 3‐1 shows the PCI104 block diagram.


PCI104 Bridge Board EV-OXU200-PCI and EV-OXU200 Evaluation Board User Guide

Figure 3-1 PCI104 Bridge Board

The PCI104 board uses the PCI9030 bridge device. The PCI configuration registers are stored in an on‐board EEPROM.

Power Distribution

The PCI104 board receives its 5 V power from the standard PCI bus edge connector (U2 – eight 5 V pins). The 5 V supply is routed directly to the EV‐OXU200 via the PC104 connectors (J1.D16, J2.B3, J2.B29).

The PCI104 board 3.3 V power is supplied by one of two sources:

1. 5.0 V‐to‐3.3 V DC regulator (U1). Install jumper on JP2 pin 1‐2, 3‐4 (default setting) and remove 5‐6 and 7‐8.

2. The standard PCI bus edge connector (U2 – twelve 3.3 V pins). Install jumper on JP2 pin 5‐6, 7‐8 and remove 1‐2 and 3‐4.

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PQFP176

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EV-OXU200-PCI and EV-OXU200 Evaluation Board User Guide PCI104 Bridge Board

Local Bus Configuration

The PCI9030 local bus is connected directly to the EV‐OXU200 board via the PC104 connectors. Refer to the PCI9030 Data Book for a detailed explanation of its operation.

PCI9030 CS1L chip select is routed to the EV‐OXU200. Register Space 1 of the PCI9030 controls CS1L. The number values programmed into Space 1 registers of the EEPROM are shown below. Changing values in the EEPROM requires an application from PLX operating across the PCI bus. Space 1 has 16‐bit local and PCI space and contains 32 Kb memory space size. There is no prefetch on space 1.

Space 1 Range 0xFFFF_8000

Space 1 Remap 0x0000_0001

Space 1 Descriptor 0x4040_A040

Space 1 Base Address 0x0000_4001

Space 1 Initialization Control 0x0024_9864

The local timing is one WAIT state for READs (address‐to‐data) and one for WRITEs (address‐to‐data) to make the PCI104 backwards compatible with previous Oxford Semiconductor chips. The other WAIT states are: zero RD (data‐to‐data), one RD/WR (data‐to‐address), zero WR (data‐to‐data), and one WR cycle hold. An optimum bus access will not create a significant increase in performance in the EV‐OXU200‐PCI system. For better performance evaluation, the OXU200 should be embedded directly on the system bus using the EV‐OXU200 board.

Local Bus Speed

LCLK, the local bus clock, operates at frequencies up to 60 MHz and is asynchronous to the PCI bus clock, BCLK. BCLK is routed back into LCLK, setting the default local bus speed at 33 MHz.

An oscillator up to 60 MHz can be soldered at the U4/U5 dual‐footprint by the customer to increase the local bus speed. R10 (33 ohms) must be installed and R11 removed in this configuration. More WAIT states may have to be added to meet the OXU200 interface timing when increasing the local bus frequency.

LEDs The PCI104 has two LEDs to enable verification of the normal operation of the board.



Mounting Holes

The PCI104 board has four un‐plated standoff holes, one near each corner of the board. Each hole is 0.146” in diameter. The placement matches the EV‐OXU200 evaluation board which together make the EV‐OXU200‐PCI.


PCI104 Bridge Board EV-OXU200-PCI and EV-OXU200 Evaluation Board User Guide



Chapter 4

Schematics

Overview This chapter provides the EV‐OXU200 and PCI104 schematics. The EV‐OXU200 uses a dual footprint so either the LQFP100 (U4) or the BGA64 (U3) package can be installed, but not both.


Schematics EV-OXU200-PCI and EV-OXU200 Evaluation Board User Guide

Figure 4-1 EV-OXU200 Top-Level Schematic

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L

DR

QA

CK

WR

L

CS

1L

D[1

5:0]


EV-OXU200-PCI and EV-OXU200 Evaluation Board User Guide Schematics

Figure 4-2 EV-OXU200 Test Headers

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

GROUND TEST POINTS

Distribute the TestPoints on top side

MH's are to be .146"

non-plated thru

holes.

Mictor Test Headers

TEST HEADERS

Mictor headers have

internal 50K

pull-ups.

Female Mictor Connector

AMP 2-5767004-2

gold-plated

AMP 767054-1

SC

-OX

200-

A1-

002

1.0

EV

-OX

U20

0 C

ard

: Mic

tor T

est H

eade

rs

26

Frid

ay, D

ecem

ber 2

2, 2

006

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:S

heet

of

A[1

0:1]

RD

L

INTL

WR

L

D[1

5:0]

DR

QA

CK

CS

1L

A5

A10

AC

K

A7

D5

INTL

D1

A1

A[1

0:1]

D15

D10

RD

L

D7

D13

D[1

5:0]

A6

D3

D6

D4

WR

L

D14

D11

A3

A8

D2

A4

D9

DR

Q

A2

A9

CS

1L

D12

D8

D0 CS

1L

INTL

AC

K

D[1

5:0]

DR

Q

A[1

0:1]

RD

LW

RL

J1 Mic

tor3

8

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38

39

4041

4243

JP7

1X2

2 1

V9

1

JP6

1X2

2 1

JP1

1X2

2 1

V7

1

JP2

1X2

2 1

MH

4

MH

2

MH

1

MH

3



Figure 4-3 EV-OXU200 PC104 Connectors

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

Bypass caps for

PC-104 connector

TPS3801K33DCKR

TPS3801J25DCKR

TPS3801E18DCKR

200ms delay

Male headers placed on

bottom side of board.

Male headers placed on

bottom side of board.

PCI104 Connector

Remove to use external

5V power supply.

SC

-OX

200-

A1-

003

1.0

EV

-OX

U20

0 C

ard

: PC

I104

Con

nect

or

36

Frid

ay, D

ecem

ber 2

2, 2

006

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:S

heet

of

SA

7

5P0V

CC

_CO

NN

SD

11

SD

1

GP

IO2

GP

IO

SA

3

SD

4

SD

15

SD

0

WR

L

SA

0

SD

2

SA

2

RE

SE

T_C

ON

N

SD

13S

D12

SA

6

SA

11S

A12

SD

8

RE

SE

T_R

SA

5

SA

9

SD

5

INTL

SA

4

SA

8

SD

7

SD

14

RD

L

SA

10

SD

6

CS

1L

DM

A_D

RQ

0

SA

1

SD

3

SD

10S

D9

SA

10

SA

7S

A8

SA

2

SA

5S

A6

SA

9

SA

4S

A3

SA

1

SD

5

SD

10

SD

13S

D12

SD

7

SD

11

SD

1

SD

15

SD

2

SD

0

SD

3S

D4

SD

8S

D9

SD

6

SD

14

DM

A_A

CK

0

RE

AD

YL

CS

2L

CS

3L

5P0V

CC

_CO

NN

5P0V

CC

VD

DW

VD

DW

VD

DW

VD

DW

VD

DW

VD

DW

VD

DW

VD

DW

VD

DW

VD

DW

R3

0_12

06R

_120

6

R13

DN

I_10

K

U1

TPS3

801

4 12

53

VDD GND1GND2

MR

RE

SE

T

R10

DN

I_10

K

S1

SW

_KT1

1P3J

M

2 1

R1

0_12

06R

_120

6

R9

10K

V1

1

C5 0.1u

F

R18

DN

I_10

K

R15

10K

R6

DN

I_10

K

R14

DN

I_10

K

V5

1

R4

10K

R17

20

V8

1

J3

PC

104_

2X32

_Hea

der

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

A32

B1

B2

B3

B4

B5

B6

B7

B8

B9

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

B27

B28

B29

B30

B31

B32

V3

1

R11

DN

I_10

K

R7

DN

I_10

K

+C

34.

7uF

V4

1

C10

0.1u

F

R16

130 R

12D

NI_

10K

R8 DN

I_10

K

V2

1

R5

DN

I_10

K

J2

PC

104_

2X20

_Hea

der

C0

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

V6

1

C1 0.1u

F

C6

22pF

C4 0.1u

F

C7 22

00pF

RE

SE

TL

AC

K

RD

L

DR

Q

INTL

WR

L

CS

1L

SA

[10:

1]

GP

IO

SD

[15:

0]



Figure 4-4 OXU200 Schematic

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

OXU200

Place components as

close to the OXU200

as possible.

De

co

up

lin

g C

ap

ac

ito

rs

Place USB_B

connector on

bottom of PCB.

Place 4.7uF cap near VREGOUT

signal of OXU200_BGA64 at A8,

OXU200_LQFP100 at 80.

SC

-OX

200-

A1-

004

1.0

EV

-OX

U20

0 C

ard

: OX

U20

0

46

Frid

ay, D

ecem

ber 2

2, 2

006

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:S

heet

of

P_O

SC

2

P_O

SC

2

P_TE

ST

P_R

RE

F

P_G

PIO

P_I

NTL

P_R

ES

ETL

P_D

RQ

P_O

SC

1P

_OS

C2

P_W

RL

P_A

CK

P_D

PP

_DM

P_D

M_S

BP

_DP

_SB

P_D

6

P_O

SC

1

P_A

9

P_D

1

P_D

5

P_D

10

P_A

4

P_D

11

P_A

1

P_D

7

P_D

2

P_A

8

P_D

15

P_C

S1L

P_A

2

P_A

6

P_D

12

P_A

10

P_D

8

P_D

0

P_A

5

P_D

3

P_A

3

P_D

9

P_D

13

P_R

DL P_D

14

P_A

7

P_D

4

P_XM

OD

E

P_D

M_S

BP

_DP

_SB

P_D

RQ

P_A

CK

P_TE

STP_

XMO

DE

P_I

NTL

P_G

PIO

P_R

DL

P_C

S1L

P_W

RL

P_R

ES

ETL

VD

VB

US

2

P_V

BU

S

VB

US

5V

P_D

M

P_V

BU

S

P_D

P

P_D

PP

_DM

P_R

RE

F

P_D

5

P_D

12

P_A

7

P_D

10

P_D

2

P_D

13

P_A

2

P_A

4

P_A

10

P_D

6

P_D

15

P_D

11

P_D

8

P_D

0

P_A

9

P_D

14

P_A

6

P_A

8

P_D

3

P_D

7

P_A

1

P_A

5

P_D

1

P_A

3

P_D

4

P_D

9

P_A

CK

P_D

RQ

P_TE

STP_

XMO

DE

P_I

NTL

P_G

PIO

P_D

0

P_A

9

P_D

14

P_D

3

P_D

7

P_D

15

P_D

11

P_D

8

P_D

1

P_D

13

P_A

6

P_A

8

P_A

10

P_D

6P

_D5

P_D

9

P_A

3P

_A2

P_A

4

P_D

4

P_A

1

P_D

2

P_A

5

P_D

12

P_A

7

P_D

10

P_W

RL

P_R

ES

ETL

P_R

DL

P_C

S1L

P_R

RE

F

P_V

BU

S

P_R

SV

D2

P_R

SV

D2

P_R

SV

D1

P_R

SV

D0

P_R

SV

D0

P_R

SV

D1

P_R

SV

D2

P_R

SV

D1 P_R

SV

D0

1P8V

DD

3P3V

CC

3P3V

CC

1P8V

DD

VD

DW

VD

DW

1P8V

DD

3P3V

CC

5P0V

CC

VD

DW

SB

11

2

BL21

2

C11

0.1u

F

C30

0.1u

F

+C

14 4.7u

F

C25

0.1u

F

C12

100p

F

U4

OX

U20

0_LQ

FP10

0

865049

39 2120 1932 30 29 28 25 24 23 16 15 14 13 11 10 9 8 5 4 3 2 99 98 97 96 87

55 54 62

59

77 76 5861

27121

56 437536072 18 40 3117 4842 473334 3536 2263

8079

38 5237 41 51 65 75 83

57 66

64 6970 73

74

78 8182

84 85

88 89 9190 92 93 94

95100

45 4467 71 68 46 6 26

RE

SE

T

OS

C1

OS

C2

CS

RD

WR

INT

A8

A7

A6

A5

A4

A3

A2

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

TES

T

NC

55N

C54

NC

62

NC

59

NC

77N

C76

NC

58N

C61

VS

S27

VS

S12

VS

S1

VD

D33

_56

AV

DD

33_4

3

VD

DW

_7

VD

D18

_53

NC

60V

BU

S

VD

D18

_18

VD

D18

_40

VD

DW

_31

VD

DW

_17

AV

DD

33_4

8A

VS

S42

AV

SS

47

A9

NC

34

A10

NC

36

A1

NC

63

VR

EG

OU

TN

C79

NC

38N

C52

NC

37

VS

S41

VS

S51

VS

S65

VS

S75

VS

S83

VD

D18

_57

VD

D18

_66

XM

OD

E

AV

SS

69A

VD

D33

_70

AV

DD

33_7

3A

VS

S74

VD

D33

_78

AV

DD

33_8

1A

VS

S82

VD

D18

_84

VD

DW

_85

GP

IO

DR

Q

RS

VD

0

AC

K

NC

92R

SV

D2

RS

VD

1

VD

DW

_95

VD

D18

_100DM DP

NC

67

NC

71N

C68

RR

EF

VD

D18

_6

VD

DW

_26

C37

0.1u

F

U2

MAX

3207

E

1 4

2 3 65IO

_A

IO_B

GN

DN

C3

NC

6

VC

C

R22

100

C38

0.1u

F

SB

21

2

C35

0.1u

F

C29

0.1u

F

C33

0.1u

F

TP1

C41

0.1u

F

R26

12K

_1%

R24

82

OX

U20

0_B

GA6

4

U3

F3 H1

C7

D4E4

C5

G5

D8

A8

B1

F6 D3

G4 A1

B8

G8 E3

C8

G1 F1H2

C6

G2

G7B3

A2

E2

A3

F7

F5

E8

F8

F2

H5

H3 B6

D1

C1

H7

D7

G3

D5 B5

C2

E6

H8

A6

A4

D6

H4

C3 A5

E1

E5

C4F4 D2 B2

B7

E7

A7

B4

G6

H6

RD

A4

VD

D33

_C7

VS

S_D

4

D13

RS

VD

1

AV

SS

_G5

XM

OD

E

VR

EG

OU

T

VD

D18

_B1

CS

D10

NC

_G4

D4

RE

SE

T

OS

C1

D14

VB

US

A2

INT

A5

VD

D33

_C6

A1

AV

SS

_G7

D1

D2

D15

D0

RR

EF

A9

NC

_E8

NC

_F8

WR

AV

DD

33_H

5

A8

DR

Q

D11

D8

AV

DD

33_H

7

VS

S_D

7

A7

D12

RS

VD

0

D7

VD

D18

_E6

OS

C2

GP

IO

NC

_A4

VD

DW

_D6

A10

D6

AC

K

VD

DW

_E1

A3

D3

A6

D9

D5

TES

T

VS

S_E

7

AV

SS

_A7

RS

VD

2

DP

DM

C24

0.1u

F

C27

0.1u

F

C34

0.1u

F

R19

82

B L1

12

C2

0.01

uF

C9

100p

F

D1

GR

EE

N_L

EDC

40

0.1u

F

C23

0.1u

F

C31

0.1u

F

R32

390

C32

0.1u

F

R2

330

C28

0.1u

F

C39

0.1u

F

C36

0.1u

F

R33

100

J4 US

B_B

321 4 5

D+

D-

+5V

GN

DS

HLD

R21

100

C42

0.1u

F

R20

82

D2

BZX

84C

5V1L

T1G

1 23

A NC

C

C43

0.1u

F

C8

100p

F R23

100

R25

100

C26

0.1u

F

P_O

SC

1

P_O

SC

2

P_R

DL

P_C

S1L

P_W

RL

P_D

[15:

0]

P_A

[10:

1]

P_R

ES

ETL

P_G

PIO

P_I

NTL

P_A

CK

P_D

RQ



Figure 4-5 EV-OXU200 Clocks

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

ECLIPTEK EH26 SERIES

OR EQUIVALENT

12 MHz

Oscillator -

3.3V

12 Mhz

Crystal

ECLIPTEK EH1345HSTS-xx.xxxM

OR EQUIVALENT. Use a DIP

socket for this location.

Clocks

Citizen Corporation P/N:

HCM49-12.000MABJUT.

Place resistors close to

crystal. Install only

one resistor at a time

on OSC1.

Place resistor near

oscillator.

SC

-OX

200-

A1-0

051.

0

EV

-OX

U20

0 C

ard

: Clo

cks

56

Mon

day,

Jan

uary

29,

200

7

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:S

heet

of

OS

C2_

CR

YS

TAL

OS

C1_

CR

YS

TAL

OS

C1_

DIP

3P3V

CC

R31

0

C22

0.1u

F

C15

22pF

R29

DN

I_0

U7

DN

I_H

alf_

size

_DIP

1

4

5

8

EN

GND

OU

T

VCC

R30

0

U6

DN

I_5x

7mm

_sm

_cer

amic

1

2

3

4

EN

GND

OU

T

VCC

R34

33

R38

10K

Y1

Cry

stal

_12M

Hz

1 2

C16

22pF

OS

C1

OS

C2



Figure 4-6 EV-OXU200 Power Distribution

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

5V to 3.3V Voltage Conversion

3.3V Output

1.8V or 3.3V I/O

1.8V Core

Power Headers

Power Indicators

Power Distribution

Install resistor

for 3.3V IO.

Install resistor to use

the internal VREGOUT

for the 1.8V IO.

Only install one

resistor at a time.

Place 4.7uF cap

near TP1.

SC

-OX

200-

A1-0

061.

0

EV

-OX

U20

0 C

ard

: Pow

er D

istri

butio

n

66

Frid

ay, D

ecem

ber 2

2, 2

006

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:S

heet

of

VD

5P0

VD

3P3

5P0V

CC

3P3V

CC

5P0V

CC

5P0V

CC

3P3V

CC

3P3V

CC

1P8V

DD

3P3V

CC

3P3V

CC

1P8V

DD

VD

DW

1P8V

DD

C21

0.00

1uF

Q1

BC

R10

8

1

23

R28

0_12

06R

_120

6

U5

LMS

1587

IS3.

3NO

PB

3

1

2 4V

IN

GND

VO

UT

TAB

+C

174.

7uF

D4

GR

EE

N_L

ED

R35

150

R36

330

JP3

1X3

3 2 1

C19 0.1u

F

R27

DN

I_0_

1206

R_1

206

D3

GR

EE

N_L

ED

TP2

+C

13 4.7u

F

R37

100

JP4

1X3

3 2 1

C20

0.1u

F+

C18

33uF

JP5

1X3

3 2 1

D5

GR

EE

N_L

ED



Figure 4-7 PCI104 Top-Level Schematic

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

PCI104 BRIDGE CARD TOP LEVEL

PCLK must be 2.5"

in length

GROUND TEST POINTS

Distribute the TestPoints

near top side and corners

MH's are to be .146" non-plated thru holes.

MH's are to be .177" plated thru holes.

These holes are for the PCI front plate mounting.

SC

-PC

I104

-A1-

001

2.0

PC

I104

Car

d: T

op L

evel

15

Tues

day,

Oct

ober

17,

200

6

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:S

heet

of

PC

104_

CO

NN

PC

104_

CO

NN

WR

LR

DL

LIN

TI2

LRE

SE

TOL

CS

2L

CS

1L

LA[1

9:2]

RE

AD

YL

AD

SL

LD[3

1:0]

GP

IO[8

:4]

CS

3L

LIN

TI1

LBE

0LLB

E1L

P1_

PC

I_E

dge_

Con

nect

or

PC

I_E

dge_

Con

nect

or

PC

LK

AD

[31:

0]

C/B

E3L

C/B

E2L

IRD

YL

DE

VS

ELL

LOC

KL

PE

RR

L

SE

RR

L

C/B

E1L

VIO

PC

I

C/B

E0L

PA

R

STO

PL

FRA

ME

L

TRD

YL

IDS

EL

RS

TL

INTA

L

PM

EL

P2_

PLX9

030

PLX9

030

LD[3

1:0]

VIO

PC

I

PC

LK

RS

TL

IDS

EL

C/B

E0L

AD

[31:

0]

C/B

E1L

C/B

E2L

C/B

E3L

FRA

ME

L

IRD

YL

TRD

YL

STO

PL

DE

VS

ELL

PE

RR

L

SE

RR

L

LOC

KL

PA

R

INTA

L

PM

EL

AD

SL

RD

LW

RL

RE

AD

YL

LRE

SE

TOL

CS

0L

CS

1L

CS

2L

LIN

TI1

LA[1

9:2]

CS

3L

GP

IO[8

:4]

LBE

0LLB

E1L

LIN

TI2

P6_

Exp

ansi

on_R

OM

Exp

ansi

on_R

OM

XR

OM

_A[1

9:2]

XR

OM

_D[7

:0]

XR

OM

_CEL

XRO

M_O

EL

XR

OM

_WEL

XR

OM

_RES

ETL

LBE

1LLB

E0L

C/B

E2L

VIO

PC

I

AD

[31:

0]

IRD

YL

LOC

KL

PM

EL

C/B

E0L

C/B

E3L

INTA

L

RE

AD

YL

RS

TL

DE

VS

ELL

LRE

SE

TOL

CS

1L

IDS

EL

PA

R

PC

LK

TRD

YL

PE

RR

L

SE

RR

L

AD

SL

CS

2LC

/BE

1L

FRA

ME

L

STO

PL

LIN

TI1

CS

3L

GP

OI[8

:4]

LBE

0L

LA[1

9:2]

LIN

TI2

WR

L

LD4

RD

L

LD3

LD6

LA[1

9:2]

RD

L

LD[7

:0]

LD1

LD5

LD0

WR

L

LD2

LBE

1L

LD7

LD[3

1:0]

CS

0LC

S0L

LRE

SE

TOL

MH

6

MH

4

JP3

1X2

2 1M

H2

MH

1

JP1

1X2

2 1

JP5

1X2

2 1

JP6

1X2

2 1

MH

3

MH

5



Figure 4-8 PCI104 PCI Connector

A A

B B

C C

D D

E E

44

33

22

11

5V to 3.3V VoltageConversion

Deco

up

lin

g C

ap

acit

ors

PRSNT1#

PRSNT2#

Function

GND

OPEN

OPEN

GND

GND

OPEN

OPEN

GND

no adapter board

15W on all rails

25W on all rails

7.5W on all rails

Power Indicators

NEAR VIO_A10

NEAR VIO_A16

NEAR VIO_A59

NEAR VIO_B19

PLACE NEAR CARD EDGE CONNECTOR PINS

PLX9030 VIO PIN

Power Headers

7-8

5-6

3-4

1-2

3.3V Board Power

Taken from PCI Bus

3.3V Board Power

Taken from Regulator

JP

Function

NOTE:

The mating daughtercard must have a

backside keep-out area for

sufficient clearance of the Jumper.

LT1587CM-3.3

2A

max.

PCI Edge Connector

SC

-PC

I104

-A1-

002

2.0

PC

I104

Car

d : P

CI C

ard

Edg

e C

onne

ctor

25

Tues

day,

Oct

ober

17,

200

6

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:S

heet

of

VIO

PC

I

3.3V

AU

X

VIO

PC

I

VIO

PC

I

PC

I_P

ME

L

VIO

PC

I

VIO

PC

I

3.3V

AU

X

VD

5

VD

3

PC

I_TD

D

5P0V

CC

AD

25

AD

16

AD

8

AD

12A

D13

AD

30A

D29

AD

6

AD

18

AD

23

AD

1

AD

22

AD

31

AD

26

AD

14

AD

10

AD

0

AD

19A

D21

AD

17

AD

4

AD

7

AD

9

AD

28

AD

24

AD

2

AD

15

AD

11

AD

27

AD

3A

D5

AD

20

3P3V

_CO

NN

3P3V

_S

5P0V

CC

5P0V

CC

3P3V

CC

5P0V

CC

3P3V

PC

I

3P3V

PC

I

3P3V

PC

I

3P3V

PC

I

3P3V

PC

I

5P0V

CC

5P0V

CC

3P3V

CC

5P0V

CC

3P3V

CC

3P3V

CC

3P3V

CC

C56

0.01

uF

TP2

C24

0.01

uF

C19

0.01

uF

C57

0.01

uF

C59

0.04

7uF

C3

0.1u

F

+C

433

uF

C25

0.01

uF

R7

DN

I_24

0K

C22

0.01

uF

C58

0.04

7uF

+C

233

uFC

10.

1uF

3.3V KEY

5.0V KEY

U2

PC

I_32

BIT

_ED

GE

_UN

V

A1

B1

A2

B2

A3

B3

A4

B4

A5

B5

A6

B6

A7

B7

A8

B8

A9

B9

A10

B10

A11

B11

A14

B14

A15

B15

A16

B16

A17

B17

A18

B18

A19

B19

A20

B20

A21

B21

A22

B22

A23

B23

A24

B24

A25

B25

A26

B26

A27

B27

A28

B28

A29

B29

A30

B30

A31

B31

A32

B32

A33

B33

A34

B34

A35

B35

A36

B36

A37

B37

A38

B38

A39

B39

A40

B40

A41

B41

A42

B42

A43

B43

A44

B44

A45

B45

A46

B46

A47

B47

A48

B48

A49

B49

A52

B52

A53

B53

A54

B54

A55

B55

A56

B56

A57

B57

A58

B58

A59

B59

A60

B60

A61

B61

A62

B62

TRS

T#-1

2V+1

2VTC

KTM

SG

ND

_B3

TDI

TDO

+5V

_A5

+5V

_B5

INTA

#+5

V_B

6IN

TC#

INTB

#+5

V_A

8IN

TD#

RE

SE

RV

ED

_A9

PR

SN

T1#

VIO

_A10

RE

SE

RV

ED

_B10

RE

SE

RV

ED

_A11

PR

SN

T2#

3.3V

AU

XR

ES

ER

VE

D_B

14R

ST#

GN

D_B

15V

IO_A

16C

LKG

NT#

GN

D_B

17G

ND

_A18

RE

Q#

PM

E#

VIO

_B19

AD

[30]

AD

[31]

+3.3

V_A

21A

D[2

9]A

D[2

8]G

ND

_B22

AD

[26]

AD

[27]

GN

D_A

24A

D[2

5]A

D[2

4]+3

.3V

_B25

IDS

EL

C/B

E[3

]#+3

.3V

_A27

AD

[23]

AD

[22]

GN

D_B

28A

D[2

0]A

D[2

1]G

ND

_A30

AD

[19]

AD

[18]

+3.3

V_B

31A

D[1

6]A

D[1

7]+3

.3V

_A33

C/B

E[2

]#FR

AM

E#

GN

D_B

34G

ND

_A35

IRD

Y#

TRD

Y#

+3.3

V_B

36G

ND

_A37

DE

VS

EL#

STO

P#

GN

D_B

38+3

.3V

_A39

LOC

K#

RE

SE

RV

ED

_A40

PE

RR

#R

ES

ER

VE

D_A

41+3

.3V

_B41

GN

D_A

42S

ER

R#

PA

R+3

.3V

_B43

AD

[15]

C/B

E[1

]#+3

.3V

_A45

AD

[14]

AD

[13]

GN

D_B

46A

D[1

1]A

D[1

2]G

ND

_A48

AD

[10]

AD

[09]

M66

EN

C/B

E[0

]#A

D[0

8]+3

.3V

_A53

AD

[07]

AD

[06]

+3.3

V_B

54A

D[0

4]A

D[0

5]G

ND

_A56

AD

[03]

AD

[02]

GN

D_B

57A

D[0

0]A

D[0

1]V

IO_A

59V

IO_B

59R

EQ

64#

AC

K64

#+5

V_A

61+5

V_B

61+5

V_A

62+5

V_B

62JP

73 2 1

U1

LMS

1587

IS-3

.3

31

2 4V

INGND

VO

UT

TAB

R9

DN

I_24

0K

JP4

3 2 1

TP3

R5

300

C32

0.01

uF

C36

0.01

uF

C11

0.01

uF

+C

56.

8uF

C41

0.01

uF

C23

0.04

7uF

C7

220

uF

R4

150

C42

0.01

uF

R8 10K

C13

DN

I_0.

1uF

C35

0.01

uF

D1

GR

EE

N2

1

U6

DN

I_FD

N33

5N

3

1 2D

rain

Gat

e

Sou

rce

C10

0.01

uF

TP1

D2

GR

EE

N2

1

C43

0.01

uF

C62

0.01

uF

CF1

0.02

2uF

C61

0.04

7uF

C63

0.01

uF

C48

0.01

uF

C18

0.01

uF

R6

0

C50

0.01

uF

C21

0.01

uF

C60

0.01

uF

JP2

2X4

21

4357

8 6

PC

LK3 A

D[3

1:0]

3

C/B

E3L

3

C/B

E2L

3

IRD

YL

3

DE

VS

ELL

3

LOC

KL

3P

ER

RL

3

SE

RR

L3

C/B

E1L

3

C/B

E0L

3

PA

R3

STO

PL3

FRA

ME

L3

TRD

YL

3

IDS

EL

3

RS

TL3

INTA

L3

PM

EL3

VIO

PC

I3



Figure 4-9 PCI9030 Bridge Chip

A A

B B

C C

D D

E E

44

33

22

11

JTAG Port

- PIN 76 (MODE) GROUNDED = non-multiplexed bus mode

- PIN 112 (BD_SEL_TEST) pulled low = outputs remain in

normal operation and PCI Hot Swap precharge resistors

are not active.

Deco

up

lin

g C

ap

acit

ors

+ XROM CHIP SELECT = CS0L

+ OTG243 CHIP SELECT = CS1L

+ ispLSI CHIP SELECT = CS2L

+ spare = CS3L

LOCAL DATA BUS

LOCAL ADDRESS BUS

SYSTEM DATA BUS

BCLK0 must be 2X

the length CS1L

NOTE:

All other signals going to the PC104

connector must be pulled-up on

the daughtercard.

ECLIPTEK EC28 SERIES

OR EQUIVALENT

Place near PLX9030.

Remove when using

external oscillator.

Place near BCLKO_R

resistor and near OSC

Option to run local bus

up to max of 60MHz

DIP8 Socket

for 93CS66

1

PLX9030

SC

-PC

I104

-A1-

003

2.0

PC

I104

Car

d : P

LX90

30 P

CI I

nter

face

and

EE

PR

OM 3

5Tu

esda

y, O

ctob

er 1

7, 2

006

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:S

heet

of

PR

E

BTE

RM

LR

EA

DY

LLW

/RL

PE

TMS

LA21

GP

IO6

AD

11

LRE

QAD

0

AD

14

AD

18

LBE

0L

MO

DE

GP

IO0/

WA

ITO

L

TDI

LA22

AD

8

AD

16

AD

28

AD

31

LA23

AD

13

AD

22

EN

UM

L

BC

LKO

EE

SKA

D29

LPM

ESET

AD

9

AD

26

AD

30

LBE

3L

EE

CSA

D24

EE

DOA

D1

ALE

GP

IO7

AD

23

AD

4

AD

17

LBE

2L

TEST

TRST

L

AD

10

AD

12

TDO

AD

3

GP

IO1/

LLO

CK

OL

GP

IO4

AD

25

AD

27

BLA

STL

AD

19A

D20

GP

IO5

AD

7

AD

21

AD

6

LA20

AD

2

AD

5

AD

15

TCK

LW/R

L

BTE

RM

L

EE

DI

LED

ON

L

LD1

LD27

LA9

LD12

LD16

LD14

LD15

LA5

LA8

LD19

LD23

LD4

LD28

LA6

LA18

LD25

LD6

LD0

LD24

LA16

LD2

LD9

LD13

LD29

LA4

LD8

LA12

LD7

LA10

LA14

LD10

LA3

LD20

LD17

LD22

LD21

LA17

LD3

LA7

LA15

LD26

LD30

LA19

LD18

LA13

LD31

LA11

LD11

LA2

LD5

CP

CIS

W

LGN

T

GP

IO8

BC

LKO

_R

BLA

STL

GP

IO0/

WA

ITO

L

ALE

GP

IO1/

LLO

CK

OL

LGN

TLR

EQ

GP

IO5

GP

IO4

GP

IO6

GP

IO7

LA21

LA23

LA22

LA20

GP

IO8

LBE

1L

LIN

TI2

LIN

TI1

CS

0LC

S1L

CS

2LC

S3L

BC

LKO

LBE

2LLB

E1L

LBE

0L

LBE

3L

3P3V

CC

3P3V

CC

3P3V

CC

3P3V

CC

3P3V

CC

3P3V

CC

3P3V

CC

3P3V

CC

3P3V

CC

3P3V

CC

3P3V

CC

3P3V

CC

3P3V

CC

3P3V

CC

3P3V

CC

3P3V

CC

3P3V

CC

C28

0.1u

F

R31

150

R17

10K

R1

10K

C34

0.01

uF

R18

10K

C31

0.01

uF

PC

I S

ign

als

PC

I S

ign

als

PC

I S

ign

als

PC

I S

ign

als

PC

I S

ign

als

PC

I9030

U7

PLX9

030-

176P

QFP

152

144

143

151

139

154

150

153

138

142

158

172

140

160

161

171 8

112

145 76

149

60 59 58 55

51169

10 155

56

52173

174

175

23416171830333435363738394142434647484950 5

4532

85

101100

70

13

117133

31

162

170

57

111215 9 28

66

44

6

78

257

88

2019

113

22

122

21

132

29

146

2440 23

128

26 27

137

136

135

13484 131

130

12995 127

125

124

12393 12192 120

119

118

11691 115

114

11190 110

109

108

10789 106

10587 86 83 81104 80102 7999 98 7797 96 74 73 72 69 68 6782 65 64 63 62 61

114

163176

159

165

166

168

164

167

53

75 141

94

147

148

157

156

54 71

103

126

LIN

Ti1

BTE

RM

#

RE

AD

Y#

LRE

Q

BLA

ST#

GP

IO0/

WA

ITo#

LGN

T

LIN

Ti2

AD

S#

LW/R

#

EE

CS

PC

LK

WR

#

EE

SK

EE

DI

RS

T#ID

SE

L

BD

_SE

L_TE

ST

LCLK

MO

DE

LRE

SE

To#

LBE

0#LB

E1#

LBE

2#LB

E3#

EN

UM

#P

ME

#

AD

22

GP

IO1/

LLO

CK

o#

VDD

LED

on#

AD

31A

D30

AD

29A

D28

AD

27A

D26

AD

18A

D17

AD

16A

D15

AD

14A

D13

AD

12A

D11

AD

10A

D9

AD

8A

D7

AD

6A

D5

AD

4A

D3

AD

2A

D1

AD

0

AD

25

VDDVDD

VDD

VSSVDD

VDD

VSS

VDDVDD

VSS

VDD

INTA

#

VSS

AD

21A

D20

AD

19

AD

23

PA

R

VSS

VSS

AD

24

VSS

LOC

K#

C/B

E3#

VSS

FRA

ME

#

C/B

E2#

VSS

TRD

Y#

VSS

IRD

Y#

VSS

C/B

E1#

VSS

STO

P#

C/B

E0#

DE

VS

EL#

LA20

PE

RR

#S

ER

R#

LA27

/GP

IO4

LA26

/GP

IO5

LA25

/GP

IO6

LA24

/GP

IO7

LD14

/LA

D14

LA23

LA22

LA21

LD6/

LAD

6

LA19

LA18

LA17

LA16

LD7/

LAD

7

LA15

LD8/

LAD

8

LA14

LA13

LA12

LA11

LD9/

LAD

9

LA10

LA9

LA8

LD10

/LA

D10

LA7

LA6

LA5

LA4

LD11

/LA

D11

LA3

LA2

LD12

/LA

D12

LD13

/LA

D13

LD15

/LA

D15

LD17

/LA

D17

LD0/

LAD

0

LD18

/LA

D18

LD1/

LAD

1

LD19

/LA

D19

LD2/

LAD

2LD

3/LA

D3

LD20

/LA

D20

LD4/

LAD

4LD

5/LA

D5

LD21

/LA

D21

LD22

/LA

D22

LD23

/LA

D23

LD24

/LA

D24

LD25

/LA

D25

LD26

/LA

D26

LD16

/LA

D16

LD27

/LA

D27

LD28

/LA

D28

LD29

/LA

D29

LD30

/LA

D30

LD31

/LA

D31

VDDVDD

VSSVSS

EE

DO

TCK

TMS

TDI

TRS

T#TD

O

VI/O

ALE

RD

#G

PIO

8

CS

0#C

S1#

GP

IO3/

CS

3#G

PIO

2/C

S2#

CP

CIS

W

BC

LKo

LPM

ES

ET

LPM

INT#

C33

0.1u

F

J4 1X6

1 2 3 4 5 6

1 2 3 4 5 6

R28

10K

R11

0

C40

0.01

uF

C54

0.1u

F

C53

0.01

uF

R23

10K

R12

1K

C15

0.1u

F

D3G

RE

EN

21

R29

DN

I_10

K

R14

10K

C39

0.1u

F

C47

0.01

uF

C9

0.1u

F

C44

0.1u

F

RN

4 4x10

K

12345 6 7 8

R19

10K

U5

DN

I_5x

7mm

_sm

_cer

amic

1

2

3

4

EN

GND

OU

T

VCC

R13

10K

U3

93C

S66

1 2 3 4

8 7 6 5

CS

SK

DI

DO

VC

CP

RE

PE

GN

D

R26

10K

RN

2 4x10

K

12345 6 7 8

TP4

R22

10K

C37

0.1u

FC

270.

1uF

RN

3 4x10

K

12345 6 7 8

RN

1 4x10

K

12345 6 7 8

C29

0.01

uF

C26

0.1u

F

R3

10K

R21

10K

R15

10K

R27

10K

C52

0.1u

F

R2

DN

I_10

K

R10

DN

I_33

C30

0.01

uF

R24

10K

RN

5 4x10

K

12345 6 7 8

C49

0.1u

FC

460.

1uF

R20

DN

I_10

K

C45

0.01

uF

U4

DN

I_H

alf_

size

_DIP

1

4

5

8

EN

GND

OU

T

VCC

R25

DN

I_10

K

C55

0.01

uFC

510.

01uF

R16

10K

R30

10K

C38

0.01

uF

LD[3

1:0]

4,5

PC

LK2

RS

TL2

IDS

EL

2

C/B

E0L

2

AD

[31:

0]2

C/B

E1L

2C

/BE

2L2

C/B

E3L

2

FRA

ME

L2

IRD

YL

2TR

DY

L2

STO

PL2

DE

VS

ELL

2

LOC

KL

2P

AR

2IN

TAL

2PM

EL2

AD

SL

4

RD

L4,

5W

RL

4,5

RE

AD

YL

4

LRE

SE

TOL

4,5

CS

0L5

CS

1L4

CS

2L4

LIN

TI1

4

LA[1

9:2]

4,5

SE

RR

L2

PE

RR

L2

VIO

PC

I2

CS

3L4

GP

IO[8

:4]

4

LBE

0L4,

5LB

E1L

4,5

LIN

TI2

4



Figure 4-10 PC104 Connectors

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

Place at connector pins

Place at connector pins

3M Female Conn: 929975-01-20

3M Female Conn: 929975-01-32

3M Female Conn: 929975-01-20

Extra Connector, Non-PC104 Standard

IRQ9 - GPIO7

IRQ10 - LINT1

IRQ11 - GPIO8

IRQ12 - CS3L

IRQ15 - CS1L

IRQ14 - CS2L

PCI104 Connector

SC

-PC

I104

-A1-

004

2.0

PC

I104

Car

d: P

C10

4 C

onne

ctor

s

45

Tues

day,

Oct

ober

17,

200

6

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:S

heet

of

IOC

HC

HK

_N

IRQ

4

EN

DX

FR_N

IOW

IOR

UC

LK

OS

C

KE

Y2

ME

MC

S16

_NIO

CS

16_N

IRQ

7IR

Q6

IRQ

5

IRQ

3

LD6

LD12

LD13

LD15

LD11

LD10

LD9

LD7

LD8

LD14

LD4

LD5

LD3

LD2

LD16

LD21

LD17

LD22

LD23

LD18

LD19

LD20

LD28

LD24

LD29

LD30

LD25

LD26

LD27

LD31

LA8

LA19

LA15

LA2

LA18

LA11

LA9

LA12

LA7

LA14

LA17

LA4

LA5

LA13

LA3

LA6

LA10

LA16

GP

IO8

GP

IO6

GP

IO4

GP

IO5

GP

IO7

LD1

LD0

MA

STE

R_N

AE

N

5P0V

CC

3P3V

CC

3P3V

CC

5P0V

CC

V19

1

J2P

C10

4-64

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

A32

B1

B2

B3

B4

B5

B6

B7

B8

B9

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

B27

B28

B29

B30

B31

B32

+C

86.

8uF

V7

1

V20

1

V18

1

C14

0.1u

F

V1

1

V6

1

V12

1

C17

0.1u

F

V16

1

+C

166.

8uF

V3

1

J3P

C10

4-40

C0

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

V15

1

V5

1

V2

1

V11

1

C12

0.1u

FC

60.

1uF

V9

1

J1P

C10

4-40

C0

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

V14

1

V4

1

V13

1

V17

1

V8

1

V10

1

WR

L3,

5R

DL

3,5

LRE

SE

TOL

3,5

CS

2L3

CS

1L3

AD

SL

3

LD[3

1:0]

3,5

LA[1

9:2]

3,5

RE

AD

YL

3

GP

IO[8

:4]

3

CS

3L3

LIN

TI1

3

LIN

TI2

3

LBE

1L3,

5LB

E0L

3,5



Figure 4-11 PC104 Expansion ROM

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

14

5 13

14

20

21

29

30

32

PLCC-32

SOCKET

LOCAL BUS CHIP SELECT 0

LOCAL BUS READ, WRITE AND RESET

Expansion ROM

SC

-PC

I104

-A1-

005

2.0

PC

I104

Car

d : P

CI E

xpan

sion

Boo

t FLA

SH

RO

M

55

Tues

day,

Oct

ober

17,

200

6

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:S

heet

of

XRO

M_D

0XR

OM

_D1

XRO

M_D

2XR

OM

_D3

XRO

M_D

4XR

OM

_D5

XRO

M_D

6XR

OM

_D7

XRO

M_A

2XR

OM

_A3

XRO

M_A

5XR

OM

_A4

XRO

M_A

6

XRO

M_A

8XR

OM

_A7

XRO

M_A

9

XRO

M_A

11XR

OM

_A10

XRO

M_A

12

XRO

M_A

14XR

OM

_A13

XRO

M_A

15

XRO

M_A

17XR

OM

_A16

5P0V

CC

5P0V

CC C

200.

1uF

U8

DN

I_A

T49F

002N

-55J

C

12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 30

13 14 15 17 18 19 20 21

22 24 31

32 161

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

A17

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

CE

OE

WE

VC

C

GN

DR

ES

ET

TP5

XR

OM

_D[7

:0]

3,4

XR

OM

_CEL

3

XRO

M_O

EL3,

4

XRO

M_W

EL3,

4 XR

OM

_RES

ETL

3,4

XR

OM

_A[1

9:2]

3,4

LBE

0L3,

4LB

E1L

3,4


Documents

EV-OXU200 and EV-OXU200-PCI Evaluation Board User Guide · EV-OXU200-PCI EV-OXU200-PCI and EV-OXU200 Evaluation Board User Guide Figure 1-2 PCI104 Register Mappings The Base Address