ESL and High-level Design: Who Cares?Anmol Mathur

CTO and co-founder, Calypto Design Systems

2

3

4

Trends in Applications and Processor Design

5

Trends Driven by Consumer Electronics

• Time-to-market is king!– Ability to re-target designs to new technology nodes

– Ability to turn around ASICs in 3 month cycles

• Flexible architectures

– Allow same semiconductor part to live in multiple design generations

• Low power designs– System-level and micro-architectural decisions impact power

very significantly

• Software is the queen!– Key differentiation in consumer products is via applications

– Early software development is key

6

Move to System-level Design

System Level Design

Economics• Development Cost• Time to Revenue• Re-spin reduction

Productivity• Design reuse• Platform design• Optimization

Optimization• Performance• Power / battery life• Design updates

Complexity• Increasing design size• HW / SW co-design• Verification testbench

Design tools to leverage system-level models for RTL design and verification are needed

7

Usage of System Level Model

System Level Model

Architectural and Performance

Analysis

SLM to RTL Flows

(High Level Synthesis)

Functional reference model

Faster Simulation

Platform for software

development

8

Manual Process Manual Process

Imp.

SLMSLM

RTLRTL

Manual ProcessManual Process

Alg

ori

thm

icM

icro

-arc

hit

ectu

re

User Control

Limited Control Broad Control

Broad Control

Pro

cess F

low

SLM to RTL Gap

9

Power Dilemma

• Greater power savings opportunities at higher levels of abstraction

• Greater accuracy of power analysis requires detailed layout information

Accu

rate

Sw

itchin

g A

ctivity

Acc

ura

te C

ap

aci

tan

ce

10

Status of High-level Modeling Today• Majority of design teams still using raw C/C++

– Proprietary modeling of simulation time

– Simulation speed and ease of coding are key criteria

• System-model and RTL partitioning is not consistent– Hard to use system-models for RTL verification

• System-level modeling and RTL teams do not talk!

• Several different system models at differing levels of abstraction often exist– Different level of interface/timing accuracy

– Different levels of computational accuracy

• Diverse/non-standard modeling makes the space very fragmented – Very hard to build tools for verification/synthesis

11

SLM to RTL FlowsManual SLM to RTL DESIGN FLOW SLM TO RTL HLS DESIGN FLOW

Floating PointModel

Fixed PointModel

Micro-architectureDefinition

RTLDesign

RTL Area/TimingOptimization

RTLSynthesis

Place & Route

HardwareASIC/FPGA

HardwareASIC/FPGA

Place & Route

RTLSynthesis

Fixed PointC++ Model

Floating PointModel

High LevelSynthesis

Constraints

ManualMethods

Logic Analyzer

+

+Logic

Analyzer

System Level Model

Precision RTLor DC

ASIC or FPGAVendor

Algorithm Functional Description

Algorithm Functional Description

Sys

tem

Des

ign

erH

ard

war

e D

esig

ner

Ven

do

r

Replaces manual RTL creation with automation

Connects system domain to hardware design

Technology based design space exploration.

Up to 20x reduction in RTL creation

12

RTL to layout

System System AnalysisAnalysis

Algorithm

GDS2GDS2C/C++

SystemC

C/C++SystemC

Design model

TargetTarget

ASIC

SLM to RTL Flow

High Level

Synthesis

Technology files(Standard Cells + RAM cuts)

RTLRTL

Formal Proof

(SEC)

FPGAsynthesis

FPGANetlist

FPGANetlist

FPGA

13

Making ESL/HLM a Reality

• Standardized levels of abstraction in system-level models– SystemC 2.0 starting to do that

• Consistency between system-level models and RTL– Coherent system-level and RTL design teams

• Tool eco-system to link system-level and RTL– System-level model validation

– Hardware-software co-simulation

– High-level synthesis

– Sequential equivalence checking

– Sequential/micro-architectural power optimizations at RTL and

micro-architectural levels

www.calypto.com