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ESE 570 Cadence Lab Assignment 2:

Introduction to Spectre, Manual Layout Drawing

and Post Layout Simulation (PLS)

Objective Part A:

To become acquainted with Spectre (or HSpice) by simulating an inverter, observingvoltage transfer characteristics and measuring its rise and fall times with variouscapacitive loads.

Background Part A:

After a circuit is logically designed and verified, we need to make sure the assumedinter-module timing characteristics satisfy their requirements so that our digital circuitwill work correctly when fabricated. That is we need to ensure that the analogcharacteristics of our digital circuit do not interfere with its ideal logical behavior. Thisis accomplished by modeling the behavior of the transistors in the circuit where such

factors as temperature, capacitance, resistance, inductance are taken into account. Thetransistor level simulator you will be using in ESE 570 is Spectre.

For all your Spectre simulations in the exercises described below, please follow theinstructions given in the on-line Cadence Manual sections:

Schematic Simulation: Creating a Test File for Simulating an Inverter;Spice Simulation: DC Analysis of the The Inverter;Schematic Simulation: Transient Analyses of the Inverter;Parametric Analysis with Spectre.

Exercises for Part A:

1. Transient simulation (20/100 pts)Review the on-line Cadence Manual section Schematic Simulation: TransientAnalyses of The Inverter. The simulation is to be performed with Wn/Ln = 6u/0.6uand Wp/Lp = 15u/0.6u. This can be done by editing the inverter schematic youcomposed in Lab 1. The manual takes the user through a transient simulation of aninverter for one value of the external component of the load capacitance, namely C

ext=

25 fF, and measures only rise time. For this exercise perform a transient simulation ofthis inverter using a C

ext= 0 and 100 fF. Use the simulation to measure both rise and

fall times for both capacitance conditions.

2. Inverter DC characteristics (25/100 pts)Perform a DC sweep analysis in Spectre for the inverter constructed in exercise 1 aboveto find its transfer characteristics for a range Wp/Wn values. For this purpose connect adc voltage source vdc to the input pin of the inverter test circuit and select DCAnalyses for the Analyses option in the Cadence Analog Artist Window. Vary theWof the nMOS transistor over the range 1u !W !10uand observe the movement ofthe switching threshold Vth. Use the Cadence Manual section Parametric Analysiswith Spectre as a guide to do this simulation and plot the group of curves in the datasweep. For a Wp/Wn ratio of 3/1, find the input voltage when the output voltage isequal to VDD/2 using the measuring tools in the waveform window.

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Objective Part B:

To create mask sequences for simple gates and a static D flip-flop, as well as usingSpectre to do Post Layout Simulation of the D flip-flop.

Background Part B:

In VLSI Design powerful automated synthesis tools are used by designers to implementthe physical design or layout of their chip, rather than labor intensive transistor bytransistor hand-layout. Using such tools increases the designer productivity and shortensthe time to market for the chip. However, before the value of such tools can beappreciated, it is instructive to do the layout of few simple circuits by hand. In doing so,one achieves a better understanding of the various timing issues associated with layoutfloor planning and routing which will provide valuable intuition when designing andimplementing more complex chip functions.

Design Flow: LayoutOnce the schematic for a circuit is captured, its behavior verified logically and its analogcharacteristics have passed all voltage, timing and power specifications the next step inthe design flow is layout. This verification is very important no designer wants towaste valuable time laying out circuits that have no chance of working.

When laying out a circuit it is helpful to have the the transistor level schematic to helpguide your placement and routing of the physical implementation of circuit elements. Thelayout ought to have a one-to-one correspondence to the schematic. However, the layoutwill undoubtedly introduce parasitic resistances and capacitances that are not accountedfor in the schematic, as has been discussed in class. These parasitics can be measured

using tools within Cadence, and they can then be back-annotated in the schematic so thatthe schematic reflects the actual layout in terms of timing and capacitance properties.Thus after a layout is completed it is necessary to extract from the layout all of theparasitic capacitances using the Layout Versus Schematic (LVS) tool as described in theLayout Versus Schematic (LVS) Verification section of the on-line Cadence Manual.With parasitic capacitances extracted and back-annotated into the schematic (actually theschematic net-list), the designer performs a post-layout Spectre simulation to to validateall of the circuit specifications using a model that best represents the fabricated circuit.

There are a few rules of thumb to keep in mind when laying out a circuit, many of whichhave been mentioned in class:

1. Avoid using polysilicon as a long wire or route. Use it only for local, < 6 m

connections because it has high sheet resistance of 15 to 30 Ohms/square, as well asintroducing parasitic capacitance.

2. Use wide metal wires or interconnect for power rails and ground, at minimum W = 4

!. especially if they are long and supplying (sourcing) a lot of current. Keep in mind that

typical current density rating for metals is about 0.5 mA/m.

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3. When changing metal layers, the number of contacts to use should follow from thecurrent rating of the contacts themselves. The current density for each contact should be

kept below 0.5 mA/m.

The Virtuoso Layout Editor:The Cadence view or window that contains the layout is called the layout view, as describedin the Create Custom Layouts section of the on-line Cadence Manual. Opening thelayout view automatically brings up the layout editor called Virtuoso. The long and thinrectangular window that contains all of the layers provided by the technology file is shownin the layer selection window (LSW). Selecting a layer in the LSW will allow one tosubsequently draw a layout feature that uses that layer. The background represents thesubstrate, which in our N-well CMOS process is p material. The mask sequence for annMOS transistor on p bulk is 1) n-diffusion; 2) active; 3) polysilicon, 4) metal1 and 5)contact. The mask sequence for an pMOS transistor on p bulk is 1) n-well diffusion, 2)p-diffusion; 3) active; 4)polysilicon, 5) metal1and 6) contact.

For simulation purposes and and standard cell design rules, it is necessary to add the PINorpn layer, which is used for the for the input/output and vdd!/gnd! pins in the schematic.Power and ground rails should be declared as jumpers. Physical input and output pinsshould be in metal2and and power/ground rail pins should be in metal1. It is a good idea tolabel your pins with the text layer, and make sure to name the labels the same as the pinsand put them on top of the labeled wires.

Once the the layout is complete run a Design Rule Check (DRC) to verify that no designrules have been violated. The running of the DRC is described in the Design Rule Checksection of the on-line Cadence Manual. After the layout has been found to be free of design

rule violations, the next set is parasitic extraction. The extraction tool takes the masksequences and matches them with known sequences for various circuit elements, e.g.whenever the mask sequence 1) n-diffusion; 2) active, 3)polysilicon; 4) metal1; 5) contactis encountered it is recognized as an nMOS transistor. Parasitic capacitances are recognizedwhenever polysilicon or a metal layer runs over field oxide, and a simple estimate of thecapacitance is made based on the area of the overlap. Parasitic resistances are not extractedbecause they are not implemented in our technology file. The extracted view isautomatically created whenever a layout is extracted. It contains the circuit element andnetlist information for the whole layout. Usually there are no errors in the extracted viewunless there are unrecognized mask sequences, which need to be corrected before movingforward.

The extracted view is used to compare the layout and schematic for differences that wouldsuggest errors. This verification step is called Layout Versus Schematic (LVS). Note thatthe LVS is to be done from the extracted view and not the layout view. After the LVSverification is passed, the designer can do the Post-Layout Simulation (PLS) usingSpectre from the extracted view. The procedure is identical to that for simulating from theschematic view. See the Post Layout Simulation section of the on-line Cadence Manual.

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Figure 1 Standard Cell

Standard Cell Design:

Like software libraries that a programmer uses to perform certain well-established or routine

functions in a large program, hardware descriptions for VLSI design can be taken from a libraryof modules or cells that can be called and inserted into a functional description, schematic andlayout for a VLSI circuit as often as needed. Such cells are called standard cellsbecause theirphysical design or layout are done to rigid geometric standards that enable the cells to beautomatically placed and routed. One such standard is that standard cells have standard height(vertical distance) and placements for power and ground rails. This enables standard cells to beplaced next to each other in rows in order for their power/ground rails to be perfectly aligned.We will design gates as standard cells to take advantage of their reusability. For our standard

cells the vertical distance from the top of the vdd! rail to the bottom of the gnd! rail is 100!=

30 m (see Fig. 1).

100!= 30 m

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Figure 2 Layouts of Inverter, 2-input NAND (ND2) gate and 2-input NOR (NR2) gate

The topology of a standard cell design is that there are rows of cells alternated with rows ofinterconnect or routing channels such that in between every pair of standard cell rows thereis a routing channel. Interconnecting wires will be routed out of and into cell blocks above

and below, and passed through spaces in between. Hence, care must be taken to ensure thatthese wires do not violate design rules when connecting with adjacent ports. In order to usestandard cells in a design it is standard procedure to first characterize each cell to specify itstiming information and input/output capacitances. In the exercises in this part you will beasked to layout the Inverter (INV), 2-input NAND gate and 2-input NOR gate. In additionfor extra credit, you may elect to layout an asynchronously resettable static D flip flop.

To summarize the guidelines for standard cell design are as follows:

1. Standard cells must adhere to rigid dimension specifications; all standard cells are to be

the same height and power and ground rails must align. In our case we use 30 m as our

standard height from the top of the vdd! rail to the bottom of the gnd! rail.

2. To effectively use standard cells, they must be fully simulated and characterized. Thismeans capturing the gate switching threshold voltage V

thand rise/fall times as a function of

load capacitance.

3. It is helpful to design the cell layout so that the input and output pins are not on the samehorizontal line, as in the layouts below in Fig. 2, and they are spaced vertically by at leastthe edge-to-edge minimum width spacing of the metal2 wires. This will enable easyrouting of interconnections between different cells while not violating design rules.

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Figure 3 Cadence outputs Manager Window

2. D flip flop layout(30/100 pts Extra Credit)Create a mask sequence for the asynchronous resettable, static D flip-flop developed inCadence Lab 1. Follow the standard cell design guidelines. Perform DRC and LVS on itbefore simulating the extracted view in Spectre. Perform PLS and make sure it works asdesired. That is satisfies the functional behavior verified in your Verilog-XL simulationexecuted in Lab 1. Using you PLS determine the clock-to-Q delay and the reset-to-Q delay

when clkin frequency = 25 MHz. Print out the mask sequence and simulation result.

3. Static D flip flop setup and hold times (20/100 pts Extra Credit)Describe how you would go about using the PLS to determine the setup and hold times foryour static D flip flop.

Please note that this cadence Lab Assignment 1 (as well as Cadence Lab Assignment 1)will count 1.5 x the score for each of the seven Text Book Homework Assignments.

KRL

Updated 19 Mar 13