Microelectronics Reliability 48 (2008) 1422–1426

Contents lists available at ScienceDirect

Microelectronics Reliability

journal homepage: www.elsevier .com/locate /microrel

ESD sensitivity investigation on a wide range of high density embedded capacitors

Frederic Barbier a,*, Sebastien Jacqueline b

a NXP Semiconductors Caen, 2 Esplanade Anton Philips, Colombelles-BP20000, 14906 Caen cedex 9, Franceb NXP Semiconductors Caen, 2 rue de la Girafe, BP 5120, 14079 Caen cedex, France

a r t i c l e i n f o a b s t r a c t

Article history:Received 1 July 2008

0026-2714/$ - see front matter � 2008 Elsevier Ltd. Adoi:10.1016/j.microrel.2008.07.023

* Corresponding author. Tel.: +33 (0) 231453934; fE-mail address: frederic.barbier@nxp.com (F. Barb

This work presents some results from electrical (TDDB, TLP, HBM and MM) measurements and ESD cal-culations/simulations on passive components such as capacitors. In a SIP context, the ESD sensitivity ofinnovative 3D capacitors is studied. A method to predict the failure threshold of a wide range of capacitorvalues under ESD events is presented and validated by measurement on silicon. This method consists ofusing the basic equation of the charge conservation for capacitors in parallel that is adapted to the modelof the ESD event.

� 2008 Elsevier Ltd. All rights reserved.

1. Introduction

For the silicon based system-in-package concept with passiveintegration, an active die is associated to a passive die [1]. Newtechnologies, such as the assembly of silicon chips onto other sili-con chips, also referred to as ‘‘double flip chip” can be used. This ispossible thanks to the combination of the most advanced micro-bumping and die placement techniques. Example is given inFig. 1 where cross section of product is presented.

Filtering, decoupling and other functionalities can be performedthanks to the passive structures with high silicon integration. Thisapproach allows the integrated circuits to tend to a strong minia-turization and also high RF performances. An example of sbSIP (sil-icon based system-in-package) component is shown in Fig. 2. Theactive die is directly placed on top of the passive die. Both are thenassembled in an appropriate package.

With this concept, the active die generally has its own on-chipESD protections. Unlike the passive technology that has resistors,capacitors and inductors in its portfolio, there is no dedicatedESD protection. This study was driven by the fact that such capac-itors are often located directly at the circuit input or output, mak-ing them the first components in the ESD transient path. That iswhy an investigation has to be performed to know the ESD capac-itor sensitivity. The goal is to prevent failures during ESD qualifica-tion of the IC but also during handling and fabrication. Two modelsare mainly used to describe ESD pulses: the human body model(HBM), which models handling of an IC by humans, and the ma-chine model (MM), which models handling by machines. Both sim-ulate different ESD events that may occur in the chain of

ll rights reserved.

ax: +33 (0) 231452112.ier).

processing and packaging of integrated circuits. In this study wepresent an ESD investigation performed on the structures thatare available in the passive technology focusing on the capacitors.We present a silicon validation of their ESD sensitivity that corre-lates with the failure prediction obtained by using the law ofcharge conservation when HBM and MM stresses are applied tocapacitors. Two different types of capacitors (two technologies)will be studied.

In this paper it will be shown for the first time that using a sim-ple method based on the results of TDDB measurements and on theapplication of charge conservation or ESD spice-like simulations, itwill be possible to predict the failure threshold of capacitors struc-tures under HBM and MM stress. The following sections will de-scribe the TDDB analysis performed on capacitors to obtain theirbreakdown voltage under ESD zap. TLP characterization will showa good correlation with the previous results. When capacitors arein parallel, like it is during an ESD event (for the HBM/MM circuits),the conservation of the charge will be introduced and used to pre-dict the failure threshold of capacitors.

2. Capacitor description

The core of the PICS (passive integration connecting substrate)technology is based on the integration of high density MOS ‘‘tren-ch” capacitors as described in [1]. In the first product generation,these are fabricated in silicon by dry-etching macropores arraysof high aspect ratio up to 20. Capacitors with �30 nm ONO (oxidenitride oxide) dielectric stack and polySi/Al top electrode yield acapacitor density of 25–30 nF/mm2 with low leakage current den-sity (<1 nA/mm2@22 V).

In the race of capacitor integration, NXP developed the nextgeneration of PICS technology, offering capacitor density of80 nF/mm2. This second generation adopts the same concept of

Fig. 2. RF transceiver in sbSIP.

Fig. 1. Cross-section of a fully integrated radio module in a molded leadframe.

F. Barbier, S. Jacqueline / Microelectronics Reliability 48 (2008) 1422–1426 1423

capacitors, embedded in highly doped dry etched 3D macro struc-tured silicon, still using ‘‘conventional” dielectric materials, andassociated high throughput, low cost and reliable CVD and thermalprocessing techniques. A scaling of the Si nitride and oxide layers,including the optimization of the films interfaces along deepermacropores arrays, allows to more than tripling the capacitordensity.

In these two technologies capacitor values from 10 pF up to10 nF have been tested.

3. Test structures description

The designed test structures have been implemented accordingto Fig. 3. A metal line is used to connect each electrode of the 3D

Fig. 3. Illustration of a 3D capacitor and its connections to the external pins of thepackage.

capacitor. A metal plate covers the whole body of the capacitor.Then two bonding wires create the connections to two externalpins. Several capacitors have been assembled in standard packagesto perform the ESD tests.

The following section will present some experiments we carriedout to study the dielectric reliability of the 3D capacitors under ESDevent. In this paper we will use the TDDB data on capacitors tostudy their ESD sensitivity.

4. TDDB measurements

The constant voltage method, in which the capacitor is stressedat a constant voltage until breakdown occurs, allows characteriza-tion of failures due to wear-out, including time-dependent dielec-tric breakdown (TDDB) lifetime reliability characterization. In aTDDB experiment, the resistance of the capacitors is measured atelevated temperature (100 �C) and electric field. A failure is definedas the time where the resistance of the capacitor has decreasedbelow 1 MX. Typically, the change of resistance at breakdown isvery sudden from GX’s to short circuit. The time to breakdown(tbd) is described by an exponential dependence on electric oxidefield Eono

tbd ¼ s0ðTÞ � exp½�cðTÞEono� ð1Þ

where s0 and the field acceleration factor (c) are temperature (T)dependant fit parameters [2]. The acceleration factors are used toextrapolate the capacitor lifetime under operating conditions. Basedon these data, the reliability for a generic reliability profile[1000 ppm failure rate in 10 year lifetime] can be predicted. Themeasurements were done at wafer level with a HP5156C (PrecisionSemiconductor Analyzer) to apply constant voltage stress and re-cord the hard breakdown time. Per stress level, a series of at least50 samples are tested with an automatic prober, equipped with aheated chuck.

The plot of the cumulative number of failures against time-to-breakdown gives the statistical parameters of the Weibull distribu-tion F(t):

FðtÞ ¼ 1� exp � tg

� �m� �ð2Þ

where m is the Weibull shape parameter which gives the lifetimespread of the intrinsic breakdown, and g is the time when the reli-ability becomes 63.2%. Once the distribution parameters are knownfrom the probability plot, the lifetime for a 0.1% failure level can becalculated.

TDDB measurements were made applying three constant volt-age stresses, within about 5–20% below the intrinsic breakdownvoltage (Vbd) of the dielectric

Vbd ¼ Eox1bd � tox1 þ Enit

bd � tnit þ Eox2bd � tox2 ð3Þ

where t is the thickness and Ebd is the estimated electric field beforebreakdown of the 1st oxide, nitride and 2nd oxide layers of the ONOsandwich: 26 V for PICS1 technology and 19 V for PICS2. In thisstudy we will use the long time-scale TDDB data in predicting thevoltage breakdown to short time-scale ESD events. For the oxidebreakdown, some publications have demonstrated that the dielec-tric degradation mechanism remains unchanged in the short timescale [3,4].

These TDDB results, extrapolated down to the ESD time domain,show that for the PICS1 technology, the failure voltage of thecapacitor for the ESD typical time range is 40 V. For the PICS2 tech-nology, the failure is predicted at 34 V. In the next paragraphs, wewill show the relevance of long time-scale TDDB data in predictingthe response to short time-scale ESD events.

ig. 5. TLP curves obtained with two similar capacitor values in PICS1 and PICS2.

Fig. 6. I/V waveforms for the last two points of the TLP curve (cut 90 pf PICS1)shown in Fig. 5.

1424 F. Barbier, S. Jacqueline / Microelectronics Reliability 48 (2008) 1422–1426

5. TLP characterization

Transmission line pulse (TLP) testing has been used to study theoxide breakdown voltage under electrostatic discharges. The 2-probe TLP system (50 X) applies 100 ns pulses (10 s rise time) tothe capacitor under test (CUT), while measuring the voltage acrossand current through it. Incrementally increasing voltage pulses areapplied on the CUT while making DC leakage measurements be-tween pulses. In a TLP system, the voltage and current levels de-pend on the relative impedance of the transmission line (TL)with respect to the CUT: ICUT = V0/(ZCUT + ZTL) where V0 is the charg-ing voltage of the TL. The capacitor has a resistance well greaterthan 50X. Then the main resistance is the one from the capacitorand we assume that the TLP stress is similar to a constant voltagestress.

Fig. 5 shows the data for two CUTs with similar values in PICS1and PICS2. The two dielectric failures are observed at 42 V and34.5 V. In addition we can notice that even if we had higher currentcapability with higher capacitor values, we always had the samevoltage failures for greater capacitor values. Then we comparedthese values to the voltage acceleration data. By extrapolation tothe 100 ns time range of the TDDB data shown in Fig. 4, we cansee a good correlation of the results found in the longer time-scale.Capacitor failure voltages measured using both transmission linepulse (TLP) and TDDB test methods are actually related to theintrinsic dielectric breakdown. To confirm this statement, the TLPcurrent/voltage waveforms have been monitored during the twolast TLP zaps leading to the failure (CUT 90 pF TLP curve fromFig. 5). We can see in Fig. 6, the resulting current/voltage wave-forms obtained at the end of the TLP pulse. The waveforms showthat the breakdown process occurs within 10 ns as already studiedby Ridley [5]. If a stress which lasts 100 ns is able to produce thesame type of failure mechanism as DC stress, the breakdown tran-sient is shorter than 100 ns. This result confirms that the samebreakdown process occurs in the DC and the ESD time domain.

A similar approach is published by Weir et al. [3]. Using thisinformation, showing a good agreement between the two methods,a failure criterion can be extracted from the voltage accelerationmeasurement. The predicted failure criteria will be implementedin the study of the conservation of charge when HBM and MM zapsare applied to capacitors. The next paragraph explains how this ap-proach allows us to predict the capacitor failure threshold versusits capacitor value.

Fig. 4. TDDB results on capacitors in PICS1 and PICS2.

F

6. Conservation of charge (part 1-calculation)

An RLC circuit can simulate the electrostatic discharge due tothe contact of a charged human body or a charged machine. In thiscircuit, a capacitor (CHBM = 100 pF or CMM = 200 pF) is used to rep-resent the body or the machine capacitance that is dischargedthrough the device under test [6,7]. If we neglect the resistance(r = 1500X for HBM) and the inductor (l = 7.5 lH for HBM andl = 0.75 lH for MM), we are then in a worst-case representationof the human body model or the machine model discharge. Duringthe discharge, the charged capacitor (CHBM or CMM) is then con-nected to the uncharged capacitor under test (CUT). Taking into ac-count we have two capacitors in parallel and the chargeconservation law, the final voltage (Vf) seen by the CUT is

V f ¼CHBM=MM

CHBM=MM þ CUT� V i ð4Þ

The initial voltage (Vi) is the stress voltage applied to theCHBM/MM. This law (Eq. (3)) has been simulated for both ESD mod-els. The capacitor value range was between 1 pF and 10 nF. Thesimulated voltage stress step for HBM was 10 V and began at30 V. Above 100 V as voltage stress, the step was 100 V. For

F. Barbier, S. Jacqueline / Microelectronics Reliability 48 (2008) 1422–1426 1425

MM, the voltage step was 10 V and began at 10 V. As failure cri-teria (Vbreak) we choose the breakdown voltage value extractedfrom the TDDB curve. We extrapolated down to the nanosecondtime frame (at 100 ns, Vbreak = 40 V for the PICS1 process and34 V for PICS2). With these values as failure criteria for both tech-nologies, the calculation gives the minimum capacitor valueneeded to keep the final voltage (Vf) below Vbreak. The resultsare described in Figs. 9 and 10. To give a better confidence inthe result obtained we performed some HBM and MM simula-tions with the Cadence spectre simulator on the studied capaci-tors. Spectre test benches were designed to simulate HBM andMM stresses. Both were calibrated according to the JEDEC stan-dards [6,7]. Fig. 7 presents the electrical circuits for the humanbody model (A) and the machine model (B). We performed some

Fig. 7. HBM (A)/MM (B) test benches used for spice-like simulations.

Fig. 8. Waveforms obtained for MM = 300 V across 3 capacitors under test.

optimizations to obtain the adequate waveforms according to theJEDEC waveforms specifications (current peak, rise time, etc). Fig.8 presents an illustration for the resulting waveforms across threeCUTs under MM zap at 300 V.

The chosen simulated CUT values were taken between 100 pFand 10 nF. The applied HBM voltages were 2 kV, 1 kV, 500 V and200 V. We analyzed the voltage responses across the CUTs and tookinto account the same failure criteria (Vresponse < Vbreak). As exam-ple, under 2 kV HBM, for CUT = 4 nF, the resulting voltage was42 V. For CUT = 5 nF under 2 kV, the voltage response was 36 Vand 31 V for CUT = 6 nF. For a capacitor C = 4 nF, the simulatedvoltage response is above the failure criteria and this value hasbeen placed in Fig. 9. We used the same process to obtain the otherpoints for both HBM and MM simulations. We can see that the re-sults are very close to those obtained thanks to Eq. (3). This corre-lation makes us confident in our approach. The followingparagraph presents the results for the silicon validation.

Fig. 9. Failure voltage versus capacitor value; measurement/calculation/simulationresults for PICS1 capacitors.

Fig. 10. Failure voltage versus capacitor value; measurement/calculation results forPICS2 capacitors.

Fig. 11. Front side Obirch pictures for a defective capacitor on two samples; sample2 (A) and sample 3 (B).

1426 F. Barbier, S. Jacqueline / Microelectronics Reliability 48 (2008) 1422–1426

7. Conservation of charge (part 2-silicon validation)

ESD tests were performed to evaluate the 3D capacitor sensitiv-ity. The tests were performed using an MK2 Keytek test system andwere based on both human body model and machine modelevents. An increasing voltage by step of 100 V for HBM and 20 Vfor MM, was applied to packaged structures comprising capacitorsof various sizes until breakdown occurs. Positive and negative zapshave been applied on separate samples. The average of five resultsfor positive zaps and four results for negative zaps are shown inFigs. 9 and 10.

We can notice that the minimum HBM voltage applied on CUTswas 100 V. Even if some failures were obtained below this stressvalue, it can not be seen with data shown in Fig. 9. We can see a

good correlation between measurements and calculations. Whenthe capacitor value increases the resulting failure voltage (ESDvoltage) also increases.

8. Physical analysis

Physical analysis has been performed on the stressed devices topoint out the failure location. We used the OBIRCH method basedon two main processes: laser-beam heating and resistance changedetection [8]. The resistance change appears as a current or voltagechange only when the laser-beam irradiates a line where a currentis flowing. This results in imaging current paths. The resistancechange caused by laser-beam heating depends on an increase intemperature. When a laser beam is irradiated, the generated heatis transmitted freely across areas that are free of defects however,heat transmission is impeded at defects. This creates a nonuniformtemperature increase, which results in imaging defects.

In our case the dielectric breakdown creates a resistive currentpath between the two electrodes.

We studied many defective capacitors after HBM/MM stress. Asexample, two OBIRCH pictures are presented in Fig. 11. The twopictures represent the same defective capacitor structure but com-ing from two different samples. We can observe two different fail-ure locations (encircled spots). Both capacitors have failed ataround 1 kV HBM. Front side and back side views have been triedon many defective capacitors and no reproducible failure locationshave been observed.

9. Conclusion

In this study we increased the range of the studied capacitorscompared to the literature [9]. For the first time, we present someESD results on 3D silicon capacitors. We validate a method to pre-dict the ESD sensitivity of a wide range of capacitance value. As ex-pected using larger capacitors increases the capacitor ESDsensitivity. To increase the robustness against ESD stress, an alter-native solution would be to use two or three capacitors in seriesthat is equivalent to use a capacitor with double or triple dielectricthickness and it would result in doubling/ tripling of the break-down voltage.

Based on both TDDB results to obtain the breakdown voltage ofthe capacitors in the typical time domain of ESD and on HBM/MMcalculations either with the law of charge conservation or withstandard spice-like simulation, a method has been proposed topredict the failure threshold of capacitors under ESD. The proposedmethod validated by the silicon data enables designers to predictthe ESD sensitivity of un-protected capacitors and/or create anESD protection strategy accordingly.

References

[1] Murray F, et al. Silicon based system-in-package: a new technology platformsupported by very high quality passives and system level design tools. Siliconmonolithic integrated circuits in RF systems, Topical meeting on 10–12 January;2007. p. 149–53.

[2] JEDEC solid state technology association. Procedure for characterizing time-dependent dielectric breakdown of ultra-thin gate dielectrics; August 2003.

[3] Weir et al. Gate dielectric breakdown: a focus on ESD protection. In: 42ndannual international reliability physics symposium; 2004. p. 399–403.

[4] Wu et al. IEEE Trans Electron Dev 2004;51:1528–31. [8th August].[5] Ridley BK. J Appl Phys 1975;46:998.[6] JEDEC standard. JESD22-A114D.[7] JEDEC standard. JESD22-A115A.[8] Beaudoin F et al. Current leakage fault localization using backside OBIRCH. IPFA

2001:121–5.[9] Voldman S. RF technology and circuits. Wiley Ed; 2006. p. 129.