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The Top 20 Errors in VHDL
.. Most Common VHDL Errors
Ref. VHDL Golden Reference, Dulous
This is a list of the most common VHDL errors. The Top 10 account for about
40% of all errors. The Top 20 account for about 60% of all errors.
1-10
- Missing or misplaced begin in architecture / process / subprogram
- Swapping <= := and =
- Missing or extra end if / end case / end loop / end process etc...
- Wrong quotes around characters / strings / integers
- Incompatible types in assignments / operators
- Missing or extra ; at end of declaration / statement
- Misspelt identifier
- Undefined signal / variable / constant
- Missing library / use
- Wrong separator , / ; / : / .
11-20
- Missing sensitivity list / wait statement in process
- Sensitivity list and wait statement in same process
- Same name used twice
- elseif or endif (instead of elsif and end if respectively)
- Using the wrong user defined identifier
- Extra / missing / mistyped character
- Missing signals in sensitivity list
- Mismatched vector lengths
- Using a reserved identifier
- Reading out ports
24 August 2012
40%
20%
40%
Errors
Top Ten Errors Next Ten Errors
Other Errors
