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Eri Prasetyo WibowoUniversitas Gunadarma
http://eri.staffsite.gunadarma.ac.idhttp://pusatstudi.gunadarma.ac.id/pscitra
DIFINISI
System-on-a-chip or system on chip (SoC or SOC) refers to integrating all components of a computer or other electronic system into a single integrated circuit (chip). It may contain digital, analog, mixed-signal, and often radio-frequency functions – all on one chip. A typical application is in the area of embedded systems. ( wikipedia)
System-on-a-chip (SoC) technology is the packaging of all the necessary electronic circuits and parts for a "system" (such as a cell phone or digital camera) on a single integrated circuit ( IC ), generally known as a microchip.For example, a system-on-a-chip for a sound-detecting device might include an audio receiver, an analog-to-digital converter ( ADC ), a microprocessor , necessary memory , and the input/output logic control for a user - all on a single microchip.
MOORE’S LAW:
2X FUNCTIONALITY EVERY 18 MONTHS
Base Design
CPU
IC
ShrinksCPU
Or Keep
Package
Same
Size
CPUFPGA
EEPROMRAM
ADC
SoC
10,000,000
Lo
gic
Tra
ns
isto
rs p
er
Ch
ip(K
)
Pro
du
cti
vit
yT
ran
s./
Sta
ff-M
o.
The Impending Design Productivity Crisis
1,000,000
100,000
10,000
1,000
100
10
1
100,000,000
10,000,000
1,000,000
100,000
10,000
1,000
100
10__ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __
1981
1983
1985
1987
1989
1991
1993
1995
1997
1999
2001
2003
2005
2007
2009
58%/Yr. CompoundedComplexity growth rate
21%/Yr. CompoundedProductivity growth rate
Source: SEMATECH
x xx
xxx
x
Logic Tr./Chip Tr./S.M.
DESIGN PRODUCTIVITY LAGS MANUFACTURING CAPABILITY
Maya Rubeiz USAF Wright Labs [email protected] http://rassp.scra.org
ApplicationSpace
HW-SW Kernel
MEM
FPGACPU Processor(s), RTOS(es)
and SW architecture
*IP can be hardware (digital or analogue) or software. IP can be hard, soft or‘firm’ (HW), source orobject (SW)
*IP can be hardware (digital or analogue) or software. IP can be hard, soft or‘firm’ (HW), source orobject (SW)
Scaleablebus, test, power, IO,clock, timing architectures
+ Reference Design
Programmable
SW IP
Hardware IP
Pre-Qualified/VerifiedFoundation-IP*
Foundry-SpecificHW Qualification
Reconfigurable Hardware Region(FPGA, LPGA, …)
SW architecturecharacterisation
SOC PLATFORM DESIGN
• FPGAs can contain soft or hard IP (including CPUs).
• www.atmel.com
• www.altera.com
• www.triscend.com
• www.xilinx.com
RECONFIGURABLE FPGA-BASED BOARDS CAN PROTOTYPE DIGITAL DESIGNS
DESIGN-FOR-REUSE and DESIGN-WITH-REUSE
APPLICATION REQUIREMENTS
FPGA FPGA FPGA FPGAVERIFICATION
DESIGN
FOR
REUSE
HDL HDL HDL HDL
TEAM
PROJECT
SoCDESIGN WITH REUSE SYSTEM INTEGRATION
SOC WITH RECONFIGURABLE COMPONENTS
High performance ASICs can now contain programmable logic (embedded FPGA tiles) as needed for flexibility.
www.lsil.com
www.adaptivesilicon.com
ARMARM
A matrix of configurable analog opamps and interconnect can be used to perform filtering and other signal
conditioning operations.
CONFIGURABLE ANALOG ARRAYS
www.anadigm.com
www.latticesemi.com
RADIATION-TOLERANT CIRCUITS CAN BE MADE USING CONVENTIONAL PROCESSES
S DG
Conventional Transistor Layout
RadiationEffects
Current
(Drain)
Voltage (Gate)
Desired Behavior
S D
G
Radiation-Tolerant Layout
REF: cern.ch
SHARING MULTI-PROJECT MASKS AND WAFERS SAVES
MONEY
Shared, Multi-Project WaferSingle-User Wafer
www.mosis.org
FEATURE SIZE vs YEAR INTRODUCED
0
100
200
300
400
500
600
19
94
19
96
19
98
20
00
20
02
20
04
20
06
20
08
20
10
20
12
20
14
YEAR
FE
AT
UR
E S
IZE
(n
m)
SIA'97 MOSIS
MULTI-PROJECT SERVICES PROVIDE ACCESS TO
STATE-OF-THE-ART COMMERCIAL PROCESSES
PROCESSES AVAILABLE VIA MOSIS
• TSMC 0.35µTSMC 0.35µ • TSMC 0.25µTSMC 0.25µ
– 5-metal, 2-poly• TSMC 0.18µ TSMC 0.18µ
– 6-metal– 2.5/3.3v I/O, 1.5/1./8v Core
• Peregrine SOI-SOS 0.50µPeregrine SOI-SOS 0.50µ
• TSMC 0.15µTSMC 0.15µ• TSMC 0.13µTSMC 0.13µ
– 6-metal, 1 poly, silicided, 6-metal, 1 poly, silicided, CuCu
• IBM SiGe 0.5µIBM SiGe 0.5µ• IBM SiGe 0.25µIBM SiGe 0.25µ
NOW NEXT 6 MONTHS
www.mosis.org
• Assemble individual components using a board with reconfigurable interconnect to finalize the system specs.
• Model the entire system and simulate at a high level.
STEPS IN MIXED-SIGNAL SOC DEVELOPMENT
• Design and prototype an analog I.C. via MOSIS or CMP.
• Design and prototype the digital components using FPGAs.
• Integrate the analog and digital sections into a single SoC.
SoC
BAGAIMANA MEMULAI DESAIN DALAM SOCs
