IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 8, AUGUST 2001 1503

Enhancement-Mode Power Heterojunction FETUtilizing Al 0:5Ga0:5As Barrier Layer with NegligibleOperation Gate Current for Digital Cellular Phones

Yasunori Bito, Member, IEEE, Takehiko Kato, and Naotaka Iwata, Senior Member, IEEE

Abstract—We have developed a novel enhancement-modedouble-doped AlGaAs/InGaAs/AlGaAs heterojunction FET(HJFET) with a 5 nm thick Al 0 5Ga0 5As barrier layer in-serted between an In0 2Ga0 8As channel layer and an upperAl0 2Ga0 8As electron supply layer. The Al0 5Ga0 5As barrierlayer reduces gate current under high forward gate bias voltage,resulting in a high forward gate turn-on voltage ( ) of 0.87V, which is 170 mV higher than that of an HJFET without thebarrier layer. Suppression of gate current assisted by a parallelconduction path in the upper electron supply layer was foundto be also important for achieving the high . The developeddevice exhibited a high maximum drain current of 300 mA/mmwith a threshold voltage of 0.17 V. A 950 MHz PDC powerperformance was evaluated under single 3.5 V operation. AnHJFET with a 0.5 m long gate exhibited 0.92 W output powerand 63.6% power-added efficiency with 0.08 mA gate current( ) at 48 dBc adjacent channel leakage power at 50 kHzoff-center frequency. This is one-thirteenth to that of theHJFET without the barrier layer. These results indicate that thedeveloped enhancement-mode HJFET is suitable for single lowvoltage operation power applications.

Index Terms—Al0 5Ga0 5As barrier layer, digital cellularphone, enhancement-mode, forward gate turn-on voltage, gatecurrent, power heterojunction FET.

I. INTRODUCTION

RECENTLY, power devices which can be operated with asingle voltage are in great demand for cellular applica-

tions. For the demand, an enhancement-mode heterojunctionFET (HJFET) which showed excellent power performance isa probable candidate [1], [2]. For the FET, a negligible drainleakage current ( ) at a gate-to-source voltage ( ) of 0.0V is desirable, because the drain bias switch can be eliminated,thus realizing low cost and small size cellular phones. In orderto realize a negligible , a positive threshold voltage ( ) ofmore than 0.2 V is necessary for about a 1 W class power FETwith a gate width ( ) of more than 20 mm [3]–[6]. With anincrease in close to forward gate turn-on voltage (), how-ever, forward gate current () under power operation increasesdue to a decrease in gate voltage swing margin. This degradespower performance of the enhancement-mode FET, thereforeincreasing becomes the key issue.

Manuscript received June 28, 2000; revised January 11, 2001. The associateeditor coordinating the review of this manuscript and approving it for publica-tion was K. M. Lau.

The authors are with the Compound Semiconductor Department, CompoundSemiconductor Device Division, NEC Electron Devices, NEC Corporation,Shiga 520-0833, Japan (e-mail: yasubito@cb.jp.nec.com).

Publisher Item Identifier S 0018-9383(01)05694-5.

FETs with a high have been reported [4], [5], [7]–[9].P-n junction gate FETs exhibited high of 0.9–1.5 V [7]–[9].However, the p-n junction gate FETs require precise control ofcomplicated processes, such as a p-type semiconductor layerregrowth process [7] or a p-type impurity diffusion process[8]. Another p-n junction gate FET, which has its epitaxiallygrown p-n junction, requires donor ion implantation and acti-vation thermal annealing processes to form nohmic contactregions [9]. On the other hand, an FET utilizing 20 nm thickAl Ga As barrier layer with doped channel layer exhibited

of 1.4 V [4], and an FET utilizing 25 nm Al Ga Asbarrier layer with a single doped heterojunction structureexhibited of 1.8 V [5]. These devices also required the ionimplantation and annealing processes. In spite of the ohmicregion formation, these devices showed a low maximum draincurrent ( ) of 200–250 mA/mm. This might be due to highresistivity of the ion implanted ohmic contact regions whereconduction electrons must pass the thick barrier layers.

In order to realize a high with a high and a low on-re-sistance ( ), which are indispensable to low voltage operationwith high efficiency [10], we have investigated the adoption of ahigh Al mole fraction AlGaAs barrier layer for a double-dopedAlGaAs/InGaAs/AlGaAs HJFET. In this paper, an optimal bar-rier design for improving with a high and a low ofthe double-doped HJFET is presented. The developed novel en-hancement-mode HJFET exhibited of 0.87 V, which is 170mV higher than that of an HJFET without the barrier layer. Con-sequently, the device exhibited a reduced(one-thirteenth tothat of the conventional HJFET) with excellent power perfor-mance.

II. DEVICE DESIGN

The effects of the position and Al mole fraction of the Al-GaAs barrier layer on forward gate current characteristics wereinvestigated by experiments and numerical simulations. We alsostudied the influence of GaAs gate burying layer thickness (adepth of a second gate recess) to of an HJFET. This GaAslayer is indispensable to form a buried gate (double recessed)structure with a dry recess etching technology.

A. Position of the AlGaAs Barrier Layer

A 5 nm thick Al Ga As potential barrier layer was in-troduced between a gate electrode and a channel layer. Fig. 1shows the cross section of the Schottky diodes studied. The po-sition of the AlGaAs barrier layer was investigated with respect

0018–9383/01$10.00 © 2001 IEEE

1504 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 8, AUGUST 2001

Fig. 1. Cross sections of the diodes: (a) Diode A and (b) Diode B.

to forward gate current characteristics. The gate electrode isWSi metal and its diameter is 100m. Diode A has the bar-rier layer between an upper AlGa As electron supply layerand an Al Ga As gate contact layer (gate electrode side).Diode B has it between the InGa As channel layer andthe upper Al Ga As electron supply layer (channel layerside). Fig. 2 shows the forward gate– characteristics of theSchottky diodes. The dashed line exhibited the gate current den-sity, which is equal to of 1 mA/mm for definition of anFET. s for Diode A and B were 0.79 V and 0.91 V, respec-tively. As compared with a diode without the barrier layer, theincrease in s for Diode A and B were 50 mV and 170 mV,respectively.

To analyze the dependence of forward gate current character-istics on the barrier position, we calculated forward gate currentdensities under different gate voltage () for each structure.First, a one-dimensional (1-D) self-consistent calculationswere carried out to obtain conduction band diagrams beneaththe gate electrode. Next, gate current densities () from thegate to the channel layer were calculated with the conduction

Fig. 2. Forward gateI–V characteristics for the diodes.

Fig. 3. CalculatedJ as a function ofV for the diodes in Fig. 1. (a) Log plotand (b) logarithmic plot.

band diagrams using the Wentzel–Kramers–Brillouin approx-imation. A barrier lowering by image force was taken intoaccount. A Schottky barrier height of WSi/AlGa As of1.0 eV was employed for calculation, which was obtainedthrough the – measurement using a WSi/AlGa AsSchottky diode fabricated. A conduction band discontinuityof Al Ga As/Al Ga As was assumed to be 0.21 eV[11]. Fig. 3 shows the calculated – characteristics in alinear and a logarithmic plot. Diode B showed a reduced

BITO et al.: ENHANCEMENT-MODE POWER HETEROJUNCTION FET 1505

Fig. 4. Calculated conduction band diagrams under differentV g for the diodesin Fig. 1.

under high forward region, thus exhibiting the highestamong the three structures. These calculated results show agood accordance with the experimental results shown in Fig. 2.Fig. 4 shows the conduction band diagrams under differentsfor Diode A and B. With increasing , the barrier height of theAl Ga As layer for Diode A is lowered. On the other hand,even biased at a high positive of 0.9 V, the barrier height ofthe Al Ga As layer for Diode B is still high, as comparedwith that of Diode A. Therefore, the barrier layer at the channellayer side (i.e., Diode B) effectively reducesat high forward

. This results in improved .

B. Al Mole Fraction of AlGaAs Barrier Layer

In order to investigate the influence of Al mole fraction ofthe AlGaAs barrier layer on , various diodes were fabricatedusing epitaxial wafers with a 5 nm thick AlGa As (

, 0.5 and 0.8) barrier layer between the channel layer andthe upper Al Ga As electron supply layer. Fig. 5 shows theforward gate – characteristics of the fabricated diodes. As theAl mole fraction of the Al Ga As barrier layer increases,the value increases. As compared with a diode without thebarrier layer, of the diode with an Al Ga As layer wasimproved by 330 mV.

Fig. 5. Forward gateI–V characteristics for the diodes with different Al molefraction AlGaAs barrier layers.

TABLE ISUMMARY OF DC CHARACTERISTICS FOR THEFABRICATED HJFETs

Then, we fabricated HJFETs using epitaxial wafers with thesame AlGaAs barrier layers as discussed above. The gate lengthof the FETs was 0.5 m. DC characteristics are summarizedin Table I. As the Al mole fraction of barrier layer increases,

, defined at gate-to-source current of 1 mA/mm, increases inthe same manner as shown in Fig. 5. However, decreasesand increases due to the presence of the AlGaAs barrierlayer beneath the ohmic electrodes. There are undesirable forlow voltage operation [10]. Among FETs tested, an FET with anAl Ga As barrier layer exhibited a high and small degra-dation in and , although the device showed a contactresistance of 0.7 mm, which was 0.4 mm higher than that ofa device without the barrier layer. Consequently, we concludedthat the HJFET with the 5 nm thick Al Ga As barrier layerat the channel layer side is suitable for the purpose.

C. Thickness of GaAs Gate Burying Layer (Depth of SecondGate Recess)

In addition to the insertion of the barrier layer, suppressionof a gate current assisted by the parallel conduction path inthe upper Al Ga As electron supply layer was also foundto be important for achieving a high for the HJFET. We

1506 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 8, AUGUST 2001

Fig. 6. Forward gateI–V characteristics for the fabricated HJFETs withdifferent thickness of GaAs gate burying layer.

Fig. 7. Cross section of HJFET showing two gate current paths.

fabricated HJFETs using epitaxial wafers with different thick-ness of a GaAs gate burying layer ( : 31, 25 and 19 nm,see Fig. 7). Each device has a 5 nm thick AlGa As bar-rier layer between the In Ga As channel layer and the upperAl Ga As electron supply layer. Fig. 6 shows the forwardgate – characteristics of the fabricated HJFETs. Forward gate– characteristics of an HJFET without the barrier layer is also

demonstrated for comparison. With a decrease in the GaAs gateburying layer thickness, gate current was found to be decreased.The decrease is evident at lowregion around 1 mA/mm, thusresulting in an improved . The increase in of the HJFETwith the 19 nm thick is 170 mV, which is same as that ofDiode B shown above.

The dependence of the gate current on the thickness of GaAsgate burying layer was also studied. Fig. 7 shows a proposedgate current model with two gate currents flowing across thecross section of the HJFET. One is a gate current from gateto channel through the Al Ga As barrier layer ( 1). An-other is a gate current from a gate to a source through the upperAl Ga As electron supply layer (2, i.e., gate current due

Fig. 8. Calculated conduction band diagram at the wide recess region (A–Ain Fig. 7).

Fig. 9. Dependence of the sheet carrier densities at channel layer and parallelconduction layer on the thickness of the GaAs gate burying layer.

to the parallel conduction path). Total gate current is the sum-mation of those. Based on the model, the total gate current wascalculated for the parallel connected diodes, where each has adifferent and a different series resistance, respectively. Thediode for 1 is composed of the WSi Schottky diode and theAl Ga As barrier with of 0.9 V, as shown in Section II-A.On the other hand, the diode for2 is the WSi Schottky diodewith of 0.7 V. The series resistance for1 was obtained tobe 1.7 through experimental measurements. Then, the seriesresistance in the parallel conduction path for2 was estimated.Fig. 8 shows the conduction band diagram at a wide recess re-gion ( – in Fig. 7), calculated by a 1-D self-consistent solver.The surface potential of GaAs was assumed to be 0.7 eV. Thesheet carrier densities at Regions 1 and 2 (see Fig. 8) are relatedto the channel conduction and the parallel conduction paths, re-spectively. Fig. 9 shows the dependence of the sheet carrier den-sities calculated at Regions 1 and 2 on . The reduction in

effectively decreases the carrier density of the parallelconduction path. Resistance () of parallel conduction pathwith of 31, 25 and 19 nm were calculated to be 260, 1040,

BITO et al.: ENHANCEMENT-MODE POWER HETEROJUNCTION FET 1507

Fig. 10. Calculated total gate current with two parallel connected diodescurrents.

and 13 000 , respectively, where the electron mobility of 6000cm /V sec, gate-to-source spacing of 0.5m and gate width of 1mm were assumed. Fig. 10 shows the calculated1s, 2s andthe total gate currents for different s. As increases, 2decreases and , defined at total gate current of 1 mA/mm,increases. The calculated results are in good accordance withthe measured forward gate– characteristics shown in Fig. 6.These results indicate the validity of the proposed model dis-cussing degradation of HJFETs with 2, and a 19 nm thick

is thin enough to suppress the2 while maintaining ahigh and a low .

III. N OVEL HIGH ENHANCEMENT-MODE HJFET

Fig. 11 shows the cross section of the developed enhance-ment-mode HJFET based on the investigation described above.The active part of the FET consists of an undoped InGa Aschannel layer sandwiched between an upper Si-dopedAl Ga As layer and a lower Si-doped AlGa As layer.A double recessed structure was fabricated by electron cy-clotron resonance plasma dry etching with SFand BCl , usingthe Al Ga As layers as etch stops. WSi gate metal wassputter-deposited onto the narrow gate recess. The Au/AuGe/Niohmic contacts were patterned by liftoff, and alloyed at 400C

Fig. 11. Cross section of the novel enhancement-mode HJFET.

Fig. 12. DrainI–V characteristics of the HJFET.

for 1 min. The device has the 5 nm AlGa As barrier layerbetween the In Ga As channel and the upper AlGa Aselectron supply layer. To suppress the gate current assisted bythe parallel conduction path, the thickness of the GaAs gateburying layer was chosen to be 19 nm, which is 12 nm thinnerthan that of the previously reported device [1]. A source-to-gatespacing, gate length and gate-to-drain spacing were 0.5m,0.5 m and 0.5 m, respectively.

IV. DEVICE PERFORMANCE

Fig. 12 shows the drain– characteristics of the devel-oped HJFET. The device exhibited an excellent pinch-offcharacteristic with a positive of 0.17 V, which is definedat a drain current ( ) of 1 mA/mm, as well as a highof 300 mA/mm. The device also exhibited an of lessthan 2 A/mm. The , obtained as a gradient of the linear

1508 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 8, AUGUST 2001

Fig. 13. g andI as a function ofV .

region of drain – characteristics, was 3.7 mm. Fig. 13shows the transconductance () and the as a function of

. The maximum was 320 mS/mm. A gate breakdownvoltage, defined at a gate-to-drain current of1.0 mA/mm,was obtained to be 23 V, which is sufficiently high for 3.5 Voperation. The of the developed HJFET was 0.87 V, whichis 170 mV higher than that of the conventional HJFET withoutthe barrier layer.

The PDC power performance of the HJFET with of 25.6mm was characterized at a drain-to-source voltage () of3.5 V with a 950 MHz /4-shifted quadrature phase shift keying(QPSK) signal. The device was operated under a quiescentdrain current of 250 mA ( 0.32 V). Fig. 14 shows theoutput power ( ), power added efficiency (PAE), gain andadjacent channel leakage power ( ) at 50 kHz off-centerfrequency as a function of the input power (). At of

48.1 dBc, the HJFET exhibited of 0.92 W (29.6 dBm),PAE of 63.6% and an associated gain of 15.1 dB withof0.08 mA. It is notable that this was one-thirteenth to that ofthe previously reported HJFET with of 0.18 V and of0.7 V [2]. The device also exhibited a maximum PAE of 72.1%with of 1.32 W (31.2 dBm).

In Fig. 15, the s at the PDC criteria were plotted as a func-tion of a gate voltage swing margin ( ), defined as a differ-ence between and . The circles represent thes underpower operation for previously reported devices [1], [2] and theconventional HJFET with of 0.27 V. The star represents thatfor the developed device. As increases, decreases. Ac-cording to the results, more than 0.7 V was required for anegligibly low of less than 0.1 mA. Since of the con-ventional HJFET is 0.7 V, more than 0.7 V can not beachieved for an enhancement-mode HJFET without the barrierlayer. These results indicate that the novel structure with theAl Ga As barrier layer is suitable for enhancement-modeHJFETs with excellent power performance.

V. CONCLUSIONS

We have developed a novel enhancement-mode HJFET withan improved of 0.87 V, which is 170 mV higher than that of a

Fig. 14. P , PAE, gain,I andP as a function ofP for the HJFET witha 950 MHz�/4-shifted QPSK signal.

Fig. 15. Dependence of theI at the PDC criteria on�V.

conventional HJFET. The device has a 5 nm thick AlGa Asbarrier layer introduced between the InGa As channellayer and the upper Al Ga As electron supply layer. Thethin GaAs gate burying layer is suitable for suppression of agate current assisted by the parallel conduction path, whichdegrades of an HJFET. The developed enhancement-modeHJFET exhibited a high of 0.87 V and a high of 300mA/mm. Under single 3.5 V operation, the 25.6 mm HJFETexhibited of 0.92 W (29.6 dBm) and PAE of 63.6% with

of 0.08 mA at of 48.1 dBc. This was one-thirteenthto that of the conventional enhancement-mode HJFET. Theseresults indicate that the newly developed enhancement-modeHJFET with the Al Ga As barrier layer is a potentialcandidate for single low voltage operation power applications.

ACKNOWLEDGMENT

The authors would like to thank H. Miyamoto, Y. Ando, W.Contrata, Y. K. G. Hau, and K. Ota for their useful sugges-tions and discussions. They are also grateful to Drs. Z. Shingu,

BITO et al.: ENHANCEMENT-MODE POWER HETEROJUNCTION FET 1509

H. Ishiuchi, T. Itoh, Y. Nashimoto, M. Kuzuhara, I. Mito, M.Ogawa and A. Mineo for their support and encouragement.

REFERENCES

[1] Y. Bito, N. Iwata, and M. Tomita, “64% efficiency enhancement-modepower heterojunction FET for 3.5 V Li-ion battery operated personaldigital cellular phones,” inProc. IEEE Microwave Theory TechniquesDig., 1998, pp. 439–442.

[2] Y. Bito and N. Iwata, “Highly efficient enhancement-mode powerheterojunction FET with multilayer cap and doped recess structure for3.5 V digital cellular phones,”IEEE Electron Device Lett., vol. 20, pp.158–160, Apr. 1999.

[3] S. Yoshida, Y. Wakabayashi, M. Kohno, and K. Uemura, “Greater than70% PAE enhancement-mode GaAs HJFET power amplifier MMICwith extremely low leakage current,” inProc. IEEE Microwave TheoryTechniques Dig., 1999, pp. 1183–1186.

[4] N. Hara, Y. Nakasha, M. Nagahara, K. Joshin, Y. Watanabe, and M.Takikawa, “Current path optimized structure for high drain current den-sity and high gate-turn-on voltage enhancement mode heterostructurefield effect transistors,” inProc. IEEE GaAs IC Symp. Tech. Dig., 1998,pp. 198–120.

[5] E. Glass, J. Huang, M. Martinez, W. Peatman, P. Hartin, W. Valentine,M. LaBelle, J. Costa, and K. Johnson, “A true enhancement mode de-vice technology suitable for dual mode dual band power amplifier ap-plications,” inProc. IEEE RFIC Symp. Dig., 1999, pp. 135–138.

[6] Y. Tkachenko, A. Klimashov, C. Wei, Y. Zhao, and D. Bartle,“E-PHEMT for single supply, no drain switch, and high efficiencycellular telephone power amplifier,” inIEEE GaAs IC Symp. Tech. Dig.,1999, pp. 127–130.

[7] S. Wada, N. Furuhata, M. Tokushima, M. Fukaishi, H. Hida, and T.Maeda, “0.1-�m p -GaAs gate HJFET’s fabricated using two-step dry-etching and selective MOMBE growth techniques,”IEEE Trans. Elec-tron Devices, vol. 45, pp. 1183–1189, June 1998.

[8] M. Nakamura, S. Wada, M. Abe, H. Kawasaki, and I. Hase, “A buriedp-gate heterojunction field effect transistor for a power amplifier of dig-ital wireless communication systems,” inProc. IEEE Microwave TheoryTechniques Dig., 1999, pp. 1095–1098.

[9] K. Nishii, M. Nishitsuji, T. Yokoyama, S. Yamamoto, A. Tamura, and K.Inoue, “High-current and high-transconductance self-aligned p-GaAsjunction HFET of complete enhancement-mode operation,”Jpn. J. Appl.Phys., vol. 38, pp. 2555–2558, 1999.

[10] N. Iwata, M. Tomita, K. Yamaguchi, H. Oikawa, and M. Kuzuhara, “7mm gate width power heterojunction FET’s for Li-ion battery operatedpersonal digital cellular phones,” inProc. IEEE GaAs IC Symp. Tech.Dig., 1996, pp. 119–122.

[11] E. E. Mendez, E. Calleja, and W. I. Wang, “Tunneling through indi-rect-gap semiconductor barriers,”Phys. Rev. B, vol. 34, pp. 6026–6029,1986.

Yasunori Bito (M’95) received the B.E. and M.E. de-grees in nuclear engineering from Kyoto University,Japan, in 1993 and 1995, respectively.

He joined NEC Corporation, Shiga, Japan, in 1995.He has been engaged in the research and developmentof GaAs power FETs for mobile communication sys-tems. His recent research interest focuses on the de-velopment of enhancement-mode power heterojunc-tion FETs for 3 G mobile handsets.

Mr. Bito is a member of the Institute of Electronics,Information, and Communication Engineers.

Takehiko Kato received the B.E. and M.E. degreesin materials physics from Osaka University, Japan, in1996 and 1998, respectively.

He joined NEC Corporation, Shiga, Japan, in 1998.He has been engaged in the development of GaAsFETs and MMICs.

Mr. Kato is a member of the Institute of Elec-tronics, Information, and Communication Engineers.

Naotaka Iwata (M’93–SM’00) received his B.E.degree in materials science from University ofElectro-communications in 1981, and the M.E. andPh.D. degrees in materials science from Universityof Tsukuba, Japan, in 1983 and 1999, respectively.

He joined NEC Corporation, Shiga, Japan, in1983. He was engaged in the growth and char-acterization of III–V compound semiconductors.Since 1989 he has been engaged in the researchand development of high power FETs using III–Vcompound semiconductor heterojunctions for

mobile communication systems.Dr. Iwata is a member of the Institute of Electronics, Information, and Com-

munication Engineers.