Engr433 – Combinational Review 1

Engr433: Digital Design

Review of Combinational Circuits

Dr. Curt Nelson

Combinational Review Topics

• Number Systems– Bases

• Decimal• Binary• Hexadecimal

– Conversions• Decimal <==> Binary• Decimal <==> Hexadecimal• Binary <==> Hexadecimal

• Basic gates– Inverters, And, Nand, Or, Nor, Xor, Xnor

Engr433 – Combinational Review 2

Combinational Review Topics - Continued

• Boolean Algebra– Basic Laws– De'Morgans Theorems

• Truth Tables– Minterms, Sum of Products– Maxterms, Product of Sums

• Karnaugh Maps– Sum of Products - Minterms– Product of Sums - Maxterms– Minimization

• Don't Cares– Entered Variable Mapping (EVM)

Combinational Review Topics - Continued

• Medium and Large Scale Integration (MSI and LSI)– Arithmetic: Adders / Subtractors– Data Format Converters: Encoders / Decoders– Data Selectors: Multiplexers/Demultiplexers– Other functions

Engr433 – Combinational Review 3

Digital Abstraction

w 0

En

y 0 w 1 y 1

y 2 y 3

(b) Graphic symbol

(c) Logic circuit

w 1

w 0 y 0

y 1

y 2

y 3

En

• Why do we use abstraction in the digital arena?– To manage complexity.

Digital Abstraction

x 1

x 2

++++++++++ ++++++ +++ ++++++++++++ ++++++ +++++++++++++++ +++++++++ +++++++++++ +++++++++++

Drain (type n)Source (type n)

Substrate (type p)

SiO 2

V S 0 V =

V G 0 V =

V D

++++++++++++++++++++++++

(a) Circuit

V f

V DD

(b) Truth table and transistor states

on

on

on

off

0

1

0

0

1

1

0

1

off

off

on

off

off

on

f

off

on

1

1

1

0

off

off

on

on

V x 1

V x 2

T 1

T 2

T 3

T 4

x 1 x 2 T 1 T 2 T 3 T 4

Engr433 – Combinational Review 4

Truth Tables

• All combinations of inputs on the left;• Outputs on the right;• 2-input AND and OR functions shown below.

Truth Table Proof of DeMorgan’s Theorem

x × y = x + y DeMorgan’s Theorem

Engr433 – Combinational Review 5

DeMorgan’s Theorems in Terms of Logic Gates

x 1

x 2

x 1

x 2

x 1

x 2

x 1

x 2

x 1

x 2

x 1 x 2

x 1 x 2 x 1 x 2 + = (a)

x 1 x 2 + x 1 x 2 = (b)

• Function vs. Gate

x 1 x 2

x 3 x 4 x 5

x 1 x 2

x 3 x 4 x 5

x 1 x 2

x 3 x 4 x 5

SOP Implementation Using NAND Gates

Engr433 – Combinational Review 6

x 1

x 2

x 3 x 4

x 5

x 1

x 2

x 3

x 4

x 5

x 1

x 2

x 3

x 4

x 5

POS Implementation Using NOR Gates

1 0

1 0

1 0

1 0

1 0

x 1

x 2

A

B

f Time

x 1

x 2

1 1 0 0 ® ® ®

f 0 0 0 1 ® ® ®

1 1 0 1 ® ® ®

0 0 1 1 ® ® ®

0 1 0 1 ® ® ®

A

B

Timing Diagram

Engr433 – Combinational Review 7

Logic Synthesis

• Logic synthesis, or logic optimization, is the process of translating a truth table, schematic, or VHDL code into a network of logic gates.

• Example:• Minterm form;• Maxterm form;• Minimum form.

f

(a) Sum-of-products realization

x 1 x 2 x 3

SOP Implementation – NAND Gates

Engr433 – Combinational Review 8

(b) Product-of-sums realization

f

x 1

x 2

x 3

POS Implementation – NOR Gates

Minimal Implementation

Engr433 – Combinational Review 9

a b c d 00 01 11 10

00

01

11

10

b

d

a

c

m 0 m 1 m 5

m 4 m 12m 13

m 8 m 9

m 3 m 2 m 6

m 7 m 15m 14

m 11m 10

4-Variable Karnaugh Map (Kmap)

Four-variable function f = S m(2, 3, 5, 6, 7, 10, 11, 13, 14)

a b c d 00 01 11 10

1 1

1 1

1 1

00

01

11

10 1 1

1

4-Variable Kmap Example

Engr433 – Combinational Review 10

f = S m(2, 4, 5, 6, 10) + d(12, 13, 14, 15)

a b c d

0 00 01 11 10

1 d 0

0 1 d 0

0 0 d 0

1 1 d 1

00

01

11

10

4-Variable Function with Don’t Cares

Entered Variable (EV) Mapping

• Sometimes called Map Entered Variables (MEV’s);• Allows many variables to be presented using a reduced

size K-map;• Occurs quite frequently in digital systems, especially state

machines;• May require K-map compression and expansion;• References (entered-variable mapping or map-entered variables):

• Tinder, Engineering Digital Design, Second Edition (Library);• Other digital logic textbooks;• Web – YouTube, etc.

Engr433 – Combinational Review 11

Entered Variable (EV) Mapping Example

f = S m(2, 5, 6, 7)

a cb a b c

0

00 01 11 10

0

1

1 1 0

0 0 1 1

f = a’bc’ + ab’c + abc’ + abc= bc’ + ac

Entered Variable Truth Table Compression

a b

0 0 0 1 1 0 1 1

0 c’

1 c

f a cb

Engr433 – Combinational Review 12

Entered Variable Map Compression

b

0

1

0 1

0 c

1 c’

a a b c

0

00 01 11 10

0

1

1 1 0

0 0 1 1

f = a’bc’ + ab’c + abc’ + abc= bc’ + ac

Three Variable Compression Example

b

0

1

0 1

1 c’

0 1

a a b c

1

00 01 11 10

0

1

1 0 1

1 1 0 0

1 = c + c’

0 = cc’

Engr433 – Combinational Review 13

The function f = S m(0, 2, 4, 5, 10, 11, 13, 15)

ab c d 00 01 11 10

1

1

1

1

1

1

00

01

11

10 1

1

Four Variable Compression Example

a bc

0

1

00 01 11 10

d’

d’

1

0

d

d

0

1

ab

0

1

0 1

c’d’+cd’ =d’

c’1 + c0 = c’

c’0+c1 = c

c’d+cd=d

Other Examples

• Expansion;• Compression and expansion using don’t cares.

Engr433 – Combinational Review 14

MSI Circuits – Half Adder

Sum

s

0

1

1

0

Carry

c

0

0

0

1

0

0 +

0

1 +

1 0 0 0

1

0 +

1 0

1

1 +

0 1

x

y +

s c

Sum Carry

(a) The four possible cases

x y

0

0

1

1

0

1

0

1

(b) Truth table

x

y s

c

HAx

y

s

c

(c) Circuit (d) Graphical symbol

MSI Circuits – Full Adder

0 0 0 1 0 1 1 1

c i 1 + 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

c i x i y i

00 01 11 100 1

x i y i c i

1 1

1 1

s i x i y i c i Å Å =

00 01 11 100 1

x i y i c i

1 1 1 1

c i 1 + x i y i x i c i y i c i + + =

c i

x i y i s i

c i 1 +

(a) Truth table

(b) Karnaugh maps

(c) Circuit

0 1 1 0 1 0 0 1

s i

Engr433 – Combinational Review 15

N-bit Ripple Carry Adder

FA

x n – 1

c n c n 1 ”

y n 1 –

s n 1 –

FA

x 1

c 2

y 1

s 1

FAc 1

x 0 y 0

s 0

c 0

MSB position LSB position

• Major issue – propagation delay.

Faster Adders – Carry Lookaheadx 1 y 1

g 1 p 1

s 1

x 0 y 0

s 0

c 2

x 0 y 0

c 0

c 1

g 0 p 0

Engr433 – Combinational Review 16

Adder / Subtractor Circuit

s 0 s 1 s n 1 –

x 0 x 1 x n 1 –

c n n -bit adder

y 0 y 1 y n 1 –

c 0

Add ⁄ Sub control

Multiplexers

• Devices that select one of many inputs to be routed to one output based on the binary value of select lines• Enable – used to enable or disable the complete function;• Select – used to select which one of the inputs gets routed to the

output.

0

i n 1 –

inputs

EnEnable

output y 0

i 2 n

select

n select lines

Engr433 – Combinational Review 17

• Mux’s can be used to synthesize logic functions as follows:– Create truth table;– Compress as necessary;– Implement.

• In general, an N variable function can be implemented with one N-1 multiplexer and at most, one inverter.

Synthesis of Logic Functions Using Mux’s

0 0 0 1 1 0 1 1

0 0 0 1

0 0 0 1 1 0 1 1

0 1 1 1

w 1 w 2 w 3 f

0 0 0 0 1 1 1 1

0 1

f w 1

w 2 w 3 w 2 w 3 +

(a) Truth table

(b) Circuit

f w 3

w 1 w 2

Example: 3-Input Majority Function

Engr433 – Combinational Review 18

• A de-multiplexer is a circuit which places the value of a single data input onto one of a number of outputs.

w 1

w 0 y 0

y 1

y 2

y 3

Data

De-Multiplexers

0

w n 1 –

n inputs

EnEnable

2 n outputs

y 0

y 2 n 1 –

w

An n-to-2n Decoder

• A decoder is a device that activates one output based on the binary value of the inputs;

• A decoder is a minterm generator;• Enable – used to enable or disable the complete decoder

function.

Engr433 – Combinational Review 19

0 0 1 1

1 0 1

y 0 w 1

0

w 0

x x

1 1

0

1 1

En

0 0 0

1

0

y 1

1 0 0

0

0

y 2

0 1 0

0

0

y 3

0 0 1

0

0

(a) Truth table

w 0

En

y 0 w 1 y 1

y 2 y 3

(b) Graphic symbol (c) Logic circuit

w 1

w 0 y 0

y 1

y 2

y 3

En

A 2-to-4 Decoder

2 n inputs

w 0

w 2 n 1 –

y 0

y n 1 –

n outputs

A 2n-to-n Binary Encoder

• An encoder is a device that outputs a binary code representing which one of many inputs is active.

• Priority encoder – assigns priority to certain inputs• Used in embedded computer systems to service interrupts.

Engr433 – Combinational Review 20

1 0 1 1

1 1 1

w 0 a

1

b

0 1

1 1

1

0 1

1 0 1

0

0

w 1

0 1 1

0

0

w 2

0 0 0

0

1

w 3

0 0 0

0

0

c

1 0 1 0

0 1 1 0

1 1 1 0

0 0 0 1

1 0 0 1

1 1 1 1

0 1 1

0

1 1

1 1

1

1 1

0 1 1

1

d

0

1 0

0

1 0

e

1 0 1

1

1

0 1

0

0 1

0 0 0

1

f

1

0 0

1

1 1

g

1 0 1

1

1

1 1

1

0 1

(c) Truth table

(a) Code converter

w 0

a

w 1

b c d w 2

w 3 e f g

a

c e g

b f

d

(b) 7-segment display

BCD to 7-segment Code Converter

i 0

i 1

i 2

i 3

b 0

a 0

b 1

a 1

b 2

a 2

b 3

a 3

AeqB

AgtB

AltB

A Four-bit Magnitude Comparator

Engr433 – Combinational Review 21

Arithmetic Logic Units (74HC381)