Engr354 Chapter 6 1

Engr354: Digital Logic Circuits

Chapter 6: Combinational Blocks

Dr Curtis Nelson

Chapter 6 Overview

In this chapter you will learn about:• Commonly used combinational sub-circuits;• Multiplexers, which can be used for selection of signals

and for implementation of general logic functions;• Circuits for encoding, decoding, and code-conversion

purposes.

Engr354 Chapter 6 2

Combinational Circuits

• Combinational circuits are those whose outputs are completely defined by the inputs, i.e. no memory is involved.

• Examples include• Basic gates like Nands, Nors and Inverters;• Multiplexers, de-multiplexers;• Decoders, encoders, code converters;• Arithmetic circuits;• Magnitude comparators;• Parity checkers;• Etc.

Multiplexers

• Devices that select one of many inputs to be routed to one output based on the binary value of select lines• Enable – used to enable or disable the complete function;• Select – used to select which one of the inputs gets routed to the

output.

0

i n 1 –

inputs

EnEnable

output y 0

i 2 n

select

n select lines

Engr354 Chapter 6 3

(a) Graphical symbol

f

s

w0w1

0

1

(b) Truth table

01

f

fs

w0

w1

(c) Sum-of-products circuit

sw0w1

2-to-1 Multiplexer

f

s 1

w 0 w 1

0001

(b) Truth table

w 0 w 1

s 0

w 2 w 3

1011

0 0 1 1

1 0 1

f s 1

0

s 0

w 2 w 3

f

(c) Circuit

s 1

w 0

w 1

s 0

w 2

w 3

(a) Graphical symbol

4-to-1 Multiplexer

Engr354 Chapter 6 4

0

w 0 w 1

0

1

w 2 w 3

0

1

f 0

1

s 1

s

Using 2-to-1 Mux’s to Build a 4-to-1 Mux

x 1 0

1

x 2 0

1

s

y 1

y 2

x 1

x 2

y 1

y 2

(a) A 2x2 crossbar switch

(b) Implementation using multiplexers

s

Practical Application

Engr354 Chapter 6 5

Multiplexer Data Sheet

• 74HC153 Dual 4-Line to 1-Line Data Selectors/Multiplexers

• Mux’s can be used to synthesize logic functions as follows– Create truth table;– Compress as necessary;– Implement.

• In general, an N variable function can be implemented with one N-1 multiplexer and at most, one inverter.

Synthesis of Logic Functions Using Mux’s

Engr354 Chapter 6 6

(a) Implementation using a 4-to-1 multiplexer

f

w 1

0 1

0

1

w 2

1 0

0

0

1

1

1

0

1

f w 1

0

w 2

1

0

(b) Modified truth table

0

1 0

0

1

1

1

0

1

f w 1

0

w 2

1

0 f

w 2

w 1 0

1

f w 1

w 2

w 2

(c) Circuit

Example 2-Input Function

w3w3

(a) Modified truth table

00011

101

fw1

0

w2

1

0 00 11 01 1

0001

0 00 11 01 1

0111

w1 w2 w3 f

00001111

f

w1

0

w2

1

(b) Circuit

w3

Example 3-Input Majority Function

Engr354 Chapter 6 7

0 0 0 1 1 0 1 1

0 0 0 1

0 0 0 1 1 0 1 1

0 1 1 1

w 1 w 2 w 3 f

0 0 0 0 1 1 1 1

0 1

f w 1

w 2 w 3 w 2 w 3 +

(a) Truth table

(b) Circuit

f w 3

w 1 w 2

Example 3-Input Majority Function

f

w 1

w 2

(b) Circuit

w 3

(a) Truth table

0 0 0 1 1 0 1 1

0 1 1 0

0 0 0 1 1 0 1 1

1 0 0 1

w 1 w 2 w 3 f

0 0 0 0 1 1 1 1

w 3

w 3

w 3

w 3

Example 3-Input XOR Function

Engr354 Chapter 6 8

• A de-multiplexer is a circuit which places the value of a single data input onto one of a number of outputs.

w 1

w 0 y 0

y 1

y 2

y 3

Data

De-Multiplexers

0

w n 1 –

n inputs

EnEnable

2 n outputs

y 0

y 2 n 1 –

w

An n-to-2n Decoder

• A decoder is a device that activates one output, whose outputs are usually active low, based on the binary value of the inputs;

• A decoder is a minterm generator;• Enable – used to enable or disable the complete decoder

function.

Engr354 Chapter 6 9

0 0 1 1

1 0 1

y 0 w 1

0

w 0

x x

1 1

0

1 1

En

0 0 0

1

0

y 1

1 0 0

0

0

y 2

0 1 0

0

0

y 3

0 0 1

0

0

(a) Truth table

w 0

En

y 0 w 1 y 1

y 2 y 3

(b) Graphic symbol (c) Logic circuit

w 1

w 0 y 0

y 1

y 2

y 3

En

A 2-to-4 Decoder

w 2

w 0 y 0 y 1 y 2 y 3

w 0

En

y 0 w 1 y 1

y 2 y 3

w 0

En

y 0 w 1 y 1

y 2 y 3

y 4 y 5 y 6 y 7

w 1

En

3-to-8 Decoder Using 2-to-4 Decoders

Engr354 Chapter 6 10

w 0

En

y 0 w 1 y 1

y 2 y 3

y 8 y 9 y 10y 11

w 2

w 0 y 0 y 1 y 2 y 3

w 0

En

y 0 w 1 y 1

y 2 y 3

w 0

En

y 0 w 1 y 1

y 2 y 3

y 4 y 5 y 6 y 7

w 1

w 0

En

y 0 w 1 y 1

y 2 y 3

y 12y 13y 14y 15

w 0

En

y 0 w 1 y 1

y 2 y 3

w 3

En

Decoder Tree

Decoder Data Sheet

• 74HC138 Single 3-Line to 8-Line Decoders/Demultiplexers

Engr354 Chapter 6 11

Combinational Design with Decoders

• Implement the function f(a,b,c) = Sm(0,3,4,5)using a decoder and random logic.

• Implement the function f(a,b,c) = P M(0,1,4,6)using a decoder and random logic.

Combinational Design with Decoders and Mux’s

• Design a digital circuit which has a 4-bit input, A = A3A2A1A0 and a single output Z. Z is high if A is exactly divisible by 3 and A is not equal to 12. Note that 0 is not divisible by 3 in this circuit. Use a 2-to-4 decoder, a 4-to-1 MUX, and minimum logic gates, if necessary. Note that all inputs and outputs of the MUX and decoder are asserted HIGH.

Engr354 Chapter 6 12

2 n inputs

w 0

w 2 n 1 –

y 0

y n 1 –

n outputs

A 2n-to-n Binary Encoder

• An encoder is a device that outputs a binary code representing which one of many inputs is active. The outputs are usually active low.

• Priority encoder – assigns priority to certain inputs! Used in embedded computer systems to service interrupts.

(b) Circuit

w 1

w 0

y 0

w 2

w 3 y 1

0 0 1 1

1 0 1

w 3 y 1

0

y 0

0 0 1

0

w 2

0 1 0

0

w 1

1 0 0

0

w 0

0 0 0

1

(a) Truth table

A 4-to-2 Binary Encoder

Engr354 Chapter 6 13

d001

010

w0 y1

d

y0

1 1

01

1

11

z

1xx

0

x

w1

01x

0

x

w2

001

0

x

w3

000

0

1

Truth Table for a 4-to-2 Priority Encoder

• Create a circuit using the following truth table for a 4-to-2 priority encoder (z is an output that is asserted whenever any output is asserted).

1 0 1 1

1 1 1

w 0 a

1

b

0 1

1 1

1

0 1

1 0 1

0

0

w 1

0 1 1

0

0

w 2

0 0 0

0

1

w 3

0 0 0

0

0

c

1 0 1 0

0 1 1 0

1 1 1 0

0 0 0 1

1 0 0 1

1 1 1 1

0 1 1

0

1 1

1 1

1

1 1

0 1 1

1

d

0

1 0

0

1 0

e

1 0 1

1

1

0 1

0

0 1

0 0 0

1

f

1

0 0

1

1 1

g

1 0 1

1

1

1 1

1

0 1

(c) Truth table

c e

(a) Code converter

w 0

a

w 1

b c d w 2

w 3 e f g

a

g

b f

d

(b) 7-segment display

BCD to 7-segment Code Converter

Engr354 Chapter 6 14

i 0

i 1

i 2

i 3

b 0

a 0

b 1

a 1

b 2

a 2

b 3

a 3

AeqB

AgtB

AltB

Four-bit Magnitude Comparator

Arithmetic Logic Unit (74HC381)

Engr354 Chapter 6 15

In this chapter you learned about:• Commonly used combinational sub-circuits;• Multiplexers, which can be used for selection of signals

and for implementation of general logic functions;• Circuits for encoding, decoding, and code-conversion

purposes.

Summary