Engr 303 Digital Logic Design

Engineering 303 Lab 14 Folsom Lake College Page 1 of 12

Engr 303 Digital Logic Design

LAB 14 Single Cycle Computer

You will implement the single cycle computer given in Figure 8-15 of the Chapter 8 handout. Implement these designs, compile, simulate, assign pins, download to hardware and test. Include all the design files and waveforms in your final report.

Deliverables: 0) Instruction Memory (InstructionMemory) 1) Single Cycle Computer (SingleCycleComputer)

Demonstration Requirement: Demonstrate Part 1, the final computer executing the given multiplication algorithm on the DE2 board.

Part 0 – Instruction Memory Implement the Instruction Memory verilog module shown below. This module outputs an instruction on IR bus for each corresponding Address input from the Program Counter (PC). This particular module simulates an assembly language program to perform multiplication. In a real system, such a program would be stored in RAM. Here, we are using verilog to implement the instruction memory as "hard-wired" gates. We would have to recompile the module to run a different "simulated assembly langauge" program.

// Instruction Memory Verilog Design

// A simulated assembly language program is implemented as a circuit

module InstructionMemory ( Address, IR );

input [7:0] Address;

output [15:0] IR;

reg [15:0] IR;

// parameters rename things for readability

// this makes it easier to write new programs

// See Table 8-8 // Register Instruction Opcode; [Opcode, DR, SA, SB]

parameter

MOVA = 7'b0000000,

INC = 7'b0000001,

ADD = 7'b0000010,

SUB = 7'b0000101,

DEC = 7'b0000110,

AND = 7'b0001000,

OR = 7'b0001001,

XOR = 7'b0001010,

NOT = 7'b0001011,

MOVB = 7'b0001100,

SFTR = 7'b0001101,

SFTL = 7'b0001110,

LOAD = 7'b0010000,

ST = 7'b0100000,

// Immediate Instruction Opcode; [Opcode, DR, SA, OP]


LDI = 7'b1001100,

ADI = 7'b1000010,

// Jump Branch Instruction Opcode; [Opcode, AD, SA, AD]

BRZ = 7'b1100000,

BRN = 7'b1100001,

JMP = 7'b1110000,

// Registers

R0 = 3'b000,

R1 = 3'b001,

R2 = 3'b010,

R3 = 3'b011,

// Numbers

ZERO = 3'b000,

ONE = 3'b001,

TWO = 3'b010,

THREE = 3'b011,

FOUR = 3'b100,

// NULL

NULL = 3'b000;

// The actual simulated assembly language "program" starts here

// This program multiplies two given inputs A * B = P

always@(Address)

begin

case(Address)

// Start

0: IR <= {LOAD, R0, NULL, NULL}; // load A

1: IR <= {LOAD, R1, NULL, NULL}; // load B

2: IR <= {LDI, R2, NULL, ZERO}; // set P to 0

3: IR <= {LDI, R3, NULL, FOUR}; // load jump address

// Loop

// if A = 0 then branch to done (Address 8)

4: IR <= {BRZ, 3'b001, R0, 3'b000};

5: IR <= {ADD, R2, R2, R1}; // add B to P

6: IR <= {DEC, R0, R0, NULL}; // decrement A

7: IR <= {JMP, NULL, R3, NULL}; // jump to loop (Address 4)

// Done

8: IR <= {ST, NULL, NULL, R2}; // output answer P

default

IR <= 255;

endcase

end

endmodule

The following is a simulation of the Instruction Memory module. We use Table 8-8 and Figure 8-14 from the Chapter 8 handout to check the instructions. The first few are Load to R0, Load to R1, LoadImmediate the value 0 to R2, LoadImmediate the value 4 to R3... and so forth.

Instruction Memory Waveform

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Part 1 – Single Cycle Computer Implement the Single Cycle computer design using the block diagram shown at the end of this document or the following Verilog module. Make sure to include the following folders in your project library. Single Cycle Computer Project Library Folders:

• SevenSeg (Lab 4)

• FullAdder (Lab 4)

• ArithStage (Lab 10)

• LogicStage (Lab 10)

• Mux2to1 (Lab 10)

• Mux4to1 (Lab 10)

• ALUStage (Lab 11)

• FunctionUnit (Lab 11)

• Mux2to1_8bit (Lab 11)

• Shifter8bit (Lab 11)

• ZeroDetect (Lab 11)

• Decoder2to4 (Lab 12)

• GenReg8Bit (Lab 12)

• Mux4to1_8Bit (Lab 12)

• RegisterFile (Lab 12)

• BranchControl (Lab 13)

• Extend (Lab 13)

• InstructionDecoder (Lab 13)

• ProgramCounter8Bit (Lab 13)

• ZeroFill (Lab 13)

• InstructionMemory (Lab 14)

// Single Cycle Computer Verilog Design

module SingleCycleComputer_Verilog

(Clock,ResetN,BusA,BusB,BusD,PCout,DataIn,IR,K,MW,BusDhighnibble,BusDlo

wnibble,BusBhighnibble,BusBlownibble,PCouthighnibble,PCoutlownibble,Bus

Ahighnibble,BusAlownibble);

input Clock,ResetN;

input [ 7:0] DataIn;

output [6:0]

BusDhighnibble,BusDlownibble,BusBhighnibble,BusBlownibble,PCouthighnibb

le,PCoutlownibble,BusAhighnibble,BusAlownibble;

output [7:0] BusA,BusB,BusD,PCout;

output [15:0] IR;

output [1:0] K;

output MW;

wire [19:0] CW;

wire Z,N;

wire [7:0] BusBX,ConstIn,F,BRNdata;

SevenSeg inst0 (.B(BusD[7:4]), .S(BusDhighnibble));

SevenSeg inst1 (.B(BusD[3:0]), .S(BusDlownibble));

SevenSeg inst2 (.B(BusB[7:4]), .S(BusBhighnibble));

SevenSeg inst3 (.B(BusB[3:0]), .S(BusBlownibble));

SevenSeg inst4 (.B(BusA[7:4]), .S(BusAhighnibble));

SevenSeg inst5 (.B(BusA[3:0]), .S(BusAlownibble));

SevenSeg inst6 (.B(PCout[7:4]), .S(PCouthighnibble));


SevenSeg inst7 (.B(PCout[3:0]), .S(PCoutlownibble));

Mux2to1_8bit_Verilog inst8 (.OUT(BusD), .IN0(F), .IN1(DataIn),

.S(CW[5]));

Mux2to1_8bit_Verilog inst9 (.OUT(BusB), .IN1(ConstIn), .IN0(BusBX),

.S(CW[10]));

InstructionMemory inst10 (.Address(PCout), .IR(IR));

InstructionDecoder_Verilog inst11 (IR,CW);

BranchControl_Verilog inst12 (.PL(CW[2]), .JB(CW[1]), .BC(CW[3]),

.Z(Z), .N(N), .K(K));

RegisterFile_Verilog i13 (.Ddata(BusD), .Aaddr(CW[16:14]),

.Baddr(CW[13:11]), .Daddr(CW[19:17]), .Write(CW[4]), .ResetN(ResetN),

.Clock(Clock), .Adata(BusA), .Bdata(BusBX));

FunctionUnit_Verilog i14 (.F(F), .V(), .C(), .N(N), .Z(Z), .A(BusA),

.B(BusB), .FS(CW[9:6]));

ZeroFill_Verilog inst15 (.IN(IR[2:0]), .OUT(ConstIn));

Extend_Verilog inst16 (.IN({IR[8:6] , IR[2:0]}), .OUT(BRNdata));

ProgramCounter8Bit_Verilog inst17 (.Clock(Clock), .JMPdata(BusA),

.BRNdata(BRNdata), .PCout(PCout), .K(K), .ResetN(ResetN));

assign MW = CW[3];

endmodule

For this design we don’t have Data Memory. Instead, we will connect the signals that would go to the memory module to switches for data input and seven segment display for the data output. These will be our primary interface to the system. Because this is a complex design, it helps to pull out some of the internal signals to verify that the system is functioning properly while testing. Explanation of Operation Below is a simulation of the single cycle computer for the operation A x B = P (02 x 03 = 06). In the first clock cycle (0-100nS) the value A=02 is read from DataIn and loaded into R0. On the second clock cycle (100-200nS) the value B=03 is read in from DataIn and loaded into R1. In the eight clock cycle (700-800nS) notice the program counter (PCout) change from 07 to 04 which corresponds to the first JMP instruction in our assembly routine. In the twelth clock cycle (1.2-1.2uS) is the second JMP of two, followed by the BRZ instruction to address 08 in the next clock cycle (1.2-1.3uS). The answer (P=06) shows up on the BusB and is indicated by MW going high. MW goes high for the STORE operation which would write the answer to Data Memory and completing the execution of the assembly routine. Don't forget to make ResetN high or nothing will happen.

Validate on DE2 Board To run on DE2 board, press RESET then enter value for A=2 (00000010) on SW[7..0] and press CLK (SW0) to load A into R0. Next enter value of B=3 (00000011) on SW[7..0] and press CLK to load B into register R1. Continue to press CLK until MW (LEDG2) illuminates. The answer P is displayed on BusB (HEX[2..1])


Single Cycle Computer Waveform (executing 2 x 3 = 6)

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Assign the signals using the following pin assignments: Bus A Seven Segment Output

Lab Signal DE2 Name DE2-115 Pin

BusAlownibble[0] HEX0[0] PIN_G18

BusAlownibble[1] HEX0[1] PIN_F22

BusAlownibble[2] HEX0[2] PIN_E17

BusAlownibble[3] HEX0[3] PIN_L26

BusAlownibble[4] HEX0[4] PIN_L25

BusAlownibble[5] HEX0[5] PIN_J22

BusAlownibble[6] HEX0[6] PIN_H22

BusAhighnibble[0] HEX1[0] PIN_M24

BusAhighnibble[1] HEX1[1] PIN_Y22

BusAhighnibble[2] HEX1[2] PIN_W21



BusAhighnibble[5] HEX1[5] PIN_U23

BusAhighnibble[6] HEX1[6] PIN_U24 Bus B Seven Segment Output


BusBlownibble[0] HEX2[0] PIN_AA25

BusBlownibble[1] HEX2[1] PIN_AA26

BusBlownibble[2] HEX2[2] PIN_Y25

BusBlownibble[3] HEX2[3] PIN_W26

BusBlownibble[4] HEX2[4] PIN_Y26



BusBhighnibble[0] HEX3[0] PIN_V21

BusBhighnibble[1] HEX3[1] PIN_U21

BusBhighnibble[2] HEX3[2] PIN_AB20

BusBhighnibble[3] HEX3[3] PIN_AA21

BusBhighnibble[4] HEX3[4] PIN_AD24

BusBhighnibble[5] HEX3[5] PIN_AF23

BusBhighnibble[6] HEX3[6] PIN_Y19


Bus D Seven Segment Output


BusDlownibble[0] HEX4[0] PIN_AB19

BusDlownibble[1] HEX4[1] PIN_AA19

BusDlownibble[2] HEX4[2] PIN_AG21

BusDlownibble[3] HEX4[3] PIN_AH21

BusDlownibble[4] HEX4[4] PIN_AE19

BusDlownibble[5] HEX4[5] PIN_AF19

BusDlownibble[6] HEX4[6] PIN_AE18

BusDhighnibble[0] HEX5[0] PIN_AD18

BusDhighnibble[1] HEX5[1] PIN_AC18

BusDhighnibble[2] HEX5[2] PIN_AB18

BusDhighnibble[3] HEX5[3] PIN_AH19

BusDhighnibble[4] HEX5[4] PIN_AG19

BusDhighnibble[5] HEX5[5] PIN_AF18

BusDhighnibble[6] HEX5[6] PIN_AH18

Program Counter Seven Segment Output


PCoutlownibble[0] HEX6[0] PIN_AA17

PCoutlownibble[1] HEX6[1] PIN_AB16





PCoutlownibble[6] HEX6[6] PIN_AC17

PCouthighnibble[0] HEX7[0] PIN_AD17

PCouthighnibble[1] HEX7[1] PIN_AE17

PCouthighnibble[2] HEX7[2] PIN_AG17

PCouthighnibble[3] HEX7[3] PIN_AH17

PCouthighnibble[4] HEX7[4] PIN_AF17

PCouthighnibble[5] HEX7[5] PIN_AG18

PCouthighnibble[6] HEX7[6] PIN_AA14


Instruction Register Outputs:

LAB SIGNAL DE2 Name DE2-115 Pin

IR[0] LEDR0 PIN_G19

IR[1] LEDR1 PIN_F19

IR[2] LEDR2 PIN_E19

IR[3] LEDR3 PIN_F21

IR[4] LEDR4 PIN_F18

IR[5] LEDR5 PIN_E18

IR[6] LEDR6 PIN_J19

IR[7] LEDR7 PIN_H19

IR[8] LEDR8 PIN_J17

IR[9] LEDR9 PIN_G17

IR[10] LEDR10 PIN_J15

IR[11] LEDR11 PIN_H16

IR[12] LEDR12 PIN_J16

IR[13] LEDR13 PIN_H17

IR[14] LEDR14 PIN_F15

IR[15] LEDR15 PIN_G15 Program Counter Indicators:


K1 LEDG0 PIN_E21

K0 LEDG1 PIN_E22

MW LEDG2 PIN_E25 Data Inputs:


DataIn[0] SW0 PIN_AB28

DataIn[1] SW1 PIN_AC28


DataIn[3] SW3 PIN_AD27

DataIn[4] SW4 PIN_AB27


DataIn[6] SW6 PIN_AD26

DataIn[7] SW7 PIN_AB26 Control Signals:


ResetN Key1 PIN_M21

Clock Key0 PIN_M23


Single Cycle Computer

(see detail the following views, as well as Mano text Figures 8-14, 8-15, 8-16)

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CW[3] CW[5] CW[9..6] CW[10] CW[4] CW[19..17] CW[13..11] CW[16..14] CW[0] CW[1] CW[2]

IR[2..0] IR[2..0

IR[8..6] ExtendIn[5..3] ExtendIn[2..0]

MW

MD

FS[3..0] MB

RW DA[2..0] BA[2..0] AA[2..0]

BC

JB PL


Single Cycle Computer Detail 1

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Single Cycle Computer Detail 2

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CW[3] CW[5] CW[9..6] CW[10] CW[4] CW[19..17] CW[13..11] CW[16..14] CW[0] CW[1] CW[2]

IR[2..0] IR[2..0] IR[8..6] ExtendIn[2..0]

ExtendIn[5..3]

MW

MD

FS[3..0] MB

RW DA[2..0] BA[2..0] AA[2..0]

BC

JB PL


Single Cycle Computer

Detail 3

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Engr 303 Digital Logic Design