ENGN3213 Digital Systems and Microprocessors Course ...courses.cecs.anu.edu.au/courses/ENGN3213/lectures/...Top Down design: ISE WebPACK Work Flow 12 ENGN3213: Digital Systems and

ENGN3213 Digital Systems andMicroprocessors

Course Overview with MU0

1 ENGN3213: Digital Systems and Microprocessors L#3-4

The MU0 Microprocessor...Our road map for the course

➤ A tour of the course by looking at the design of a working microprocessorcalled MU0

➤ The MU0 design in Verilog HDL can be downloaded from the course website. This code can be used for simulation using ICARUS VERILOG

➤ Dont worry if you dont understand everything. Just keep your eye onthe map.

➤ Colour coded viewgraphs...➤ GREEN COLOUR: Take good notice of this,➤ BLUE COLOUR: Look here for more information and➤ RED COLOUR: Be careful of this: either unlearn it or fix it


Microprocessor Design

The central processing unit of a computer is a microprocessor. The CPU is usually the most complex part of acomputer system.

The following two lectures outline the detailed design and implementation of a simple microprocessor.

We will answer the question: How do we do the detailed design of a complex digital system such as amicroprocessor?

The approach taken will be based on the Register Transfer Level Abstraction .

Our vehicule in the discussion will be the design of a realistic but simplistic microprocessor known as MU0.

MU0 is a complete microprocessor and is quite capable of running useful programs. It is also simple enough for a

complete RTL based design and HDL implementation to be discussed from scratch in just two - three lectures.


Overview of the Overview: A top down design of microprocesso r MU0

What we do in the overview...➤ MU0 design assumptions - Specifications

➤ Present some ideas about microprocessors, Verilog hardware definitionlanguage (HDL) and some electronic circuits (L5 - L6)

➤ Simulate the design (L5, L6)

➤ Discuss Finite State Machines (FSM) (L12-L13) and do a RegisterTransfer Level Design and implement the design showing some designtips (L16,L17)

➤ Understand how microprocessors work (L18-22)What we do NOT do in the overview...➤ Do not discuss Picoblaze or C, certain combinational and sequential

circuits in detail, detailed design of finite state machines and the non-idealcharacteristics of digital devices


Introduction to MU0

➤ University of Manchester design (although the resultant design here is myown based on their descriptions)

➤ Very simple processor but somewhat like the Manchester Mark I a SmallScale Experimental Machine.

➤ The SSEM was built using valves and would just fit into a reasonably sizedroom.

➤ The same machine these days would take just a fraction of a percent of theresources of the XC3S500E Xilinx FPGA (Field Programmable Gate Array)



How can we make MU0 so small? ( L8: Configurable logic devices )

➤ Very Large Scale Integration➤ Field Programmable Gate Arrays consist of thousands of logic blocks➤ Interconnect them using software called Hardware Definition Language

➤ FPGA main building block is the Configurable Logic Block (CLB)➤ The basic building block of the Spartan-II CLB is the logic cell (LC).➤ An LC includes a 4-input function generator, carry logic, and storage

element.➤ Output from the function generator in each LC drives the CLB output and

the D input of the flip-flop.➤ Each Spartan-II CLB contains four LCs, organized in two similar slices; a

single slice is shown in the figure.





...How do we design complexdigital systems?

Top down design

Register Transfer Level Abstraction


Top Down design: ISE WebPACK Work Flow


The figure is someone’s idea of a top-down design approach to a digital design.

1. MATLAB is a useful tool for the simulation of physical systems. Even in MATLAB simulations can occur atseveral levels. Microprocessors are simulated at the fixed point/Boolean level. The simulation of a wirelesscommunications link would also require the modelling of antennas and analogue circuits. These affect thespecifications but are not involved in the final digital system. You have no doubt had some exposure to MATLABmodelling. MATLAB could also be used to model MU0 for the purpose of estimating its overall performance for theassumed architecture.

2. At the culmination of this activity emerges a specification for how to realise this system in a digital design.

3. We will be concerned in this course with the Register transfer level design.

4. RTL (Behavioural) simulation provides a description at the system level. This first pass simulation is typicallyperformed to verify code syntax and to confirm that the code is functioning as intended. At this step, real physicaleffects at the gate level are not relevant. An RTL simulation can be performed as soon as the circuit schematic hasbeen drawn.

5. Synthesis will take the RTL and generate a gate level description that can then be placed and routed.

6. The gate level simulation allows you to verify that your design has been synthesised correctly, and you canbegin to identify any differences due to the lower level of abstraction. In particular that the:

* RTL written is SYNTHESISABLE. * have any un-initialized outputs. * design works at the targeted FREQUENCY.* timing violations. * Power requirements.

RTL simulation is not architecture-specific. It can be performed using either ICARUS VERILOG, MODELSIM(Mentor Graphics) or Xilinx XST simulator while steps 5 and 6 will be done in the Electronic Design Automation(EDA) software, ISE WebPACK 9.2i, in this course.

http://www.xilinx.com/itp/xilinx4/data/docs/sim/simu4.html


Design I: Register Transfer Level Abstraction ( L14-15)

➤ Use this approach for all complex digital designs

➤ Split the design into a control path and a data path

➤ The data path consists of the basic functional digital blocks that comprisethe system.

➤ The control path is a Finite State Machine that controls the executionsequence of the different digital blocks in the data path


Design II: Register Transfer Level Abstraction (ctd)


The purpose of the RTL design approach is to break down a complex system into manageable bits that we cantreat in a unified manner.

The control path is a Finite State Machine (FSM) . We will look at these a little in a minute once we have adefinition of a sequential circuit . We will also dedicate several lectures and labs specifically to FSMs. FSMs havea simple VERILOG coding style that we will always adhere to. The standard VERILOG code for an FSM is onpage 651 Table 7-58 of the Fourth Edition book by Wakerly and coding and synthesis with verilog.pdf

The approach to the design of the data path is a less clear. It is the creative part of the design. The data path isthe block diagram of the system and therefore attracts most attention in the RTL design. We will also adhere toVERILOG coding rules here as most of the pitfalls of digital design occur in the data path.

When using VERILOG to describe hardware we will find it advantageous to think of the data path as a bunch ofinterconnected devices with precisely defined functionality. We will generate the HDL description from theseblocks rather than churning out a spaghetti of behavioural VERILOG. We will then better understand the hardwareproduced by the EDA synthesiser. We will learn VERILOG code that describes basic functional blocks such as flipflops, arithmetic logic units etc.

In the case of MU0 we will see that the system blocks (Multiplexer, Arithmetic Logic Unit, program counter,memory etc) will have enable / disable switches that connect them to the control path FSM. The microprocesor willtherefore resemble a FSM controlling switches - very intuitive.

The formal theory of data path design will also be treated in the course. RTL datapath design is discussed in

chapters 13-15 of the book by Ercegovac.


Electronic Device Abstractions: Combinational Devices ( L7, L8)

➤ A combinational circuit is a device that takes a digital input and producesa unique instantaneous digital output (save propagation delays etc)

➤ A combinational circuit is like a function y = f(x) and we must allowsufficient time for its outputs to settle.


Electronic Device Abstractions: Sequential Devices ( L9, L10)

➤ In a sequential device the result is only transferred to the output at theactive edge of a clock (e.g. D-type flip flop )


The above are actually idealised definitions of combinational and sequential circuits. Hence the use of the termabstraction.

Real combinational circuits are subjected to propagation delays which delay the output y with respect to the inputx. The circuit will not operate correctly if the inputs are changing too quickly. The function f(x) is therefore acomplex time delayed function.

When the combinational circuit operates in a design where there are also sequential circuits, the period of theclock that controls the sequential circuits may be limited by the propagation delays of the combinational circuits.

In sequential circuits, propagation delays affect the stability of of the outputs when the inputs are changing withtime. Firstly, the clock speed has to be low enough that the outputs can settle. The inputs must also be setupsufficiently early before the active clock edge for the output to be valid and the output is only valid if it remains in astable state for a sufficiently long period of time after the active clock edge. In sequential circuit design, minimumsetup and hold times have to be observed.


The Finite State Machine Abstraction ( L12-13)

➤ Changes state according to different inputs. In each state there is a uniqueoutput. (Moore machine) (c.f. (Mealy machine) )

➤ FSMs are sequential systems (use flip-flops to make transitions). In eachstate combinational circuits produce the outputs from inputs.

➤ Only use synchronous state machines in this course


The control path of an RTL system is based on a finite state machine. An FSM is quite abstract, but for thisdiscussion one can think of an FSM as a system that possesses a finite number of states. In each state the outputof the system is fully deterministic. When a new set of inputs is applied, the system undergoes a transition to adifferent state with different outputs. The bubbles in the above figures represent the states and the arrow loopsrepresent the transitions.

Notice that the inputs are written on the loops in the case of the Moore machine. Generally the outputs can bewritten inside the state bubbles of the Moore machine.

In the case of the Mealy machine both the inputs and the outputs are written on the loops. (WHY?)

In this course we will only consider synchronous FSMs. Synchronous FSMs are FSMs in which all transitionsoccur on the active edge of the clock. Moreover, even external inputs to the FSM, though naturally asynchronousbecause they cannot know about the clock, will be rendered synchronous through an appropriate circuit.

Apart from the above state diagrams one can also represent a FSM with a state transition table as follows...

InputsPresentState State

Next Outputs

State transition table


Example: Pedx Controller: Circuit (CLOCK not shown)

➤ Input: Push-button W➤ Car outputs: GYR light➤ Pedestrian outputs: HALT/WALK

s0

G, HALT

Y, HALT

s1

R, WALK

s2

R, HALT

s3

W

W

RESET


Example: Pedx Controller: Circuit


Simple Datapath


...How do we describe and designcircuits?

Schematics and HardwareDefinition Language


Circuit Design I: Schematics

➤ Schematics: Circuits are drawn and connected using software. E.g.PSPICE. An extension of the old days of hand sketching. Normallycomponents can be loaded from libraries.

➤ Works OK for small circuits. Impossible as the sole design tool for complexcircuits (millions of gates).

➤ Schematics are a very inefficient representation of hardware. They requireattention to ALL levels of detail at the same time => incapable ofabstraction.

➤ Generally we will not use schematics in the course, however they areintuitive and we will meet them in the early labs.


Circuit Design II: Hardware Definition Language

➤ Hardware Definition Language (HDL): is a programming language tosimulate and implement hardware in much the same way that JAVA is aprogramming language to implement algorithms on a computer.

➤ Verilog and VHDL are the major HDLs. We will use Verilog (but VHDL forPICOBLAZE)

➤ HDLs are a much more efficient representation of hardware. Capable ofhierarchical abstractions... as we shall now see.

➤ Any HDL can be combined with a schematic in a design thanks to theXilinx ISE WebPACK IDE. We will do this from time to time.

➤ There are concrete conceptual differences between HDLs and ordinaryprogramming languages such as JAVA, C and assembler. HDL programscannot be used in the same way


Verilog HDL ( L5, L6 )

➤ Verilog is based on the combinational and sequential abstractions

➤ This is consistent with the fact that FSMs, datapaths and RTLsystems all contain combinational and sequential sub-circ uits

➤ Verilog can be either for simulation or for synthesis.➤ Simulation is for modelling on a computer (ICARUS VERILOG or XST

Xilinx ISE WebPACK simulator)➤ Synthesis is the hardware implementation process (XST Xilinx ISE

WebPACK synthesiser)

➤ The following figure shows a RTL cartoon of a Verilog program.


Intro to Verilog I: Verilog RTL Program Structure ( L5 )


Intro to Verilog II: Anatomy of a Verilog Module ( L5)


Intro to Verilog III: Modelling sequential and combination al circuits ( L5 )


The main construct in VERILOG for modelling circuit behaviour is the always block. The ampersand character isplaced before a parenthesised list of sensitivity parameters . If the sensitivity list contains a posedge clk ornegedge clk , where clk is a clock variable then the contents of the always block will be executed at the positive(resp. negative) edge of the clock. This clock can represent any clock in the design: not just the system clockwhich is the main clock into the FPGA.

In this case the always block is edge sensitive . This is the verilog construct for modelling a sequential circuit.

If more than one parameter is present in the sensitivity list then they are each separated by an ’or ’.

If the sensitive list only contains parameters without a posedge or negedge , then the contents of the alwaysblock is executed whenever any of the parameters in this list changes.

In this case the always block is level sensitive . This is the verilog construct for modelling a combinational circuit.

Notice that edge sensitive always blocks can also contain level sensitivities. These can be thought of assequential circuits with enables . But they are still sequential circuits .

It is important that all the inputs to which your circuit is sensitive appear in the always block sensitivity list. Failureto do so is akin to clipping the input wire from that input to your circuit. Erratic unpredictable behaviour will ensueas one would expect for the case of a real circuit .

Important Concept: Blocking and Non-blocking assignments . Notice that the sequential VERILOG circuitwhich triggers on the clock edge transitions uses a <= operator to make assignments whereas thecombinational VERILOG circuit which triggers on input levels uses a = operator to make assignments.

These are known respectively as non-blocking (<=) and blocking assignments (=).

(PTO).


Non-blocking assignments do exactly what you would expect for sequential circuits. When the clock transitionsoccur the variable on the left hand side is set to the value of that at the right hand side at the instant of the clocktransition. Thus in the example X would take on the value that Y had when the clock transition occurred. Y takeson the value that A had when the clock transition occurred. After the clock transition X and Y may or may nothave the same value (depending on the value of A) .

Blocking assignments do exactly what you would expect for combinational circuits. When some input levelchanges, the variables on the left hand side of the = sign settle to the values on the right. The settling processimplies that assignment is blocked until all variables take on their time asymptotic values. This is exactly what onewould hope for a combinational circuit. In some (infinitely short ) time the left hand sides will settle to the righthand sides.

Question 1: In a sequential ALWAYS block can the same variable appear on both sides of the equations in theassignment block? (WHY?)

Question 2: In a combinational ALWAYS block can the same variable appear on both sides of the equations in theassignment block? (WHY?)

Sometimes you will read that the blocking equals sign is executed sequentially as in C or JAVA. Thus in the aboveexample, if we first have D = B and instead follow this with B = A, then after settling we would find that D takeson the initial value of B and B settles to the initial value of A.

This is in fact what Verilog simulators DO. However combinational circuits do NOT do this.

Consequently, when using blocking assignments in Verilog we will NOT have the same variable on boththe left and the right handside

Moreover we will not use both blocking and non-blocking assi gnments in the same always block

Finally note that blocking and non-blocking assignments onl y ever appear inside ALWAYS blocks


Verilog Description of an FSM ( L5 )

➤ Verilog can be used to describe higher levels of abstraction thancombinational and sequential circuits.

➤ The transition between states is a sequential operation (in the sense of asequential circuit )

➤ In a FSM the actions that produce outputs from the inputs arecombinational

➤ Consider the following Verilog template for a synchronous FSM


Verilog Description of an FSM ( L5 )


RTL design of MU0...


MU0 Design: Step 1 Specifications

➤ MU0 is a microprocessor with a Von Neumann architecture

➤ A 16 bit machine with a 12 bit address space.

➤ One instruction will execute in two clock cycles

➤ An instruction consists of fetch , store , decode and execute

➤ Instruction format: 4 bit instruction (opcode ) with a 12 bit address. Noimmediate operand.


MU0 Design: Step 1 Specifications: Assembly Language Instru ctions ( L21)


Example: An assembly language program ( L16-17: RTL Systems )


A microprocessor is a device that can perform mathematical operations on data stored in memory by followinginstructions that are also stored in memory. If the instructions are stored in the same memory as the data, themicroprocessor is said to have a Von Neumann Architecture. It is also possible to store the instructions in aseparate memory. Such an architecture is a Harvard Architecture.

A 16 bit machine is one in which the data words are 16 bits wide. A 16 bit word can represent the integers from 1to 65536 (WHY?). Can it represent negative integers as well?

A 12 bit memory address space refers to the number of locations where data bits can be stored in the memory ofthe microprocessor. How many memory locations are possible with 12 bit addresses?

Note that even though the address is only 12 bits deep, the dat a stored at the addresses must still be 16bits wide

The instruction has the same width as a data word (16 bits). It consists opcode which in the case of MU0 is a 4 bitnumerical mneumonic that represents the operators. Having 4 bit opcodes means that MU0 can interpret up to 16instructions. In fact MU0 will only have eight instructions defined for it and this is quite minimal by modernstandards.

Finally notice that the remainder of the instruction word is 12 bits. This has the same length as the memory depth.Thus the instruction word consists of the opcode and the address in memory of the operand (data word on whichthe operation will be performed).

It is the job of the control path FSM to interpret the opcodes and instigate the execution of instructions. We willshow how this is done.

The requirements listed above more or less completely specify t he RTL design of MU0.


Review: RTL Design


MU0 Design Step 2: Datapath - Specify the basic hardware blocks

➤ A program counter (PC) . A register from which the address of the currentinstruction is fetched. The PC is incremented everytime an instruction isexecuted. This is how programs run sequentially

➤ An instruction register (IR) which stores the current instruction wordwhile it is being executed

➤ A memory bank in which program and data are stored. In the VonNeumann architecture we assume that the program data comes first inmemory and the data follows

➤ An arithmetic logic unit (ALU) that does arithmetic and other functions

➤ An accumulator (or working register) . A register in which data can betemporarily stored

➤ Some multiplexers to allow datapaths to be switched


What does this example teach us about digital design?

➤ Always design hardware systems using well defined hardware blocks withclean interfaces and avoid coding Verilog in a logical fashion like ir were C

➤ Always be prepared and able to draw schematics that clearly describe yourhardware

➤ Be able to relate your VERILOG to hardware


Always design hardware systems using well defined hardware blocks with clean interfaces and avoid codingVerilog in a procedural fashion

It might seem that any requirement to treat the data path design from a hardware block approach with well definedinterfaces would appear to detract from Verilog’s heirarchical advantage. However this is not the case. Already wehave seen several Verilog abstractions. The abstraction of combinational and sequential circuits, the FSMabstraction and soon an RTL abstraction. These abstractions represent different heirarchies of design. Once youunderstand Verilog well enough you will be able to design functional blocks with well defined interfaces such thatyou will understand what they do and have a pretty good idea of how they synthesise into hardware.


Program Counter, Instruction Register and Accumulator are Registers

➤ Whenever we need to take a snapshot of a data word we need a oneaddress memory

➤ A one address memory is known as a register➤ When enabled a register latches data present at its input to its output on

the active edge of a clock➤ A register is a sequential circuit (or D-type flip-flop)


Memory

➤ A memory is a sequential circuit which can store a bank of data wordsaccording to their addresses.

➤ The width of the memory is the length of the data words that it stores.➤ The depth of the memory is the number of addresses where it can store

data.➤ Memory is just a bunch of registers numbering the depth of the memory.➤ A memory is written to by applying a voltage level to its write-enable (Wen)

port while applying the data word to be stored on its input bus. As for aregister, the input word is latched into memory by an active clock transition.

➤ A memory is read from by applying a voltage level to its read-enable (Ren)port while reading the data word on its output bus after an active clocktransition.

➤ Examples of memory are RAM and ROM.


Memory


A Multiplexer (MUX)

➤ A MUX allows us to choose between two inputs X or Y by applying avoltage level to a select input, Sel.

➤ A MUX is a combinational circuit because it acts instantaneously and doesnot use a clock.


Arithmetic Logic Unit ( L6: Digital system components )

➤ An ALU takes two inputs X and Y and performs a mathematical operationon them to produce output Z.

➤ ALUs may perform several functions according to a programmable multibitselect input, M.

➤ The MU0 ALU performs addition, subtraction, incrementation of one inputport and thru connection on one input port.

➤ The MU0 ALU is combinational.➤ Unlike most ALUs, the MU0 ALU does not perform Boolean operations .


MU0 Arithmetic Logic Unit ( L6: Digital system components )


Each of these building blocks can be easily realised in hardware and described in Verilog. Not mentioned is theclock signal which is the MU0 heart beat. The rising edge of the clock will be considererd the active edge.

However there is an important exception to this in which for one process (memory transfers) that the negativeclock will be the active edge. This is a contradiction of the design spec since it effectively doubles the FPGAperformance requirements.

Take a look at the Verilog code for the memory: mem.v to see this negedge clock.


A VERILOG Memory for MU0 ( Not synthesisable!!! )


A VERILOG Multiplexer for MU0 ( L8: Verilog )


A VERILOG Register for MU0 (PC, Accumulator, Instruction re gister ( L8: Verilog )


MU0 Design Step 3: The Control Path (FSM) - The Instruction Cy cle


MU0 Design Step 3: The Control Path FSM

➤ The above control path algorithm can be achieved with just a two stateFSM with a fetch/store state (FETCH) and a decode/execute state (EXEC)

➤ In the FETCH state, the PC is connected to the memory address bus bythe address mux, the next instruction from memory is then read and storedin the IR. The PC is also incremented.

➤ In the EXEC state the first four bits (opcode) in the IR is decoded.

➤ The action to be taken given the opcode is then handled by a bunch ofCASE statements in the EXEC state. The operand for the opcode islocated in the memory address referred to in the last 12 bits of the IR.

➤ Some of the opcodes refer to JUMP instructions. When this is the case thelast 12 bits of the IR refer to the next memory location to which the PCshould point. This new memory location becomes the new PC value eventhough the PC was incremented in the FETCH state.


MU0 Design Step 3: Data Path Control

➤ The controller controls the microprocessor through switches that areassigned definite values in the EXEC state

➤ These switches are the enables on the data path hardware blocks➤ Note that the switches are already on before the active edge of the clock


MU0 Datapath Block Diagram


The way that MU0 uses datapath hardware blocks to execute a program with just these two states in the controlpath FSM is as follows.

➤ To start an operation the contents of the memory location pointed to by the address stored in the PC areread. This is a two step process. By this step the PC has already been disabled. The contents of the PCregister are muxed onto the memory address bus by deasserting Asel (i.e. set Asel = 0). This occurs in thefetch state at the positive edge of the clock.

➤ At the negative of the clock with an asserted Ren (read enable on the memory set to Ren = 1), the contentsof the memory location are transferred into the instruction register.

➤ The next positive edge of the clock sees the instruction register latch this 16 bit word to its output.

➤ The fetch and store process is now complete.

Since the PC points to an instruction (as opposed to data) in the memory, this location will contain a 16 bit word inwhich the first 4 bits is the opcode and the last 12 bits is the location in memory of the operand of the assemblylanguage instruction belonging to the opcode.

In the EXEC state, there are eight cases to consider, one for each opcode. In each case statement the outputs ofthe FSM are the new values for all the switches (Xsel, Ysel, Asel, Wen, Ren, PCen, IRen, AccEn and M) for thedata path hardware blocks that perform the operation specified by the opcode.

The best thing to do now is to go to the Verilog source code for mu0 ctrl.v and read the comments in thecombinational ALWAYS block of the decoder. Note that there are some dont care states in which certain signalshave no effect in certain states.

The timing diagram may also help.


MU0 Control Path FSM Implementation ( L12-13: FSM )


Example: ADD Instruction ( L16-17: RTL systems )


MU0 Control Path: The State Transition Diagram ( L12-13: FSMs )


mu0 ctrl.c (A VERILOG Controller for MU0): FETCH case


mu0 ctrl.c (A VERILOG Controller for MU0): LDA Instruction


The End

Exercise: Try and understand the operation of

mu0 ctrl.v in terms of the state transition diagram

See

http://engnet.anu.edu.au/DEcourses/engn3213/Softwar e/


GTKWAVE


GTKWAVE


C.F. PIC16F84C Datapath Block Diagram


PICOBLAZE Datapath Block Diagram


PICOBLAZE Schematic ( L12-13: FSM )


Documents

ENGN3213 Digital Systems and Microprocessors Course ...courses.cecs.anu.edu.au/courses/ENGN3213/lectures/...Top Down design: ISE WebPACK Work Flow 12 ENGN3213: Digital Systems and