ENGG2410: Digital Design

Digital Design Laboratory Manual

School of Engineering, University of Guelph

Fall 2017

Digital design is concerned with the design of digital electronic circuits. The subject is also known byother names such as logic design, switching circuits, digital logic and digital systems. Digital circuits areemployed in the design of systems such as digital computers, electronic calculators, digital control devices,digital communication equipment, and many other applications that require electronic digital hardware.This lab manual presents the basic tools that we will be using in ENGG2410 in the design of digital circuitsand provides a number of methods and procedures suitable for a variety of digital design applications.

1 Laboratory Objectives and Practices

The ENGG2410 Digital Design labs are an integral part of the course. The objectives of the laboratoryare:

• to help you understand and assimilate the lecture material.

• to give you practical experience with the process of design and implementation of digital circuits.

• to expose you to two common digital hardware implementation technologies; wire-interconnectedIC’s and field programmable gate arrays (FPGA’s).

• to give you hands-on-experience with CAD tools for digital hardware development.

Laboratory Practices

1. Absolutely no food or drink in the laboratories.

2. Clean up after yourselves. Put paper in the recycling bin and garbage in the trash.

3. Do not leave the door open.

The room will be closed after-hours if these rules cannot be followed.! Please check the Safety rules thathave to be obeyed and followed in the last section of this document.

Laboratory Recommendations

• Labs are to be done in groups of 3 to 4 students.

• The labs are to be demonstrated during the lab period on the due date.

• All written lab reports are due the following lab.

• Students are encouraged to work ahead.

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Define Inputs and Outputs

Get Specifications

Create Truth Tables

Derive Boolean Equations

Create gate-level Design

Simulate gate-level Design

Build Digital Circuit

Debug Digital Circuit

Figure 1: The flow of tasks involved in digital design

• Your grades will depend on your preparation of the labs.

• Please read all tutorials found on the WEB before attempting any lab.

2 The Digital Design Process

A design always starts with specifications (or “specs”) such as “the circuit must be able to add two 4-bitnumbers in less than 12 nanoseconds”. Specifications describe what the circuit must do, but not how itis done. The specifications are usually set by the customer who wants the final product, but the designercan set specs as well since the customer does not always know what he or she wants.

The digital design flow is shown in Figure 1. Once the designer knows what the circuit must do, he orshe can begin to determine how it is done. Defining what the circuit receives as inputs and the outputsit generates is a good first step. Once the inputs and outputs are known, the designer has to create truthtables, which list what values the outputs will have for each possible combination of input values. Once thetruth table is written down, the designer has to derive Boolean equations that describe how each binaryoutput can be computed from the binary inputs using the logical operations of AND, OR and NOT.There are a variety of manual and computer-assisted methods to accomplish this step.

Next, the Boolean equations derived in the previous step are transformed into a gate-level circuitschematic drawing. Each AND, OR and NOT operation in the Boolean equations is replaced with acorresponding AND gate, OR gate, or Inverter symbol in the schematic.

Before building the circuit, it is a good thing to check and make sure that all the previous steps havebeen completed correctly. Therefore, the gate-level design of the previous step is simulated to check itsoperation. In its most primitive form, simulation is performed by the designer, who traces various input.

3 Wire Interconnected TTL Integrated Circuits

The logic circuits that you will be building in the lab (first few) will be created using small-scale integrationchips (SSI chips) that contain only a few logic gates. This will give you a better appreciation of theadvantages of programmable logic when it is presented at a later stage of the course. SSI chips have been

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Figure 2: 7400 TTL Gates

around since the 1960s, and there are many different functions they can perform. We will only use thesimple SSI chips as shown in Figures 2, 3 (these are examples of chips built using older transistor-transistorlogic (TTL) technology) Transistor-transistor logic (TTL) is a class of digital circuits built from bipolarjunction transistors (BJT) and resistors. It is called transistor-transistor logic because both the logic gatingfunction (e.g., AND) and the amplifying function are performed by transistors (contrast this with RTL andDTL). Today most modern chips are fabricated using complementary metal-oxide semi conductor (CMOS)technology instead due to low power consumption, reliability and cost.

Each chip is contained in a dual-in-line package (DIP), which has 14 pins that allow you to connectwires to the inputs and outputs of the logic gates and to supply power and ground connections.

For a comperhensive list of all TTL gates see the following web pagehttp://www.cs.uiowa.edu/~jones/logicsim/man/node5.html or you can find a link of this web-site onour ENGG241 web page.

You will basically use a solder-less breadboard for constructing your digital circuits. The solder-lessbreadboard provides a “sea of holes” that chips and wires can be plugged into to make connections as seenin Figure 4.

When wiring a circuit using TTL or CMOS SSI logic you should follow the following steps:

1. Turn the power off before you begin to build anything.

2. Connect the +5 V and ground leads of your supply to the power and ground bus bars of yourbreadboard.

3. Plug the chips you will be using into the breadboard. Point all the chips in the same direction withpin 1 at the upper-left corner. (Pin 1 is often identified by a dot next to it on the chip package.)

4. Connect the +5 V and GND pins of each chip to the power and ground bus bars on the breadboard.

5. Select a connection on your schematic and identify the beginning and ending pins on the chips. Thenplace a piece of 22 to 26 gauge hookup wire between the corresponding pins of the chips on yourbreadboard.

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Figure 3: 7400 TTL Gates

Figure 4: Breadboard for prototyping

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6. Using different colors for your interconnections i.e red for +5 V, black for ground, blue for input,yellow for output, green for circuit connection. Use the shortest possible length of wire to makeconnects and route the wires clearly.

Input and Output Indicators

There are several methods of exciting the inputs of a digital circuit and also observing the output of thecircuit. In our ENGG2410 lab we will use switches (toggle and Dip) as inputs. Mechanical switches couldbe single-pole single throw (spst) or single-pole double throw (spdt) or any combination. As shown inFigure 5, when the switch is open, V0 = 5V; when it is closed, V0 = 0V, that is, V0 is either a logic “0” ora logic “1”.

SW

+5V

Vo

An SPST Switch

Figure 5: Single Pole Single Switch.

Light Emitting Diodes (LEDs) are mainly used for observing the output of a digital circuit. An LEDcan illuminate if it is forward-biased and has sufficient current flowing through it. The current requiredto light an LED may range from a few to more than 10 mA. The voltage drop across the LED when it isforward-biased can range from 1.6V to more than 2.2V. As shown in Figure 6, an LED can be connectedeither in active low or active high configuration. Using a 5-volt supply and assuming that the LED hasa 1.7 volt drop across it, a suitable resistor will limit the current to 10 mA. In the figure on the left aninverter is used as a switch to turn the LED on and off. When the inverter’s output is low (close to 0V),the diode has a 2.0V voltage drop, and by ohm’s law: 5V = 2.0V + Irx × Rx. When setting the Irx to10mA, the resistor Rx is solved to be 300Ω.

7408

VCC

R

74HC04

GND

xR x

Figure 6: Light Emitting Diode (LED) Interface.

Figure 7 shows the LEDs and Switches that can be used. A logic probe can also be used as will beexplained in lab1.

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Figure 7: Switches and LEDs used for I/O

Logic Probe

The logic probe is used for measuring the logic values of signals on the board as shown in Figure 8. Besure that it has power attached to the correct terminals. To test the probe, touch it to the +5V on theproto-board and ground, to ensure that it correctly indicates the values high (1) and low (0) respectively.For this lab, since we’ll be using TTL chips you should set the switch to TTL; in other labs we might beusing CMOS chips, and so the switch setting should be changed. The logic probe is also used to indicate

Figure 8: Logic Probe

when a signal is changed (oscillating). Touch the probe to the clock on the signal generator to see how theprobe indicates oscillation.

Wire Strippers and Chip Puller

The wire strippers are attached to each workstation to make sure they don’t get lost. If you haven’t everstripped a wire, try it! The chip puller should always be used to remove chips from the proto-board. Doingit with your fingers will bend the pins and ultimately break them, so don’t.

Debugging the Circuit

Once the circuit is built, the debugging begins. This involves placing a pattern of logic ones and zeros onthe inputs and observing the output with a logic probe.

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4 The Xilinx ISE Foundation Design Flow

Xilinx’s ISE Foundation Series Software is an environment for creating programs which describe logicdesigns (Figure 9).

4.1 Steps of Design Flow

When using ISE, your main design flow (shown in Figure 1) progresses as follows:

1. Digital designs are entered using the schematic editor, state machine editor, or by writing Verilog orVHDL programs with the HDL text editor. You can describe a design using just one or a mix ofthese methods.

2. A functional simulator checks the operation of the compiled design and lets you view the results tosee if it is doing what you want. You can go back and edit the Verilog or VHDL file, schematic,and/or state machine diagram if any errors are found.

3. The ISE Implementation tools compile the list of gates and connections, or net-list, into a bit-streamwhich is used to program the Field Programmable Logic Device (FPLD). It is in this step that aparticular device is targeted, such as the Spartan 6 or Virtex device. For Spartan/Virtex devices, theimplementation requires mapping the circuit to the FPGA architecture, placing the gates in specificConfigurable Logic Blocks (CLBs), and then routing the wires.

4. A timing simulation of your design can be run after the Foundation Implementation tools have de-termined the gate and routing delays associated with a particular mapping to an FPLD architecture.

5. Downloading the bit-stream onto the FPGA board:

• The iMPACT program (integrated within the Xilinx ISE Foundation) can be used to down-loadthe bit-stream into the Digilent NEXYS 3 Board (See the next section for a description of theseboards).

• An alternative would be to use Digilent Adept Application which is not only useful to configurethe Digilent NEXYS 3 board but also allows you to run tests to confirm proper operation andexpand I/O capability.

These steps will be described in the tutorial supplied with the first lab. It is important to notice thatthe Xilinx ISE Foundation Software has two distinct design flows:

• Schematic mode is used if your top-level design is described using schematics, state diagram, orVerilog.

• HDL mode is used if your top-level design is described using VHDL.

Figure 10 shows the changes in the digital design flow (previously shown in Figure 1) when using theXilinx ISE Foundation Series Software with the XC2S200E FPGA.

4.2 Saving your Project (work): Very Important

The lab computers employ restore-point software to prevent modifications on drive C. This means that ifanyone saves their work on Drive ”C” IT WILL BE LOST AFTER REBOOTING. The computersreboot everyday at 4 am automatically. PLEASE SAVE YOUR PROJECTS ON THE ”T” DRIVE

AND COPY IT TO YOUR ”H” DRIVE WHEN YOU ARE DONE WORKING. The T drive is common

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Figure 9: Xilinx ISE Foundation Series Software Main Window

Define Inputs and Outputs

Get Specifications

Create Truth Tables

Derive Boolean Equations

Create gate-level Design

Simulate gate-level Design

Build Digital Circuit

Define Inputs and Outputs

Get Specifications

Debug Digital Circuit

State-Machine, or HDL EditorDesign Entry Via Schematic

Functional Simulation of the Design

Fit to CPLD or Map, Place, RouteTo FPGA

Timing Simulation of the MappedDesign

Download to the XS95 or XS40Board

Debug the Design Using the PC and 7-Segment LED

Figure 10: The flow of tasks involved in digital design

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to anyone on that computer, and someone may delete your work accidentally, so always backup your projectson your network (or ”H”) drive. Also, to prevent plagiarism of your projects, remove your projects offthe ”T” drive once they are stored on the network drive. Do not operate out of the network drive asXilinx simulator software have trouble handling network socket connections which are utilized when savinga project on a network drive.

5 A Quick Introduction to the Digilent NEXYS 3 Board

The Digilent Corporation has many products based around FPGAs and CPLDs. Our School of Engineeringhas obtained a number of the NEXYS 3 FPGA development boards, and these are what students inENGG2410 will be using. The NEXYS 3 is a basic development board (as seen in Figure 11) containing

Figure 11: The Digilent NEXYS 3 FPGA board

a Xilinx Spartan 6 LX16 series FPGA chip. This chip is a medium size FPGA in comparison to otherFPGAs that Xilinx manufacturers ; Nonetheless, it is unlikely that you will “fill up” the entire FPGAwith the designs in ENGG2410. The Spartan-6 LX16 contains 2,278 Slices which is equivalent to 9112“Configurable Logic Blocks” (CLBs), which corresponds to over 500,000 “usable gates”. This means thatwhen creating a real-world hardware design, the Spartan-6 chip can implement a circuit that is equivalentto about 14,579 Logic Cells. The Spartan-6 LX16 also contains 576K bits of block RAM, 32 DSP Slicesand much more.

As a side note, Xilinx makes one of the industry’s largest FPGAs, the Virtex 7. This chip providesover 300 million gates, which is probably large enough to implement an entire System-on-chip on it. Asingle Virtex 7 chip costs hundreds of dollars.

The Spartan-6 FPGA on the NEXYS 3 board is an 232 pin BGA package. The FPGA the large squarechip located is roughly in the center of the board. Most of the 232 pins on the chip can be used for genericI/O, which means that each pin can become anything you want via the UCF file. Also on the NEXYS 3 isa 100MHz oscillator, 10/100 Ethernet, 8-bit VGA port, USB2 port for programming. The board also has72 I/O’s routed to expansion connectors in addition to GPIO which includes 8 LEDs, 6 buttons, 8 slideswitches and 4-digit seven segment display.

The FPGA is programmed through the USB port using the JTAG ports on the FPGA. After the FPGAis programmed the parallel port may be switched, using the PORT/PROG slide switch, to allow the parallelport from the computer to control some of the I/O pins of the FPGA. At the http://www.digilentinc.comDigilent web-site you can down-load schematics, manuals, tutorials, etc. for the NEXYS 3 board.

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Setting up the NEXYS 3 Board

This is intended to allow the student to quickly set up the NEXYS 3. It does not attempt to explain theconfiguration and is in no way a substitute for the documentation provided with the board. It will allowyou to use the slide switches as input and the LEDs as outputs.

1. Connect the USB cable to the NEXYS 3 board.

2. Connect the host computer to your USB cable.

3. When the power switch to the board is on a small yellow LED labeled Done should glow.

You can test if the Digilent NEXYS3 Board is operational by using the Digilent Adept Tool. Double

click on the icon and you will see the Digilent Adept GUI on your screen:

Press the Test icon. A new menu will appear. Press the “Start Perihperals Test”. The test will displaydifferent values on the 7-segment display. You can also test the switches and light emitting diodes bysliding the switches to the on-off position. Once a switch is turned on the corresponding LED will glow.You will also notice that the switches on the Digilent Adept tool will change value. You can also test thepush buttons by pressing on them. You will see the color of the corresponding button on the Adept toolchange from transparent to black. Once you are satisfied that the FPGA board is operational you canpress the “Stop Peripherals Test”. By pressing the “Reset Button” on the FPAG you will reset the boardto the factory setting where it tests all other modules on the PCB board. Power off the board using theslide switch found at the top left part of the board.

User Constrained File (UCF) and Digilent FPGA Board

A User Constraint File (UCF) is used to assign I/O pins in a design to the actual pins on the FPGA.The UCF file has the following format:

NET <pin name in VHDL design> LOC=P<pin number on FPGA>

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5.1 LEDs

The Digilent NEXYS 3 Board provides a series of eight LEDs (LD0–LD7) for use. All of these LEDsare Large active high meaning that an LED segment will glow when a logic-high is applied to it. Thefollowing table show the connection from the NEXYS 3 Board to and LEDs expressed as UCF constraints.

—Description —Location

NET LD0 LOC=U16NET LD1 LOC=V16NET LD2 LOC=U15NET LD3 LOC=V15NET LD4 LOC=M11NET LD5 LOC=N11NET LD6 LOC=R11NET LD7 LOC=T11

Table 1: NEXYS 3 (Light Emitting Diodes) LEDs

5.2 Seven Segment Displays

The Digilent NEXYS 3 Board provides four multiplexed 7-segment displays (DSP1) for use. The follow-ing tables show the connection from the NEXYS 3 Board to the 7-segment displays expressed as UCFconstraints.

—Description —Location

NET CA LOC=T17;NET CB LOC=T18;NET CC LOC=U17;NET CD LOC=U18;NET CE LOC=M14;NET CF LOC=N14;NET CG LOC=L14;NET DP LOC=M13;

NET AN0 LOC=N16;NET AN1 LOC=N15;NET AN2 LOC=P19;NET AN3 LOC=P17

Table 2: NEXYS 3 (7-Segment display)

5.3 Slide Switches

The Digilent NEXYS 3 board has a bank of eight slide switches which are accessible by the user.When closed or ON, each DIP switch pulls the connected pin of the NEXYS 3 Board to ground. When

the DIP switch is open or OFF, the pin is pulled high through a 10KΩ resistor.

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The table below show the connections from the the Digilent NEXYS 3 Board to the switches expressedas UCF constraints.

—Description —Location

NET SW0 LOC=T10NET SW1 LOC=T9NET SW2 LOC=V9NET SW3 LOC=M8NET SW4 LOC=N8NET SW5 LOC=U8NET SW6 LOC=V8NET SW7 LOC=T5

Table 3: NEXYS 3 (Slide Switches)

5.4 Push Buttons

The Digilent NEXYS 3 board has five pushbuttons (labeled BTNS through BTNR) which are accessibleby the user.

When pressed, each pushbutton pulls the connected pin of the NEXYS 3 Board to ground. Otherwise,the pin is pulled high through a 10KΩ resistor. The table below show the connections from the the DigilentNEXYS 3 Board to the push buttons expressed as UCF constraints.

—Description —Location

NET BTNS LOC=B8NET BTNU LOC=A8NET BTNL LOC=C4NET BTND LOC=C9NET BTNR LOC=D9

Table 4: NEXYS 3 (Pushbuttons)

6 Laboratory Assignments

The course labs are structured as eight modules. They cover the following material:

• lab0: introduction to lab equipment and creation of lab groups.

• lab1: introduction to TTL logic, logic probe, design methodology.

• lab2: introduction to Xilinx ISE Foundation Tools (Schematic Capture) and FPGA programming.

• lab3: introduction to Xilinx ISE Foundation Tools (VHDL Entry Design).

• lab4: design of combinational logic “Trip-Genie”.

• lab5: modular designs and hierarchy using VHDL (Arithmetic Circuits).

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• lab6: simple sequential logic design (implementing flip).

• lab7: advanced sequential logic design (implementing state machines).

• lab8: design and implementation of arithmetic logic units (ALUs).

• lab9: design and implementation of algorithmic state machines.

These labs will expose you to a range of design activities, tool functionalities and implementation tech-nologies. Each lab has a set of deliverables. These typically include the circuit schematics, simulationcommand file, simulation waveform plots, demonstration of hardware implementation and a brief report.

Due Dates

The following are the due dates of the labs:

Item Takes Place Due Date Report Topic

Lab #0 (Week #01) - None Introduction to Lab Equipment

Lab #1 (Week #02) (Week #03) (in Lab) Yes Combinational Logic & TTL

Lab #2 (Week #03) (Week #04) (in Lab) Yes Schematic Capture

Lab #3 (Week #04) DEMO SAME DAY in LAB Yes Combinational Logic Design

NO LABS (Week #05) - - -

Lab #4 (Week #06) (Week #7) (in Lab) None Design Entry Using VHDL

Lab #5 (Week #07) (Week #08) (in Lab) Yes Arithmetic Circuits (VHDL)

Lab #6 (Week #08) DEMO SAME DAY in LAB None Sequential Logic (Flip Flops)

Lab #7 (Week #09) (Week #10) (in Lab) Yes Sequential Logic (Seq Rec)

Lab #8 (Week #10) (Week #11) (in Lab) Yes Data Path Design (ALU)

Lab #9 (Week #11) (Week #12) (Tue Lect) Yes Algorithmic State Machines

Demonstration

Be prepared to:

• demonstrate the operation of the system

• explain how your design works

• explain how the components of the system works

Writeup

• Problem Statement

• Assumptions and Constraints

• System Analysis, Design and Justifications of Decisions

• Hardware

1. used components and their specifications

2. schematic

3. brief explanation of operation

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4. any required calculations

5. timing diagram if appropriate (i.e Simulation: Functional, post synthesis and post place androute).

• Your analysis should include:

1. How you would improve upon your project given more time.

2. Problems encountered during the lab.

3. Your approach to debugging the problem.

7 Laboratory Safety

The School of Engineering is dedicated to providing a safe and comfortable environment for research andteaching. This Section of the Lab Manual provides a broad overview of safety in the Digital Design Lab.

• If unsure of any aspect of the laboratory be sure to obtain the information before starting anyexperiments.

• All laboratories are different requiring different equipment and tools, therefore cause different hazards.

• The instructor of the course and lab technicians have the following responsibilities as ”Supervisors”

1. Ensure that an appropriate safety orientation lecture has been given to students when they arefirst assigned to a laboratory space or prior to starting the first experimental work.

2. Ensure that adequate emergency equipment is in proper working order and readily available.

3. Ensure that an incident investigation report is completed for every incident or injury that occursin his/her lab.

4. Ensure that the student has and uses appropriate safety gear. (e.g. Eye protection, anti-staticwrist straps, ..)

Laboratory Participant Responsibilities

All students performing procedures in the lab have the following responsibilities:

• Follow all applicable safety rules and practices

• Use all recommended protective equipment according to instructions.

• Report all incidents to the supervisor/lab technician no matter how trivial it may seem.

• Report all unsafe conditions to the instructor/lab technician.

• Attend all training courses as directed by the instructor/lab technician.

Safety Resources

If you have any question regarding the safety of an experiment, equipment, board then immediately askthe instructor or lab technician. All students should resort to the SOE Safety Lab Manual posted on theweb page of the course:http://islab.soe.uoguelph.ca/sareibi/TEACHING_dr/ENG241_html_dr/eng241.html

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