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ENG3190Logic Synthesis
General Information Handout
Winter 2014, January 7th
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Shawki Areibi
Research Interests• VLSI Physical Design Automation (CAD Tools)• Reconfigurable Computing Systems• Embedded Systems
PhD, Waterloo 1995
Office, Email, Phone• Office: 2335, EXT 53819• Email: [email protected]• Web: http://www.uoguelph.ca/~sareibi• Office Hours: M/F 2:00-3:00 PM
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Outline
• Info about Staff (TAs, LabTech)• Lecture and Lab Schedule.• Course Text and References.• Course contents, Tentative Schedule.• Assignments, Labs, Exams.• Evaluation• Important Information
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• Joel Best• B.Sc.., M.Sc. University of
Guelph• Office: Rich 3501, ext. 54234• Email: [email protected]
System Admin
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Teaching Assistants
• Dennis Wong, M.Sc. Student• Research: VLSI Design• Room THORN xxx, ext. xxx• Email: [email protected]
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Lecture & Lab Schedule
Lectures 1. 10:00–11:20, (TUE, THUR)2. MACK 314 RICH 2531
Tutorials/LABS1. RICH 2531.
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Text Book and References
Text Book: “Logic Synthesis and Verification Algorithms”, by G. Hachtel, Springer 2007.
References1. “Synthesis and Optimization of Digital
Circuits”, by G. De Micheli, McGraw-Hill 94.
2. “Algorithms for VLSI Design Automation”, by S. Gerez, Wiley 1999.
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Resources & Communication
http://www.uoguelph.ca/~sareibi Communications
1. E-mail, listserv2. Eng3190 Web Page (Announcement)
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Course Objectives
This is an introductory course in Logic Synthesis for Computer Engineers.
Achieves the following goals:1. Teaches you the fundamental concepts of logic
synthesis.2. Teaches you the way in which Electronic Design
Automation Systems are designed today.3. Teaches you the difference between front end
tools and back end tools for Electronic Design Automation.
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Tentative Schedule
1. Week #1, Overview of Synthesis and EDA 2. Week #2, #3, Computational Boolean Algebra3. Week #4, BDDs, AIGs, SAT (data structures)4. Week #5, Two Level Logic Synthesis5. Week #6, #7, Multi Level Logic Synthesis6. Week #8, Sequential Logic Synthesis7. Week #9, Technology Mapping8. Week #10, High Level Synthesis9. Week #11, #12 Physical Design Automation
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Assignments
1. Assignment#1, Computational Boolean Algebra2. Assignment#2, Two Level Logic Optimization3. Assignment#3, Multi Level Logic Optimization4. Assignment#4, Sequential Logic Optimization
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LABS
Labs are an integral part of the course. The objectives of the labs are:
1. Understand and assimilate lecture material2. Give practical experience using off the
shelve tools such as ESPRESSO, SIS, ABC3. Program in high level language (C or C++)
some algorithms
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Labs: Reports, Preparation ..
1. Lab#0, Week#1, Introduction to Unix System.2. Lab#1, Week#2-3, Q-M Method.3. Lab#2, Week#4-5, CUDD Package (BDDs)4. Lab#3, Week#6-7, ESPRESSO for Logic
Synthesis5. Lab#4, Week#8-9, SIS Tool for Logic Synthesis6. Lab#5, Week#10-11, ABC Tool for Synthesis.
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Exam Schedule
1. MidtermWeek#7, Tuesday Feb 25th (material Week 1-6).
2. Final Exam Week#13, April 9th, Time: 7:00 PM – 9:00 PM
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Evaluation
Topic Weight Details
Assignments 20% 4-5 Assignments
Labs 20% 4 Labs
Midterm 20% Week 7
Final Exam 40% Week 13
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Important Issues
It is important to remember that the midterm and final exam will be based on the assignment problems, so it is in your best interest to seriously attempt all questions alone.
In order to pass the course, you must pass both the lab and exam course portion. Students must obtain a grade of 50% or higher on the exam portion of the course.
If a laboratory is missed due to illness or other reason, arrangements must be made with the teaching assistant to complete a make-up lab.
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Academic Misconduct
Please refer to the regulation outlined in the student handbook regarding academic misconduct.
The policy for this course is zero tolerance for any form of plagiarism and academic misconduct.
All cases will be dealt by the Dean of the College.
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Simple Advice
• Attend all Lectures!• Attempt all assignments• Make use of your Teaching Assistant• Prepare for the Labs prior to lab session• Study in groups (don’t rely on others!)• Identify your strengths and weaknesses• Manage your time!!!!!!!!!!
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