Energy Efficient RF Communication System for Wireless

Energy Efficient RF Communication System for Wireless

Microsensors

by

SeongHwan Cho

Bachelor of Science, Electrical Engineering,Korea Advanced Institute of Science and Technology (1995)

Master of Science, Electrical Engineering and Computer Science,Massachusetts Institute of Technology (1997)

Submitted to the Department of Electrical Engineering and Computer Sciencein partial fulfillment of the requirements for the degree of

Doctor of Philosophy in Electrical Engineering

at the

MASSACHUSETTS INSTITUTE OF TECHNOLOGY

June 2002

c© Massachusetts Institute of Technology 2002. All rights reserved.

Author . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Department of Electrical Engineering and Computer Science

May 24, 2002

Certified by. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Anantha Chandrakasan

Associate Professor of Electrical EngineeringThesis Supervisor

Accepted by . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Arthur C. Smith

Chairman, Department Committee on Graduate Students

Energy Efficient RF Communication System for Wireless Microsensors

by

SeongHwan Cho

Submitted to the Department of Electrical Engineering and Computer Scienceon May 24, 2002, in partial fulfillment of the

requirements for the degree ofDoctor of Philosophy in Electrical Engineering

Abstract

Emerging distributed wireless microsensor networks will enable the reliable and fault toler-ant monitoring of the environment. Microsensors are required to operate for years from asmall energy source while maintaining a reliable communication link to the base station. Inorder to reduce the energy consumption of the sensor network, two aspects of the systemdesign hierarchy are explored: design of the communication protocol and implementation ofthe RF transmitter. In the first part of the thesis, energy efficient communication protocolsfor a coordinated static sensor network are proposed. A detailed communication energymodel, obtained from measurements, is introduced that incorporates the non-ideal behav-ior of the physical layer electronics. This includes the frequency errors and start-up energycosts of the radio, which dominate energy consumption for short packet, low duty cyclecommunication. Using this model, various communication protocols are proposed from anenergy perspective, such as MAC protocols, bandwidth allocation methods and modulationschemes. In the second part of the thesis, design methodologies for an energy efficient trans-mitter are presented for a low power, fast start-up and high data rate radio. The transmitteris based on a Σ-∆ fractional-N synthesizer that exploits trade-offs between the analog anddigital components to reduce the power consumption. The transmitter employs closed loopdirect VCO modulation for high data rate FSK modulation and a variable loop bandwidthtechnique to achieve fast start-up time. A prototype transmitter that demonstrates thesetechniques is implemented using 0.25µm CMOS. The test chip achieves 20µs start-up timewith an effective data rate of 2.5Mbps while consuming 22mW.

Thesis Supervisor: Anantha ChandrakasanTitle: Associate Professor of Electrical Engineering

Acknowledgments

I would express my sincere gratitude to those who have contributed to the completion of

this thesis. One valuable lesson I learned throughout these years is that nothing can be

done alone.

My foremost gratitude goes to Prof. Chandrakasan. He has guided me since 1995 when

I was a fresh blind graduate student. I truly appreciate his patience and support throughout

the long years at MIT. I would like to thank Prof. Sodini for numerous feedbacks he has

given me during RF meetings as well as in the thesis. His intuitive thoughts on many of

the thesis topics were invaluable and helped the completion of this thesis. I’d also like to

thank Prof. Chan for the constructive comments on the thesis. I am also grateful to Prof.

White, Prof. Lee and Prof. Lim for their advice.

I’d like to acknowledge the ABB Corporation Research in Norway for funding this

project. I’m especially grateful to Snorre Kjesbu for guiding me on the wireless sensor

networks with the real world examples and experimental results.

I’d like to thank the members of technical staff at IBM T.J. Watson Research Center

for their support in fabricating the chip. I can’t thank Herschel Ainspan enough for his

advice in layout. I would still be trying to get over DRC errors if it were not for him. He

has answered all my tedious questions with patience during the course of the chip design.

I’d like to thank Mehmet Soyuer for giving me an opportunity to work with him in the RF

area in 1999. Jungwook Yang was also helpful in numerous ways at IBM.

I am indebted to Dan McMahill and Don Hitko for their kind and patient answers to

various RF questions in the beginning of this work. I’ve also had many invaluable discussions

with Andy Wang on link budget analysis and modulation schemes. His intuitive ideas and

expertness in these fields have helped me on numerous occasions, including the writing and

proof reading of the thesis. Jung-hoon Lee was also helpful in optimization problems.

I’d like to thank the members of ananthagroup for their support. Alice Wang has sup-

ported me since the beginning of my Ph.D study in various ways. Rex Min has kindly

volunteered to go through the pain of reading the rough draft of this thesis and gave me

constructive feedbacks. Manish Bhadwarj gave me many intriguing ideas on the communi-

cation protocols and helped with license setups in various CAD tools. Eugene Shih helped

me with the first generation of µAMPS radio design. I’d like thank Fred Lee for taking

the lead role in the radio development of µAMPS project; he has done a wonderful job in

making the radio to work.

The OBs of ananthagroup, Duke Xanthopolous, Raj Amirtharaja, Jim Goodman and

Tom Simon have all helped me not only in cadence questions, but also in numerous academic

areas and in ways to survive at MIT. I’d also like to thank Margaret Flaherty and Beth

Chung for assisting me with numerous orders and reimbursements.

I’d like to thank Engim Inc. for providing me with an opportunity to experience the

unique life of a start-up company.

I’d also like to thank the Korea Foundation for Advanced Studies for their support.

My friends have given me delightful memories in Boston that I could always cherish.

I’d like to thank Sungtae Kim for the cheerful talks. Sports conversation with SongJoon

Park was always great. The words of Park was another joy in Boston. SungJun Woo was

always ready when I needed a party for go-stop or any kind of gambling. I’d like to thank

Ki-hyuk Park for arranging the airline tickets to Korea. Their girlfriends also deserve some

credit for keeping them busy or I would have spent too much time with them, prolonging

my years as a graduate student.

I am grateful to EECS sunbaes, ChangDong Yoo, Won-Jong Kim, SaeYoung Chung,

Junehee Lee, DongHyun Kim, JeungYoon Choi, and Seokwon Kim for their support. In

addition, Choongyeun has been a great friend, Zhifuan’s baseball and entertainment talks

were another pleasure at MIT. Seongmoo Heo has been a great hoobae in many ways and

Jin-chul had been a great roommate, until he got married =]. Junmo’s inquisitiveness on

all fields of life is something I should learn from and I’m relieved that I graduated before

Gookwon (this kid’s got something). I’m also also thankful to Sokwoo, Hyuksang, Sangjun

and Jinwoo hyung for being great big brothers.

My proud high school alumni at MIT and Harvard, too many names to write in one

page, have also given me cherishable memories to keep in Boston.

Lastly, my deepest love goes to my family, Appa, Umma, Nuna for raising me to the

person I am.

Contents

1 Introduction 17

1.1 Distributed Wireless Microsensor Network . . . . . . . . . . . . . . . . . . . 17

1.1.1 Related work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

1.2 Contribution and Scope of Thesis . . . . . . . . . . . . . . . . . . . . . . . . 20

1.2.1 Low power communication protocol . . . . . . . . . . . . . . . . . . 22

1.2.2 Energy efficient transmitter . . . . . . . . . . . . . . . . . . . . . . . 22

1.3 Overview of Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2 Design Considerations of a Microsensor Node 25

2.1 Node Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.2 Transmitter Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.2.1 Link budget . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.2.2 Phase noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2.2.3 Start-up time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.2.4 Data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2.3 Considerations on Receiver and Base Station Design . . . . . . . . . . . . . 34

2.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3 Low Power MAC Protocol 37

3.1 Previous Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.2 Radio Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.3 Low Power MAC Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.3.1 Contention vs. scheduled MAC . . . . . . . . . . . . . . . . . . . . . 40

7

8 CONTENTS

3.3.2 Hybrid TDM-FDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.3.3 Effect of fading on MAC . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.4 Variable Bandwidth Allocation Scheme . . . . . . . . . . . . . . . . . . . . . 49

3.4.1 Energy vs. bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.4.2 Variable time-frequency slot allocation . . . . . . . . . . . . . . . . . 50

3.4.3 Energy efficient time-frequency slot allocation algorithm . . . . . . . 51

3.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

4 High Data Rate Low Power Transmitter 59

4.1 Binary vs. M-ary Modulation Scheme . . . . . . . . . . . . . . . . . . . . . 60

4.2 High Data Rate Low Power FSK Modulator . . . . . . . . . . . . . . . . . . 63

4.2.1 Related work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

4.2.2 Closed loop direct VCO modulation . . . . . . . . . . . . . . . . . . 67

4.2.3 Modulation error and bit error rate . . . . . . . . . . . . . . . . . . . 70

4.2.4 Equalization at base station . . . . . . . . . . . . . . . . . . . . . . . 75

4.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

5 Fast Start-up Transmitter 79

5.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

5.2 Loop Switching in Fractional-N Synthesizer . . . . . . . . . . . . . . . . . . 80

5.2.1 Variable loop bandwidth technique . . . . . . . . . . . . . . . . . . . 80

5.2.2 Effect of quantization noise . . . . . . . . . . . . . . . . . . . . . . . 82

5.2.3 Multiple stage loop switching . . . . . . . . . . . . . . . . . . . . . . 82

5.3 Digital Lock Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

5.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

6 Implementation of Energy Efficient Transmitter 89

6.1 Frequency Synthesizer Basics . . . . . . . . . . . . . . . . . . . . . . . . . . 89

6.1.1 Fractional-N synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . 91

6.2 Low Power VCO: Architectural Approach . . . . . . . . . . . . . . . . . . . 93

6.3 Low Power Divider: Architectural Approach . . . . . . . . . . . . . . . . . . 97

CONTENTS 9

6.3.1 Divider vs. Σ-∆ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

6.4 Low power VCO: Circuit Techniques . . . . . . . . . . . . . . . . . . . . . . 99

6.4.1 Low phase noise VCO . . . . . . . . . . . . . . . . . . . . . . . . . . 99

6.4.2 VCO with modulation input . . . . . . . . . . . . . . . . . . . . . . 101

6.4.3 CMOS varactor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

6.5 Low Power Divide-by-112/120: Circuit Techniques . . . . . . . . . . . . . . 106

6.5.1 Divide-by-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

6.5.2 Divide-by-14/15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

6.6 Σ-∆ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

6.7 Phase Frequency Detector and Charge Pump . . . . . . . . . . . . . . . . . 109

6.7.1 Charge pump for variable loop filter . . . . . . . . . . . . . . . . . . 110

6.8 Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

6.9 Energy Efficient BFSK Modulator . . . . . . . . . . . . . . . . . . . . . . . 111

6.10 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

7 Prototype Test Results 115

7.1 Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

7.1.1 VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

7.1.2 Fractional-N frequency synthesizer . . . . . . . . . . . . . . . . . . . 119

7.2 BFSK Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

7.3 Variable Loop Bandwidth Technique . . . . . . . . . . . . . . . . . . . . . . 122

7.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

8 Conclusion 127

8.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

8.2 Critique and Future Works . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

A Prototype Chip Testing 139

A.1 Chip Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

A.2 Serial Register Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

A.2.1 Program timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

10 CONTENTS

A.2.2 Register value description . . . . . . . . . . . . . . . . . . . . . . . . 142

A.3 Test Board Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

B PLL model 145

B.1 Noise properties of 2nd order PLL . . . . . . . . . . . . . . . . . . . . . . . 145

B.2 Maximum Quantization Noise on VCO Control Voltage . . . . . . . . . . . 146

List of Figures

1-1 Applications of distributed wireless microsensor network. . . . . . . . . . . . 18

1-2 System design hierarchy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

1-3 Comparison of energy efficiency between a traditional radio and an ideal

radio for different packet sizes. . . . . . . . . . . . . . . . . . . . . . . . . . 23

2-1 Microsensor node architecture. . . . . . . . . . . . . . . . . . . . . . . . . . 26

2-2 Received power vs. transmit distance (Courtesy of ABB Corporation Re-

search in Norway). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2-3 BER vs. output power in a slow Rayleigh fading channel. . . . . . . . . . . 31

2-4 Degradation of SNR due to phase noise in adjacent channel. . . . . . . . . . 32

2-5 Start-up transient of a commercial low power transceiver (Tstart ≈ 470µs). . 32

2-6 Effect of start-up transient on transmitter’s energy consumption in a 100 bit

packet transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3-1 Block diagram of a sensor radio. . . . . . . . . . . . . . . . . . . . . . . . . 39

3-2 Comparison of energy consumption between scheduled and contention based

MAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3-3 Multiple access methods: TDM,FDM and hybrid TDM-FDM. . . . . . . . . 45

3-4 Drift in transmitted packets due to reference clock error. . . . . . . . . . . . 46

3-5 Energy consumption of a sensor network using hybrid TDM-FDM with dif-

ferent Tstart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3-6 Energy consumption of a sensor network using hybrid TDM-FDM with dif-

ferent Erx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

11

12 LIST OF FIGURES

3-7 Energy consumption of a sensor network with equaliztion. . . . . . . . . . . 48

3-8 Example of slot allocation in different available bandwidth. . . . . . . . . . 50

3-9 Average energy consumption of a sensor radio vs. available bandwidth. . . 51

3-10 Bandwidth allocation schemes in a cellular network. . . . . . . . . . . . . . 52

3-11 Variable bandwidth allocation scheme with time-frequency slots. . . . . . . 52

3-12 Notations used in a cellular network (frequency reuse=7). . . . . . . . . . . 53

3-13 Guard time of slots in the same frequency channel. . . . . . . . . . . . . . . 53

3-14 Number of sensors in joint macrocell network. . . . . . . . . . . . . . . . . . 55

3-15 Power consumption of the sensor network for a variable bandwidth allocation

(VBA) and a fixed bandwidth allocation (FBA) scheme. . . . . . . . . . . . 58

4-1 Transmitter architecture of binary and M -ary modulation. . . . . . . . . . . 61

4-2 The ratio of the energy consumed by M -ary modulation to the energy con-

sumed by binary modulation versus α, the ratio of the modulation circuitry

power consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

4-3 Effect of start-up time on the energy consumption of different type of mod-

ulation schemes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

4-4 Indirect modulation architecture using Σ-∆ fractional-N synthesizer. . . . . 65

4-5 High data rate modulator using pre-emphasis filter and automatic calibration. 65

4-6 Open loop direct VCO modulation architecture. . . . . . . . . . . . . . . . . 66

4-7 Block digram of a closed loop direct VCO modulation architecture. . . . . . 67

4-8 Effect of closed loop PLL on direct VCO modulation. . . . . . . . . . . . . 68

4-9 Simulated eye diagram of a raw data. . . . . . . . . . . . . . . . . . . . . . 69

4-10 Simulated eye diagram of a Manchester encoded data. . . . . . . . . . . . . 69

4-11 Coherent demodulator of the base station receiver. . . . . . . . . . . . . . . 71

4-12 SNR degradation (γ) from closed loop modulation. . . . . . . . . . . . . . . 73

4-13 BER vs. Eb/No of closed loop modulation scheme in AWGN channel. . . . 73

4-14 BER of closed loop modulation in a Rayleigh fading channel. . . . . . . . . 74

4-15 BER degradation due to quantization noise in fractional-N synthesizer. . . . 76

4-16 Equalization of the transmitted data at the base station. . . . . . . . . . . . 76

LIST OF FIGURES 13

5-1 Variable loop bandwidth technique. . . . . . . . . . . . . . . . . . . . . . . . 81

5-2 Bode plot of a PLL with variable loop switching method. . . . . . . . . . . 81

5-3 Effect of quantization noise in loop switching. . . . . . . . . . . . . . . . . . 82

5-4 VCO control voltage in multi-stage variable loop bandwidth technique. . . . 83

5-5 Settling time vs. number of variable loop stages. . . . . . . . . . . . . . . . 85

5-6 Settling time vs. intermediate loop bandwidth in a two stage variable loop

technique. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

5-7 Schematic of digital lock detector. . . . . . . . . . . . . . . . . . . . . . . . 86

6-1 Direct frequency synthesizer using frequency multipliers and dividers. . . . 89

6-2 Direct frequency synthesizer using DAC and lookup table. . . . . . . . . . . 90

6-3 Indirect frequency synthesizer using PLL. . . . . . . . . . . . . . . . . . . . 91

6-4 Noise sources in a fractional-N frequency synthesizer. . . . . . . . . . . . . . 94

6-5 Effect of loop bandwidth on VCO and Σ-∆ noise. . . . . . . . . . . . . . . . 95

6-6 Power consumption of VCO and Σ-∆ in different loop bandwidths. . . . . . 96

6-7 Multi-modulus divider architectures. . . . . . . . . . . . . . . . . . . . . . . 98

6-8 Output noise of the PLL for different divider architectures. . . . . . . . . . 98

6-9 Power consumption of divider and Σ-∆. . . . . . . . . . . . . . . . . . . . . 98

6-10 Circuit schematic of the VCO. . . . . . . . . . . . . . . . . . . . . . . . . . 100

6-11 Schematic of the 6.5GHz VCO. . . . . . . . . . . . . . . . . . . . . . . . . . 102

6-12 A CMOS varactor in high capacitance mode. . . . . . . . . . . . . . . . . . 103

6-13 A CMOS varactor in low capacitance mode. . . . . . . . . . . . . . . . . . . 104

6-14 Capacitance of two varactor structures. . . . . . . . . . . . . . . . . . . . . 104

6-15 Circuit schematic of the divide-by-8 prescaler. . . . . . . . . . . . . . . . . . 107

6-16 Schematic of the divide-by-14/15. . . . . . . . . . . . . . . . . . . . . . . . . 107

6-17 Quantization error and divider range of single loop Σ-∆ and MASH. . . . . 109

6-18 Architecture of the single loop Σ-∆. . . . . . . . . . . . . . . . . . . . . . . 109

6-19 Circuit schematic of the phase frequency detector. . . . . . . . . . . . . . . 110

6-20 Circuit schematic of the charge pump. . . . . . . . . . . . . . . . . . . . . . 111

6-21 Charge pump of the variable loop frequency synthesizer. . . . . . . . . . . . 112

6-22 Loop filter of the frequency synthesizer. . . . . . . . . . . . . . . . . . . . . 113

14 LIST OF FIGURES

6-23 Variable loop bandwidth frequency synthesizer. . . . . . . . . . . . . . . . . 113

7-1 Measured phase noise at 5.68GHz. . . . . . . . . . . . . . . . . . . . . . . . 116

7-2 Die photo of the 5.3GHz VCO. . . . . . . . . . . . . . . . . . . . . . . . . . 116

7-3 Tuning characteristic of the VCO on main control input. . . . . . . . . . . . 117

7-4 Tuning characteristic of the VCO on modulation input. . . . . . . . . . . . 117

7-5 Phase noise plot of the VCO. . . . . . . . . . . . . . . . . . . . . . . . . . . 118

7-6 Phase noise at different frequencies. . . . . . . . . . . . . . . . . . . . . . . 118

7-7 Figure of merit for different VCOs. . . . . . . . . . . . . . . . . . . . . . . . 120

7-8 Output spectrum of the fractional-N synthesizer at 6.3800GHz. . . . . . . . 121

7-9 Output spectrum of the fractional-N synthesizer at 6.3813GHz. . . . . . . . 121

7-10 Power consumption of different components in the modulator. . . . . . . . . 121

7-11 Eye diagram of 5Mbps Manchester encoded data with 100kHz PLL loop

bandwidth (h = 0.3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

7-12 Eye diagram of 5Mbps raw data with 100kHz PLL loop bandwidth (h = 0.3). 122

7-13 Eye diagram of the 5Mbps Manchester encoded data (h = 0.5). . . . . . . . 123

7-14 Spectrum of the 5Mbps Manchester coded data. . . . . . . . . . . . . . . . . 123

7-15 Start-up transient of frequency synthesizer with fixed loop bandwidth. . . . 124

7-16 Start-up transient of frequency synthesizer with variable loop bandwidth. . 124

7-17 Energy efficiency comparison of different high data rate modulators. . . . . 124

7-18 Die photo of the 6.5GHz modulator chip. . . . . . . . . . . . . . . . . . . . 125

7-19 PCB test setup of chip. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

A-1 Pin out of the packaged chip. . . . . . . . . . . . . . . . . . . . . . . . . . . 139

A-2 Timing diagram of the register value programming. . . . . . . . . . . . . . . 141

A-3 Test board schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

B-1 Linearized model of the PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . 146

B-2 Maximum phase difference in a fractional-N synthesizer. . . . . . . . . . . . 147

List of Tables

1.1 Comparison of wireless sensor network and conventional wireless device. . . 18

1.2 Specification of a machine monitoring sensor network (Courtesy of ABB Cor-

porate Research in Norway). . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7.1 Summary of VCO test results. . . . . . . . . . . . . . . . . . . . . . . . . . . 116

7.2 Figure of merit of different VCOs. . . . . . . . . . . . . . . . . . . . . . . . 120

A.1 Pin descriptions of the packaged chip. . . . . . . . . . . . . . . . . . . . . . 140

A.2 Description of function register. . . . . . . . . . . . . . . . . . . . . . . . . . 142

15

16 LIST OF TABLES

Chapter 1

Introduction

1.1 Distributed Wireless Microsensor Network

Recent advance in micro-fabrication technology has expanded the use of integrated devices

in a wide variety of applications for commercial and military use. The distributed wireless

microsensor network is one of the emerging technologies that will enable reliable monitoring

and control of various environments that span from home networking and medical sensing

to machine diagnosis and military surveillance as shown in Figure 1-1. In a distributed

microsensor network, a large number of sensor nodes are scattered over an environment of

interest to collect and transmit data to a base station, where the end user can extract the

necessary information.

The microsensor network presents several advantages to a macrosensor system. Due

to the large number of nodes, the microsensor network offers high quality fault tolerant

monitoring capability. While a failure of a macrosensor results in an event miss or possibly

an entire system failure, a network of sensors provides redundant monitoring of events,

which can be exploited for collaboration to ensure a high quality, fault tolerant system. In

addition, the small form factor of a microsensor node will be followed by ease of deployment,

which will enable new applications that are inconceivable with macrosensors.

The constraints of a wireless microsensor network are quite different from those of con-

ventional wireless hand-held devices, as listed in Table 1.1. First of all, sensors have small

packet size (∼ hundreds of bits) and low average data rate (∼ hundreds of bits/sec) due to

17

18 CHAPTER 1. INTRODUCTION

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Figure 1-1: Applications of distributed wireless microsensor network.

low event rates. Second, the transmission distance is very short, typically on the order of ten

meters or less, and the communication link is highly asymmetric (i.e., traffic flow is mostly

up-link from the sensors to the base station). Third, sensors have low mobility and form a

quasi-static network. Last and most important, the battery lifetime of the sensor network

is crucial and must be maximized. Since the network may be deployed in inaccessible or

hostile environments, battery replacement of a sensor node is undesirable, if not impossible.

Sensors are typically required to operate for years from a small energy source and therefore,

minimizing the energy consumption of the sensor network is a key design challenge. An

example that shows these requirements of a sensor network is listed in Table 1.2, which is

used for a machine monitoring industrial environment.

Specs WLANs/cellular phones Sensor networkAverage data rate ∼ Mbps < kbps

Packet size > kbits ∼100 bitsCommunication range up to kilometers ∼10 meters

Traffic mostly down-link/bidirectional mostly up-linkNetwork mobility mobile staticBattery lifetime few hours few years

Table 1.1: Comparison of wireless sensor network and conventional wireless device.

1.1. DISTRIBUTED WIRELESS MICROSENSOR NETWORK 19

Cell Density < up to 300 in 5m x 5m< up to 3000 in 100m x 100m

Range of Link < 10 mMessage rate average : 20 msgs/sec

(message = 2bytes) maximum : 100 msgs/secminimum : 2 msgs/sec

Error Rate and 10−6 after 5msLatency 10−9 after 10ms

10−12 after 15msLifetime 5 years

Size slightly larger than AA batteryFrequency Band 2.400 – 2.4835GHz (ISM)

5.15 – 5.35GHz (U-NII)5.725 – 5.875GHz (ISM)

Table 1.2: Specification of a machine monitoring sensor network (Courtesy of ABB Corpo-rate Research in Norway).

Due to such unique characteristics of the sensor network, design methodologies for con-

ventional wireless devices would result in inefficient use of energy if they are applied to

microsensor network. Hence, various levels of system design hierarchy, from software algo-

rithms and communication protocols to circuit techniques, must be explored to maximize

the lifetime of the sensor network. At the communication protocol level, the sensor network

must be operated with a scheme that is optimized for low duty cycle, short packet size and

short transmission distance. At the physical layer, the sensor electronics must be designed

for low duty cycle activity. This implies that the sensors must have small overhead during

start-up.

1.1.1 Related work

The advantages of the wireless sensor network has spawned many interesting work in the

recent years. In industry, IEEE 802.15 Working Group has been formed for wireless per-

sonal area network (WPAN), which focuses on the development of consensus standards for

short distance low rate wireless networks [1]. In academia, there are several projects that

involve wireless sensor network on various topics. One of the leading research in this area

is the µAMPS (Micro Adaptive Multi-domain Power-aware Sensors) project that focuses

on developing a complete and flexible power-aware system for wireless sensor networks [2].


The goal is no longer simply the development of low-power techniques in hardware and soft-

ware, but rather to create and develop a flexible platform that can adapt computation in

order to trade-off quality and system lifetime. Other research in the field of wireless sensor

networks include PicoRadio [3] and WINS [4] that focus on radio communication aspect

of the sensor network and smartDust [5] that focuses on micro-electro-mechanical-system

(MEMS) technology.

Many papers have also been published in a wide range of technical areas from software,

signal processing algorithms, communication protocols to physical layer circuit implementa-

tions [6, 7, 8, 9, 10]. Research in network protocols includes scalable coordination of sensor

networks [11], multi-hop routing protocols [12], and adaptive clustering algorithms [13] that

aim to increase the network lifetime and aid the self-configuration of an autonomous net-

work. In the signal processing area, efficient data aggregation methods such as data fusion

and beamforming techniques have been explored, which trade-off communication and com-

putation energy [14]. Research has also been conducted in digital and RF circuits as well as

the MEMS area that explore low power systems and circuit techniques as well as miniature

implantable devices with energy harvesting techniques [15, 16, 17, 18].

1.2 Contribution and Scope of Thesis

This thesis primarily focuses on two aspects of energy efficient sensor network design: com-

munication protocol and physical layer electronics. While there exists extensive research in

both of these areas, many have neglected the impact of one level of system hierarchy on

another. That is, the underlying electronics of the physical layer were not considered in

communication protocol design, but rather, treated as an ideal black box, resulting in sub-

optimal solutions. In this thesis, designs are based on multiple levels of system abstraction

as shown in Figure 1-2. Impact of physical layer electronics is considered in the protocol

design and protocols are taken into account in the radio design. Designing across different

levels of system abstraction raises many interesting issues that are not seen when each level

is treated exclusively. These include:

• What are the issues that arise from low duty cycle activity and how do they affect

1.2. CONTRIBUTION AND SCOPE OF THESIS 21

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Figure 1-2: System design hierarchy.

communication protocol?

• How do the non-ideal characteristics of the radio electronics, such as start-up transient

and frequency errors affect communication protocol?

• How does the choice of modulation scheme affect the energy consumption of the

transceiver electronics?

• Can the specifications of the radio be relaxed in order to lower the energy consump-

tion?

• How can an energy efficient radio, not a low power radio, be designed?

As will be seen throughout this thesis, these design strategies lead to a much more

efficient solution than that of the traditional approach where design is focused only on one

level of system abstraction.


1.2.1 Low power communication protocol

In communication protocol design, media access control (MAC) protocol and modulation

schemes are explored from the standpoint of circuit energy consumption. A detailed com-

munication energy model, obtained from measurements, is introduced that incorporates

the non-ideal behavior of the physical layer electronics. This includes frequency errors and

start-up energy costs of the radio, which dominates energy dissipation for short packet sizes.

Using this model, various levels of communication protocols are proposed from an energy

perspective, which include MAC protocols, bandwidth allocation methods and modulation

schemes. These methods are applied to a coordinated sensor network used for machine

monitoring in an industrial environment. The main contribution is that the protocol design

incorporates the detailed model of the radio that includes the non-ideal behavior , rather

than treating the radio as an ideal component.

As will seen, this has a great impact on the energy consumption of the sensor network.

1.2.2 Energy efficient transmitter

In the second part of the thesis, design methodologies for an energy efficient transmitter are

presented. From the sensor network’s perspective, energy efficient transmitter implies the

combination of the following parameters in a transmitter: fast start-up time, high data rate

and low power consumption. Fast start-up time is necessary in order to minimize the energy

consumption when a sensor node is turned on from an off state. High data rate reduces

the transmit time of a packet and hence reduces the active time of the radio. Low power

will reduce the energy consumption during active and start-up states. Today’s commercial

radios do not meet all of these requirements and lead to an inefficient use of energy. This is

shown in Figure 1-3, where energy consumption per bit is plotted versus packet size. The

graph shows two plots, one for conventional radio and the other for an ideal radio that

only consumes RF output power of 0dBm, which is enough for a 10 meter transmission,

with 100% efficiency. It can be seen that there is a large separation between the two

curves, especially when the packet size is small. While the overall gap can be reduced by

employing low power, high data rate techniques, the difference for short packets can be

improved only by reducing the start-up time of the radio. In order to achieve fast start-up

1.3. OVERVIEW OF THESIS 23

Low power & High rateFast startup

102 103 104 105 106

10-1

100

101

102

103

104

Conventional radio

Ideal radio

Packet Size (bits)

Ebi

t(nJ)

0dBm output power at 1Mbps

Figure 1-3: Comparison of energy efficiency between a traditional radio and an ideal radiofor different packet sizes.

time, variable loop bandwidth technique is used in a fractional-N synthesizer. For high

data rate, the transmitter employs closed loop direct VCO modulation. To reduce power

consumption, trade-offs between the analog and the digital components of a fractional-

N frequency synthesizer are exploited. A prototype transmitter implemented in 0.25µm

CMOS that demonstrates these ideas will be presented.

1.3 Overview of Thesis

This thesis demonstrates how design methodologies across various levels of system abstrac-

tion can improve the performance of a system, which in the scope of this thesis, is minimizing

the energy consumption. Each of the chapter presented in this thesis covers a specific topic

associated with design of energy efficient microsensor network. First of all, design consid-

erations of a sensor node is studied in Chapter 2 with emphasis on the radio specifications

such as link budget, noise and start-up time. This sets up basis for investigations on MAC

protocol analysis and radio implementation. The low power MAC protocols are examined


based on a comprehensive radio model that includes the non-ideal characteristics of the

radio. Different MAC protocols are compared and an optimal MAC protocol for a coordi-

nated sensor network is derived. Next, implementation of an energy efficient transmitter

for microsensors are studied. Techniques for high data rate, fast start-up and low power are

examined and the experimental results from prototype chip are presented. With contribu-

tions of all these techniques from MAC to circuits, more than an order magnitude energy

reduction is possible compared to existing solutions.

Chapter 2

Design Considerations of a

Microsensor Node

The characteristics of a wireless sensor network are quite different from those of conventional

wireless hand-held devices. In this chapter, requirements of the sensor node will be inves-

tigated from the standpoint of circuits and communication protocols design. In particular,

requirements of the sensor radio will be analyzed, such as link budget, noise specifications

and start-up time.

2.1 Node Architecture

The basic building blocks of a sensor node can be categorized into the sensor, analog-to-

digital converter (ADC), digital signal processing (DSP) unit and radio as shown in Figure 2-

1. The ADC extracts digital bits from external stimulus such as temperature, pressure,

mechanical or acoustic vibration. The DSP unit processes the digitized bits into necessary

information and codes the data for efficient communication. The DSP unit also handles

communication control protocols and manages the sensor components to their appropriate

modes of operation such as active, idle, or sleep mode [19]. The processed data is then fed

to the radio and sent to the base station by means of high frequency electromagnetic wave.

The complexity and power consumption of these components are quite dependent on

the application of the sensor network. In the general scope of sensor applications, the

25

26 CHAPTER 2. DESIGN CONSIDERATIONS OF A MICROSENSOR NODE

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Figure 2-1: Microsensor node architecture.

requirements of each sensor component can be regarded as the following.

First, the requirements of the ADC are quite loose considering where ADC technologies

stand today. The sensor applications typically exhibit signals that are very low in frequency,

typically less than a few kiloHertz at a resolution of less than 12 bits per sample [20]. Since

commercially available ADCs with tens of kilo-samples per second(kSPS) consume about

a milliwatt (mW) of power [21], the sensor ADC does not exhibit a bottleneck in the low

power microsensor node design.

The complexity of a DSP unit depends on the role of a sensor node as well as the appli-

cation. For example, sensors in a collaborative network are assigned to different roles such

as sensing, relaying or beamforming [12]. Hence the workloads of the DSP will vary from

as little as bit sequencing to complex algorithms, such as FFTs and Viterbi decoding [22].

While the recent technology advance in DSP has shown that dedicated solutions consume

orders of magnitude less power than a general programmable CPUs, which consume several

hundreds of mW [23, 24, 25], designing a low power DSP encompassing all the functions

necessary for a microsensor node will be a challenging task.

The radio module is the most critical bottleneck in the microsensor node design. Unlike

the DSP where complexity scales with functionality, the radio is required to operate under

a certain specification that cannot be scaled or compromised, such as output RF power and

noise. Considering that today’s state-of-the-art low power transceivers [26, 27, 28] consume

hundreds of milliwatts of power with many off chip components, designing a radio for the

microsensor node will be a difficult task.

2.2. TRANSMITTER REQUIREMENTS 27

From the above discussions, the DSP unit and the radio unit are the critical components

in the microsensor node. While the DSP unit exhibits challenges of its own, the focus of this

thesis will be on reducing the energy consumption of the radio by improving the physical

layer electronics and communication protocols. In the following sections, specifications of

the radio components are developed. First, radio wave propagation is studied in order to

carry out the link budget analysis.

2.2 Transmitter Requirements

2.2.1 Link budget

Knowledge of channel characteristics is essential in a communication system design. In a

wireless network, radio wave propagation must be analyzed in order to determine various

specification of the system, such as output power and complexity of equalization.

Large scale path loss

In an ideal free space environment, the radio wave is attenuated along the transmit distance

(D) as D2. In reality however, the surrounding environments, especially indoors, often

cause reflections and scattering of the original signal that result in attenuation on the

order of Dn, where the path loss factor n varies from 3 to 4. Since the path loss depends

heavily on the surroundings of the radio wave’s propagation path, it cannot be exactly

modeled for any arbitrary environment. However, for the general purpose of sensor network,

valid assumptions can be made about the channel based on various test results that have

already been reported [29, 30, 31, 32]. For sensor networks, short distance path losses

for indoor environments will be considered since they exhibit harsher conditions for radio

waves than outdoors. The reported measurement results [32] show that path loss at 10 meter

distance can vary from as little as 40dB to as large as 70dB depending on the surrounding

environment. The large path loss of 70dB is seen in environments that are likely to absorb

electromagnetic energy, such as office buildings with concrete walls, while small path loss

is seen in industrial surroundings with metallic objects that have good reflections of the

radio waves. In terms of path loss factor n, the indoor office environments show n of 3 to


100

101

102

−70

−65

−60

−55

−50

−45

−40

−35

−30

−25

−20

Distance(meters)

Rec

eive

d po

wer

(dB

m)

Receiver power vs. distance

Path1

Path2

Path3

Path1 n=1.09Path2 n=1.03Path3 n=1.37

Figure 2-2: Received power vs. transmit distance (Courtesy of ABB Corporation Researchin Norway).

4, while factory environments with steel machinery show n of less than 2. An example of

path loss that is seen in an industrial factory is shown in Figure 2-2, where it can be seen

that the path loss factor is less than 2, which points out the vigor of reflected signals from

metallic objects. It also shows that the received power level does not drop monotonically

with distance, representing the effect of multi-path in non-line of sight (LOS) conditions.

Multi-path fading

While large-scale path loss describes the average signal attenuation as a function of spatial

separation, small-scale fading characterizes the statistics of the rapid variation of signal

amplitude over a short period of time [33].

For indoor environments that are prone to multi-path fading, the two main properties

of interest are the RMS delay spread and the probability distribution of the signal envelope.

The RMS delay spread measures the time dispersion of a signal. It gives an indication of

the time interval between the reception of the first and the last multi-path components.

In order to avoid equalization, the data symbol period must be kept longer than this time

interval since otherwise channel-induced inter-symbol interference will occur.


In an office environment with typical length of 10 to 30 meters, measurement results

show that the RMS delay is around 10 to 100ns [34, 31], which translates to more than

10MHz of coherence bandwidth1. For industrial environments filled with metal equipment,

the RMS delay is greater since metals have good reflection coefficients and thus it takes

longer to attenuate the multi-path components. Measurement results show that the RMS

delay for a 30 meter factory room filled with metal machinery is about 80ns, for which the

coherence bandwidth is approximately 3MHz [32].

While the RMS delay spread limits the maximum data rate without equalization, the

probability distribution of the signal envelope determines the amount of transmit power

required to achieve a certain BER. In an obstructed environment, the probability density

function (PDF) of the signal envelope can be characterized by a parameter KdB defined as

KdB = 10 log

(Pdominant

Preflected

)(2.1)

If KdB is large then the strength of multi-path components are small and the PDF of

the envelope is approximately Gaussian. If KdB is small, the multi-path components are

strong and the PDF approaches a Rayleigh distribution. In typical indoor environments,

KdB is measured to be around 1dB, for which the distribution is close to Rayleigh [33].

Link Budget

Based on the analysis given in the previous section, link budget of the sensor transmitter

can be calculated. The received signal to noise ratio (SNR) is

SNR =Preceived/W

(kT )Nf(2.2)

where, Preceived is the signal power, Nf is the noise figure of the base station receiver,

W is the bandwidth of the transmitted signal and kT is the thermal noise constant. Taking

1The delay spread will roughly depend on the size of the room, since the arrival time of a reflected signalis a function of radio wave’s traveled distance [35].


path loss into account and taking the logarithms of each side, Eq. 2.2 at room temperature

becomes

SNR(dB) = P(dBm)out − αP

(dB)loss −N

(dB)f − 10 log (W )(Hz) + 174(dBm/Hz) (2.3)

where Pout is the output power of the transmitter, Ploss is the average large scale path

loss and α is the variation of the path loss caused by fading. In order to calculate BER,

we must take into account the statistical variation of α, which is Rayleigh distributed. The

Raleigh fading conditions degrade the BER significantly more than an Additive White Gaus-

sian Noise (AWGN) channel, resulting the BER to drop linearly with Eb/No rather than

exponentially, as shown in Figure 2-3. It can be seen that more than 20dBm output power

is needed to achieve BER as low as 10−6 for an uncoded transmission. This is obviously

an unacceptable amount for a sensor node. The BER can be improved by employing diver-

sity and coding techniques. Diversity technique can be imposed on the high powered base

station, such as spatial diversity (multiple antennas) or time diversity (RAKE receiver).

The BER performance can also be improved at the transmitter side by employing forward

error correcting codes, which is effective in fading conditions as shown in Figure 2-3. In the

case of indoor environment, convolutional coding is appropriate due to the short packet size

and low circuit overhead at the transmitter [36]. Using these techniques, it is possible to

achieve less than 10−6 BER with 20dB of SNR in a 70dB path loss condition, which relates

to about -10dBm output power at the sensor transmitter with a data rate of 1Mbps. This

verifies the assumption that output power is negligible to power consumption of other radio

electronics.

2.2.2 Phase noise

Phase noise of the transmitter degrades the SNR of the signals in the adjacent channel. To

understand this problem, consider two sensors transmitting signals S1 and S2 in adjacent

channels as shown in Figure 2-4. If the signal S1 undergoes a larger attenuation (deeper

fade) than S2, the resulting degradation in SNR of S1 at the base station can be expressed


−30 −20 −10 0 10 20 3010

−8

10−7

10−6

10−5

10−4

10−3

10−2

10−1

Output Transmit Power (dBm)

Pro

babi

lity

of e

rror

Path loss=70dB, Receiver NF=10dB, Rate=1Mbps, Rayleigh flat fading

R = 1/2, K = 5

uncoded

R = 2/3, K = 3R = 1/2, K = 3

Figure 2-3: BER vs. output power in a slow Rayleigh fading channel.

as

SNR =

∫ f1

f0S1(f)df

∫ f1

f0S2(f)df

≥ Ps1

S2(f0)(f1 − f0)=

Ps1

Ps2Φ2(f0)(f1 − f0)(2.4)

=1

DΦ(f0)(f1 − f0)=

1DΦ(f0)W

(2.5)

where Si(f) is the power spectral density of the signal Si, Psi is the total power of the

signal in the bandwidth W , from f0 to f1, D is the excessive attenuation that S1 undergoes,

and Φ2(f) is the phase noise of S2 at f frequency from the carrier. Rearranging the terms

and taking logarithms, we achieve

Φ2(f0) = −SNR(dB) − 10 log D − 10 log R (2.6)

To achieve 30dB fading margin and 20dB SNR when the signal bandwidth is 2MHz, the

required phase noise is -110dBc at 1MHz from the carrier.


SNR

S1(f)

S2(f)

fch

f1f0

DB.S.

S1

S2

Figure 2-4: Degradation of SNR due to phase noise in adjacent channel.

Figure 2-5: Start-up transient of a commercial low power transceiver (Tstart ≈ 470µs).

2.2.3 Start-up time

Start-up time is a critical parameter in short packet low duty cycle communication systems.

In a sensor network, the radio module needs to be turned on/off during the active/idle

periods (i.e. duty cycled) in order to save power. Unfortunately transceivers today require

initial start-up times on the order of hundreds of microseconds to go from the sleep state

to the active state as shown in Figure 2-5, where VCO control voltage is plotted against

time. This is achieved from a commercial low power transceiver [26] which is capable

of transmitting data up to 1Mbps while consuming 81mW. For short packet sizes, the


transient energy during the start-up can be significantly higher than the energy required by

the electronics during the actual transmission This effect of start-up transient is shown in

Figure 2-6, where energy consumption per bit is plotted versus packet size.

We see that as the packet size is reduced, the energy consumption is dominated by the

start-up transient and not by the transmit on-time.

101

102

103

104

105

10−7

10−6

Packet size (bits)

Ene

rgy

per

bit (

J)

R=1Mbps, Tstartup

=450µ s, Ptx

=81mW, Pout

=0dBm

Figure 2-6: Effect of start-up transient on transmitter’s energy consumption in a 100 bitpacket transmission.

2.2.4 Data rate

As will be seen in the later part of this thesis, power consumption of the transmitter

in GHz frequencies is dominated by the frequency synthesizer and is not affected by the

data rate. Therefore, high data rate will allow lower transmitter energy consumption by

reducing the transmit time of a fixed sized packet. Unfortunately, this is true only from the

circuit’s perspective. From the communication standpoint, increase in data rate will require

training sequence to overcome frequency selective fading as the occupying bandwidth of the

transmitted signal exceeds the coherence bandwidth of the channel. Hence, higher data rate

will not necessarily reduce the transmit time since packet length will increase from training

sequence. In such cases when equalization is necessary to overcome frequency selective

fading, the on-time of the transmitter when sending an L-bit packet with rate R bits/sec


can be represented as

Ton−tx = Tpacket + Ttraining−sequence =L

R+ αtrainTdelay (2.7)

where Tdelay is the effective excess delay of the channel which determines the coherence

bandwidth and αtrain is a variable that depends on the the type of equalizer, characteristics

of delay spread, SNR, target accuracy, etc. As the data rate increases, Eq. 2.7 will be

dominated by the length of training sequence and hence high data rate will no longer offer

significant energy reduction. Therefore, it is important to take the effect of frequency

selective fading into account when the data rate approaches the coherence bandwidth of

the channel.

2.3 Considerations on Receiver and Base Station Design

Although the sensor’s primary function is to transmit information to the base station,

receiver on the sensor node is also necessary in order to handle various control signals from

the base station. In typical wireless devices, the receiver circuitry consumes 2∼ 3 times

more power than that of the transmitter circuitry, resulting in hundreds of milliwatts of

power. While the receiver is not used as often as the transmitter in the sensor network,

it is important to consider how the receiver power consumption can be reduced. For a

microsensor network, complexity of the sensor’s receiver can be reduced by exploiting the

high-powered base station. That is, specifications on sensitivity and noise figure can be

reduced if the base station transmits at maximum power that the FCC allows. For example

at 2.4GHz ISM band, up to 30dBm output power can be transmitted, which would require

about -20dBm sensitivity with 50dB path loss. In addition, requirements on dynamic range

can be reduced if power control is employed at the base station. These can significantly

reduce the power consumption of the receiver components such as mixers LNA and IF

amplifiers.

2.4. SUMMARY 35

2.4 Summary

Design considerations of a microsensor node were studied with focus on the radio. The

important criteria of the transmitter are link budget, start-up time, data rate and noise.

The link budget analysis shows that RF output power of the transmitter is small compared

to the power consumption of the transmitter electronics. Start-up time is found to be a most

critical parameter for low duty cycle sensor communications as it may dominate the energy

consumption. While data rate reduces the on-time of the transmitter, training sequence

must be considered if the data rate exceeds the coherence bandwidth of the channel. Lastly,

the noise must be kept below a certain level to ensure enough SNR. A low power receiver

on the microsensor node can be implemented by exploiting the high-powered base station.


Chapter 3

Low Power MAC Protocol

The need for medium access control (MAC) protocol arises from limited bandwidth. The

available bandwidth determines the capacity of a communication system with a given energy,

as described by the well known equation by Shannon. However, MAC protocols studied

in this chapter are viewed from a different perspective, from the standpoint of energy

efficiency of the entire system and not just the symbol energy that is typically considered in

conventional communication system design. Hence, bandwidth plays a different role from

its traditional role. To develop low power MAC protocols, a radio model that includes

non-ideal behavior of the physical layer electronics, is introduced. Based on the model,

low power MAC protocols for a single cell network and multiple cell network are explored.

These are applied to a coordinated sensor network used in an industrial environment. It

will be seen that bandwidth is indeed an important factor in power consumption, in that

larger available bandwidth leads to lower energy consumption of the network. However, it

will be seen that this is in a different sense than how it is traditionally perceived.

3.1 Previous Work

The study of communication protocols for wireless sensor network has mostly been con-

centrated on network level protocols such as scalable coordination of sensor networks [11],

multi-hop routing [12], and clustering algorithms [37] in an autonomous sensor network.

The design of MAC protocols for microsensor networks has not been considered by many

37

38 CHAPTER 3. LOW POWER MAC PROTOCOL

researchers and hence its impact on network’s energy consumption has not been studied in

depth. In a broader range of wireless networks that include wireless LANs, there are some

published results on low power MAC protocols [38, 39]. In Kishore’s work [38], an energy

efficient hybrid CDMA/TDMA is suggested, which schedules the network traffic based not

only on the priority of the user’s information but also on the user’s battery status. The

average lifetime of a user can be increased by granting transmission priorities based on the

user’s energy status. In the paper by Chen [39], various standard MAC protocols such

as IEEE802.11 and Bluetooth are evaluated. The conclusion drawn is that protocols with

lower number of transceiver activity results in lower power and hence, collisions in trans-

mitted packets should be avoided to lower the number of retransmissions. These papers

however, did not address the energy consumption of the radio in a detailed manner. The

MAC protocols studied in this chapter will be examined based on a detailed radio model,

which is described in the next section.

3.2 Radio Model

The sensor radio is composed of many modules; VCO, frequency synthesizer, mixers base-

band DSP, filters, etc. To analyze the radio power consumption for a MAC protocol, these

modules are categorized into three components: transmitter, output power amplifier and

receiver, as shown in Figure 3-1. Note that transmitter will be regarded as the modulator

part of the radio (i.e., mixer, frequency synthesizer) and excludes the output power ampli-

fier stage. The output amplifier stage is decoupled from the transmitter because its power

consumption is primarily determined by the link budget, which the designer does not have

any control over. The average power consumption of the radio can be described by the

following equation,

Pradio = Ntx[Ptx(Ton−tx + Tstart) + PoutTon−tx]

+NrxPrx(Ton−rx + Tstart) (3.1)

where Ntx/rx is the average number of times per second that the transmitter/receiver is

3.2. RADIO MODEL 39

Demod

Mod

BasebandDSP

Ptx

Prx

Pout

Figure 3-1: Block diagram of a sensor radio.

used per unit time, Ptx/rx is the power consumption of the transmitter/receiver, Pout is the

output transmit power, Ton−tx/rx is the transmit/receive on-time (actual data transmis-

sion/reception time), and Tstart is the start-up time of the transceiver. It is assumed that

transmitter and receiver shares the same frequency synthesizer and since the start-up time

is determined by the frequency synthesizer, start-up times of transmitter and receiver are

equal. For an environment monitoring application, Ntx depends on the event occurrence

rate of the application (i.e. how many times the sensor must report to the base station) and

Nrx depends on the media-access protocol used. Also note that Ton−tx = L/R, where L is

the length of a transmitted packet in bits and R is the data rate in bits per second. In this

radio model, the power amplifier needs to be on only when transmission occurs. During

the start-up time, data cannot be sent or received by the transceiver, because the internal

frequency synthesizer of the transceiver must be locked to the desired carrier frequency

before data can be modulated or demodulated.

It is important to highlight a few key points about this specific radio model. First,

it should be noted that power consumption of the transceiver dominates over the output

transmit power(Ptx/rx ¿ Pout). As studied in Section 2.2.1, the required output power for 10

meter distance is less than 0dBm (1mW), which results in less than 10mW even with a power

amplifier with 10% efficiency. Therefore the power consumption of the radio electronics

is dominated by the analog RF circuitry which typically consumes tens to hundreds of

milliwatts (mW) [9, 26]. In addition, the transmitter power (Ptx) does not vary much over


data rate to a first order approximation. In GHz frequency bands, power consumption

of the transceiver is dominated by the frequency synthesizer which generates the carrier

frequency and it is not effected by the data rate to the first order [40]. Hence for low power

operation, it is desirable to send the data at maximum rate in order to reduce the transmit

on-time (Ton−tx). Second, the start-up time (Tstart) should receive special attention due

to the short packet size. In order to save power, the radio module needs to be turned

on/off during the active/idle periods (i.e., duty cycled). Unfortunately transceivers today

require initial start-up times on the order of hundreds of microseconds to go from the sleep

state to the active state. For short packet sizes, the transient energy during the start-up

can be significantly higher than the energy required by the electronics during the actual

transmission (i.e. Tstart > Ton−tx). Hence it is important to take this inefficiency into

account when designing energy efficient communication protocols. Lastly, although the

data traffic is mostly up-link from the sensors to the base station, down-link may also be

necessary for certain protocols. That is, Ntx is governed by the application scenario and

Nrx is determined by the protocol. It should also be noted that Prx is usually 2− 3 times

higher than Ptx in typical commercial radios and hence MAC protocol should try to avoid

receiver activity.

3.3 Low Power MAC Protocol

A media access protocol determines the activity of the transceivers, which directly impacts

the power consumption of a network. In this section, low power MAC will be developed for

a coordinated sensor network for the one shown in Table 1.2.

3.3.1 Contention vs. scheduled MAC

Multi-access schemes can be categorized into contention based or schedule based schemes.

The contention based MACs, such as Aloha, CSMA or slotted Aloha, are generally used for

networks that do not have a scheduled occurrence of events. Scheduled schemes on the other

hand, operate by means of strict scheduling of time, frequency or code as seen in TDMA,

FDMA or CDMA. The pros and cons of these two methods depend on the application.

3.3. LOW POWER MAC PROTOCOL 41

For a sensor network, scheduled MAC protocols have the advantage that the latency of

a transmitted packet is guaranteed and that there is no collision of transmitted packets,

thereby eliminating the need for retransmission. The disadvantage is that bandwidth may be

wasted since the scheduling will be based on a worst case scenario, which is when the event

rate is at maximum and all the sensors try to transmit to the base station. Contention

based schemes on the other hand, have the advantage that the bandwidth can be used

more efficiently. If the average event rate is low and sensors seldom transmit to the base

station, then a sensor node can fully utilize the bandwidth when transmitting a packet.

The disadvantage is that the latency of a packet is not guaranteed due to retransmissions

caused by collision. The more severe problem of the contention based MAC arises from

the fact that it requires handshaking between the base station and the sensor every time a

packet is sent. This means that the receiver on the sensor side must be activated every time

a packet is sent. Therefore, sensors in contention scheme will always have more transceiver

activity than those in scheduled scheme. It should be noted that more transceiver activity

does not necessarily mean higher energy consumption, since the transceivers in contention

scheme will be able to use more bandwidth, which may be helpful in reducing the energy

consumption of the radio.

In order to compare the power consumption of the sensors in both schemes, let Ps, Pc

denote the average power consumption of a sensor in scheduled scheme and contention based

scheme respectively. The transmitter’s energy consumption is represented by Etx and Etx,c

for scheduled and contention based schemes respectively. The power consumption can be

described by the following equation,

Ps = NtxEtx + NrxErx = REEtx + NrxErx (3.2)

Pc = Ntx(1 + mc)(Etx,c + Erx) = RE(1 + mc)(αEtx + Erx) (3.3)

where RE is the average number of times that a sensor transmits a packet to the base

station (i.e., event rate), α is the ratio of transmitter’s energy consumption between the

two schemes (α = Etx,c

Etx) and mc is the the average number of retransmission trials before a


packet is successfully sent to the base station for a contention based scheme. In a scheduled

MAC, the number of receiver activity Nrx is determined by the protocol, while in a con-

tention based scheme, it is equal to number of the transmitter activity due to handshaking.

Note that the energy consumption of the sensor receivers for both schemes are assumed

to be equal. The transmitters may consume different energy, since transmitter circuitry

in contention based scheme will benefit from the fact that it is given more bandwidth.

Comparing the above two equations by subtracting Eq 3.2 from Eq 3.3,

Pc − Ps = R (αmc + α− 1)Etx + (1 + mc)Erx −NrxErx (3.4)

In order for a scheduled MAC to achieve lower power than a contention based MAC, the

average receiver usage Nrx determined by the scheduled protocol must satisfy the following

inequality.

Nrx < RE

1 + mc + (αmc + α− 1)

Etx

Erx

(3.5)

= REKc (3.6)

In other words, the scheduled protocol should make sure that the receiver usage is lower

than the event rate, RE , by a factor of Kc, to achieve lower energy than a contention

based scheme. It can be seen that Kc is a function of average retransmission trials mc in a

contention based scheme. The factor Kc is plotted against mc in Figure 3-2 for different α.

mc is regarded as a variable since it is a function of many parameters including available

bandwidth, event rate, etc. In the figure, scheduled scheme achieves lower power in the

region below the plotted line, which is where the Nrx is lower than the event rate by a

factor of Kc. α = 1 and α = 0 are the upper and lower limits for the transmitter energy

consumption of Etx,c.

In order to figure out how well a scheduled protocol must be designed to achieve lower

energy than the contention based schemes, Nrx must be calculated. It will be seen in the

next section that the Nrx is given by the following equation,


0 0.2 0.4 0.6 0.8 10.5

1

1.5

2

2.5

mc : Average number of retransmissions

in a contention based scheme

Kc

Pc < P

s

Ps < P

c

α =1 α=0.5α=0

Figure 3-2: Comparison of energy consumption between scheduled and contention basedMAC.

Nrx =ρ

Tguard(3.7)

where ρ is the frequency difference between sensors’ reference clock and Tguard is the

guard time between two transmitted packets. Typical low cost crystal oscillators today have

ρ of about 50ppm. For a 100 sensor network that sends 100bit packet at 1Mbps with 10ms

latency, Nrx comes out to be two times per second. Therefore, if the average event rate

is more than one occurrence per second, then scheduled scheme will always achieve lower

energy than contention based scheme. If the average event rate is lower, than the designer

must consider other factors such as mc and α. In the example of the factory machine

monitoring, RE À Nrx, and therefore scheduled scheme is better than the contention based

MAC.


3.3.2 Hybrid TDM-FDM

TDMA-FDMA

In this section we derive a low power MAC protocol based on the radio model from Eq. 3.1

for a single cell network where a high powered base station gathers data from the sensors.

It is assumed that the bandwidth is sufficiently enough such that network’s maximum

possible aggregate data rate (i.e., when all sensor transmit to the base station) is less than

the available bandwidth. This is a valid assumption for for general low data rate sensors

that use ISM band with more than 80MHz of bandwidth at 2.4GHz and 5.8GHz. Assuming

we have control over data rate, whether by means of designing a custom transmitter or

choosing from an off-the-shelf component, Ton is minimized in TDMA since the bandwidth

is at maximum, allowing the highest data rate. For FDMA, the available bandwidth is at

minimum, resulting in the longest on-time. A hybrid scheme of TDM-FDM is also possible,

where both time and frequency are divided into transmission slots. This is illustrated in

Figure 3-3 where shaded area indicates a valid transmit slot for sensor Si. In cases where

time division is employed, we should note that a down-link from the base station to the

sensors is required in order to maintain time synchronization among the sensors [41]. Due

to the finite error among each sensor’s reference clock, the transmitted packets will drift

in time. For example, suppose two sensors have reference clocks that are ρ ppm apart.

After these two sensors are synchronized, the sensor with slightly higher frequency will

send the packet sooner than originally scheduled as shown in Figure 3-4. This will continue

in time and the sensor with faster clock will eventually smear into the other time slot. The

minimum time that take for these two sensor to collide is hence given by Tguard/ρ.

In order to avoid collision, the base station must send out sync signals. Hence the sensor

receiver must be turned on every so often to receive these sync packets. The number of

receptions (Nrx) depends on the guard time (Tguard) which is the minimum time difference

between two time slots in the same frequency band, as shown in Figure 3-3. If two slots in

the same frequency band are separated by Tguard, it will take Tguard/ρ time for these two

packets to collide, where ρ is the difference between the two reference clocks. Hence the

sensor must be resynchronized at least ρ/Tguard number of times every second.


...

...

freq

uenc

y

time

S1

S1

FDMA (h=n) Hybrid (h=3 )

TDMA (h=1)Hybrid (h=2 )

BW

S2

S3

SM

S2 S4 SM

S1 S3 SM-1

S2 S3 S4... ... SM

S2

S1

S3

SM-2

SM-1

SM

Tlat

S5

S4

S6

...

Ton Tguard

Tavail

Figure 3-3: Multiple access methods: TDM,FDM and hybrid TDM-FDM.

This is described in Eq. 3.8, where W is the total available bandwidth, L is the size

of the transmit packet in bits, Tlat is the latency requirement of the sensor data, h is the

number of channels in the given bandwidth W , Tavail is the time difference between start of

two packets and M is the number of sensors. It is also assumed that the data rate is equal

to the occupying signal bandwidth and hence Ton = L/(W/h).

Nrx =ρ

Tguard=

ρ

Tavail − Ton=

ρ

(TlatM − L

W )h(3.8)

From the above equation, we see that as the number of channels decreases, guard time

becomes larger and receiver activity is reduced. It is also apparent that the advantage of

pure FDMA is that it does not need a receiver (i.e. Tguard →∞, Nrx = 0).

Since (A + B) ≥ 2√

AB, by plugging in Eq. 3.8 into Eq. 3.1, we can find an analytical

formula for the optimum number of channels which gives the minimum power. This is given

in Eq. 3.9, where in addition to the previous notations, hopt represents the optimum number

of channels to achieve lowest power consumption.


S1 S2 S1 S2

Frame1 Frame 2 Frame3 Framen

S1’s ref clk

S2’s ref clk

collision!

Figure 3-4: Drift in transmitted packets due to reference clock error.

hopt =

√√√√ δPrx(Ton−rx + Tstart)(Tlat

M − DataW )Ntx(Ptx + Pout)Data

W

∝√

Prx

NtxPtx(3.9)

We see that hopt is determined by the power consumption ratios between the transmitter

and the receiver. As expected, receivers which consume less power favor TDMA with fewer

channels, while receivers with larger power prefer FDMA with more channels.

An example of the previous analysis is performed in a scenario where a sensor on average

sends twenty 100-bit packets/sec (Ntx = 20/sec,Data = 100bits) with 5ms latency require-

ment (Tlat = 5ms). The bandwidth available to the cell is 10MHz (W = 10MHz), and

the number of sensors is 300. The resulting average power consumption is plotted in Fig-

ure 3-5 and 3-6, where average power consumption is plotted versus the number of channels

(i.e., h = 1: TDMA, h = 300: FDMA). The graph shows power consumption for different

Prx/Ptx and Tstart. It can be seen that hopt increases for higher receiver power, so that the

number of receptions is reduced. As the start-up time increases, the energy consumption is

dominated by the start-up time and choice of MAC does not effect the energy consumption


100

101

102

10−1

100

101

number of channels(h)

Ave

rage

Pow

er C

onsu

mpt

ion

(mW

)

Prx

=300mW, 100bit packet

Tstart

=10µ s

Tstart

=100µ s

Tstart

=1m s

Tstart

=10m s

Figure 3-5: Energy consumption of a sensornetwork using hybrid TDM-FDM with differentTstart.

100

101

102

100

101


Ave

rage

Pow

er C

onsu

mpt

ion

(mW

)

Ptx

=81mW, 100bit packet, Tstart

=450µ s

Prx

=50mWP

rx=100mW

Prx

=300mW

Figure 3-6: Energy consumption of a sensornetwork using hybrid TDM-FDM with differentErx.

very much. Again, the reason why TDMA with minimum on-time does not achieve the

lowest power is because of the receiver power consumption from network synchronization.

As the data rate increases, guard time becomes smaller and the receiver power starts to

become a significant portion of overall power consumption.

3.3.3 Effect of fading on MAC

The previous analysis demonstrates how appropriate MAC protocol can reduce the energy

consumption of a network. It is under the assumptions that power consumption of the

radio is dominated by the transceiver electronics, which does not change over data rate.

However, it was seen in Chapter 2 that excessive data rate can increases the packet length for

equalization to overcome frequency selective fading. If the training sequence for equalization

is taken into account, the radio model now becomes,

P ′radio = Ntx[Ptx + Pout](

L

R+ αtrainTdelay) + PtxTstart

+NrxPrx(Ton−rx + Tstart) (3.10)

The result of optimum MAC scheme from the revised radio model is shown in Figure 3-7,


which assumes that excess delay of the channel is 1000ns. The graph shows that the energy

consumption of TDM is increased as due to equalization. However, the optimum number

of channel for MAC does not vary much since effect of equalization is small when the data

rate is below coherence bandwidth.

100

101

102

100

101


Ave

rage

Pow

er C

onsu

mpt

ion

(mW

)

Ptx

=81mW, Ptx

=100mW, 100bit packet, Tstart

=450µ s

α=0

α=2

α=10

Figure 3-7: Energy consumption of a sensor network with equaliztion.

3.4. VARIABLE BANDWIDTH ALLOCATION SCHEME 49

3.4 Variable Bandwidth Allocation Scheme

The previous section presented a low power design methodology for a single cell sensor

network with a fixed cell density. This section investigates how energy consumption can be

reduced in a multi-cellular network where each cell has a different cell density.

3.4.1 Energy vs. bandwidth

In the traditional perspective of communications, available bandwidth determines the re-

quired energy of a transmitted symbol. However, for short distance communications where

the symbol energy is small compared to the transceiver energy, bandwidth has a different

impact on energy consumption. To see this illustratively, consider an example where a cell

consists of 6 sensors and each sensor sends a 100bit packet every 1ms at 1Mbps. Using hy-

brid TDM-FDM, two schemes are shown in Figure 3-8, where the scheme in (a) has larger

available bandwidth than the scheme in (b). While the sensors in both scheme meet the

latency requirement of 1ms, the sensors in scheme (a) have larger guard time and hence less

receiver activity. Therefore, larger available bandwidth reduces the energy consumption

of the sensor network. This can be analytically shown by describing the average energy

consumption of a sensor radio with the following equation, which is derived from Eq 3.1

and Eq 3.8.

Eavg = Etx +Nrx

NtxErx = Etx +

ρ

TguardNtxErx

= Etx +ρ

Ntx(TlatM − L

W )hErx (3.11)

If the specification of the radio is fixed (i.e., data rate, power consumption), then the

energy consumption of the sensor radio is a function of available bandwidth, W . This is

shown in Figure 3-9, where average energy consumption is plotted versus W . The energy

consumption reduces as the available bandwidth increases, due to the lower receiver activity.


freq

uenc

yTlat = 1msTlat = 1ms

Tguard,1

Tguard,2

W=1MHz

Ton=100us

(a) Available bandwidth = 3MHz (b)Available bandwidth = 2MHz

Figure 3-8: Example of slot allocation in different available bandwidth.

3.4.2 Variable time-frequency slot allocation

One of the unique characteristics of the sensor network is that variation in cell density is

large, as shown in Table 1.2. Since the available bandwidth impacts the energy consumption

of the sensors, the bandwidth must be well managed in order to increase the battery lifetime

of the sensors. In a cellular network with frequency reuse, bandwidth is typically allocated

equally to all the cells regardless of its density. This scheme is wasteful in bandwidth if the

network has large variation in the cell density. A better way of bandwidth allocation is to

assign bandwidth according to the number of sensors in each cell, as shown in Figure 3-

10(b). Basically, cells with more sensors are assigned larger bandwidth than those with

fewer sensors. Unfortunately, the problem of this approach is that it is difficult to allocate

different amounts of bandwidth as the cellular network becomes large. For example in

Figure 3-10(b), suppose we have allocated different amounts of bandwidth to cells A through

G and F ended up consuming dominant part of the total available bandwidth. If cells H,I

or K has more sensors than F, then the bandwidth allocation scheme on A ∼ G must be

revised. As the cellular network becomes large, assigning bandwidth to the cells will resort

back to the fixed bandwidth allocation scheme.

This problem can be resolved if we allocate a time-frequency slot to each sensors instead

of allocating a band of frequency to a cell as shown in Figure 3-11. The requirement here

is that time synchronization must kept throughout the entire cellular network. This allows

sensors in different cells to use the same frequency at a different time. Hence cells with

more sensors can have more time-frequency slots, which is effectively same as having more


1 2 3 4 5 6 7 8 9 100

1

2

3

4

5

6x 10

−4

Bandwidth (MHz)

Ene

rgy

(J)

Ptx

=100mW,Prx

=300mW,ρ=100ppm,Tlat

=1ms,L=100bits,R=1Mbps,M=100

Figure 3-9: Average energy consumption of a sensor radio vs. available bandwidth.

bandwidth. Furthermore, a time-frequency slot can be shared by two different sensors at

the same time if the sensors are placed far apart so as not to cause any interference to

one another. This is similar to the conventional cellular network with frequency reuse,

where users in different region can communicate at the same frequency channel at the same

time without interference. While this reuse of time-frequency slot can reduce the energy

consumption of the network, it is difficult to optimally assign time-frequency slots to the all

the sensors in the entire network. This is because the slot assignment of one cell affects the

entire network through time-frequency slot reuse. In the following section, time-frequency

slot allocation algorithm is proposed to minimize the energy consumption of the entire

network.

3.4.3 Energy efficient time-frequency slot allocation algorithm

To approach this problem analytically, a set of notations is defined as the following. It is

assumed that the cellular network has the regular hexagonal structure shown in Figure 3-12.

Definition 1 (Neighbor) A cell is a neighbor to another cell if the boundaries of the

cells touch each other. A cell is also a neighbor to itself.


A

B G

C

D E

FH

I

J

...C1

C6

C11

C2

C7

C12

C5

C10

C15

freq

uenc

y

time

A i

cell index

sensor number

frequency

A B C D E F G

(a) fixed frequency bandwidth allocation

A B C D E F G

(b) variable bandwidth allocation

A

B G

C

D E

FH

I

J

K

Figure 3-10: Bandwidth allocation schemes in a cellular network.

...

...3

A1

A2

B13

B2

B3

C23

F1

G1

G10

..

frequency

freq

uenc

ytime

A

B G

C

D E

FH

I

J

Figure 3-11: Variable bandwidth allocation scheme with time-frequency slots.

Definition 2 (Macrocell) A macrocell(Θ) is a group of cells that are enclosed in a

closed space, in which the nodes are not allowed to use to same slot. Figure 3-12 shows an

example of macrocells that have frequency reuse of 7.

Definition 3 (Joint Macrocells) Macrocells are called joint if there exists more than

one cell that are included in both macrocells. In Figure 3-12, Θ1 and Θ2 are joint macrocells.

Definition 4 (Disjoint Macrocell) Macrocells are called disjoint if there does not exist

any cell which is included in both macrocells. In Figure 3-12, Θ2 and Θ3 are disjoint.

Definition 5 (Energy cost function) Energy cost function is defined as Ec(i) =

Macrocellneighbors

Θ2

Θ3

Θ1

i-1 i i+1

di-1 di

Figure 3-13: Guard time of slots in the same frequency channel.

1/min(di−1, di), where di−1 and di are the guard time between other slots as shown in

Figure 3-13.

The energy cost function directly follows from Eq. 3.11. Basically, min(di−1, di) is guard

time of ith sensor since ith slot can drift in either direction to slot i−1 or i+1. With Etx,Erx

and ρ being same for all the sensors, the energy cost function determines the number of

receiver activity and hence minimizing energy consumption is equivalent to minimizing the

energy cost function, Ec.

In order minimize the energy consumption of the entire network, slot allocation method

is approached from a network with a single macrocell and then generalized to a network

that has joint macrocells.

Single Macrocell optimization

A single macrocell can be treated as a single cell, since frequency reuse is not allowed.

Hence there is a unique slot that corresponds to each sensor. The energy consumption can


Figure 3-12: Notations used in a cellular network (frequency reuse=7).


be minimized through following theorems.

Theorem 1 When assigning slots for the n sensors in the same frequency band, equi-distant

placement of the slots results in the lowest energy.

Proof. The statement can be rewritten as follows:∑

i Ec(i) is minimized when d1 = d2 = · · · = dn, where

∑

i

Ec(i) =1

min(d1, d2)+

1min(d2, d3)

+ · · ·+ 1min(dn, d1)

(3.12)

subject to∑n

i=1 di = constant

Proof. Since arithmetic mean is always greater than or equal to the geometric mean,

Eq. 3.12 is minimized when min(di, di+1) are same for all i. Also since∑

di = constant,

1/min(di, di+1) achieves minimum when di = di+1 and hence di must be same for all i in

order to achieve minimum energy.

Theorem 2 Energy consumption of a macrocell is minimized if the difference in the number

of nodes per frequency channel is minimized.

Proof. Suppose frequency channels i and j have nf (i) and nf (j) number of nodes respec-

tively, where nf (i) + nf (j) = constant. In order for the nodes in each frequency channel to

achieve minimum energy the slots of the sensors must be equally spaced apart as explained

in Theorem 1. Hence the energy cost function of a sensor in the frequency channel i, Eic is

Eic = (1/nf (i))−1 and Ej

c = (1/nf (j))−1. The total energy cost function is then,

Ec,total = nf (i)2 + nf (j)2

=12((nf (i) + nf (j))2 + (nf (i)− nf (j))2)

=12(k2 + |nf (i)− nf (j)|2)

Hence, it is clear that |nf (i)− nf (j)| must be minimized.


Based on the above two theorems, an optimum slot assignment function, F (Θ), for a

single macrocell can be defined as the following.

F (Θ): Slot allocation function for sensors in macrocell Θ

1. Assign slots to sensors so that the difference in the number of sensors

in different frequency channel is minimized.

2. For each frequency channel, assign slots to sensors so that the guard

time between all the slots are equal.

Slot assignment in joint macrocells

For joint macrocells, the slot assignment function is extended to two macrocells: Θi and

Θj . We define F (Θi|Θj) as a function that assigns slots to Θi with subject to F (Θj). This

function is further explained below, where ni and nj are the number of nodes that are

exclusively in Θi and Θj and m is the number of nodes which are both in Θi and Θj as

shown in Fig. 3-14.

A B

Θi Θj

Cni m nj

Figure 3-14: Number of sensors in joint macrocell network.


F (Θi|Θj): Slot assignment function for two macrocells.

1. F (Θj); (i.e.,assign slots to sensors in Θj such that energy of Θj is

minimized.)

2. In order to assign slots to sensors in Θi, empty the nj slots which are

exclusive to Θi

3. if ni < nj , choose ni slots from the emptied nj slots such that the

distance between the slots are maximized.

4. if ni > nj , add ni − nj additional slots so as to accommodate for the

extra nodes. When adding extra slots, follow theorem 1& 2.

With the slot assignment function defined as above, we can minimize the energy con-

sumption of a network consisting of joint macrocells based on the following theorem.

Theorem 3 When assigning slots to joint macrocells and ni < nj, energy consumption of

sensors whose slots are assigned by F (Θi|Θj) is smaller than that by F (Θj |Θi).

Proof. Since ni < nj , slots from F (Θi|Θj) has smaller average guard time than slots

from F (Θj |Θi). Therefore, energy consumption of F (Θi|Θj) is smaller.

Slot allocation for entire network

Based on the previous theorems, an energy efficient slot allocation algorithm is shown below.

Global network optimization

for (i = 1; i < Ntotal; i++;)for (k = 1; k < Ntotal; k++;)

F (Θk|(Θmax|Θi));

Calculate the energy cost function for the entire network.

3.5. SUMMARY 57

This is a full search of the entire network with slot optimization subject to F (Θmax|Θi).

Following from Theorem 3, F (Θi|Θmax) will achieve minimum energy for macrocells Θi and

Θmax, where Θmax denotes the macrocell with maximum number of sensors in the network.

Therefore, it may seem that the energy consumption of the entire network can be minimized

by allocating slots according to F (Θi|Θmax). However, note that that F (Θi|Θmax) achieves

minimum energy only when Θi and Θmax are considered. For Θi alone, F (Θi) will achieve

minimum energy. If there are more macrocells that achieve lower energy with F (Θi) than

F (Θmax), then the slots must be assigned subject to F (Θi). For example, suppose the

network consists of 1 macrocell that has 10 nodes and 1000 other nodes that has 2 nodes. In

this case, assigning the slots to the macrocell that have 2 nodes will result in lower energy. In

the above algorithm, F (Θk|(Θmax|Θi)) accounts for scenario like these. The above algorithm

has been implemented in Matlab for a network that has 30 average number of sensors. The

simulation results are shown in Figure 3-15, where total average power consumption of the

sensors is plotted vs. standard deviation of the cell density. Two graphs are shown, one for

a conventional fixed bandwidth allocation (FBA) scheme and variable bandwidth allocation

(VBA) scheme. It can be seen that VBA approach consumes lower power than the FBA

scheme as the variation in the cell density is increased.

3.5 Summary

Low power MAC protocols were investigated based on the radio model that includes the

start-up time of the radio. The energy consumption of the network is minimized by em-

ploying a hybrid TDM-FDM system that trades-off energy consumption of the transmitter

and the receiver. The TDMA scheme reduces the energy consumption of transmitter by

decreasing the the on-time, while the FDMA scheme reduces the energy consumption of

the receiver by lowering the number of time synchronizations. For short distance commu-

nications, the available bandwidth has a different impact on energy consumption from the

traditional perspective of Eb/No, in the sense that large available bandwidth allows less

synchronization and hence lower energy consumption in the receiver. This is exploited in

allocating bandwidth to the sensor network that has wide variation in the sensor distribu-


10 15 20 25 30 35 40 45 50 55 6015

20

25

30

35

40

45

50

55

60

Standard deviation in number of sensors per cell

Ave

rage

pow

er c

onsu

mpt

ion

of th

e to

tal n

etw

ork(

mW

) Fixed vs Variable Bandwidth Allocation Scheme

VBA

FBA

Figure 3-15: Power consumption of the sensor network for a variable bandwidth allocation(VBA) and a fixed bandwidth allocation (FBA) scheme.

tion. By employing time-frequency slot allocation, bandwidth is used more effectively and

energy consumption of the network is reduced. Another interesting research area is to in-

corporate more detailed circuit models into protocol development. For example, allocating

larger bandwidth to a sensor can relax the specification of the transmitter’s output noise

which in turn can reduce the power consumption of the transmitter circuitry significantly.

Chapter 4

High Data Rate Low Power

Transmitter

In the preceding chapters, multi-access protocols for a microsensor network were examined.

In the following chapters, a different aspect of the sensor network, implementation of the

sensor transmitter, will be investigated at the circuits and system level. Since the network

traffic of the sensor network is mostly up-link from the sensors to the base station, reducing

the energy consumption of the transmitter will have a dramatic impact on the network’s

energy consumption.

Implementing an energy efficient transmitter is different from designing a low power

transmitter. Since we are trying to maximize the sensor’s battery lifetime, energy con-

sumption, rather than power dissipation, must be reduced. As seen earlier, the energy

consumption of a transmitter when sending a packet can be represented by the following

equation,

Etx = (Ptx + Pout)Ton−tx + PtxTstart

= (Ptx + Pout)L

R+ PtxTstart (4.1)

where the parameters have been defined in Eq. 3.1. In order to reduce the energy consump-

tion, it is important to reduce the transmit time and the start-up time as well as lowering the

59

60 CHAPTER 4. HIGH DATA RATE LOW POWER TRANSMITTER

power consumption of the transmitter. In other words, implementing an energy efficiency

transmitter means designing a high data rate, low power, and fast start-up transmitter. In

the following chapters, each of these tasks will be examined and accomplished by exploiting

architectural and circuit level trade-offs between various components of the transmitter.

As a first step, techniques for designing a low power high data rate transmitter will be

studied in this chapter. In the first section, modulation scheme that is appropriate for low

power high data rate transmitter will be chosen. Different types of modulation scheme

will be viewed from the standpoint of circuits, rather than the traditional perspective of

Eb/No owing to the short transmit distance. Based on this analysis, a low power high

data rate transmitter architectures will be explored. Specifically, a closed loop direct VCO

modulation architecture will be studied.

4.1 Binary vs. M-ary Modulation Scheme

The modulation scheme strongly impacts the energy consumption of a sensor node. As

evidenced by Eq.3.1, one way to increase the energy efficiency of communication is to reduce

the transmit on-time of the radio. This can be accomplished by sending multiple bits per

symbol, that is, by employing M -ary modulation. Using M -ary modulation, however, will

increase the circuit complexity and power consumption of the radio. In addition, when M -

ary modulation is used, the efficiency of the power amplifier is also reduced due to higher

linearity requirements. This implies that more power will be needed to obtain a certain

level of transmit output power.

The architecture of a generic binary modulation scheme is shown in Figure 4.1(a), where

the modulation circuitry is integrated together with the frequency synthesizer [26, 42]. To

transmit data using this architecture, the VCO can be either directly modulated or indirectly

modulated by using Σ-∆ modulator. The radio architecture of an M -ary modulation is

shown in Figure 4.1(b). Here, the data encoder parallelizes serially input bits and then

passes the result to a digital-to-analog converter (DAC). The analog values produced serve

as output levels for the in-phase (I) and quadrature (Q) components of the output signal.

The energy consumption for the binary modulation and the M -ary architecture can be

4.1. BINARY VS. M-ARY MODULATION SCHEME 61

cos(ωRF t)data

LPF

PFS-B, Pmod-B

(a) Binary Modulation

cos(ωRF t)Σ

DAC

DAC

DataEncode

data

sin(ωRF t)

LPF

LPF

I

Q

PFS-M

Pmod-M

(b) M -ary Modulation

Figure 4-1: Transmitter architecture of binary and M -ary modulation.

expressed as

Ebin = (Pmod−B + PFS−B)Ton + PFS−BTstart + Pout−BTon (4.2)

EM = (Pmod−M + PFS−M )Ton

n(TstartPout−M

Ton

n

=(αPmod−B + βPFS−B)Ton

log2 M+ βPFS−BTstart +

Pout−MTon

log2 M(4.3)

In these equations, Pmod−B and Pmod−M represents the power consumption of the binary

and M -ary modulation circuitry such as mixers and DACs, PFS−B and PFS−M represent

the power consumed by the frequency synthesizer, Pout−B and Pout−M represent the output

transmit power for binary or M -ary modulation, Ton is the transmit on-time, and Tstart is

the start-up time. As mentioned, for a given packet size, Ton for M -ary modulation is less

than Ton for binary modulation by a factor of n, where n is the number of bits per symbol

(n = log2 M). The factors α and β can be expressed as

α =Pmod−M

Pmod−Bβ =

PFS−M

PFS−B(4.4)

where α represents the ratio of the modulation circuitry’s power consumption between


M -ary and binary modulation, while β is the ratio of synthesizer power between the M -ary

and binary schemes. Basically these parameters represent the overhead that is added to the

modulation and frequency synthesizer circuitry when one switches from a binary modulation

scheme to an M -ary modulation scheme. For example, the frequency synthesizer in M -ary

modulation scheme must generate quadrature signals. The quadrature components are

usually achieved by operating the VCO at twice the desired frequency and dividing it by

two. In addition M -ary modulation requires mixers and A/D that are not necessary in

binary modulation scheme. Hence these added components contribute significantly to the

power consumption of an M -ary scheme.

By comparing Eq. 4.2 and Eq. 4.3, it can be seen that M -ary modulation achieves a

lower energy consumption when the following condition is satisfied.

α < n

[1 +

PFS−B[(1− βn)Ton + (1− β)Tstart]

Pmod−BTon

]+ n

Pout−B

Pmod−B− Pout−M

Pmod−B(4.5)

≈ n

[1 +

PFS−B[(1− βn)Ton + (1− β)Tstart]

Pmod−BTon

](4.6)

The last two terms of Eq. 4.5 are small since Pout−B and Pout−M are negligible compared

to the power of the frequency synthesizer.

A comparison of the energy consumption of binary modulation and M -ary modulation

is shown in Figure 4-3. In this figure, the ratio of the energy consumption between M -ary

and binary modulation scheme is plotted versus the overhead α. It is assumed that β =

1.5, which is a reasonable assumption considering quadrature VCO is needed in the M -ary

scheme. It is plotted for the cases when start-up time is 20µs and 450µs. For each start-up

time, the graphs are plotted for M = 4, 8 and 16. When the start-up time is 20µs, the

M -ary modulation achieves lower energy consumption as the power consumption of the

overhead circuitry is reduced. The saving increases as M gets higher, since transmit time

gets shorter. However, when the start-up time is 450µs, the binary modulation always

achieves lower energy, independent of the overhead circuitry. This is because the start-up

time already dominates the transmit time of the packet and hence there is no savings in

energy consumption by going to the M -ary modulation scheme.

4.2. HIGH DATA RATE LOW POWER FSK MODULATOR 63

1 1.5 2 2.5 3 3.5 4 4.5 50.6

0.7

0.8

0.9

1

1.1

1.2

1.3

1.4

1.5

α

Em

ary/E

bina

ry

M=16

M=8

M=4

M=16

M=8M=4T

start=450µs

Tstart

=20µs

PFS−B

=20mW, Pmod−B

=20mW, Pout

=0dBm, β=1.5

Figure 4-2: The ratio of the energy consumed by M -ary modulation to the energy consumedby binary modulation versus α, the ratio of the modulation circuitry power consumption.

The effect of start-up time on modulation scheme is better seen in Figure 4-2, where

the energy consumption ratio between the two schemes are plotted against start-up time.

It can be seen that the M -ary modulation scheme achieves lower energy only if the start-

up time is small enough compared to the transmit time. Therefore, the radio designer as

well as the protocol designer must keep the effect of start-up time in mind when designing

a transmitter or a communication protocol. An in-depth analysis of various modulation

schemes for sensor network is studied in [43].

4.2 High Data Rate Low Power FSK Modulator

In the previous section modulation schemes were compared from the standpoint of trans-

mitter’s energy consumption. While M -ary modulation scheme can achieve lower energy

by reducing the on-time, it is true only if the start-up time is small compared to the

transmission time of the packet. Since the packet size is very short for sensor applications,

M -ary modulation scheme does not offer much advantages over binary modulation schemes.

Therefore, low power high data rate binary modulators will be investigated.


101

102

103

0.6

0.7

0.8

0.9

1

1.1

1.2

1.3

1.4

1.5

Tstart(µ s)

Em

ary/E

bina

ry

M=16

M=8

M=4

PFS−B

=20mW, Pmod−B

=20mW, β=1.5 α=1.5

Figure 4-3: Effect of start-up time on the energy consumption of different type of modulationschemes.

4.2.1 Related work

Of the various binary modulation schemes, continuous phase modulation scheme has the

advantage that its modulation circuitry can be made simple with high output power ampli-

fier efficiency. For continuous phase modulated signals, there are several architectures that

can be used. The most popular method is the heterodyne architecture that is used not only

in continuous phase modulators but also in non-continuous phase modulators as well. This

architecture can achieve very high data rate since the limitations on data rate come from

the linear range of the mixers and speed of DACs. However, the main drawback is that its

complexity is high, since mixers, DAC and low pass filters require power and area, both on

and off chip.

A better suited architecture for low power FSK modulation is based on a Σ-∆ fractional-

N synthesizer [44]. The idea is that fine frequency contents of the modulation can be gen-

erated by proper dithering of the divider value with a high resolution Σ-∆ modulator. This

architecture removes majority of the modulator components in the heterodyne architecture

except the frequency synthesizer and hence consumes low power. The disadvantage is that


/N, /N+k

PFDfref

Σ−∆data

fout

Figure 4-4: Indirect modulation architecture using Σ-∆ fractional-N synthesizer.

the data rate is limited by the PLL loop bandwidth, since the PLL shows a low pass trans-

fer function from the Σ-∆. Although the loop bandwidth can be increased, this leads to

higher power dissipation at the Σ-∆ in order to maintain low quantization noise. While

this architecture is very promising for low power continuous phase modulation, reducing

the power consumption of the divider and Σ-∆ is crucial for high data rate and low power

operation.

/N, /N+k

PFDfref

Σ−∆data

Calibration

fout

Figure 4-5: High data rate modulator using pre-emphasis filter and automatic calibration.

To avoid the limitation of data rate from PLL loop bandwidth, a clever solution was

suggested by Perrott [40], by adding a transmit pre-emphasis filter to the Σ-∆ modulation

path as shown in Figure 4-5. The beauty of this technique is that the modulated data

and quantization noise each see different loop characteristics. While both the data and the

quantization noise goes through the low pass nature of the PLL, the data sees a much wider

loop bandwidth with the help from the pre-emphasis filter. Hence, high data rate can be


data

channelselect

/N, /N+k

PFDfref fout

Figure 4-6: Open loop direct VCO modulation architecture.

achieved even with a small loop bandwidth, which in turn enables low power consumption

at the Σ-∆. A potential problem of this approach is the gain mismatch between the PLL

loop and the pre-emphasis filter. If the data does not see a flat band over its spectrum, the

modulated signal will be distorted. Since the PLL loop bandwidth depends on parameters

that cannot be controlled precisely (e.g. VCO gain, charge pump current, etc), manual

calibration of the PLL loop bandwidth or the pre-emphasis filter is necessary. The solution

to this problem has been proposed by McMahill [45], by adding an automatic calibration

circuitry. The basic idea is to compare the sampled output phase to the original data and

correct the loop response by adjusting the loop gain. While the above method is very

promising for low power high data rate continuous phase modulation schemes, a minor

drawback is that the power consumption of the calibration circuitry is quite high, since the

output sample must be produced from the high frequency RF output.

Another popular method that achieves high data rate low power modulation is the open

loop direct VCO modulation architecture. The underlying idea is to open the loop after the

PLL settles to a desired frequency and directly modulate the VCO. Since the loop is open

during modulation, the PLL does not affect the modulation in any way and hence the data

rate is not limited by the PLL. Furthermore, power consumption is dramatically reduced

since the VCO is the only component that needs to be turned on during transmission. A

critical drawback of this approach however, is the instability of the VCO when the loop is

open. The charge stored in the capacitor of the VCO control input will eventually leak away

and cause the carrier frequency to drift. In addition, great care must be taken as to avoid


1

s

1

N

kvco

kmod

Icp2π L(s)

data

+

-

+

+

Pulse shapefilter

φ(t)

vmod

kmodvmod

He(s)vmod

Figure 4-7: Block digram of a closed loop direct VCO modulation architecture.

any VCO pulling when the loop is opened. Efforts to reduce these effects often lead to high

quality off-chip resonant tanks of the VCO, which loses the merit of integration [26, 46].

4.2.2 Closed loop direct VCO modulation

Closed loop direct VCO modulation [47] on the other hand is robust to these problems and

still has the advantage that the upper bound on data rate is not affected by the PLL loop

bandwidth. Since the data is modulated in closed loop, any drifts that are seen in the open

loop architecture are no longer an issue. The disadvantage is that the modulated waveform

will be distorted from the negative feedback loop of the PLL. Since the PLL acts as a

high pass filter when viewed from the VCO, low frequency components of the modulated

data will be corrupted by the PLL. In other words, long strings of zeros or ones will not

be modulated correctly. The effect of PLL on modulation accuracy can be decreased by

reducing the loop bandwidth, which is also favored for low power frequency synthesizer as

will be seen in the following chapters.

For a detailed analysis of this architecture, a linear model of the closed loop direct VCO

modulator is shown in Figure 4-7. The output modulated waveform under locked condition

can be described as


2 4 6 8 10 12 14

x 10−6

−60

−50

−40

−30

−20

−10

0

10

20

30

40

time (s)

freq

uenc

y de

viat

ion

from

car

rier(

kHz)

Effect of PLL on direct VCO modulation (BT=0.5, h=0.5, loopBW=100kHz)

Ideal Gaussian shapedClosed loop modulatedOriginal bits

Figure 4-8: Effect of closed loop PLL on direct VCO modulation.

φmod−out =(Kmod −He(ωn)

)vmod

s(4.7)

where φmod−out is the modulated output phase when the synthesizer is in lock, He(ωn)

is the error transfer function from the modulation input to the output, Kmod is the VCO

gain of the modulation input and vmod is the input signal of the pulse-shaped data. For a

second order charge pump PLL, the frequency error e(s) from the ideally modulated signal

is,

e(s) = −He(s)vmod (4.8)

= Kmodωn

2(1 + sτz)s2 + 2ζωns + ωn

2vmod

where the parameters are those defined in Appendix B. It can be seen that the error shows

a low pass characteristics with a natural frequency of ωn. Hence the error will decrease if

the loop bandwidth is reduced. Unfortunately, even for an arbitrary small loop bandwidth,


0 0.1 0.2 0.3 0.4 0.5 0.6

−1.5

−1

−0.5

0

0.5

1

1.5

GFSK @ 5Mbps ωc=100kHz, BT=0.5,h=0.5

time(µs)

freq

uenc

y de

viat

ion

from

car

rier(

MH

z)

Figure 4-9: Simulated eye diagram of a rawdata.

0 0.1 0.2 0.3 0.4 0.5 0.6

−1.5

−1

−0.5

0

0.5

1

1.5

Manchester Coded GFSK @ 5Mbps ωc=100kHz, BT=0.5, h=0.5

time(µs)

freq

uenc

y de

viat

ion

from

car

rier(

MH

z)

Figure 4-10: Simulated eye diagram of aManchester encoded data.

the error will eventually show up if the transmitted data has a sequence of zeros or ones

that is longer than the time constant of H(ωn). An example of the closed loop direct VCO

modulation is shown in Figure 4-8, which shows how the modulated data is corrupted by

the high pass nature of the PLL. The dotted line represents the original bit sequence of the

data, and the dashed line shows the pulse-shaped waveform of the data, which in this case

is a Gaussian shaped waveform with BT1 of 0.5. The solid line shows the modulated output

in closed loop, where we can see the distorted waveform of the data by the PLL, especially

on the series of ones.

Simulation Results

The effect of closed loop modulation can be better seen in an eye diagram as shown in

Figure 4-9, which shows the eye diagram of a 5Mbps GFSK data when the loop bandwidth

is 100kHz. The effect of PLL is severe as the eye opening is reduced to about 50% of the

ideal value. Closed loop modulation is more effective if the DC component of the data is

removed. This can be done through Manchester encoding, which replaces 0’s and 1’s with

transitions. The eye diagram of the Manchester encoded data is plotted in Figure 4-10,

which shows significant improvement as compared to the raw data. The drawback is that

the effective data rate is halved.

1BT is defined as filter bandwidth over data rate.


4.2.3 Modulation error and bit error rate

Modulation error from closed loop PLL

It is important to see how the modulation error of closed loop direct VCO modulation

scheme impacts the system performance. It is assumed that the base station performs

coherent demodulation since the complexity of the base station receiver is not a critical

issue.

The transmitted waveform si(t) at the output of the modulator can be expressed by the

following equation,

si(t) =

√2A

Tcos[wi − e(t)]t i ∈ 0, 1 (4.9)

where A is the transmitted energy of the bit with time duration T , wi is the frequency of the

modulated bit i, and e(t) is the error signal that results from the closed loop modulation.

Note that e(t) has memory and depends on the previous bits, thereby causing inter-symbol

interference.

Assuming white additive Gaussian noise is added to the transmitted signal, the signal

arriving at the baseband receiver, r(t), can be described as the following equation, where

Eb is the received energy2 of the bit.

r(t) = si(t) + n(t) =

√2Eb

Tcos[wi − e(t)]t+ n(t) (4.10)

The baseband receiver performs coherent demodulation as shown in Figure 4-11, where

it correlates the incoming signal to the orthonormal basis φi(t), which is defined by the

following equation.

φi(t) =√

2T

cos(wit) (4.11)

The maximum likelihood detector compares the output of the correlator and makes a

decision based on the following:

2The term energy is different from what we have discussed in the previous chapters. While Eb denotedin this section indicates the RF energy, the energy that was described previously is the energy consumptionof the entire transmitter, which includes the RF energy as well as other transceiver circuitry.


r(t)φ0(t)

Maximum

Likelihood

Decision

( ) td0

T

∫

φ1(t)

( ) td0

T

∫

T

T

Figure 4-11: Coherent demodulator of the base station receiver.

〈r(t), φ0(t)〉 < 〈r(t), φ1(t)〉 : s1 is sent (4.12)

〈r(t), φ0(t)〉 > 〈r(t), φ1(t)〉 : s0 is sent

where 〈a, b〉 represents the correlation between a and b. To calculate the BER, assume that

s0 is sent. The output of each correlator can be simplified as the following equation,

〈r(t), φ0(t)〉 =√

Eb

T

∫ T

0cos(e(t)t)dt + n0 (4.13)

= α0 + n0

〈r(t), φ1(t)〉 =√

Eb

T

∫ T

0cos(∆wt + e(t)t)dt + n1 (4.14)

= α1 + n1

where α0 and α1 are the correlator output of the receiver, ∆w is the frequency difference

between the two signals (i.e., |w1−w0|) and n0, n1 are additive white Gaussian noise. Also

note that ∆wT = π since φ0 and φ1 are orthogonal. Equations 4.13 and 4.14 cannot be

solved in closed analytical form due to the complexity of e(t). Therefore, an upper bound

on bit error rate must be calculated. Since n0, n1 are Gaussian random variables with zero

mean and variance 12No, n0 − n1 is also a Gaussian random variable with zero mean and


variance No. Therefore, the probability of error is,

Perror = Prob[〈r(t), φ0(t)〉 − 〈r(t), φ1(t)〉 < 0|s0 sent]

= Prob[n0 − n1 < α1 − α0]

< Prob[n0 − n1 < (α1 − α0)min] (4.15)

=1√

2πNo

∫ (α1−α0)min

−∞e−x2/(2No)dx

= Q(−(α1 − α0)min√

No

)(4.16)

To calculate (α1 − α0)min, the maximum value of error is denoted as emax. Assuming

the error is not excessive ( emaxT < π) and that e(t) > 0, then

α1 − α0 =√

Eb

T

∫ T

0cos(∆wt− e(t)t)− cos(e(t)t)dt

=∫ T

0−2sin

(∆wt

2

)sin

(∆wt

2− e(t)t

)dt

>

∫ T

0−2sin

(∆wt

2

)sin

(∆wt

2− emaxt

)dt

=sin(emaxT )

emaxT

emaxT

π − emaxT− 1

√Eb = −γ

√Eb (4.17)

Substituting (α1 − α0)min into Eq. 4.15, we achieve

Perror < Q(

γ

√Eb

No

)

where, γ =sin(emaxT )

emaxT

1− emaxT

π − emaxT

(4.18)

Assuming that 0 and 1 are equality likely, the overall probability of error is bounded by

Eq. 4.18. The closed loop modulation impacts the SNR by the factor γ. The term γ

depends on the data rate and the loop bandwidth of the PLL. A simulation has been done

for different data rates and loop bandwidths, and the results are shown in Figure 4-12

and 4-13. In Figure 4-12, γ is plotted against ωcT . As the loop bandwidth,ωc, gets closer

to the data rate, the degradation in SNR becomes larger. In Figure 4-13, BER is plotted


0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Symbol period * Loop bandwidth (T*ωc)

γ (S

NR

deg

rada

tion)

modulation error due to closed loop modulation

Figure 4-12: SNR degradation (γ) fromclosed loop modulation.

0 1 2 3 4 5 6 7 8 9 1010

−12

10−10

10−8

10−6

10−4

10−2

100

ωcT=0.1

ωcT=0.05

ωcT=0.02

ideal

Eb/N

o (dB)

BE

R

BER vs. Eb/N

o in closed loop modulation scheme

Figure 4-13: BER vs. Eb/No of closed loopmodulation scheme in AWGN channel.

vs. Eb/No. It can be seen that the ωcT must be kept below 0.1 in order to achieve BER

without increasing Eb/No too much. An ωcT of 0.05 results in less than 2dB degradation in

SNR. Considering the small output power that is required, this is certainly an acceptable

level of degradation.

Modulation error in Rayleigh fading

In the indoor environment, signals not only suffer from additive white Gaussian noise but

from multi-path fading as well. As mentioned in Chapter 2, the indoor channel in a sensor

network can be assumed as a slowly Rayleigh fading channel. This implies that the atten-

uation over one symbol period can be considered constant. Hence the received signal in

Eq. 4.10 can be modified as

rf (t) = αe−jφsi(t) + n(t) (4.19)

where α and φ are amplitude and phase variations of the received signal due to fading.

Assuming that the fading is slow enough such that the phase deviation φ can be estimated

without error, the receiver can still perform coherent detection. The BER in the fading

condition is simply,

Perror,fading =∫ ∞

0PerrorProb(α)dα =

∫ ∞

0Q

(αγ

√Eb

No

)Prob(α)dα (4.20)


5 10 15 20 25 3010

−4

10−3

10−2

10−1

100

ωcT=0.1

ωcT=0.05

ωcT=0.02

ideal

Eb/N

o (dB)

BE

R

BER vs. Eb/N

o in Rayleigh fading

Figure 4-14: BER of closed loop modulation in a Rayleigh fading channel.

Since the channel is a Rayleigh fading channel, the probability density function, Prob(α)

has a Rayleigh distribution. The result of the integral [48] can be expressed as,

Perror,fading =12

1−

√√√√ γ2f

2 + γ2f

(4.21)

where γ2f = γ

Eb

NoE(α2)

The resulting BER is plotted in Figure 4-14. The required Eb/No to achieve a certain

BER increases as the loop bandwidth becomes larger compared to the data rate. The

penalty in output power is small if ωcT is kept below 0.05. For a 100kHz loop bandwidth,

this relates to data rate of 2Mbps.

Modulation error from quantization noise

As will be seen later in this thesis, fractional-N synthesizer provides the advantage that the

loop bandwidth can be increased without being limited by frequency resolution and stability

issue. The increased loop bandwidth allows fast start-up which is essential to minimizing


energy consumption. In a fractional-N synthesizer, the phase error at the PFD does not

become zero even in locked condition. This results in fluctuation of the VCO control voltage

under locked condition, which shows up as quantization noise and causes modulation error.

For the second order PLL described in Section 6.1.1, the maximum fluctuation on the VCO

voltage (∆Vmax) can be expressed as 3

∆Vmax =Icp

C∆Tmax =

2πNnom

Kvcoω2

n∆Tmax =2πNnom

Kvcoω2

n

(Nmax

Nnom− 1

)Tref (4.22)

= Kquantω2n (4.23)

where in addition to other parameters already defined, Nnom and Nmax are the nominal

and maximum values of the divider. Note that the fluctuation in the control voltage in-

creases with loop bandwidth, which is consistent with the fact that more quantization error

shows up as the loop bandwidth is increased.

Carrying out a similar analysis to that shown in the previous sections, the bit error rate

from quantization error can be drawn. The resulting BER is plotted against loop bandwidth

in Figure 4-15, which shows that a loop bandwidth of less than 500kHz has little effect on

BER. It should be noted that effect of quantization noise on BER is smaller than that of

closed loop PLL.

4.2.4 Equalization at base station

From the receiver’s perspective, the modulation error induced by the closed loop modulation

can be considered as fading from a communication channel. The received signal can be

represented as

R(s) = HPLL(s)Hchannel(s)X(s) (4.24)

where HPLL(s),Hchannel are the transfer function from the PLL and channel respectively

3See Appendix B for derivation


5 10 15 20 25 3010

−4

10−3

10−2

10−1

100

ωc=1MHz

ωc=500kHz

ideal

Eb/N

o (dB)

BE

R

BER degradation from quantization noise in Rayleigh fading

Figure 4-15: BER degradation due to quantization noise in fractional-N synthesizer.

and X(s) is the transmitted data. Since HPLL(s) results from the PLL, the base station can

employ equalization and cancel out the effect of PLL as shown in Figure 4-16. Moreover,

since HPLL(s) is a deterministic function, there is no need for a training sequence and

energy efficiency is not affected.

ω

ω

Figure 4-16: Equalization of the transmitted data at the base station.

4.3 Summary

In this chapter, high data rate low power transmitter architecture was investigated. The

direct VCO modulation architecture achieves high data rate FSK modulation with minimal

overhead to the synthesizer. Basically, one CMOS varactor is the only component that is

added to the frequency synthesizer to perform FSK modulation. The modulation error from

4.3. SUMMARY 77

closed loop PLL is overcome by low loop bandwidth, Manchester encoding and equalization

at the base station. While the closed loop direct VCO modulation may not be suitable for

other applications which require precise modulation and large output power, it is certainly

applicable to sensors that require small output power.


Chapter 5

Fast Start-up Transmitter

The most critical issue in sensor communication is the start-up time of the transmitter,

which dominates energy consumption in short packet transmission. The start-up time is

usually dominated by the frequency synthesizer due to its inherent feedback loop. Other

components of the transmitter such as mixers or power amplifiers have negligible effect as

start-up time of these components are determined by their bias currents.1 In the transmitter

architecture discussed in this thesis, the effect of start-up time is even more crucial, since

frequency synthesizer dominates the transmitter’s energy consumption. Hence, fast start-up

techniques for the frequency synthesizer are investigated in this chapter.

5.1 Background

Start-up time of the frequency synthesizer is basically the lock time or the settling time2

of the synthesizer, which is inversely proportional to the loop bandwidth of the PLL. Al-

though reducing the settling time may seem trivial by increasing the loop bandwidth, there

are several obstacles that prevent the increase in loop bandwidth. First of all, the loop

bandwidth is limited by stability requirement that keeps the loop bandwidth below approx-

1Start-up time of the bias current depends on the amount of bias current. While the start-up time canbe made very small for large bias-currents, it can be large for small bias-currents, in which case the biascurrent consumes negligible power in the overall system.

2Strictly speaking, the term start-up time has the inherent notion of zero initial conditions and can bedistinguished from settling or lock time that may not have zero initial conditions. However, zero initialconditions are assumed throughout the thesis and these terms will be used interchangeably.

79

80 CHAPTER 5. FAST START-UP TRANSMITTER

imately one-tenth of the reference frequency [49]. In an integer-N synthesizer architecture

with a prescaler value of 8, the stability requirement limits the loop bandwidth to below

12.5kHz if frequency resolution of 1MHz is to be achieved. This results in settling time on

the order of milliseconds, which is unacceptable for microsensors. While the loop band-

width limitation due to stability can be improved by employing a fractional-N synthesizer,

power consumption is another factor that limits the loop bandwidth. As will be seen in

the next chapter, low loop bandwidth allows low power at Σ-∆ and divider. In addition, it

allows low power FSK modulator by closed loop direct VCO modulation. Hence, small loop

bandwidth is desirable for low power high data rate transmitter discussed in this thesis.

There have been numerous studies on fast locking PLLs for a variety of applications,

from frequency synthesizers to clock recovery circuits. The most popular approach is the

variable loop bandwidth method [49]. The main idea is to start the PLL with a wide loop

bandwidth and change it to a smaller loop bandwidth when the loop is close to being locked.

Variations of this architecture have also been published with different loop filter [50, 51]

and phase detector [52]. There are other fast settling techniques such as initial-value PLLs

and type-I PLLs. In the initial-value PLL, the desired VCO control voltage is stored in a

register so that the PLL can start near the final value. Unfortunately, this method requires

A/D and D/A in order to store the desired VCO control voltage. In a type-I PLL, phase

error does not need to be zero in lock and hence fast settling can be achieved. However, it

requires large phase acquisition range, requiring A/D and D/A in order to extend the phase

range of the PFD [53, 54]. This results in added power consumption and is not a suitable

solution for low power application. Therefore, loop switching method is used for the fast

start-up synthesizer.

5.2 Loop Switching in Fractional-N Synthesizer

5.2.1 Variable loop bandwidth technique

The basic architecture of a variable loop bandwidth method is shown in Figure 5-1. To

allow minimal disturbance on the VCO control voltage during loop switching, the resistive

component of the loop is changed by opening the resistor path. In addition, the current

5.2. LOOP SWITCHING IN FRACTIONAL-N SYNTHESIZER 81

R U

DD

ref

div

Loop switch

Ndivider

I

I

N2I

N2I RRN

C1C2

Figure 5-1: Variable loop bandwidth technique.

Frequency (rad/sec)

Pha

se (

deg)

Bode Diagrams of Variable Loop Switching

−100

−50

0

50

100

103

104

105

106

107

108

109

−180

−160

−140

−120

−100

Mag

nitu

de (

dB)

Figure 5-2: Bode plot of a PLL with variable loop switching method.

source for the large loop bandwidth mode is turned off when the charge pump is in tri-state

mode. These keeps the same charge on the loop filter capacitors throughout the bandwidth

transition and hence seamless switching is achieved. Also, the values of the current source

and the resistors are chosen such that the phase margin is kept the same in both large and

small loop bandwidth modes. The bode plot of the PLL in the two bandwidth modes are

shown in Figure 5-2, where the phase margin is kept the same in both modes of operation.


desiredaveragevalue

Loop switching occurrs

(a) Single stage loop switching (b) Dual stage loop switching

1st swtich

2nd swtich

Figure 5-3: Effect of quantization noise in loop switching.

5.2.2 Effect of quantization noise

The previous variable loop bandwidth technique has worked well in integer-N synthesizers

or clock recovery PLLs, where phase error is zero when the PLL is in lock [50, 52]. Un-

fortunately, the phase error does not become zero for a fractional-N synthesizer even in

locked condition, since the divider value is constantly changed. This non-zero phase error

results in quantization error on the VCO control voltage in locked conditions. As discussed

in Section 4.2.3, the magnitude of the quantization error is proportional to the loop band-

width. The quantization noise on the VCO control voltage can be a serious problem when

loop switching is employed, especially when there is a large difference in loop bandwidths.

Suppose the loop switches from a large bandwidth to a small bandwidth after the PLL is

locked. Since the VCO control voltage fluctuates around a desired average value, the loop

switching may occur at an instant when the control voltage is far away from the desired

value as shown in Figure 5-3 (a). In such cases, the settling time is dominated by the small

signal settling time of the small loop bandwidth and the loop switching technique does not

help the fast settling of the synthesizer. This problem can be alleviated if the loop switching

is applied in multiple stages as shown in Figure 5-3 (b). By changing the loop bandwidth

to an intermediate value, the magnitude of the quantization noise can be reduced and the

settling time in the small loop bandwidth can be reduced.

5.2.3 Multiple stage loop switching

In order to obtain the optimum number of loop switching and the values of loop components

in each stage, the behavior of the VCO control voltage in multi-stage loop switching method

5.2. LOOP SWITCHING IN FRACTIONAL-N SYNTHESIZER 83

Settling time : Ts1 Ts2 Ts3

∆V3

Loop bandwidth : ω1 ω2 ω3

Settling accuarcy : ρ1 ρ2 ρ3

: Average value of Vctrl

: Fluctuation range of Vctrl

∆V2

Final Vctrl

Figure 5-4: VCO control voltage in multi-stage variable loop bandwidth technique.

is modeled as shown in Figure 5-4. The shaded region indicates the fluctuation range of

VCO control voltage due to quantization noise. For a second order PLL with an under-

damped response, the error of the average VCO control voltage from the final value can be

approximated by the following equation,

Verror(t) = ∆V e−ζωnt (5.1)

where ∆V is the difference between the final and the initial control voltage of the VCO.

Hence, the time it takes to settle to within ρ accuracy of the final value, Vf , is

Tsi =1

ζωln

∆V

ρVf(5.2)

For the multi-stage loop switching scheme, the initial voltage difference at the beginning

of the ith stage can be described as,

∆Vi = Kquant(ω2i−1 − ω2

i ) + ρi−1Vf i ≥ 2


∆V1 = Vf i = 1 (5.3)

where Kquant is the parameter defined in Eq. 4.22, ωi−1 and ωi are the loop bandwidth

of stages i − 1 and i Hence the time it takes to settle to ρi of the final value Vf can be

expressed as

Tsi =1

ζωiln

∆Vi

ρi=

1ζωi

ln

(K(ω2

i−1 − ω2i ) + ρi−1

ρi

)

The total settling time it takes for an M step variable loop switching is

Tsettle =M∑

i=1

Tsi

In the above equation, only the loop bandwidth and settling accuracy of the final stage are

fixed parameters (ωf , ρf ) and those of previous stages are variables. In addition, the number

of loop stages (M) is also a variable. It is difficult to obtain a closed form expression for

the optimum number of stages that minimizes the settling time. Therefore, the variables

are swept across their possible values. The results are shown in Figure 5-5, where minimum

settling times are plotted against the number of variable loop stages for different initial loop

bandwidths. The graphs shows that the settling time decreases as the number of stages

increases, since each stage minimizes the effect of quantization noise. Ideally, settling time

will be minimized by maximizing the number of stages, M . However, keeping M to a

minimum is desirable from the implementation standpoint since addition of a variable loop

stage requires increased complexity in charge pump and loop filter. Keeping this in mind,

M=2 with ωi=1MHz is appropriate for the scenario when ωf=100kHz and ρf=50ppm.

More number of stages provides little improvement in settling time while adding circuit

complexity. The graph also confirms that multi-stage switching is more effective when the

difference between initial and final loop bandwidth is large. When the loop bandwidth

starts from 5MHz and jumps directly to 100kHz, the settling time is large due to the large

difference in the two loop bandwidths. However, addition of another variable loop stages

5.3. DIGITAL LOCK DETECTOR 85

wf = 100kHz, ρ

f=50ppm

Number of variable loop stages

Set

tling

Tim

e(s)

1 1.5 2 2.5 3 3.5 41

1.2

1.4

1.6

1.8

2

2.2

2.4

2.6x 10

−5

wi=500kHz

wi=1MHz

wi=5MHz

Figure 5-5: Settling time vs. number of variableloop stages.

105

106

1.3

1.35

1.4

1.45

1.5

1.55

1.6

1.65

1.7

1.75x 10

−5ω

initial = 1MHz , ω

final=100kHz

Intermediate loop bandwidth frequency(Hz)

Set

tling

Tim

e

Figure 5-6: Settling time vs. intermediate loopbandwidth in a two stage variable loop tech-nique.

immediately reduces the settling time. As the difference in two switching loop bandwidths

is small, the impact of adding variable loop stages becomes insignificant as shown in the

graph. In Figure 5-6, settling time is plotted against the intermediate loop bandwidth

for the case when M=2 with ωi=1MHz. It is seen from this graph that the settling time

can be reduced by employing two stage variable loop method, starting with 1MHz of loop

bandwidth and then to 280kHz before switching to final loop bandwidth of 100kHz.

5.3 Digital Lock Detector

In order to switch the loop bandwidth, a lock detector circuit is necessary. In a type-2

PLL system, the PLL is considered as locked if both phase difference and frequency change

over time is zero. In a fractional-N synthesizer the lock condition is different due to the

quantization error and can be defined as,

Lock:d∆Φdt

= ρ ∆Φ < ∆Φmax−lock (5.4)

where ∆Φ represents the phase difference of the reference clock and the divided out-

put of the synthesizer and ∆Φmax−lock is the maximum phase difference in a fractional-N


4 bit counter

enableupdn

fout/8

up

dn

fout/8

16 bit serial register

ref/2

. . .

lock

. . .

. . .

. . .

refdiv

lock

/14, 15 /8

fout

fout/8up

dn

LFPFD

monitor

CP Delay

second switch forvariable loop filter

Figure 5-7: Schematic of digital lock detector.

synthesizer under locked condition. In order to detect lock, the phase difference (∆Φ) is

monitored by a digital counter located at the output of the prescaler-by-8 as shown in

Figure 5-7. The counter is enabled only when the up or down signal from the PFD is

high, i.e., when there is phase difference. Basically, the counter counts the number of high

frequency prescaled-by-8 pulses during the phase difference of the reference clock and the

divided output of the synthesizer. The output of the counter will represent the quantized

value of the phase difference and it will decrease as the loop approaches lock. Since the lock

condition also requires the frequency to settle, the lock detector must monitor the phase

difference for some amount of time before it decides that the loop is in lock. That is, the

output of the counter must stay below the phase-lock threshold for some amount of time.

The amount of time that the detector has to monitor depends on the loop bandwidth of

the PLL. As discussed in previous section, the frequency error, ∆f , and phase error, ∆Φ,

can be approximated by the following equation,

∆f = e−ζωnt ∆Φ =e−ζωnt

ζω(5.5)

5.4. SUMMARY 87

where ζ is the damping factor and ωn is the natural frequency of the system. Hence,

the time that the lock detector must monitor the phase difference after the occurrence of

first zero quantized phase error is,

Twait = Tlock − Tq0 = lnρ

ζωn− ζωn ln

∆Φmax

ζωn(5.6)

where Φmax = 2πfref

fout/8(5.7)

For the case when ρ=50ppm, ζ = 1, fref=50MHz,fout=6GHz, and a 1MHz loop band-

width, Twait ∼ 200ns which corresponds about 10 cycles of a 50MHz reference clock. The

lock detector circuit is implemented using a serial shift register at the output of the counter

and OR gates. The lock detector needs to produce two signals, one for the first loop filter

stage and the other for the second loop filter stage. The first signal comes directly from the

lock detect signal while the second signal comes from the delayed version of the first lock

detect signal. The amount of delay corresponds to the loop bandwidth of the second stage.

5.4 Summary

Fast start-up techniques for a fractional-N frequency synthesizer was investigated. The vari-

able bandwidth technique provides simple form of aiding fast settling without adding much

overhead to the synthesizer. While this technique is successful for integer-N architectures,

quantization noise can be a problem for fractional-N synthesizers. To overcome this effect

of quantization noise, a multiple stage loop bandwidth technique is employed.


Chapter 6

Implementation of Energy Efficient

Transmitter

This chapter discusses the implementation details of the energy efficient transmitter. Mini-

mizing the power consumption of the frequency synthesizer is explored by exploiting trade-

offs between digital and analog component of the synthesizer. The building blocks for

continuous phase modulator and variable loop filter are also described.

6.1 Frequency Synthesizer Basics

A core component of a transceiver circuitry is the frequency synthesizer. The synthesizer

generates carrier frequencies for passband modulation schemes and often determines the

start-up time of a transmitter. Implementation of a frequency synthesizer can be categorized

into either direct synthesis or indirect synthesis.

x

Figure 6-1: Direct frequency synthesizer using frequency multipliers and dividers.

89

90 CHAPTER 6. IMPLEMENTATION OF ENERGY EFFICIENT TRANSMITTER

! "$#

%'&( )+* !-, "/.-0-1

Figure 6-2: Direct frequency synthesizer using DAC and lookup table.

A direct synthesis method uses a reference clock as the source of sine waves and does

not have an oscillator of its own. A generic direct synthesis method based on frequency

multipliers is shown in Figure 6-1. By using mixers and dividers, a rational multiple of

the reference frequency can be achieved. The advantage of this architecture for a sensor

network is that its start-up is fast, since it is determined by the settling time of the mixers.

The drawback however, is that its power consumption is high due to the mixers and that its

frequency resolution is limited. Another method of direct frequency synthesis is the direct

digital frequency synthesis (DDFS). This method implements sine waves from a digital

reference clock by using DACs and lookup tables as shown in Figure 6-2. While DDFS has

the advantage of fast settling time and high frequency resolution, the critical drawback is

that its power consumption is very high due to the high operating frequency. The DDFS

requires the reference clock frequency to be at least twice the output frequency [55] and

hence it is not practical to use DDFS at GHz frequencies due to high power consumption.

For example, DDFS at hundreds of MHz easily consumes watts of power due to the high

complexity of the digital circuitry. Hybrids of these two schemes are also possible but do

not solve the problem of high power dissipation.

While the direct synthesis method suffers from power dissipation, indirect synthesis using

a phase locked loop (PLL) is a simple approach that is agile and consumes low power. Due to

the ease of implementation in integrated circuits, it has gained great popularity in frequency

synthesizers and clock recovery circuits. A basic block digram of the PLL based frequency

synthesizer is shown in Figure 6-3. The voltage controlled oscillator (VCO) generates the

carrier frequency that is divided down to a lower frequency for phase comparison with the

reference clock. The charge pump phase frequency detector (CP-PFD) produces a phase

6.1. FREQUENCY SYNTHESIZER BASICS 91

N

fref

fout

R U

DD

CP-PFD Loop Filter

VCO

Figure 6-3: Indirect frequency synthesizer using PLL.

difference that is smoothed out by the loop filter. When the reference clock and the divided

output are phase aligned, the PLL is in lock and the VCO’s output frequency is equal to N

times the reference frequency, where N is the divider value (i.e., fout = Nfref ). The output

frequency can be changed in integer multiples of the reference frequency by changing the

divider value N and hence this architecture is called the integer-N frequency synthesizer.

6.1.1 Fractional-N synthesizer

Stability

An important aspect of a charge pump PLL is that it is a mixture of discrete and continuous

time systems. While the VCO output and its control input are continuous time signals,

charge pump PFD outputs are discrete time signals. This is due to the charge pump PFD

that essentially samples the phase difference every reference clock. Since the PLL is changed

from an s-domain to a z-domain from sampling, the issue of stability must be considered. In

order to maintain a stable system, the loop bandwidth must be kept low enough such that

the discrete time samples are averaged out to be seen as a smooth continuous time signal,

or else the feedback will force the loop out of stability. While the details of the stability

requirements can be found in Gardner’s paper [56], a general rule of thumb for stability is

that the loop bandwidth of the PLL be kept below one tenth of the reference frequency.

Since the PLL is a negative feedback system, there is another stability issue that arises

if the loop gain is -1. This can be solved by designing the loop filter such that enough phase


margin is achieved at the unity gain frequency.

Frequency resolution and lock time

In an integer-N frequency synthesizer architecture, a large loop bandwidth is desirable.

A large loop bandwidth results in a fast settling time and helps to reduce the contribu-

tion of the VCO phase noise to the output, which is often dominant in integrated circuits.

Unfortunately, the loop bandwidth cannot be increased indefinitely since it must be kept

below the reference frequency for stability reason. The reference frequency also cannot be

increased in integer-N frequency synthesizer architectures, because the frequency resolution

is determined by the reference frequency. For example, frequency resolution of 1MHz re-

quires reference frequency to be less than 1MHz. This will limit the loop bandwidth to less

than 100kHz, resulting settling times as large as 100µs. Therefore, integer-N architectures

cannot be used for systems that require both high frequency resolution and fast start-up

time.

Fractional-N synthesizer

The frequency resolution and the reference frequency can be decoupled by using fractional-

N synthesis. The idea is to dither the divider value such that on average, the divider

value is equal to the desired value. The averaging is done through the low pass loop filter.

For example, if the divider value is 100 for nine reference clock cycles and 101 for one

reference clock cycle, the average divide value over 10 cycles will be 100.1. Therefore,

frequency resolution that is independent of the reference frequency can be achieved. Hence,

the reference frequency can be increased without degrading the frequency resolution, which

implies that loop bandwidth can also be increased without being limited by stability issue,

helping to reduce the start-up time. However, there are some drawbacks of the fractional-N

synthesizer, namely the fractional spur and the quantization noise. Since the instantaneous

division value is not a fractional value but an integer value, quantization error is bound to

show up as undesired noise at the output spectrum. In addition, if any periodic contents

are found in the dithering pattern of the divider value, sideband called ‘fractional spur’

will show up at the output as well. The fractional spur can be reduced by removing the

6.2. LOW POWER VCO: ARCHITECTURAL APPROACH 93

periodic pattern of the dithering value, by employing a digital Σ-∆ modulator. The Σ-∆

modulator basically produces pseudo-random dithering patterns for the divider so that the

fractional spur is suppressed while the average value of the dithering pattern is unaffected.

In addition, Σ-∆ moves the quantization noise to a higher frequency, which is suppressed

by the PLL in closed loop.

In summary, the fraction-N synthesizer has the advantage over integer-N architecture in

that it allows higher reference frequency since frequency resolution is not limited to integer

multiples of the reference frequency. Consequently, a high loop bandwidth is realizable and

hence fast start-up time can be achieved. The challenge, however, is to reduce the quanti-

zation noise with low power consumption. In the following sections, low power techniques

for a Σ-∆ fractional-N synthesizer will be proposed from architecture and circuits.

6.2 Low Power VCO: Architectural Approach

A key component of the frequency synthesizer is the VCO. Needless to say, achieving low

phase noise, wide tuning range and low power consumption in a VCO are the key issues

in implementing an energy efficient transmitter. In this section, power consumption of the

VCO is reduced by exploiting the loop characteristics of the PLL.

The power consumption of a Σ-∆ fractional-N synthesizer is given by the following

equation, which is the summation of each component’s power consumption.

Ptotal = PV CO + PDIV + PΣ∆ + PCP + PPFD

' PV CO + PDIV + PΣ∆ (6.1)

In most cases, the power consumption is dominated by three components: VCO, divider,

and Σ-∆. When reducing the power consumption of these components, great care must be

taken in order not to increase the output noise, since power often has a direct impact on

noise. In a fractional-N synthesizer, the output noise can be represented by the following

equation,


/N,/N+k

PFDfref

Σ−∆

+

+

φΣ∆

φvco

+ φtotal

PLL

PLL

fout

Figure 6-4: Noise sources in a fractional-N frequency synthesizer.

Φtotal = fV CO(ωc)ΦV CO + fΣ∆(ωc)ΦΣ∆ + fCP−PFD(ωc)ΦCP−PFD

+fDIV (ωc)ΦDIV + fLoop(ωc)ΦLoop + fref−clk(ωc)Φref−clk

' fV CO(ωc)ΦV CO + fΣ∆(ωc)ΦΣ∆ (6.2)

where Φx is the noise of the component x and fx() is the loop transfer function seen by

the component x when the loop bandwidth of the synthesizer is ωc. The output noise is

usually dominated by the phase noise of the VCO (ΦV CO) and quantization noise (ΦΣ∆)

from the Σ-∆ modulator. In detail, ΦV CO can be described by the following equation,

ΦV CO =2FkT

PV CO

1 +

(fo

2Qf

)2

1 +f3

f

(6.3)

where PV CO is the power consumption of the VCO, Q is the quality factor of the oscillator

tank, 2FkT is the thermal noise constant, f3 is the flicker noise corner of the device and f

is the frequency of interest.

The quantization noise, ΦΣ∆, can be described by

ΦΣ∆ =(2πE)2

12fref

sin

(π

f

fref

)2(m−1)

(6.4)

where fref is the operating frequency of the Σ-∆, E is the maximum quantization error,

and m is the order of the Σ∆. In the Σ-∆, the power consumption is proportional to

6.2. LOW POWER VCO: ARCHITECTURAL APPROACH 95

its order and the reference frequency (i.e., PΣ∆ ∝ mfref ). From these equations, it can

be seen that noise is inversely related to power consumption. Therefore, any efforts in

trying to reduce power consumption of the VCO or the Σ-∆ will increase the noise of that

component. Fortunately, recall that the component noise is filtered by the PLL before it

appears at the output, as seen in Eq. 6.2 and Figure 6-4. For the VCO phase noise (ΦV CO),

PLL exhibits a high pass characteristics. Hence the contribution of ΦV CO to the output can

be reduced if the loop bandwidth(ωc) is increased. In other words, the power consumption

of the VCO (PV CO) can be reduced and yet, the same output noise can be achieved by

increasing ωc. However, for the Σ-∆, an increase in ωc will increase the noise from Σ-∆,

since the quantization noise (ΦΣ∆) goes through a low pass characteristics of the PLL. In

order to keep the same noise contribution from Σ-∆ to the output, power consumption of

the Σ-∆ (PΣ∆) must be increased in order to lower ΦΣ∆. Therefore, it can be seen that

there is a trade-off between the power consumption of the VCO and the Σ-∆, as illustrated

in Figure 6-5. A large loop bandwidth reduces the contribution of VCO phase noise to the

output while increasing the contribution of quantization noise. Consequently, VCO power

consumption can be reduced at the cost of higher Σ∆ power consumption. On the other

hand, a small loop bandwidth reduces quantization noise and increases the VCO phase noise

at the output, which leads to higher VCO power and lower Σ∆ power consumption.

+

φvco PLL

ωc

φtotal = constantPvco

+φΣ∆ PLL

ωc

PΣ∆

+ =

Figure 6-5: Effect of loop bandwidth on VCO and Σ-∆ noise.

A circuit level simulation that shows this trade-off is shown in Figure 6-6. In this

simulation, output noise level is kept constant in all conditions. It can be seen that higher


0 2 4 6 8 100

1

2

3

4

5

Loop bandwidth (MHz)

Pow

er(m

W)

PTotal

Pvco

PΣ∆

Figure 6-6: Power consumption of VCO and Σ-∆ in different loop bandwidths.

loop bandwidth reduces the power consumption of the VCO. The total power consumption

is minimized when the loop bandwidth is kept to a minimum. It should be noted that this

result is highly dependent upon process and digital technology. Considering the previous

analysis between VCO and Σ-∆ as trade-offs between analog (VCO) and digital (Σ-∆)

circuitries’ power consumption, an analog-friendly process will favor a low loop bandwidth

while a state of the art digital technology with poor analog components will favor high

loop bandwidth. In the simulation above, the Σ-∆ is implemented in a 0.25µm CMOS

technology, while the VCO’s is implemented using an inductor with a quality factor of 15.

Such a high Q inductor is a benefit of BiCMOS technology which is analog friendly, and

this results in phase noise of -113dBc at 1MHz with only 3mW of VCO power dissipation

at 5.8GHz. If a standard digital CMOS technology is used, it can be expected that the

inductor Q would be much lower and the power consumption of the VCO will increase in

a quadratic fashion to compensate for the lower Q as seen in Eq. 6.3. On the other hand,

better digital technology (i.e. shorter gate length) will reduce the power consumption of the

Σ-∆. Therefore, wide loop bandwidth will be preferred in a pure digital CMOS technology

that lacks high Q passive components.

6.3. LOW POWER DIVIDER: ARCHITECTURAL APPROACH 97

6.3 Low Power Divider: Architectural Approach

6.3.1 Divider vs. Σ-∆

In the GHz regime, the power consumption of the frequency synthesizer is often dominated

by the multi-modulus dividers, especially in the first few stages where operating frequency

is very high [40, 57]. Examples of multi-modulus divider architectures are shown in Fig. 6-

71. From the standpoint of power consumption, fixed prescalers are more desirable than a

multi-modulus divider, since multi-modulus dividers require digital logic that operate near

the carrier frequency and consume much more power. Therefore power consumption can

be reduced if fixed prescalers are used at the first few stages of the divider chain and multi-

modulus divider are moved to later stages with a lower operating frequency. The penalty,

however, is that the quantization noise from Σ-∆ will increase by 6dB each time a divide-

by-two prescaler is inserted. Moreover, the achievable frequency resolution is decreased

by a factor of two. In order to cancel out the increased quantization noise and keep the

same frequency resolution, complexity of the Σ-∆ must be increased, which results in a

larger Σ-∆ power consumption. Hence there is a trade-off between divider and Σ-∆ power

consumption. As we try to decrease the divider power consumption by inserting fixed

prescalers at high frequency stages, we lose the frequency resolution and noise property

that need to be overcome by increasing the power consumption of the Σ-∆. A circuit level

simulation which shows this trade-off has been conducted and the results are shown in

Figure 6-9. In order to keep the same output noise and frequency resolution with more

number of prescalers, complexity of the Σ-∆ is increased accordingly. It can be seen that

the total power consumption reaches minimum when a fixed prescaler of divide-by-8 is used

before a dual modulus divider. The output noise of the synthesizer is shown in Figure 6-8,

for the cases when the number of divide-by-2 are 1, 2, 3 and 4. Quantization noise increases

as the number of divide-by-two stages is increased. However, the increased phase noise is

under the target specification.

1Although other divider techniques exist such as pulse swallow architectures, cascade of divide-by-2/3stages are shown here just for conceptual illustration.


Lower divider power

Larger quantization noise

/N, /N+4, /N+8,..fo /2/2 /2,3 /2,3 ...

/N, /N+2, /N+4,..fo /2,3/2 /2,3 /2,3 ...

/N, /N+1, /N+2,..fo /2,3/2,3 /2,3 /2,3 ...

6GHz 3GHz 1.5GHz 0.75GHz

+6dB

+6dB

φΣ∆

φΣ∆

Figure 6-7: Multi-modulus divider architectures.

105

106

107

−150

−140

−130

−120

−110

−100

−90

−80

Frequency(Hz)

Out

put N

osie

(dB

c/H

z)

Second order PLL, loop BW = 100kHz, VCO noise=−110dBc/Hz @ 1MHz

Npre=1Npre=2Npre=3

Figure 6-8: Output noise of the PLL for different divider architectures.

1 2 3 40

1

2

3

4

5

Pow

er(m

W)

number of divide-by-2 prescalers

PΣ∆

Pdiv

Ptotal

Figure 6-9: Power consumption of divider and Σ-∆.

6.4. LOW POWER VCO: CIRCUIT TECHNIQUES 99

6.4 Low power VCO: Circuit Techniques

The performance of a stand-alone VCO is measured by its phase noise, power consumption

and tuning range. While low phase noise and power consumption are required for a high

performance, energy efficient communication, tuning range is necessary to switch the carrier

frequency over a wide frequency band. More importantly, tuning range is essential to

overcome process variations in fabrication. In this section, design methodologies for a low

power VCO will be viewed from the circuit perspective. In particular, the CMOS varactor

will be focused in order to achieve high Q and wide tuning range.

6.4.1 Low phase noise VCO

Over the past years, various models have been proposed to analyze the phase noise of a

VCO. A fundamental theory was proposed by Leeson [58], which relates phase noise to

signal power, quality factor (Q) of the tank, and 1/f noise, as described below.

ΦV CO =2FkT

PV CO

1 +

(fo

2Qf

)2

1 +f3

f

(6.5)

A recent linear time varying theory by Hajimiri [59] went a step further and suggested

that phase noise is related to the signal waveform. One key theory of this work was that 1/f

noise can be controlled by the waveform, and that 1/f noise is proportional to the DC value

of the impulse sensitivity function, which in most cases is similar to the time derivative of

the oscillating waveform. Hence, 1/f noise could be lowered if time integral of the waveform

is reduced. Therefore, if we are able to keep the waveform perfectly symmetric, 1/f noise

could ideally be eliminated.

Circuit topology

The circuits shown in Fig. 6-10 illustrate two types of VCO schematics. Basically, the L-C

tank generates the oscillation at a desired frequency and the transistor pair forms a negative

gm tank to account for the loss in the L-C tank. Following from the theory by Hajimiri,

the circuit in Fig. 6-10(b) achieves lower phase noise from the fact that the NMOS and


out- out+

(a) (b)

Noise from

GND

Noise from VDD

Noise fromcurrent mirror

M1 M2

M3 M4

M5 M6

M7 M8

Figure 6-10: Circuit schematic of the VCO.

PMOS pair provide a more symmetric waveform, thereby reducing 1/f noise [60]. However,

it should also be noted that this structure has advantages over the structure in (a) when

outside noise source is considered together with how it is coupled to the output. In Fig. 6-

10(b), the sources of noise other than the negative gm transistor pair are the supply, ground,

and substrate noise. The ground and supply noise are coupled through the low gain common

gate amplifier formed by M5 through M8. In Fig. 6-10(a), there are additional noise sources

from the current mirror that contribute to the output noise. This noise is coupled through

the high gain common source amplifier at M2 and results in higher phase noise than the

circuit in (b). In addition, power is wasted by the bias current in M1. This bias current

cannot be made small compared to the current in M2, since current multiplication in the

mirror will increase the output noise [61]. The circuit in (b) does not suffer from these

issues and therefore it is chosen as the VCO for the frequency synthesizer.

Resonant tank optimization

The Q of the L-C tank is important as it has a quadratic effect on phase noise as seen in

Eq. 6.5. While many L-C combinations exist at the desired frequency, it is advantageous to

use a small inductor and a large capacitor, since it is easier to implement a high Q inductor

with a small value than a large value. Given a certain value of inductor, the required

capacitor to achieve the desired resonant frequency can be calculated by the following


equation,

fo =1

2π√

LC=

1

2π√

L(Cvar + Cp)=

12π

√L(Cvar + kWLCox)

(6.6)

where fo is the desired resonant frequency, L,Cvar are the value of the inductor and

varactor and Cp is the capacitance of the −gm transistor pairs, which can be expressed by

their width and length (kWLCox). The tuning range can be maximized if Cp is minimized,

which requires the use of a minimum length devices for the transistor pair to achieve a

certain gm. However, 1/f noise is inversely proportional to WL and minimum length

device will increase the 1/f noise. In order to reduce the 1/f noise, it is advantageous to

use a long length device and sacrifice the tuning range. The implemented VCO uses NMOS

devices that are twice the minimum size device to reduce the 1/f noise.

6.4.2 VCO with modulation input

The direct VCO modulation architecture requires two control inputs for the VCO, one for

the main control from the PLL and the other for modulation. These control inputs can be

implemented using CMOS varactors as shown in Figure 6-11. In addition to the varactor

design methodologies that will be explained in the next section, there are a couple of more

things to note for the modulation varactor.

First, the tuning range should be on the same order as the data rate. If the tuning

range of the varactor is too large, then the modulation input need to be adjusted to a

small level, resulting in high susceptibility to noise. For example, if the tuning range of the

modulation varactor is 100MHz over 1V range, the voltage swing of the modulation input

need to be less than 10mV to achieve 1Mbps BFSK. This significantly reduces the SNR of

the modulation input. On the other hand, if the tuning range is too small then the desired

data rate cannot be achieved. Second, the modulation varactor must have a linear tuning

range over the modulation input. If the modulation input operates in the non-linear mode,

the spectrum will be distorted from the ideal spectrum. For example, if the voltage in the

’1’ regime has lower gain than the voltage in the ’0’ region, side-lobes of ’1’ will be smaller


Vctrl

Vmod

8u0.26u

M1 M2

M3 M4

M5

M7

M6

M8

M1,M2 : x 12

7u0.52uM3,M4 : x 12

6u0.26uM5,M6 : x 74

2u0.26uM5,M6 : x 3

W L

x Nfinger

Figure 6-11: Schematic of the 6.5GHz VCO.

in the output spectrum. Finally, the varactor must be designed for maximum Q. Since the

Q of the overall L-C tank is given by parallel connection of inductor and two varactors, the

Q of the modulation varactor must be maximized in order not to affect the original Q set

by the inductor and the high gain varactor. This can be easily achieved since the tuning

range of the modulation varactor is small.

6.4.3 CMOS varactor

Improving the quality factor of the oscillator tank has been an active area of research and

is critical to reducing phase noise and power consumption of the VCO. The effective Q of

an LC tank is given by the following equation, where QL and QC are the Q of the inductor

and capacitor respectively.

Q−1 = Q−1L + Q−1

C (6.7)

In most standard silicon processes, Q is dominated by the on chip inductors. How-

ever, recent improvements in process and design technologies, such as low resistance copper

metal [62] with circular structures [63] and substrate loss reduction techniques such as pat-

tered ground shields [64] and deep trench [62], have made it possible to achieve high inductor

Qs of 15 to 20. Furthermore, inductor Q will tend to increase with frequency since high Q

inductors are easier to achieve at higher frequencies since a smaller inductor size will have

less resistance in metal and have lower loss through substrate coupling [63]. Therefore the


"!#%$'&)(+*++,.-

/02143657/8#9#:; /<= 0>1?365 =@BA

/C<

=@DA/8#9

=FEHG=FE =FE

=C@JI=C@JI

/CK#L>M

/021

= 021

Figure 6-12: A CMOS varactor in high capacitance mode.

Q of the varactor has gained increased importance in addition to its ability to provide wide

tuning range.

Several approaches have been proposed to increase the tuning range of the varactor such

as the accumulation region varactor and gated varactor [65, 66]. These techniques provide

wide tuning range by reducing the parasitic junction capacitance in the off state of an MOS

device. However, these approaches do not follow common layout procedures, which often

leads to design rule violations in standard processes. A regular CMOS varactor on the other

hand, follows common layout procedures, offering ease of design. Moreover, recent study

shows that the tuning range of a regular CMOS varactor is comparable to that of other

sophisticated techniques [67].

In order to analyze the Q and the tuning range of a regular CMOS varactor, a detailed

model of an NMOS is shown in Fig. 6-12 and Fig. 6-13, each representing the state when

the NMOS is on and off. The MOS device is further simplified to a series of equivalent

resistance and capacitance.

Increasing the tuning range

In the on-state, the equivalent capacitance reaches maximum, which is dominated by the

gate oxide capacitance (Cox). In the off-state, the capacitance is at minimum, which is

given by the parasitic capacitances of the junction and the overlap capacitances. Therefore,

the capacitance of a multi-finger device can be described by the following equation, where

N is the number of fingers and Cox, Cov, Cj are the capacitance of the gate oxide, overlap


"!#%$'&()+*,-./0,213&(45&(

6879 :

; 6 ;

<=

%$

,> >

0

<0?A@CB

,- ,-< <= <?A@B

D>< <=

EGFHGI#FCJFELKMGNPOQOGFI KRPSHGI#FJFCIUTVRPWW

Figure 6-13: A CMOS varactor in low capacitance mode.

and junction between the diffusion and substrate, respectively.

Con = NCoxWL Coff = 2N(Cov + Cj) (6.8)

For a given required capacitance, the tuning range can be maximized by using a single

finger device. For example, if the required capacitance in the on-state is 3CoxWL, then it

can be implemented using a one-finger device or a three-finger device as shown in Fig. 6-14.

While both have same on capacitance, the single finger structure has a lower off capacitance,

due to the lower overlap capacitance.

Coff = 6Cov+6Cj Coff = 2Cov+2Cj

diffusion

poly

Con = 3Cox WLW

L

Con = 3Cox WL

3L

W

Figure 6-14: Capacitance of two varactor structures.

Increasing Q

In order to maximize Q, the equivalent resistance (Req) must be minimized. In the on-

state, Req is approximately equal to the sum of the gate and channel resistances (Req =

Rch/4+Rg). The gate resistance can be modeled as sheet resistance, and hence for a given


on capacitance (NWLCox), a long length, square shaped device lowers the gate resistance.

The channel resistance on the other hand, is inversely proportional to the gm of the device

and hence short length device will reduce the channel resistance. Therefore, there is a

trade-off between the gate and the channel resistances. While low gate resistance requires

a long length device, low channel resistance needs a short length device. The equivalent

on-resistance can be described by the following equation,

Req = Rg +Rch

4=

k1

N

W

L+

k2

N(W/L)≥ 2

N

√k1k2

equality :W

L=

√k2

k1(6.9)

where k1 and k2 represent constants from device parameters. It can be seen that the

Req can be reduced by increasing the number of fingers,N . For a given N , Req reaches

minimum when the W/L specified in the above equation is used.

In the off-state, the equivalent resistance is determined by the gate and substrate resis-

tance (Req = Rsub + Rg). This can be minimized by placing many substrate contacts close

to the varactor and increasing the number of fingers of the device.

From the above discussion, it can be seen that the on and off resistance can both be

reduced by increasing the number of fingers. Recalling that the tuning range favors fewer of

fingers, a trade-off between the quality factor and the tuning range can be seen. While more

fingers will lower the resistance and raise Q of the varactor, fewer fingers will increase the

tuning range. In many cases, the Q is a more important factor and hence a large number

of fingers should be used.


6.5 Low Power Divide-by-112/120: Circuit Techniques

6.5.1 Divide-by-8

The prescaler divide-by-8 is based on high speed divide-by-2 flip-flops as shown in Figure 6-

15. The first divide-by-2 is based on the design by Wang [68]. The internal cross-coupled

NMOS pair with PMOS loads form a latching pair while the PMOS transistors outside

form a sensing pair. An important property of this circuit topology is that the PMOS loads

have low impedance in the transparent mode (clock=low) and high during latched mode

(clock=high). RC time constant is therefore small, resulting in a very fast divider. The

next two divide-by-two stages are based on the design by Razavi [69]. This circuit has the

advantage of less input clock capacitance and larger output swing.

In order to operate these dividers at a low supply voltage of 1.6V with small input

amplitude, the input clocked transistors are biased separately from the input RF signals with

DC blocking capacitors. The blocking capacitors are implemented using MIM capacitors

and the bias is fed through a poly resistor. The values of the capacitor and the resistor are

set such that the input RF signal undergoes little attenuation. In the design, the capacitance

value is set to be 100fF, which results in about 5% attenuation of the input signal swing.

The resistor value is set large enough to be seen as a high impedance node from the input

signal and small enough as not to add significant thermal noise to the output. The thermal

noise due to the resistor goes through the PLL loop transfer function and shows up at the

output, which can be calculated using the following equation,

Φres =

∣∣∣∣∣Gopen

(1 + Gopen)

∣∣∣∣∣2

4kTR (6.10)

where Gopen is the open loop gain of the PLL. Assuming a maximum VCO gain of

500MHz/V and a loop bandwidth of 100kHz, resistors as large as 100kΩs contribute about

-145dBc of noise at 100kHz offset, which is negligible compared to the VCO phase noise.

Resistor values used in the chip are 10kΩ. Test measurement from the fabricated chip does

not show any degradation in output phase noise whether the divider is on or off, which

verifies the above analysis.

6.5. LOW POWER DIVIDE-BY-112/120: CIRCUIT TECHNIQUES 107

II

clk

clk

QQ

II

QQ

clk

clk

6.5GHz II

clk

QQ

II

QQ

clk

II

Q Q

clk

clkclk

I I

QQ

II

clk

QQ

II

QQ

clkbp

bn br

brbp

bn

bias circuitry

CLK

CLK

Figure 6-15: Circuit schematic of the divide-by-8 prescaler.

φ

φ

D Q

QDmc

mc

D Q

QD

φ φφ φ

D Q

QD

φ φ

Div 3/4

D D

mc

fin

fin

Div 14/15

Figure 6-16: Schematic of the divide-by-14/15.


6.5.2 Divide-by-14/15

The divide-by-14/15 stage is shown in Figure 6-16. It is composed of a divide-by-3/4

followed by a cascade of two divide-by-2 circuits. The divide-by-3/4 is formed using two

edge triggered flip-flops with differential control logic that divides the input by 4 when the

modulus control (mc) is high and by 3 when mc is low. The cascaded divided-by-2 forms

an asynchronous divide-by-4 circuit. The different skew path seen in the control logic of

divide-by-3/4 (nand vs nor gates) does not affect the performance of the divider, since it

is based on a synchronous positive edge triggered flip-flop. By employing a positive edge

triggered flip-flop in the asynchronous circuit, critical path has three clock cycles to work

with rather than one clock cycle seen in a negative edge triggered flip-flop. All the signal

paths are differential to increase power and ground noise rejection.

6.6 Σ-∆

The Σ-∆ is based on a single loop architecture. Although the MASH architecture offers

several advantages that are favored in many Σ-∆ modulators, single loop architecture is

better suited for the frequency synthesizer shown in this chapter for the following reasons.

First of all, the single loop architecture produces less quantization noise than the MASH.

While an Mth order MASH produces an M bit output, an Mth order single loop Σ-

∆ provides a single bit output. Hence the quantization error for a MASH lies between

[0, 2M − 1] while that of a single loop lies between [0, 1]. Therefore, lower quantization

noise is produced from a single loop architecture. Second, the larger output bit width of a

MASH requires more complex divider and phase detector. Due to the larger division range,

a MASH needs a multi-modulus divider instead of a dual modulus divider. In addition,

the phase detector must have larger linear range than a single loop architecture, since the

instantaneous phase error is larger. With the prescaler value of 8 used in the frequency

synthesizer, the quantization error and phase error of the MASH becomes even larger,

as shown in Fig. 6-17. Finally, as will be seen in the Chapter 5, the large phase difference

produced by MASH is not well suited for variable loop bandwidth techniques. While MASH

presents some merits such as unconditional stability and easily pipelined architecture, the

6.7. PHASE FREQUENCY DETECTOR AND CHARGE PUMP 109

above reasons make the single loop architecture a more suitable choice.

"!$#&%'

...

Qerror

Qerror

Divide Value

Divide Value

Figure 6-17: Quantization error and divider range of single loop Σ-∆ and MASH.

The single loop architecture used in the design is shown in Figure 6-18. The designed

MASH only requires three adders since the first adder always adds of ±29, which can be

implemented using inverters.

Figure 6-18: Architecture of the single loop Σ-∆.

6.7 Phase Frequency Detector and Charge Pump

The PFD is based on a popular flip-flop structure used in many PLLs [50, 52]. The dead

zone is avoided by allowing enough delay through the OR gate so that current flows through

the charge pump even for small phase differences. The charge pump is based on a current


steering switch [70] as shown in Figure 6-20. The inherent mismatch between PMOS and

NMOS is avoided by using NMOS only switches. An important thing to avoid in this

charge pump is the reverse current flow that result from finite output resistance of the

current source. As the output voltage varies, the current from M6 and M8 will change from

its ideal value due to the channel length modulation effect and therefore current mismatch

will occur. While some mismatches are acceptable as long as the output current increases

monotonically with of phase difference, it becomes a serious problem if the output current

reverses its direction. That is, even if the UP signal is asserted high for a longer duration

than the DN signal, the output voltage may be high enough to cause smaller current from

M8 than the current from M6. Hence charge on the loop filter is taken away when it

should be added. Although this problem is often solved by increasing the output resistance

with cascoded transistors at the output, it cannot be applied when the supply voltage is

low. Therefore, long channel devices are used in order to increase the output resistance.

Moreover, it is important to not oversize the tail current source M1 and M2, since large

sized devices will increase the gm of these devices, which will increase the effect of channel

length modulation.

Figure 6-19: Circuit schematic of the phase frequency detector.

6.7.1 Charge pump for variable loop filter

The schematic of the charge pump used in the variable loop bandwidth modes are shown in

Figure 6-21. The charge pumps for both large and intermediate loop values have the same

schematic and their only difference is the size of the transistors. In order to save power

6.8. LOOP FILTER 111

2u0.24uM1,M2 : x 2

2u0.24uM3~M6 : x 1

2u0.24uM7,M8 : x 2

2u0.24uM9 : x 2

Figure 6-20: Circuit schematic of the charge pump.

consumption in the final loop bandwidth mode, all the current paths are shut down by the

switch SHDN .

6.8 Loop Filter

The loop filters are implemented off chip as shown in Figure 6-22. The switches in the

resistor paths are implemented using NMOS devices. The parasitic capacitances of the

chip package and the PCB board form very high frequency poles and does not affect the

PLL performance. The low pass filter of R3 and C3 aids the suppression of the reference

frequency leakage to the output spectrum.

6.9 Energy Efficient BFSK Modulator

The block diagram of the energy efficient BFSK modulator is shown in Figure 6-23. The

Σ-∆ provides 1MHz of frequency resolution with a reference frequency of 55MHz. The

high reference frequency allows large loop bandwidth in the initial stage of the variable

loop bandwidth method. The power consumption of the divider is dramatically reduced by

using a low power prescaler divider-by-8. The BFSK modulation is achieved by directly

modulating the VCO.


Figure 6-21: Charge pump of the variable loop frequency synthesizer.

6.10 Summary

Design methodologies for low power frequency synthesizer were investigated. The high

frequency VCO and the digital Σ-∆ modulator has opposite effect on each other’s power

consumption in conjunction with the loop bandwidth. While large loop bandwidth reduces

the power consumption of the VCO, it increases the power consumption of the Σ-∆. In

that regards, the loop bandwidth can be considered as a measure of process technology

on whether it is analog-friendly or digital-friendly. The Σ-∆ modulator also reduces the

power consumption of the dual-modulus divider by allowing more prescaler stages at high

frequency. On the circuit side, the trade-off is also seen between the tuning range and the

phase noise of the VCO.

6.10. SUMMARY 113

! "

#!" #!" "

$

#!$

&% '( ' ')

Figure 6-22: Loop filter of the frequency synthesizer.

R U

DD

ref

lock detect

/14, 15

Σ∆channelselect

Prescaler /8

fout

I0

I1

I2

s

s

off-chip

C2 C3

R3

C1

R2

clk

Figure 6-23: Variable loop bandwidth frequency synthesizer.


Chapter 7

Prototype Test Results

The design methodologies discussed in the previous chapters are applied to a prototype chip

fabricated in IBM’s 0.25µm SiGe BiCMOS technology. The implemented chip uses only the

CMOS part of the technology to test the capability of CMOS at high frequencies.

7.1 Frequency Synthesizer

7.1.1 VCO

Two VCOs have been fabricated for the RF transmitter. The first is a stand-alone VCO

fabricated in IBM’s 0.35µm BiCMOS technology and the second one is a VCO that is

integrated together with the frequency synthesizer using 0.25µm BiCMOS technology. The

first stand-alone VCO achieves 15% tuning range around the center frequency of 5.3GHz and

the phase noise is -120dBc/Hz at 1MHz offset from the 5.7GHz, while consuming 24mW

from a 3V power supply. The 1/f noise corner is around 500kHz and the phase noise

variation over the tuning range is less than 3dB. The measured phase noise plot, die photo

and the summary of chip test results are shown in Figure 7-1, 7-2 and Table 7.1, respectively.

The VCO also operates at 1.8V with 2.7mA, in which case the phase noise increases to -

104.1dBc/Hz @ 1MHz. This value of phase noise is very close to the theoretical value when

we account for the reduction in VCO’s power consumption from 28mW to 4.8mW, which

causes 15dB increase in phase noise from Leeson’s equation. The measured tuning range

at 1.8V is 14.6%. The tuning range is not effected much by the reduction of power supply

115

116 CHAPTER 7. PROTOTYPE TEST RESULTS

Figure 7-1: Measured phase noise at 5.68GHz.

Figure 7-2: Die photo of the 5.3GHz VCO.

Frequency 4.89 ∼ 5.72GHz (15.6%)Power 8mA from 3V

Phase Noise -120dBc @ 1MHzArea 0.49mm2

Table 7.1: Summary of VCO test results.

7.1. FREQUENCY SYNTHESIZER 117

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 26100

6200

6300

6400

6500

6600

6700

6800

6900VCO tuning range vs. control voltage

Control Voltage(V)

Fre

quen

cy(G

Hz)

Figure 7-3: Tuning characteristic of the VCO onmain control input.

0 0.2 0.4 0.6 0.8 1 1.2 1.46.182

6.183

6.184

6.185

6.186

6.187

6.188

6.189

6.19

6.191

6.192VCO tuning range vs. modulation input

Modulation input voltage(V)

Fre

quen

cy(G

Hz)

Figure 7-4: Tuning characteristic of the VCO onmodulation input.

voltage, since the varactor can still change from on to off state.

The second VCO’s center frequency is at 6.5GHz and the tuning range is 12%(6.1GHz

∼ 6.9GHz) as shown in Figure 7-3. The tuning curve shows linear characteristic when the

control voltages is near 1V. This is where the MOS varactor is in the linear region, changing

its state from an inverted mode to a depletion mode. As the control voltage reaches closer

to the supply voltage or the ground, the varactor enters completely on or off state and

the voltage gain is reduced. The tuning characteristics of the low gain varactor for the

modulation input is shown in Figure 7-4. It has similar curve as the large gain varactor,

except that its turning range is 8MHz. Ideally, this tuning range determines the maximum

data rate in a closed loop direct VCO modulation. However, in practice, the maximum

achievable data rate is smaller than the tuning range, due to the non-linearity of the tuning

curve. When the measured tuning curve is compared to the dashed line that represents the

ideal linear tuning curve, the graph is linear for 3.5MHz, which corresponds to 7Mbps of

BFSK data with a modulation index of 0.5.

The phase noise of the VCO is plotted in Figure 7-5, which shows -112dBc/Hz of noise at

1MHz offset from the center frequency, while consuming 7.7mA from a 2.3V power supply.

The 1/f noise is approximately 120kHz, which is significantly lower than a single NFET’s

1/f corner of couple of MHz. The phase noise over the tuning range is plotted in Figure 7-6.

It shows measured phase noise and the ideal phase noise with constant tank Q. The ideal


Figure 7-5: Phase noise plot of the VCO.

6 6.2 6.4 6.6 6.8 7−112.5

−112

−111.5

−111

−110.5

−110

−109.5VCO phase noise vs frequency, @ 1MHz from the center

Frequency (GHz)

Pha

se N

oise

(dB

c/H

z)

constant tank Q

measured

Figure 7-6: Phase noise at different frequencies.

phase noise assumes that the the Q of the tank is constant throughout the tuning range

with the value at 6.1GHz and extrapolates phase noise at different frequencies from Eq. 6.5.

The measured phase noise increases with operating frequency more than the ideal value.

The difference between the two phase noise reaches maximum of 1.5dB when the operating

frequency is maximum. This is due to the degradation of Q of the L-C tank. While the

Q degradation can be caused by both the varactor and inductor, it is more likely that it is

because of the inductor. The varactor Q of the off-state is determined by the substrate and

the gate resistance as discussed in Section 6.4.3 and this is often smaller than the Q in the

on-state. For the inductor, the Q peaks at only a particular frequency and rolls off at other

frequencies. From the measured plot, it can be estimated that the frequency at which the

inductor Q reaches maximum is below 6GHz.

While the results of 5GHz VCO is satisfactory, the performance of 6GHz is disappoint-

ing given that it uses better technology. The original target specification of the second

VCO was 5.8GHz of center frequency with -112dBc/Hz and 4.2mW of power consumption.

Unfortunately the target frequency and the power consumption was not met. The reason

for the poor VCO performance can be considered from the miscalculations of the resonant

tank. While slow process corners can explain the high power consumption, it does not jus-

tify the higher center frequency. If the resonant frequency of the L-C tank is miscalculated

(i.e., parasitic capacitance extraction), then it not only changes the VCO’s center frequency

but also impacts the power consumption as well. This is due to the frequency dependent

7.1. FREQUENCY SYNTHESIZER 119

characteristics of the inductor, of which the Q peaks at a certain (in this case 5.8GHz)

frequency. As seen in Eq. 6.5, Q of the tank has a quadratic impact on power consumption

and hence the mismatched frequency of the tank results in poor performance.

As to fairly compare the result of these VCOs to other VCOs that have been published,

we employ figure of merit (FOM) defined as the following equation [71],

FOM = L(foffset)− 20log(fosc

foffset) + 10log(

Pvco

1mW) (7.1)

where L(foffset) is the phase noise at foffset from the VCO frequency of fosc and Pvco is

the power consumption of the VCO. The figure of merit of recently published LC oscillators

around 5GHz are shown in Table 7.2 and plotted in Figure 7-7.

7.1.2 Fractional-N frequency synthesizer

The frequency synthesizer is a 4th order PLL with Σ-∆ for fractional channel selection of the

reference frequency. The frequency synthesizer is able to change its frequency in about 1MHz

steps with a 55MHz reference clock as shown in Figure 7-8 and 7-9. With the prescaler

value of 8 and a 10-bit Σ-∆ , an exact resolution of (55·8)210 MHz was not achieved due to the

non-linearities from the phase frequency detector and the charge pump. The resolution can

be easily increased by adding more bits to the accumulator of the Σ-∆ modulator. The

estimated increase in power consumption with additional 5 bits in the Σ-∆ modulator is

about 1mW. The total power consumption of the synthesizer is 22mW, where VCO draws

7.7mA of current from 2.3V power supply, while the rest of the synthesizer draws 2.7mA

from 1.6V. The detailed profile of synthesizer’s power consumption is shown in Figure 7-10.

The divide-by-112/120 consumes 3.2mW with the input RF range of 6GHz to 6.9GHz. The

performance of this divider can be compared to other dividers by power efficiency, which

is defined as the ratio of divider’s maximum operating frequency to its power consumption

expressed in GHz/mW . The dual modulus divider achieves 2.15GHz/mW, which is the

most power efficient dual-modulus divider yet reported above 5GHz. In the divider, about

2mW of power is consumed in the prescaler-by-8. Hence it can be seen that the high

frequency components of the synthesizer accounts to more than 90% of the total power


Reference freq power process phase noise tuning FOMPlou99 [71] 6GHz 22mW Bipolar -116@1MHz 15% -178.1 @ 1MHzKing98 [72] 4.7GHz 10.8mW .35 µm CMOS -110@1MHz 4.3% -173.1 @ 1MHzLiu99 [73] 6.3GHz 18mW .35µm CMOS -98.4@1MHz 16.8% -161.8 @ 1MHzNik99 [63] 4.4GHz 12mW Bipolar -100@100kHz 6% -180.5 @ 100kHz

Hung00 [74] 5.2GHz 7mW .25µm CMOS -117@1MHz 7% -183.3@1MHzSamori01 [75] 4.6GHz 13.8mW .25µm CMOS -114@1MHz 18% -175.8@1MHzHitko02 [61] 5.8GHz 6mW CMOS -107@1MHz 11% -174.5@ 1MHz5GHz VCO 5.3GHz 24mW .35µm CMOS -120.1@1MHz 15.6% -181.3 @ 1MHz6GHz VCO 6.5GHz 17.7mW .25µm CMOS -112@1MHz 12% -175.2 @ 1MHz

Table 7.2: Figure of merit of different VCOs.

4 4.5 5 5.5 6 6.5 7−185

−180

−175

−170

−165

−160Figure of merit of different VCOs

Frequency (GHz)

Fig

ure

of M

erit

Plou99

King98

Liu99

Nik99

Hung00

Samori01

Hitko02

VCO−1

VCO−2

Figure 7-7: Figure of merit for different VCOs.

7.2. BFSK MODULATOR 121

consumption. The PFD, charge pump and the lock detector consumes 400µW. The reference

spur is approximately 40dB below carrier.

Figure 7-8: Output spectrum of the fractional-Nsynthesizer at 6.3800GHz.

Figure 7-9: Output spectrum of the fractional-Nsynthesizer at 6.3813GHz.

VCO:17.7mW(80%)

Σ∆:0.9mW(4%)

Divider:3.2mW(14%)

Mscl:0.4mW(2%)

Figure 7-10: Power consumption of different components in the modulator.

7.2 BFSK Modulator

The modulation performance of the closed loop direct VCO modulator is shown in Figure 7-

12 and Figure 7-12, where eye diagram of raw and Manchester encoded data is plotted for


Figure 7-11: Eye diagram of 5Mbps Manchesterencoded data with 100kHz PLL loop bandwidth(h = 0.3).

Figure 7-12: Eye diagram of 5Mbps raw datawith 100kHz PLL loop bandwidth (h = 0.3).

synthesizer loop bandwidth of 100kHz. The eye is measured at the output of the prescaler-

by-8 using HP89440A vector signal analyzer. Hence the output modulated frequency is

scaled by 1/8. The data rate is 5Mbps and the modulation index is 0.3. The graphs are

very much similar to the simulation result shown in Chapter 4 and it is verified that the

Manchester encoded data indeed achieves higher modulation accuracy by removing the DC

component of the data. For the raw data, the modulated signal is severely corrupted by

the closed loop PLL and the eye opening is very small.

The eye diagram and the spectrum of 5Mbps Manchester encoded data for modulation

index of 0.5 is plotted in Figure 7-13 and Figure 7-14, respectively. The peak that occurs

every 2.5MHz in the output spectrum is from Manchester encoding.

7.3 Variable Loop Bandwidth Technique

The start-up time of the frequency synthesizer is shown in Figure 7-15 and 7-16 for fixed

and variable loop methods, respectively. While the start-up time of the fixed loop achieves

approximately 70µs, the variable loop method achieves 20µ start-up time with the help of

multi-stage variable loop method, where the bandwidth is switched from 1MHz to 250kHz

before it is changed to final loop bandwidth of 100kHz.

7.4. SUMMARY 123

Figure 7-13: Eye diagram of the 5Mbps Manch-ester encoded data (h = 0.5).

Figure 7-14: Spectrum of the 5Mbps Manchestercoded data.

7.4 Summary

Test results of the prototype chip has been shown. To compare energy efficiencies of different

radios in sensor applications, we define Energy per bit as the energy it takes to transmit

a bit when sending a packet, which includes the start-up energy of the transmitter. The

comparison is shown in Figure 7-17, where energy efficiencies of low power high data rate

radios are plotted versus packet size. It is be seen that reducing the start-up time is crucial

in energy efficiency for short packet transmission. The die photo and the PCB test setup

of the chip are shown in Figure 7-18 and Figure 7-19, respectively.


Figure 7-15: Start-up transient of frequency syn-thesizer with fixed loop bandwidth.

Figure 7-16: Start-up transient of frequency syn-thesizer with variable loop bandwidth.

102

103

104

105

10−8

10−7

10−6

Packet size (bits)

Ene

rgy

per

bit (

J)

Energy efficiencies of different modulators

This work, 6.5GHz, 2.5Mbps

[40], 1.8GHz, 2.5Mbps[42], 2.4GHz, 1Mbps

[70], 2.4GHz, 2Mbps

[26], 2.4GHz, 2Mbps

Figure 7-17: Energy efficiency comparison of different high data rate modulators.

7.4. SUMMARY 125

VCO

Prescaler

Div 14/15

Σ∆

CPPFD

programlock detect

Figure 7-18: Die photo of the 6.5GHz modulator chip.

Figure 7-19: PCB test setup of chip.


Chapter 8

Conclusion

8.1 Conclusion

Energy reduction techniques have been investigated for a wireless microsensor network.

Two aspects of system hierarchy, communication protocol and RF transmitter, were studied

based on multiple levels of system abstraction.

In the communication protocol design, the key aspect of this research is that protocols

are explored with the underlying physical layer electronics in mind. Rather than treating

the radio of the sensor node as ideal hardware, a model is derived that takes into account

the non-ideal characteristics of the radio. The non-ideal behavior of the physical layer

electronics plays a crucial role in the design of energy efficient microsensor network. The

most critical parameter is the start-up time, which dominates the energy consumption

for a short packet transmission. The frequency errors in the reference oscillators are also

important as they cause time synchronization of the network, resulting in increased receiver

activity. Understanding these behaviors of the radio helps to minimize the network’s energy

consumption at multiple levels of system abstraction.

The energy consumption of the network is further minimized by employing a hybrid

TDM-FDM protocol that trades-off energy consumption of the transmitter and the re-

ceiver. The TDMA approach exploits the fact that energy consumption of the transmitter

is dominated by the frequency synthesizer rather than the modulation circuitry and hence

transmits the data at maximum rate. However, this results in time synchronization of the

127

128 CHAPTER 8. CONCLUSION

network that requires receiver activity. The FDMA approach maximizes the number of

frequency channels so that the guard time can be maximized, thereby reducing the receiver

energy consumption. The available bandwidth has a different impact on energy consump-

tion from the traditional perspective of Eb/No, in the sense that large available bandwidth

allows less time synchronization and hence lower energy consumption in the receiver. This

is exploited in utilizing the bandwidth of the sensor network that has wide variation in the

sensor distribution. By employing time-frequency slot allocation, bandwidth is used more

effectively and energy consumption of the network is reduced.

The choice of modulation scheme depends heavily on the start-up time. Multi-level

modulation is more energy efficient than a binary modulation only if the start-up time of

the radio is small compared to the data transmission time. In addition, complexity of the

modulation circuitry for multi-level modulation must be minimized in order to achieve lower

energy than a binary modulation scheme.

In the second part of the thesis, design methodologies for a low power, high data rate

and fast start-up transmitter were explored. The key to achieving low energy consumption

is finding and optimizing the various design trade-offs that exist in the system.

To achieve a high data rate transmitter, the VCO is directly modulated in closed loop

PLL. This architecture provides the simplest form of modulation circuitry to perform BFSK

on the frequency synthesizer and hence achieves low power. The modulation error of the

closed loop PLL can be overcome by low loop bandwidth, Manchester encoding and equal-

ization at the base station.

Fast start-up time is obtained by a employing variable loop bandwidth technique. The

PLL changes its bandwidth as the loop approaches lock and hence fast start-up time is

achieved. To overcome the effect of quantization noise on loop switching, a two-stage

variable loop bandwidth method is used.

In the low power frequency synthesizer, trade-offs between analog and digital compo-

nents are exploited. The high frequency VCO and the digital Σ-∆ modulator have opposite

effect on each others’ power consumption in conjunction with the loop bandwidth. While

large loop bandwidth reduces the power consumption of the VCO, it increases the power

consumption of the Σ-∆. In that regard, the loop bandwidth can be considered as a measure

8.2. CRITIQUE AND FUTURE WORKS 129

of whether the process technology is analog-friendly or digital-friendly. The Σ-∆ modulator

also reduces the power consumption of the dual-modulus divider by allowing more prescaler

stages at high frequency. On the circuit side, the trade-off between the tuning range and

the phase noise of the VCO was seen.

8.2 Critique and Future Works

While this thesis presents energy efficient design methodologies for both communication

protocols and transmitter for a microsensor node, there is still room for improvements.

Although the radio model includes the start-up time as a critical design parameter, it

does not incorporate some of the other parameters that impact power consumption. These

include phase noise of the VCO, efficiencies of the power amplifier and accuracy of the

modulator. Incorporating these into design will result in a more accurate optimization of

the system.

The MAC protocol developed in the thesis is primarily aimed at a coordinated static

sensor network. However, many of the sensor applications require ad-hoc autonomous and

sometimes even a mobile network. The extension of low power MAC to mobile ad-hoc

network presents an interesting challenge as the network becomes more complicated. MAC

for multi-hop routing network is another area in which the MAC can have a significant

impact on the higher level protocol.

In the transmitter, high data rate is achieved through closed loop direct VCO modula-

tion. The critical drawback is the modulation error from the closed loop PLL. Although

the error can be reduced by Manchester coding, this increases the bandwidth by a factor of

two. While this is acceptable for a low data rate sensor network, it may not be acceptable

for other applications. Therefore, ways to increase the modulation accuracy of the closed

loop direct VCO modulation must be found, in order for this architecture to be successful

in other applications. Calibration through digital Σ-∆ modulator or a dual PLL loop are

some of the methods that could reduce the modulation error.

The fundamental limit in achieving a low power frequency synthesizer is noise. While

fractional-N synthesizer helps to reduce the power consumption of the PLL, it introduces

130 CHAPTER 8. CONCLUSION

quantization noise. Therefore, implementation of fractional-N synthesizer architecture that

is free of quantization noise will greatly reduce the power consumption.

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tions,” in ISSCC Digest of Technical Papers, 1998, pp. 226–227.

[73] T.P. Liu, “A 6.5GHz monolithic CMOS voltage-controlled oscillator,” in ISSCC Digest

of Technical Papers, 1999, pp. 404–405.

[74] C.M. Hung et al., “A fully integrated 5.35GHz CMOS VCO and a prescaler,” in

Proceedings of RFIC Symposium, 2000, pp. 69–72.

[75] C. Samori et al., “A -94dBc/Hz @100kHz, fully integrated, 5GHz CMOS VCO with

18% tuning range for Bluetooth applications,” in Proceedings of IEEE Custom Inte-

grated Circuits Conference, 2000, pp. 201–204.

138 BIBLIOGRAPHY

Appendix A

Prototype Chip Testing

A.1 Chip Description

The chip is packaged in a 32 micro-lead frame by Amkor Inc. The micro-lead frame has

pins underneath the package, which minimizes the bond wire inductance and capacitance.

The pin designations of the packaged chip are shown in Figure A-1 and its description is

shown in Table A.1.

01

04

02

03

07

05

06

08

09 10 11 12 13 14 15 16

32 31 30 29 28 27 26 25

21

23

22

18

20

19

17

24

Figure A-1: Pin out of the packaged chip.

139

140 APPENDIX A. PROTOTYPE CHIP TESTING

Pin No. Pin Name I/O Description1 GND - Ground2 VCO- O 6.4GHz RF Output, open drain terminal.3 GND - Ground4 Vctrl I Control Voltage of the VCO.5 R1 I/O Resistor connection of the high gain loop filter.6 R2 I/O Resistor connection of the medium gain loop filter.7 Loop Out I/O Charge pump output. For connection to a loop filter.8 Ismall I Current source input of the small charge pump.9 GND - Ground10 Imedium I Current source input of the medium charge pump.11 Ibig I Current source input of the large charge pump.12 Ref Clk I Reference clock input for the PLL. High impedance CMOS input.13 LE I Load Enable signal for the parallel register. High impedance CMOS

input.14 Data Clk I Clock for the serial register programming. High impedance CMOS

input.15 Data I Data input for the program registers. High impedance CMOS in-

put.16 GND - Ground17 VΣ-∆ I Power supply for the Σ-∆ .18 Lock O Lock monitor detector output. Active low.19 Σ-∆ out O Output of the Σ-∆ .20 Σ-∆ in I Σ-∆ input for external control of division values. High impedance

CMOS input.21 Div8 Out O Output of the prescaled oscillator. 800MHz RF output with non-

zero DC.22 GND - Ground23 VCO+ O 6.4GHz RF output with non-zero DC.24 N/C - No Connection25 GND - Ground26 Vdiv I Power supply for the dual-modulus divider.27 Mod In I Modulation input of the VCO.28 Vvco I Power supply for the VCO.29 Vbuf I Power supply for the output buffers.30 Ibias I Current source to set up bias for the prescaler.31 Vmscl I Power supply for the charge pump, PFD and variable loop band-

width control unit.32 N/C - No Connection

Table A.1: Pin descriptions of the packaged chip.

A.2. SERIAL REGISTER PROGRAM 141

A.2 Serial Register Program

A.2.1 Program timing

To reduce the number of pins, the 12 bit data needed for Σ-∆ and program register are

fed serially. The serial register and a parallel latch requires three signals (Data,Data Clk

and Load Enable) to load the data. The required timing for these signals are shown in

Figure A-2. Each signal drives a CMOS buffer on chip. Registers can be programmed using

the PLL CodeLoader from National Semiconductor Corp.

MSB LSB

! "# %$ "&')(*,+ "-./

0!# " # 1/2 $

3 45

/

6)Σ∆

87!+!9: 2 $

Figure A-2: Timing diagram of the register value programming.


Control Bit Name Control value descriptionF15 - No connection.F14 Lock Select ’1’ enables lock detect for a window of 10 reference cycles. and ’0’

enables lock detect for a window of 30 reference cycles.F13 Return ’0’ returns to high bandwidth mode if the PLL loses lock and ’1’

remains in the low bandwidth mode even after the PLL loses lock(works together with variable loop bandwidth).

F12 Stage ’0’ enable single stage loop switching and ’1’ enables dual stageloop switching.

F11 Variable loop en-able

’1’ enables variable loop bandwidth technique and ’0’ disables vari-able loop bandwidth.

F10 Σ-∆ select ’0’ enables built-in Σ-∆ and ’1’ enables off-chip control of dividervalue

F9 Σ∆9 Bit 9 of Σ-∆ (MSB)F8 Σ∆8 Bit 8 of Σ-∆F7 Σ∆7 Bit 7 of Σ-∆F6 Σ∆6 Bit 6 of Σ-∆F5 Σ∆5 Bit 5 of Σ-∆F4 Σ∆4 Bit 4 of Σ-∆F3 Σ∆3 Bit 3 of Σ-∆F2 Σ∆2 Bit 2 of Σ-∆F1 Σ∆1 Bit 1 of Σ-∆F0 Σ∆0 Bit 0 of Σ-∆ (LSB)

Table A.2: Description of function register.

A.2.2 Register value description

The 16 bit registers perform the functions described in Table A.2. These functions enable

testability of the chip in various modes. F15 is the first bit that goes into the register.

A.3 Test Board Design

The test board is implemented using a FR-4 material. The schematics of the board are

shown in Figure A-3. The thick line represents 50 Ω matched impedance.

A.3. TEST BOARD DESIGN 143

LT17

62

inou

t

adj

gnd

Low

noi

se V

olta

ge R

egul

ator

R1

R2

LM

334

Ra

dj

I BI M

I S

Dat

a

Dat

a C

lk

LE

Ref

OSC

(55

MH

z) f

rom

HP8

656B

Σ∆ in

Loc

kΣ∆

out

Div

/8 o

ut

VC

O+

out

VC

O-

out

Inpu

t Dat

a

Var

iabl

e C

urre

t Sou

rce

50oh

m m

atch

ed im

pede

nce

AL

VC

125

(TI)(f

rom

TE

K H

FS 9

003)

Figure A-3: Test board schematic.


Appendix B

PLL model

B.1 Noise properties of 2nd order PLL

Noise properties of the PLL is important since it is directly affected by power consumption.

The PLL can be represented in a linear model as shown in Figure B-1. The linearized

model helps to understand the properties of the PLL that will later be used to improve

the performance of the transmitter. From the VCO side, the PLL will act as a a high pass

filter. Intuitively, this can be seen since the negative feedback will only affect the signal that

are slow enough for the loop the respond. The high frequency components will show up at

the output without being affected by the loop since the feedback loop is not fast enough to

affect the fast signals. For a typical second order charge pump PLL shown in Figure B-1,

the transfer function from VCO noise to the output phase can be represented as

φout

nvco=

11 + Gopen

=s2

s2 + 2ζωns + ω2n

(B.1)

where, for a second order charge pump PLL shown in Figure 6-3

ωn =

√KvcoIch

2πCNζ =

R

2

√KvcoIchC

2πN(B.2)

145

146 APPENDIX B. PLL MODEL

+

-

GLF(S)

1/N

φs

φoutφrefφe Kvco

s

Ich

2π

nvco

Figure B-1: Linearized model of the PLL.

For any input that lies outside of the loop filter, the PLL presents a low pass characteristic.

This is readily seen since the loop filter (which is a low pass filter in nature) suppresses

any high frequency component. The transfer function from reference to the output can be

represented as

φout

φref=

Gopen/N

1 + Gopen

=1N

[ω2

n(1 + sτz)s2 + 2ζωns + ω2

n

](B.3)

where τz is the zero location of the loop transfer function, which is RC.

From the above discussions, we see that it is helpful to increase the loop bandwidth when

VCO is the dominant source of noise and vice versa when noise from other components are

dominant.

B.2 Maximum Quantization Noise on VCO Control Voltage

The maximum fluctuation on the VCO control voltage due to modulus change in the divider

of a fractional-N synthesizer can be described as the following. The maximum change in

the VCO control voltage occurs when the phase difference between the reference and the

divided output frequency is maximum. For a second order PLL described in the previous

section, the maximum voltage change on the VCO control voltage, ∆Vmax, can be expressed

B.2. MAXIMUM QUANTIZATION NOISE ON VCO CONTROL VOLTAGE 147

∆

Νmax

ref

div

Figure B-2: Maximum phase difference in a fractional-N synthesizer.

as

∆Vmax =Ich

C∆Tmax (B.4)

where Tmax is the maximum time difference the reference and the divided output fre-

quency. This maximum time difference occurs when the divider value changes to a maximum

value, as shown in Figure B-2. Therefore,

∆Tmax = Tdiv − Tref = NmaxTo − Tref (B.5)

=(

Nmax

Nnom− 1

)Tref

Combining the above two equations, we achieve

∆Vmax =Ich

C∆Tmax =

Ich

C

(Nmax

Nnom− 1

)Tref (B.6)

=2πNnom

Kvcoω2

n

(Nmax

Nnom− 1

)Tref

148 APPENDIX B. PLL MODEL

= Kquantω2n (B.7)

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