ENEE 408C LabENEE 408C LabCapstone Project: Digital System Capstone Project: Digital System

DesignDesignSpring 2006Spring 2006

Class Web Site:Class Web Site:http://www.ece.umd.edu/class/enee408chttp://www.ece.umd.edu/class/enee408c

TA’s InformationTA’s Information

Alessandro GeistAlessandro Geist

ageist@umd.eduageist@umd.edu

Office Hours: TBDOffice Hours: TBD

Cyclic Behavioral ModelsCyclic Behavioral Models

Model both level-sensitive behavior (combinational) and Model both level-sensitive behavior (combinational) and edge-sensitive behavior (flip-flop) of an element.edge-sensitive behavior (flip-flop) of an element.

always@ (a or b) beginalways@ (a or b) begin

sum = a ^ b;sum = a ^ b;

c_out = a & b;c_out = a & b;

endend

always@ (posedge clk)always@ (posedge clk)

dff_out <= dff_in;dff_out <= dff_in;

Blocking vs. NonblockingBlocking vs. Nonblocking

In always blocksIn always blocksBlockingBlocking– Execute in orderExecute in order– Better for combinational logicBetter for combinational logic

NonblockingNonblocking– Execute Concurrently (in parallel)Execute Concurrently (in parallel)– Better for sequential logicBetter for sequential logic– RHS of all statements calculated first from RHS of all statements calculated first from

values before executionvalues before execution

Combinational Examples of Combinational Examples of Blocking vs. NonblockingBlocking vs. Nonblocking

BlockingBlockingReg D, B;Reg D, B;always @ (E or D) beginalways @ (E or D) begin

// D=2, E=5, B=3 initially// D=2, E=5, B=3 initially

D = E;D = E; // D=5// D=5B = D;B = D; // B=5// B=5

endend

NonblockingNonblockingReg D, B;Reg D, B;always @ (E or D) beginalways @ (E or D) begin

// D=2, E=5, B=3 initially// D=2, E=5, B=3 initially

D <= E;D <= E; // D=5// D=5B <= D;B <= D; // B=2// B=2

endend

Data Types — RegistersData Types — Registers

A register is a data storage element that A register is a data storage element that retains its value until another value is retains its value until another value is placed on it. Like a Variableplaced on it. Like a VariableNOT A FLIP-FLOPNOT A FLIP-FLOP– Flip-flops are synchronous.Flip-flops are synchronous.– Registers can be set at any time.Registers can be set at any time.

RegistersRegisters– Set by other registers, from wires, or from Set by other registers, from wires, or from

constants constants – Default to Default to xx..

Operators — ConditionalOperators — Conditional

??::

cond_exprcond_expr ?? expr1expr1 :: expr2expr2– wirewire[0:2] [0:2] STUDENTSTUDENT = =

MARKSMARKS > 75 > 75 ?? GRADE_AGRADE_A : : GRADE_CGRADE_C ; ;– alwaysalways

#5 #5 CTRCTR = ( = (CTRCTR != 25) != 25) ?? ( (CTRCTR + 1) : 5 ; + 1) : 5 ;

If If cond_exprcond_expr is an is an xx or a or a zz, the result is , the result is a bitwise operation on a bitwise operation on expr1expr1 and and expr2expr2..– 0 with 0 gives 0, 1 with 1 gives 1, the rest 0 with 0 gives 0, 1 with 1 gives 1, the rest

are are xx..

““If” StatementIf” Statement

Behavioral codeBehavioral codeMust be contained within an “always” blockMust be contained within an “always” blockIf statement is incomplete (not all cases handled) will result in If statement is incomplete (not all cases handled) will result in inference of a transparent latch in hardwareinference of a transparent latch in hardwareSyntax:Syntax:

reg a;reg a;always @ (sel or b)always @ (sel or b)

beginbeginif (sel == 1)if (sel == 1)

a = b;a = b;endend

While sel is high, a will follow b. When sel is low, a will remain constantWhile sel is high, a will follow b. When sel is low, a will remain constant

““If-else” StatementsIf-else” Statements

always @ (sel or b or c)always @ (sel or b or c)

beginbegin

if (sel == 1)if (sel == 1)

a = c;a = c;

elseelse

a=b;a=b;

endend

““If” StatementsIf” Statements

Remember we are designing hardware and Remember we are designing hardware and nonblocking more closely resembles actual hardwarenonblocking more closely resembles actual hardware

reg a, x;reg a, x;always @ (sel or b or c or d or e) beginalways @ (sel or b or c or d or e) begin

if (sel == 1) beginif (sel == 1) begina <= c;a <= c;x <= d | a;x <= d | a;

endendelse beginelse begin

a <= b;a <= b;x <= e;x <= e;

endendendend

D-type Flip-FlopD-type Flip-Flopmodule registerDFF(Q,D, clk, reset_n);module registerDFF(Q,D, clk, reset_n);

outputoutput Q;Q; // the 1-bit output bus// the 1-bit output bus

inputinput D;D; // the 1-bit input data bus// the 1-bit input data businputinput clk;clk;inputinput reset_n;reset_n; // active low reset signal// active low reset signal

regreg Q;Q; // must be a register so it can hold a value// must be a register so it can hold a value

always @ (posedge clk or negedge reset_n) beginalways @ (posedge clk or negedge reset_n) beginif (!reset_n)if (!reset_n) // active low reset// active low reset

Q<=1'b0;Q<=1'b0;elseelse

Q<=D;Q<=D; // otherwise it's a positive edge of clk so Q is updated // otherwise it's a positive edge of clk so Q is updated to D.to D.

endendendmoduleendmodule

Transparent LatchesTransparent Latches

When the circuit is synthesizedWhen the circuit is synthesized

Formed when not all possibilities are Formed when not all possibilities are specifiedspecified

Case StatementsCase Statements

Case statement executes first match Case statement executes first match found and does not consider remaining found and does not consider remaining possibilitiespossibilities

Default case allows capture of remaining Default case allows capture of remaining cases cases

Usually used to generate a multiplexer Usually used to generate a multiplexer (MUX)(MUX)

Case StatementsCase Statementsmodule ALU(alu_out, Opcode, A, B);module ALU(alu_out, Opcode, A, B);outputoutput [7:0] alu_out;[7:0] alu_out;inputinput [3:0] Opcode;[3:0] Opcode;inputinput [7:0] A, B;[7:0] A, B;reg reg [7:0] alu_out;[7:0] alu_out;

always @ (Opcode or A or B) beginalways @ (Opcode or A or B) begincase (Opcode)case (Opcode)

4’b0000:4’b0000: alu_out = 0;alu_out = 0; // NOP// NOP4’b0001:4’b0001: alu_out = A+B;alu_out = A+B; // ADD// ADD4’b0010:4’b0010: alu_out = A-B;alu_out = A-B; // SUB// SUB4’b0011:4’b0011: alu_out = A & B;alu_out = A & B; // AND// AND4’b0100:4’b0100: alu_out = ~B;alu_out = ~B; // NOT// NOTdefault:default: alu_out = 0;alu_out = 0;

endcaseendcaseendmoduleendmodule

Case StatementsCase Statements

parameter NOPparameter NOP == 4’b0000;4’b0000;parameter ADDparameter ADD = = 4’b0001;4’b0001;parameter SUBparameter SUB = = 4’b0010;4’b0010;parameter ANDparameter AND == 4’b0011;4’b0011;parameter NOTparameter NOT = = 4’b0100;4’b0100;……always @ (Opcode or A or B) beginalways @ (Opcode or A or B) begin

case (Opcode)case (Opcode)NOP:NOP: alu_out = 0;alu_out = 0; // NOP// NOPADD:ADD: alu_out = A+B;alu_out = A+B; // ADD// ADDSUB:SUB: alu_out = A-B;alu_out = A-B; // SUB// SUBAND:AND: alu_out = A & B;alu_out = A & B; // AND// AND

……

Lexical TokensLexical Tokens

Verilog source files consist of streams of Verilog source files consist of streams of lexical tokens separated by white space.lexical tokens separated by white space.

Types of lexical tokens:Types of lexical tokens:white space (newline, tab, space)white space (newline, tab, space)commentscommentsoperatorsoperatorsnumbersnumbersstringsstringsidentifiers (case sensitive)identifiers (case sensitive)keywords (lower case)keywords (lower case)

Lexical ConventionsLexical Conventions

White space :White space : Ignored in Verilog except when separating Ignored in Verilog except when separating

tokens. Not ignored in strings.tokens. Not ignored in strings.Comments (like C++, Java):Comments (like C++, Java):– Single Line //Single Line //– Multiple Lines /* … */Multiple Lines /* … */

Use comments abundantly and Use comments abundantly and meaningfully!meaningfully!

Operators — ArithmeticOperators — Arithmetic

Binary operators (e.g., c = a * b) :Binary operators (e.g., c = a * b) :

Multiply (*)Multiply (*)

Divide (/)Divide (/)

Add (+)Add (+)

Subtract (-)Subtract (-)

Modulus (%)Modulus (%)

Power (**)Power (**)

Unary operators:Unary operators:

Unary plus (+)Unary plus (+)

Unary minus (-)Unary minus (-)

Operators — RelationalOperators — Relational

> (greater than)> (greater than)

< (less than)< (less than)

>= (greater than or equal to)>= (greater than or equal to)

<= (less than or equal to)<= (less than or equal to)

Operators — EqualityOperators — Equality

==, != (logical equality, inequality)==, != (logical equality, inequality)– Yields an Yields an xx if either operand has an if either operand has an xx or or zz in in

it.it.

===, !== (case equality, inequality)===, !== (case equality, inequality)– Checks Checks xx’s and ’s and zz’s for equality.’s for equality.

Operators — LogicalOperators — Logical

Logical OperatorsLogical Operators

!! !m!mIs m not true? Is m not true? (1-bit (1-bit True/False True/False result)result)

&&&& m && nm && nAre both m and Are both m and n true? (1-bit n true? (1-bit True/False True/False result)result)

|||| m || nm || nAre either m or Are either m or n true? (1-bit n true? (1-bit True/False True/False result)result)

Operators — BitwiseOperators — Bitwise

Bitwise OperatorsBitwise Operators

~~ ~m~m Invert each bit of mInvert each bit of m

&& m & nm & n AND each bit of m AND each bit of m with each bit of nwith each bit of n

|| m | nm | n OR each bit of m with OR each bit of m with each bit of neach bit of n

^̂ m ^ nm ^ n Exclusive OR each bit Exclusive OR each bit of m with nof m with n

~^~^^~^~

m ~^ nm ~^ nm ^~ nm ^~ n

Exclusive NOR each Exclusive NOR each bit of m with nbit of m with n

These operators operate on all bits of a single operand and produce a 1-bit result.

Unary Reduction OperatorsUnary Reduction Operators

&& &m&m AND all bits in m AND all bits in m together (1-bit result)together (1-bit result)

~&~& ~&m~&m NAND all bits in m NAND all bits in m together (1-bit result)together (1-bit result)

|| |m|m OR all bits in m OR all bits in m together (1-bit result)together (1-bit result)

~|~| ~|m~|m NOR all bits in m NOR all bits in m together (1-bit result)together (1-bit result)

^̂ ^m^m Exclusive OR all bits Exclusive OR all bits in m (1-bit result)in m (1-bit result)

~^~^^~^~

~^m~^m^~m^~m

Exclusive NOR all bits Exclusive NOR all bits in m (1-bit result)in m (1-bit result)

Operators — Concatenation and Operators — Concatenation and ReplicationReplication

{} - concatenation{} - concatenation

– {a,b} is the concatenation of a and b{a,b} is the concatenation of a and b

– if a and b are 10 bits, {a,b} is 20 bitsif a and b are 10 bits, {a,b} is 20 bits

{ %{ %dd {} } - Replication inside {} } - Replication inside concatenationconcatenation

– {5 {a}} is the same as {a,a,a,a,a}{5 {a}} is the same as {a,a,a,a,a}

Operators — ShiftOperators — Shift

>> (right shift) Vacated bit positions filled with >> (right shift) Vacated bit positions filled with zeroszeros<< (left shift) Vacated bit positions filled with << (left shift) Vacated bit positions filled with zeroszerosExample: Example: A = A << 2;A = A << 2; shifts A two bits to left shifts A two bits to left with zero fill. with zero fill. Arithmetic shifts:Arithmetic shifts:>>> >>> <<< (same as <<)<<< (same as <<)

Operators — ConditionalOperators — Conditional

??::

cond_exprcond_expr ?? expr1expr1 :: expr2expr2– wirewire[0:2] [0:2] STUDENTSTUDENT = =

MARKSMARKS > 75 > 75 ?? GRADE_AGRADE_A : : GRADE_CGRADE_C ; ;– alwaysalways

#5 #5 CTRCTR = ( = (CTRCTR != 25) != 25) ?? ( (CTRCTR + 1) : 5 ; + 1) : 5 ;

If If cond_exprcond_expr is an is an xx or a or a zz, the result is , the result is a bitwise operation on a bitwise operation on expr1expr1 and and expr2expr2..– 0 with 0 gives 0, 1 with 1 gives 1, the rest 0 with 0 gives 0, 1 with 1 gives 1, the rest

are are xx..