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Portable Stimulus Leader
End-to-end Verification with Portable Stimulus on a Mixed Signal DSP & Automotive SoC
Courtney Fricano, ADI Gaurav Bhatnagar, ADI Leigh Brady, Breker
MotivationAccellera Portable Stimulus Standard (PSS) ratified at DAC’18• Promises reduced UVM/SoC test complexity, portability and test reuse
ADI evaluated PSS on two existing, complex testbenches• Multi-core DSP SoC with an analog front-end• Automotive mixed signal SoC
Some interesting methodology improvements• VIP reuse from IP to SoC, across simulation, emulation, final silicon• UVM sequence and SW tests complexity reduction • Abstractions to allow non-verification experts to create test scenarios
Test Generation Support• IP and SOC level support• Test authoring ease by non-DV engineers• Layering into existing environments• Initial bring up time and effort• Test read-ability and ease of debug• SystemVerilog and C Test support• Speed of test generation• Code/Functional Coverage of Generated
Tests• Generation of invalid tests
Re-use Requirements• IP level to SOC level reuse• Cross SoC platform reuse• Post silicon driver development• Derivative test regeneration/reuse
Generalized Test Requirements
SOC Level Requirements• Supports Cache Testing• Supports Coherency Testing• Control of UVM VIP virtual sequences• Low power and security feature testing• Advanced Testing of multi-core SoCs
Mixed Signal, Automotive Audio SoC Dual Core DSP SoC with Analog Front-End
• Layer PSS effectively into existing UVM and SoC testbenches, use sequence generation based on abstract scenario models from non-verification engineers• Effective methods to reuse IP simulation test scenarios within system level tests without rewriting, to drive SoC emulation and post-silicon verification• Debug through mailbox mechanisms that monitors transactions. Particularly useful during post silicon where probing into the design impossible• Complex random scenarios over the entire SoC provided powerful abstract tests, and coupled with coverage was able to enhance system analysis
Summary of Interesting Findings
Why is this an interesting testcase?• Mixed signal elements modeled• I2C & I2S interfaces modeled• Very flexible design configuration
leading to many possible tests• Reusing existing UVM components
DUTMaster
DUTSlave
0
DUTSlave
1
I2CAgent
I2SAgent
I2CAgent
I2CAgent
I2SAgent
I2SAgent
XCVR DUTSlave
N
I2CAgent
I2SAgent
XCVRXCVR
UVM sequences easily written for individual interfaces
Much more complex to create sequences for all interfaces to
drive entire design
The Verification Problem
Single Abstract Scenario For Entire Design
DUTMaster
DUTSlave
0
DUTSlave
1
I2CAgent
I2SAgent
I2CAgent
I2CAgent
I2SAgent
I2SAgent
XCVR XCVR DUTSlave
N
I2CAgent
I2SAgent
…XCVR
BrekerTrekUVM
IP Tests
PSS abstract model of entire system scenario described in
single graph
New PSS scenario operates with existing UVM testbench
Think of PSS as powerful virtual sequencer
Automated, Multi-Threaded Sequence Synthesis
Sequences hard to generate manually given the synchronization complexitySingle scenario graph driving multi-threaded sequences simplifies this issue
Test map view makes test monitoring and design debug far easier
VIP
SoC Testbench
Core0 Core1
SYSTEM FABRIC
SRAM
FLASH AFE IP
Peripherals
IP 1
IP 2
IP n
I/O
Verification challenges:• Test case authoring by architects
with limited verification expertize• Synchronization of C-tests and HW
transactions• UVM model reuse at the SoC level• Test case sharing from simulation
to emulation and beyond
Test1.c
test.tbx
TrekSoC
Trek
Box
(libt
rekb
ox.so
)
mailbox
Multi-threaded C-tests generated from abstract scenarios
PSS tests layered into existing SoC testbench
VIP
SoC Testbench
Test2.c
Core0 Core1
SYSTEM FABRIC
SRAM
FLASH AFE IP
Peripherals
IP 1
IP 2
IP n
I/O
Drive/check IP data
SW test synchronized with HW transaction Analysis
SoC Test Graph
Smaller scenario graph reused in larger graph
SoC Test Creation Advantages
Test1.c
test.tbx
TrekSoC
Trek
Box
(libt
rekb
ox.so
)
Test self checking with auto-scenario coverage
Test2.c
mailbox
VIP
SoC Testbench
Core0 Core1
SYSTEM FABRIC
SRAM
FLASH AFE IP
Peripherals
IP 1
IP 2
IP n
I/O
System services, inclHSI and memory
management
Simulation Emulation Silicon
SoC Test Execution Advantages
Multi-threaded test map view
Test map view allows easy monitoring and debug of multi-threaded tests
Mailbox mechanism enhancing debug on emulation, silicon, etc
SoC verification portability
DUTMaster
DUTSlave
0
DUTSlave
1
I2CAgent
I2SAgent
I2CAgent
I2CAgent
I2SAgent
I2SAgent
XCVR XCVRDUT
SlaveN
I2CAgent
I2SAgent
XCVR
BrekerTrekUVM