E.N. Spencer SCIPP-UCSC 18 May 2006 FEE Perugia Silicon Germanium BICMOS: Irradiation Resistance and Low Power Analog Applications 1 FEE2006 Workshop on

18 May 2006 FEE Perugia

Silicon Germanium BICMOS: Irradiation Resistance and Low Power Analog Applications

1E.N. SpencerSCIPP-UCSC

Silicon Germanium BICMOS: Irradiation Silicon Germanium BICMOS: Irradiation Resistance and Low Power Analog ApplicationsResistance and Low Power Analog Applications

FEE2006 Workshop on Front-End electronics

Perugia, Italia

18-May-2006

E. N. SpencerSCIPP – UCSC




The ATLAS Strip Detector ReadoutThe ATLAS Strip Detector Readout

The present ATLAS strip detector readout IC (named ABCD) is fabricated on the DMILL biCMOS technology.

• The front-end amplifier, shaper and discriminator is biCMOS.

• The back-end pipeline, readout, command decoder, etc. is all CMOS devices.

The DMILL technology is no longer available and it would likely not be sufficiently rad-hard for the higher SLHC luminosity, at least not at the same radii.

A new technology must be chosen.




Deep Sub-micron CMOS a PossibilityDeep Sub-micron CMOS a Possibility

One obvious possibility is a complete IC in deep sub-micron CMOS.

• Radiation hardness of 0.25 m CMOS has been demonstrated at levels sufficient for strip use at SLHC

• Newer 0.13 m technologies are now being evaluated and are likely more rad-hard .

A demonstration front-end circuit was designed and fabricated in 0.25 m CMOS a few years ago and was shown to meet present ATLAS noise and timing requirements.

A proposal is now being discussed to build a CMOS replacement for the full ABCD chip to demonstrate feasibility and evaluate performance.




Past ExperiencePast Experience

A biCMOS technology was ideal for the existing ATLAS readout IC because:

• We have shown for past experiments that the bipolar technology has advantages over CMOS in power and performance for front-end amplification when the capacitive loads are high and the shaping times short.

• ZEUS-LPS Tek-Z IC• SSC-SDC LBIC IC• ATLAS-SCT ABCD, CAFE-M, CAFE-P ICs

• CMOS is the preferred technology for memory and logic circuits of the back-end.

• BiCMOS technology afforded both of these optimizations in one IC.

Experience with commercial 0.25 m CMOS has shown the advantage of using a volume commercial rather than a niche technology.




Technical IssuesTechnical Issues

The ATLAS-ID upgrade will put even greater constraints on power.

Can we meet power and shaping time requirements with deep sub-micron CMOS?

• Achieving sufficient transconductance of the front-end transistor typically requires large bias currents.

The crossing time of the SLHC is not yet fixed. If this dictates a

faster shaping time, the transconductance vs. power will become a bigger issue.

If past experience still applies, a bipolar front-end may be able to meet noise and timing requirements for less power than a CMOS solution.

Are there commercial biCMOS technologies that could meet all of our stringent requirements?




biCMOS with Enhanced SiGebiCMOS with Enhanced SiGe

The market for wireless communication has now spawned many biCMOS technologies where the bipolar devices have been enhanced with a germanium doped base region (SiGe devices).

We have identified at least the following vendors:

• IBM (at least 3 generations available)

• STm

• IHP, (Frankfurt on Oder, Germany)

• Motorola

• JAZZ

Advanced versions include CMOS with feature sizes of 0.25 m to 0.13 m.

The bipolar devices have DC current gains () of several 100 and fTs up to 200s of GHz. This implies very small geometries that could afford higher current densities and more rad-hardness.

Growing number of fab facilities




Technical QuestionsTechnical Questions

The changes that make SiGe Bipolar technology operate at 100s of GHz for the wireless industry coincide with the features that enhance performance for our application.

• Small feature size increases radiation tolerance.

• Extremely small base resistance (of order 10-100 ) affords low noise designs at very low bias currents.

Can these features help save power?

Will the SiGe technologies meet rad-hard requirements?




Radiation vs. Radius in Upgraded TrackerRadiation vs. Radius in Upgraded Tracker

The usefulness of a SiGe bipolar front-end circuit will depend upon its radiation hardness for the various regions (i.e. radii) where silicon strip detectors might be used.

1

10

100

0 20 40 60 80 100

Fluence for 2,500 fb -1

Radius [cm]

InnerPixel

Mid-RadiusShort Strips

Outer-Radius “SCT”

Flu

ence

[10

14 n

eq/c

m2 ]




Tracker Regions Amenable for SiGeTracker Regions Amenable for SiGe

For the inner tracker layers, pixel detectors will be needed, and their small capacitances allow the use of deep sub-micron CMOS as an efficient readout technology.

Starting at a radius of about 20 cm, at fluence levels of 1015 n/cm2, short strips can be used, with a detector length of about 3 cm and capacitances on the order of 5 pF. At a radius of about 60 cm, the expected fluence is a few times 1014 n/cm2, and longer strips of about 10 cm and capacitance of 15 pF can be used.

It is in these two outer regions with sensors with larger capacitive loads where bipolar SiGe might be used in the front-end readout ASICs with welcome power savings while still maintaining fast shaping times.




Evaluation of SiGe Radiation HardnessEvaluation of SiGe Radiation Hardness

The Team

D.E. Dorfan, A. A. Grillo, A. Jones, G.F. Martinez-McKinney, M. Mendoza, P. Mekhedjian, J. Metcalfe, H. F.-W. Sadrozinski,

G. Saffier-Ewing, A. Seiden, E. N. Spencer, M. WilderSCIPP-UCSC

Collaborators: A. Sutton, J.D. Cressler, A.P. Gnana PrakashGeorgia Tech, Atlanta, GA 30332-0250, USA

F. Campabadal, S. Díez, C. Fleta, M. Lozano, G. Pellegrini, J. M. Rafí, M. Ullán

CNM (CSIC), Barcelona

S. Rescia et al.BNL




J. Kaplon et al., 2004 IEEE Rome Oct 2004, use 0.25 m CMOS

For CMOS: Input transistor: 300 A, other transistors 330 A (each 20 – 90 A)

Potential CMOS Front-EndPotential CMOS Front-End




High-Rate Front-End Initial Targets for ATLAS-SHigh-Rate Front-End Initial Targets for ATLAS-S

• Input signal polarity: Both, either positive from p-strips or negative from n-strips, polarity switch needed

• Gain at comparator input, >100 mV/fC.

• Noise:

<= 1500 e- for unirradiated module.

<=1800 e- for irradiated module.

• Peaking time: 20 ns, for 25 ns crossing for this study. Upgrade could use 25 ns crossing as at present, but could be 20, 15, or 10 ns, with correspondingly lower analog shaping time.

•Total time walk for signal at comparator output: < 16 ns, 1.05 fC to 10 fC, for 1 fC threshold

•Minimum PSRR, 10 kHz-100 kHz: 20 dB, 10 MHz-60 MHz10: -14 dB (Should be improved if feasible).

•Power: minimum net power dissipation, as other specifications permit, < 400 W for analog section including differential comparator output @ 15 pF detector load. < 160 W @ 6 pF load.




Evaluating SiGe with Design: IHP SubmissionEvaluating SiGe with Design: IHP Submission

Depending upon the performance (especially radiation hardness) of the bipolar process, power savings could be realized in both the front transistor and in the other parts of the analog circuit.

To evaluate these design questions, UCSC recently submitted for fabrication the High Rate Front –End IC, HRFE, using the IHP SG25H1 SiGe BiCMOS process through the Europractice mini@sic program.

IHP SG25H1:

• 200 GHz ft npn’s , minimum .21 x .84 m• npn is ~150 • npn re is 50 for minimum npn• 0.25 m CMOS• Available on mini@sic Europractice• Full Cadence kit supported by IHP• Back annotation of layout is supported




HRFE: BiCMOS Front-EndHRFE: BiCMOS Front-End




HRFE Digital LVDS BufferHRFE Digital LVDS Buffer




Transient Differential Shaper Response 2 fC to 32 fCTransient Differential Shaper Response 2 fC to 32 fC




Noise versus Detector Capacitance @ 40 Noise versus Detector Capacitance @ 40 A bias for Q1A bias for Q1




Noise versus Detector Capacitance @ 150 Noise versus Detector Capacitance @ 150 A bias for Q1A bias for Q1




Timewalk: 10 fC as Zero time, 50 attoF drive needed Timewalk: 10 fC as Zero time, 50 attoF drive needed above 1 fC for 16 ns timewalkabove 1 fC for 16 ns timewalk




Comparator Latching with small Threshold Control Comparator Latching with small Threshold Control Steps through Voltage ThresholdSteps through Voltage Threshold

Apply 400 A threshold steps: Comparator LVDS output either full width or fully off.




First SiGe High-rate Radiation Testing First SiGe High-rate Radiation Testing

Radiation testing has been performed on some SiGe devices by our Georgia Tech collaborators up to a fluence of 1x1014 p/cm2 and they have demonstrated acceptable performance. (See for example: http://isde.vanderbilt.edu/Content/muri/2005MURI/Cressler_MURI.ppt)

In order to extend this data to higher fluences, we obtained some arrays of test structures from our collaborator at Georgia Tech. These were from a -enhanced 5HP (called 5AM) process from IBM. (i.e. the was ~250 rather than ~100.)

The parts were tested at UCSC and with the help of RD50 collaborators (Michael Moll & Maurice Glaser) they were irradiated in Fall 2004 at the CERN PS and then re-tested at UCSC.

For expediency, all terminals were grounded during the irradiation This gives slightly amplified rad effects compared to normal biasing.

Annealing was performed after initial post-rad testing.




Irradiated SamplesIrradiated Samples

Pre-rad

1.15 x 10144.15 x 1013 3.50 x 1014

1.34 x 10153.58 x 1015

1.05 x 1016

ATLAS Upgrade

Outer Radius

Mid RadiusInner Radius




Radiation Damage MechanismRadiation Damage Mechanism

10-14

10-12

10-10

10-8

10-6

10-4

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Forward Gummel Plot for 0.5 mm x 2.5 mm:

IC, IB vs. VB pre-rad and after 1*10 15 p/cm2 + anneal

IC (pre-rad)IB (pre-rad)IC (1e15, anneal)IB (1e15, anneal)

VB [V]

Ionization Damage (in the spacer oxide layers)• The charged nature of the particle creates oxide trapped charges and

interface states in the emitter-base spacer increasing the base current.

Displacement Damage (in the oxide and bulk)• The incident mass of the particle knocks out atoms in the lattice

structure shortening hole lifetime, which is inversely proportional to the base current.

Radiation damage increases base current causing the gain of the device to degrade.

Gain=Ic/Ib (collector current/base current)

I c , I

b [A

]

Forward Gummel Plot for 0.5x2.5 m2

Ic,Ib vs. Vbe Pre-rad and After 1x1015 p/cm2 & Anneal Steps

Vbe [V]

Base current increases after

irradiation

Collector current remains the same




Annealing EffectsAnnealing Effects

0.1

1

10

100

1000

10-10 10-9 10-8 10-7 10-6 10-5 10-4 10-3

Annealing of 0.5 um x 2.5 um: Current Gain beta vs. Ic

pre-rad and after 1*1015 p/cm2 and anneal steps

pre-rad1e15, no anneal1e15, 5 days RT1e15, +6 days RT+1 day 60deg C1e15, +1 day 100deg C1e15, +6 days 100deg C

IC [A]

We studied the effects of annealing. The performance improves appreciably. In the case above, the gain is now over 50 at 10A entering into the region where an efficient chip design may be implemented with this technology. The annealing effects are expected to be sensitive to the biasing conditions. We plan to study this in the future.

Cur

rent

Gai

n,

Ic [A]

Annealing of 0.5x2.5 m2: Current Gain, , vs. Ic

Pre-rad and After 1x1015 p/cm2 & Anneal Steps

Before Irradiation

After IrradiationAfter Irradiation & Full Annealing




Initial ResultsInitial Results

0.1

1

10

100

1000

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

Current Gain beta vs. Ic for 0.5 um x 10um pre-rad and for all Fluences including full annealing

Pre-rad3e131e143e141e153e151e16

IC [A]

After irradiation, the gain decreases as the fluence level increases. Performance is still very good at a fluence level of 1x1015 p/cm2. A typical Ic for transistor operation might be around 10 A where a of around 50 is required for a chip design. At 3x1015, operation is still acceptable for certain applications.

Cur

rent

Gai

n,

Current Gain, , vs. Ic for 0.5x10 m2

Pre-rad and for All Fluences Including Full Annealing

Ic [A]

Before Irradiation

Highest Fluence

Lowest Fluence

Cur

rent

Gai

n,

Increasing Fluence




Universality of ResultsUniversality of Results

0.0001

0.001

0.01

0.1

1013 1014 1015 1016

Delta(1/beta) post-rad+anneal to pre-rad @ Jc = 10 uA

0.5 um x 1 um0.5 um x 2.5 um0.5 um x 10 um0.5 um x 20 um4 um x 5um

Proton Fluence F [p/cm2]

0

0.2

0.4

0.6

0.8

1

1013 1014 1015 1016

Ratio of Current Gain beta post-rad+anneal to pre-rad @ Jc = 10 uA

0.5 um x 1 um0.5 um x 2.5 um0.5 um x 10 um0.5 um x 20 um4 um x 5um

Proton Fluence F [p/cm2]Proton Fluence [p/cm2]

1/(

fina

l) -

1/

( ini

tial

)

(1/)

Post-rad & Anneal to Pre-rad @ Jc=10A

Proton Fluence [p/cm2]

Ratio of Current Gain, Post-rad & Anneal to Pre-rad @ Jc=10 A

Rat

io

(fin

a l)/ (

init

ial)

Universal behavior independent of transistor geometry when compared at the same current density Jc. For a given current density (1/b) scales linearly with the log of the fluence. This precise relation allows the gain after irradiation to be predicted for other length SiGe HBTs. Note there is little dependence on the initial gain value.




5HP Log-Log Plot of I5HP Log-Log Plot of Ib b Radiation Induced Leakage versus I Radiation Induced Leakage versus Icc

Change in Base Leakage Current for a 0.5x10 m2

Transistor for Several Fluences

1.E-13

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-13 1.E-11 1.E-09 1.E-07 1.E-05 1.E-03

I c [A]

I b(p

ost-

irra

d)

- I b

(pre

-irr

ad

) [A

]

3.00E+13

1.00E+14

3.00E+14

1.00E+15

3.00E+15

1.00E+16

Fluence p/cm2

Vce=0.75 V




Feasibility for ATLAS ID UpgradeFeasibility for ATLAS ID UpgradeQualifications for a good transistor:

A gain of 50 is a good figure of merit for a transistor to use in a front-end circuit design.

Low currents translate into increased power savings.

At 3.5x1014 in the outer region (60 cm), where long (10 cm) silicon strip detectors with capacitances around 15pF will be used, the collector current Ic is low enough for substantial power savings over CMOS!

At 1.34x1015 closer to the mid radius (20 cm), where short (3 cm) silicon strip detectors with capacitance around 5pF will be used, the collector current Ic is still good for a front transistor, which requires a larger current while minimizing noise. We expect better results from 3rd generation IBM SiGe HBTs.

Fluence: 3.50E14 p/cm2 (2.17x1014 neq/cm2)=50

Transistor Size m2 cirrad Ic anneal

0.5x1 2.E-060.5x2.5 4.E-06 5.E-080.5x10 3.E-05 8.E-070.5x20 5.E-05 2.E-064x5 9.E-06 5.E-07

Fluence: 1.34E15 p/cm2 (8.32x1014 neq/cm2)=50

Transistor Size m2 cirrad Ic anneal

0.5x1 3.E-05 1.E-070.5x2.5 7.E-05 4.E-060.5x10 4.E-04 9.E-060.5x20 6.E-054x5 1.E-04 1.E-05




IHP - Another SiGe Vendor IHP - Another SiGe Vendor

CNM has obtained a first set of test structures from IHP and is proceeding with that evaluation.

• 2 Test chip wafer pieces with ~20 chips

• 2 Technologies:

SGC25C (bipolar module equivalent to SG25H1)

SG25H3 (Alternative technology)

• Edge effects:

Test chips came from edge of wafer

Will be solved in future samples

Irradiations with gammas to 10 Mrad and 50 Mrad have been performed. Neutrons and protons to be done.




Preliminary Results for IHP from CNMPreliminary Results for IHP from CNM

IHP SGC25C SiGe technology• Bipolar transistors equivalent to SG25H1 technology (fT = 200 GHz)• No Annealing !




Second IHP TechnologySecond IHP Technology

IHP SG25H3 SiGe technology• fT = 120 GHz, Higher breakdown voltages• Annealing after 50 Mrads: 48 hours, very good recovery• Very low gains before irradiation (edge wafer transistors)




Continuing Studies of IBM TechnologiesContinuing Studies of IBM Technologies

Neutron irradiation is in progress at Ljubljana. Gammas are being done at BNL now(May 2006) with protons to follow this spring.

We are continuing the studies of three IBM technologies (5HP, 7HP and 8HP) using neutrons, gammas and protons.

8HP comes with0.13 m CMOS

5AM & 5HP comes with 0.25 m & 0.50 mm CMOS

5AM & 5HP comes with 0.25 m & 0.50 mm CMOS




Preliminary! 8HP Beta change with 10 MRad Gamma IrradiationPreliminary! 8HP Beta change with 10 MRad Gamma Irradiation(Biased During Irradiation)(Biased During Irradiation)




Conclusions on SiGe Evaluation So FarConclusions on SiGe Evaluation So Far

First tests of one SiGe biCMOS process indicate that the bipolar devices may be sufficiently rad-hard for the upgraded ATLAS tracker, certainly in the outer-radius region and even perhaps in the mid-radius region.

A design on the IHP SG25 H1 process indicates that such a SiGe front-end circuit will achieve significant power savings.

More work is needed to both confirm the radiation hardness and arrive at more accurate estimates of power savings.

In particular, with so many potential commercial vendors available, it is important to understand if the post-radiation performance is generic to the SiGe technology or if it is specific to some versions. Other ATLAS Upgrade collaborators are optimizing the minimum analog power achievable with CMOS.




Work AheadWork AheadAlong with our collaborators, we plan two parallel paths of work.

We will complete the irradiation studies of several SiGe processes. In particular, we plan to test at least the IBM 5HP, IBM 7HP, IBM 8HP, IHP SGC25C (eq. to SG25H1), IHP SG25H3 and IHP SGB25VD.

• CNM will focus on the IHP technologies.

• UCSC on IBM.

To obtain a better handle on the true power savings, we have submitted an IHP 8 channel amplifier/comparator April 2006. This work is in parallel with IHP radiation characterization. UCSC will continue this direct evaluation by design with testing.

The BNL LAr Calorimeter group is also engaged in SiGe qualification and is gamma irradiating the IBM SiGe.

Once the SiGe evaluation is mature, a choice can be made between SiGe bipolar or CMOS for the front-end to be married with the CMOS backend.

Documents

E.N. Spencer SCIPP-UCSC 18 May 2006 FEE Perugia Silicon Germanium BICMOS: Irradiation Resistance and Low Power Analog Applications 1 FEE2006 Workshop on