Embedded System Design - Bubble Sort Algorithm, Embedded System Implementation

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Embedded System Design, RMIT University, Wilson Castillo:An embedded system is a special-purpose system in which the computer is completely encapsulated by the device it controls. Unlike a general-purpose computer, such as a personal computer, an embedded system performs one or a few pre-defined tasks, usually with very specific requirements. Since the system is dedicated to specific tasks, design engineers can optimize it, reducing the size and cost of the product.(www.en.wikipedia.org, 2006/11/17). The development of a development system can be classified depending of the technology; Full-custom/VLSI, Semi-Custom ASIC and FPGA/PLD (Beckett P, 2006). This project has to do with the development of a embedded system using a FPGA development system.

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<p>EEET2039 Embedded Systems Design</p> <p>Final Project Report</p> <p>Professor: Paul Beckett (paul.beckett@rmit.edu.au) Tutor: Surendran Devadoss (surendran_80@ieee.org)</p> <p>Student: Wilson Castillo Bautista s3143667@student.rmit.edu.au Email: Subject Code: EEET2039 Embedded Systems Design</p> <p>Melbourne, November 17th, 2006</p> <p>EEET2039 Embedded Systems Design Final Project Report Laboratory Report</p> <p>Complete Bubblesort Embedded System Implementation Student: Wilson Castillo (s3143667)</p> <p>Table of Contents1 2 3 Introduction ......................................................................................................................................4 Aim......................................................................................................................................................4 Methodology....................................................................................................................................4 3.1 Project Design ........................................................................................................................5 3.1.1 Clock of the System .........................................................................................................6 3.1.2 PS/2 Keyboard Reader ....................................................................................................6 3.1.3 RS-232 Transmitter .............................................................................................................7 3.1.4 Memory of the system .....................................................................................................7 3.1.5 Assembly Code .................................................................................................................8 Complete System ............................................................................................................................8 Testing the System ...........................................................................................................................9 Annex ...............................................................................................................................................10 Conclusions .....................................................................................................................................26 References ......................................................................................................................................27</p> <p>4 5 6 7 8</p> <p>RMIT University 2006 School of Electrical and Computer Engineering</p> <p>2 of 27 Melbourne, 17th November, 2006</p> <p>EEET2039 Embedded Systems Design Final Project Report Laboratory Report</p> <p>Complete Bubblesort Embedded System Implementation Student: Wilson Castillo (s3143667)</p> <p>Table of FiguresFigure 1: Architecture of the system implemented ..........................................................................5 Figure 2: VHDL Symbol for clock generator........................................................................................6 Figure 3: Clock signals generated by VHDL Clock generator code. ............................................6 Figure 4: VHDL Symbol for PS/2 Reader...............................................................................................6 Figure 5: VHDL Symbol for RS-232 transmitter .....................................................................................7 Figure 6: Memory of the system ............................................................................................................8 Figure 7: Multiplexer 16 x 8 .....................................................................................................................8 Figure 8: System Flow ..............................................................................................................................9 Figure 9: Flow Diagram of the System when it is working (user point of view) ..........................10 Figure 10: VHDL Code for clock generator ......................................................................................11 Figure 11: VHDL code for RS-232 transmitter ....................................................................................12 Figure 13: VHDL code for PS/2 Reader ..............................................................................................15 Figure 14: VHDL Symbol for devices handler....................................................................................15 Figure 15: VHDL Code for Devices handler ......................................................................................21 Figure 16: Bubble Sort Algorithm Implemented in the HC11 VHDL Core....................................22 Figure 17: Test Bench VHDL Code for testing the design...............................................................25</p> <p>RMIT University 2006 School of Electrical and Computer Engineering</p> <p>3 of 27 Melbourne, 17th November, 2006</p> <p>EEET2039 Embedded Systems Design Final Project Report Laboratory Report</p> <p>Complete Bubblesort Embedded System Implementation Student: Wilson Castillo (s3143667)</p> <p>Embedded System Design1 Introduction</p> <p>An embedded system is a special-purpose system in which the computer is completely encapsulated by the device it controls. Unlike a general-purpose computer, such as a personal computer, an embedded system performs one or a few pre-defined tasks, usually with very specific requirements. Since the system is dedicated to specific tasks, design engineers can optimize it, reducing the size and cost of the product. (www.en.wikipedia.org, 2006/11/17). The development of a development system can be classified depending of the technology; Full-custom/VLSI, Semi-Custom ASIC and FPGA/PLD (Beckett P, 2006). This project has to do with the development of a embedded system using a FPGA development system.</p> <p>2</p> <p>Aim</p> <p>The purpose of this project is to design a complete embedded system to implement the bubble sort algorithm that was tested in laboratory 3. This includes the use of a FPGA development system, which is the VIRTEX-II Microblaze Development Kit board. This project includes both hardware and software design and encompasses some of key aspects covered by the course of Embedded System Design (EEET2039).</p> <p>3</p> <p>Methodology</p> <p>RMIT University 2006 School of Electrical and Computer Engineering</p> <p>4 of 27 Melbourne, 17th November, 2006</p> <p>EEET2039 Embedded Systems Design Final Project Report Laboratory Report</p> <p>Complete Bubblesort Embedded System Implementation Student: Wilson Castillo (s3143667)</p> <p>Figure 1: Architecture of the system implemented</p> <p>As can be seen in Figure 1, the system is divided into three different sections: 1) Keyboard Receiver, HC11 Core and RS-232 transmitter. The schematic of the design can be seen at the end of this document in the annex part of this document.</p> <p>In the hardware design part, the system uses the CPU core (68HC11, http://www.gmvhdl.com/hc11core.html, 2006/09/13), a PS2 interface and RS232 code VHDL interfaces. The development of the system will be using the software from Xilinx (Xilinx ISE 8.1i, www.xilinx.com, 2006/09/01) development tools and ModelSim for simulation. Xilinx ISE is a fully featured FPGA development environment that enables designs to be entered as schematics, state charts, or VHDL. Additionally, ModelSim which can be integrated with Xilinx ISE to simulate the design. In the software design part this project includes the Bubble Sort algorithm implemented using assembly language and then convert it to the machine code to embed it to the ROM system.</p> <p>3.1</p> <p>Project Design</p> <p>The design of the project could be described by the following steps: 1. Design the CPU core part. This part based on laboratory 3 (68HC11 core VHDL code) and with additional components such as RAM, ROM and peripherals to create a fully CPU core.) 2. Design the PS2 Interface. 3. Design the RS232 Interface. 4. Design the Bubble Sort program and embed it to the ROM. 5. Simulate the system. 6. Synthesize the whole system.</p> <p>RMIT University 2006 School of Electrical and Computer Engineering</p> <p>5 of 27 Melbourne, 17th November, 2006</p> <p>EEET2039 Embedded Systems Design Final Project Report Laboratory Report</p> <p>Complete Bubblesort Embedded System Implementation Student: Wilson Castillo (s3143667)</p> <p>7. 8.</p> <p>Download the system to the FPGA on the VIRTEX-II board. Test the system.</p> <p>The following will describe the main components of the system. It is clear that the HC11 is working and it is not necessary to offer any additional explanation about it.</p> <p>3.1.1</p> <p>Clock of the System</p> <p>The purpose of this block is to generate the necessary signals for the system. As can be seen in Figure 3, the block delivers the signals as, E, ph1, ph2 and clk_9600. The last one is used for the RS_232_W block to write serial data to the dummy terminal. This block is based on the fact that the Microblaze system has a 24Mhz crystal generator. The code for this block could be seen in the annex of this document.</p> <p>Figure 2: VHDL Symbol for clock generator</p> <p>Figure 3: Clock signals generated by VHDL Clock generator code.</p> <p>3.1.2</p> <p>PS/2 Keyboard Reader</p> <p>Figure 4: VHDL Symbol for PS/2 Reader</p> <p>RMIT University 2006 School of Electrical and Computer Engineering</p> <p>6 of 27 Melbourne, 17th November, 2006</p> <p>EEET2039 Embedded Systems Design Final Project Report Laboratory Report</p> <p>Complete Bubblesort Embedded System Implementation Student: Wilson Castillo (s3143667)</p> <p>The basic code for the keyboard reader is based on rapid prototyping of digital systems (Hamblen J O, Hall T S and Furman, 2006). Basically this block uses a digital filter to avoid noise. Using the clock input signal (24 Mhz) it is possible to filter data with a period of 333 ns. However it is a user discretion to reduce or increase this time. The filter use a shifting register to create the filter effect. One of the improvements made to this code are, besides others, the translation of the scan code into ASCII code. The code of this block can be seen at the annex of this document.</p> <p>3.1.3</p> <p>RS-232 Transmitter</p> <p>Figure 5: VHDL Symbol for RS-232 transmitter</p> <p>The design of this block is based on the input signal CLK which is the clock reference for the block. In this design to this CLK is connected the clk_9600 output of the clock generator block. The characteristics of this block are: 9600 bps 8 data bit 1 start bit 1 stop bit No parity bit The block produces its output based on the rising edge of the CLK input. The code of this block could be seen in the annex of this document.</p> <p>3.1.4</p> <p>Memory of the system</p> <p>The system uses three VHDL codes as a source of memory, RAM, ROM and DEV blocks. The last one simulates the presence of ports PA to PE in the microcontroller.</p> <p>RMIT University 2006 School of Electrical and Computer Engineering</p> <p>7 of 27 Melbourne, 17th November, 2006</p> <p>EEET2039 Embedded Systems Design Final Project Report Laboratory Report</p> <p>Complete Bubblesort Embedded System Implementation Student: Wilson Castillo (s3143667)</p> <p>Figure 6: Memory of the system</p> <p>The ram is composed by 10 bytes and the rom is composed by 112 bytes. Additionally, dev block contains 32 bytes of ram. This memory ram is used by the bubble sort algorithm to put the data once they are ordered. Multiplexer One inconvenient founded at the beginning of this project (from laboratory 3 ) was the conflict when it is necessary to connect two output signals between them. For instance, it was necessary to create a multiplexer to avoid this problem. The signal to control the output of the multiplexer depends of the address given by the HC11 core.</p> <p>Figure 7: Multiplexer 16 x 8</p> <p>The internal composition of the multiplexer can be seen in the annex at the end of this document. 3.1.5 Assembly Code</p> <p>The assembly code used in this project is based on the laboratory 1 for this subject. This code can be seen in the annex of this document. There is a handshaking necessary to deal with the data transfer between the VHDL code and the core (Despite the fact that there is only one FPGA chip it is a way to understand how the system is composed).. This handshaking will be explained in the next section.</p> <p>4</p> <p>Complete System</p> <p>The interconnection of the different components of this design can be seen in the schematic annexed at the end of this document. To deal with the transfer of data between the VHDL code and the core (as it was described before, despite the fact that there is only one FPGA chip. The way to call VHDL</p> <p>RMIT University 2006 School of Electrical and Computer Engineering</p> <p>8 of 27 Melbourne, 17th November, 2006</p> <p>EEET2039 Embedded Systems Design Final Project Report Laboratory Report</p> <p>Complete Bubblesort Embedded System Implementation Student: Wilson Castillo (s3143667)</p> <p>code and Core it is a way to understand how the system is composed) it was necessary to create a handshaking system that can be described in the following paragraphs: According to the Hardware design, we defined some port in the system. Port A: put the data to RS232 Port E: the data from PS2 keyboard The main functions on the system were implemented in hardware, such as read number from keyboard, convert the user input to an integer, prompt the information for user etc. For the software design, it just uses the Port E to read the number that the user input. Only three cases can read from Port E, the number from 0-99, number 251 or number 252 The numbers from 0-99 (BCD) represent the number should be sorted, the number 251 represents the user will input next number and the 252 represents the user finish inputting numbers and then the system will do the Bubble Sort function to sort these numbers which were stored in the specific memory. After that, the system will check the memories which store the numbers, if the size become 0, the program will restart. The following diagram shows in a clearer way how the system works.</p> <p>Figure 8: System Flow</p> <p>5</p> <p>Testing the System</p> <p>To test the system it is necessary to connect a PS/2 keyboard to the Microblaze PS/2 port and to connect the serial port of the P160 communication card to a Hyperterminal station running at 9600, 8, N,1.</p> <p>RMIT University 2006 School of Electrical and Computer Engineering</p> <p>9 of 27 Melbourne, 17th November, 2006</p> <p>EEET2039 Embedded Systems Design Final Project Report Laboratory Report</p> <p>Complete Bubblesort Embedded System Implementation Student: Wilson Castillo (s3143667)</p> <p>1. 2. 3. 4.</p> <p>Prompt the user (via an RS-232 dummy terminal) for numbers ranging in value from 0-99. Accept and parse user input from PS/2 keyboard. Sort the number into ascending order. Display the correctly sorted numbers back to the user (via an RS232 dummy terminal).</p> <p>Print Message: Enter numbers to order (0-99): NO</p> <p>User Type Something? Do Nothing YES NO</p> <p>Is Digit?</p> <p>NO</p> <p>Is Space?</p> <p>NO</p> <p>Is Enter?</p> <p>YES Store the Number in memory</p> <p>YES...</p>