Embedded Software Design 25

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Sri Lanka Institute of Information Technology

B.Sc. Special Honours DegreeIn

Information Technology(Computer Systems &Networking)

Mid-term Examination

Year 2, Semester 2 (2009)

Embedded Software Design (252)

Duration: 1Hour

Thursday, 6th August 2009

(Time 11.00 a.m. - 12.00 noon)

Instructions to Candidates:

• This paper has 2 questions. Answer All Questions.

• Total Marks: 20.

• This paper contains 2 pages with cover page.

• PIC] 6F84 Instruction set and the SPR summary is provided

separately. Retain these for subsequent lectures.

• Calculators are not allowed.

Page 1



1. [Total:8 marks]

Write concise notes on the following to show your understanding of the function andoperation in respect of the PIC 16F84 microcontroller. You may use a diagram to support

your description. Hint: You may indicate - What is it? Where is it located? What is its

function?

a) FSR

b) EEPROM

c) RPO

d) Instruction Pipeline

2. [Total:12 marks]

(a) In a PIC Microcontroller crystal oscillator frequency Jose is divided by 4 in order

to calculate the instruction cycle rate. Explain using a diagram, why this is done.

[Total:4 marks]

(b) Write a program, which will set the memory area from h'20' to h'2f to 0 using

indirect addressing.

[Total:4 marks]

(c) Explain the difference between SPRs and GPRs.

[Total:2 marks]

(d) What are the advantages of mirrore d registers? Give at least 2 examples.

[Total:2 marks]

- End of paper-

Page 2



TABLE 2·1: SPECIAL FUNCTION REGISTER FILE SUMMARY

Value on DetailsA clclr Name Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 P ower-OnRESET

on paae

Bank 0

00r- it\OF U ses cooten.s of FSR 10 acorsss Data Mel'1ory (no: a phys ical reQister) - - - - - - - - 11

01t- TM RO 8-bit Real-Time C locklCounter x x x x x x x x 20

0 2 1 ' P CL Low O rder 8 brts of the P rogram Counter (P C ) 0000 0000 11

03h STA TUS(2) IRP RP 1 R?O TO P O Z DC, . ..

0001 l x x x e-,

04h FSR Indirect Data Mem~ry Address P ointer 0 xxxx xxxx 11

O l) h P ORTAI"I - - - RA4lTOCKI RA3 RA2 RA1 RAO - - - x x x x x 16

0 5 1 1 PORTS(61 RB7 RB6 RB5 RB4 RB3 RS2 RB1 RBD IINT XXXX xxxx 18

OT h - Unimptsmanted location. read as '0' - -

OB r EDAT A EEPROM Da1a Register xxx.x XXX): 13 .14

O tm EEADR =:::P ROM Addres s Register xxxx xxxx 13 .14

O A .h P C L .l . . T I - I - - - Wrtte Buffer for upper 5 bits o f the c eC i ) - --0 0000 11

aSh INTCON GIE EE IE TOlE INTE RBIE TG IF INTF RsrF OCi00 ' J OOx 10

Bank 1

801' INDF Uses Contents of FSR to address Dat;] Memory (not a physical regIster) - --- --- - 11

81r OP TION_REG RBPU INTEDG TaC S TO SE P SA P S2 P S1 P SO 1111 1111 9

82n P C l low order 8 bits or P rogram Counter (P C} 0000 0000 11

8 . 2 o r - STATUS (2) IR P RP 1 ROO TO PD Z DC C occi l X X>: e

~4r FSR Indirect da:a memory address poi!':er 0 >:XXX xxxx 11

8:·~ -R ISA - - - PO"T .,), Data Direction Regl$;sr - --1 1111 16

85r 7R ISB P ORTB Data Direc.ion Register 1111 1111 18

87h - Unimplemented focation. read as '0' - -

SSt' E :::CON1 - - - EEIF WRERR 'NREN \'VR RD ---0 xecc 13

89" EECON2 :::EP ROM Control Register 2 (not a physical iaglster) .• . _ . ... •. . •. . •. . •. . •. 14

OAll PClATH - - - Wnte buffer for upper 51lilS o f !he P CP ) - --0 01)(,0 11

aSh INTCON GIE EE IE TO lE J NTE RBIE TG IF INTF RBfF 0(1)1) ' J O ( ' X 10..Legend: x = unknown. u= uncoanceo. - = unlrnpternented, read as G'.q = value depends on condition

Note 1: The oper by~eof the oroqrari counter Is not directly accessible. PCLA.TH is a slave register for P C<-12:8:o, The contents

o PCLAJ H can be transferred : 0 the upper I)yte otthe oroora counter, but the contents of PC<12:8> are never trans-

ferred to ::>CLATH.

2: The T O and PO status bits in t ,e S TATUS register are not affe cted b)' a MC LR R eset.

3: O ther ( .on POW6Htp) RESE TS include: extemal R E SE T through MC R and the watc dog T imer Reset

4: On any device RESET, these pins are configured as inp is.

5: T I)is Is the value U1a! will t)e J Il the con output latch.

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TABLE 7-2: PIC16CXXX INSTRUCT10N SET

I Mnemonic, 14-Bit Opcocle

StatusDescription Cycles NotesOperandsMSb LSb

Affected

BYTE·ORIENTED FILE REGISTER OPERATIONS

ADD'NF f . d A dd \IV anc f 1 00 0111 df f f f f f f C,OC,l 1.2A .f \D ' /' .'F t. d ."'NO W with f 1 00 0101 c . uf f f f f f Z 1.2CL~F f Clear r 1 00 c-io r l t t f f f t ! : Z 2

CL~lv' - Clear .",~ 1 C 'O 0001 0= xxxx Z

C:J MF r. d Como-emeut f 1 00 1001 d f f f f i f f Z 1.2

'OECF f.d Decre'nen: f 1 00 0011 dr f f f f t f Z 1,2

OECFSZ f. d Decremer,! ', S l<; ;p i f a 1 (2) 00 1')11 df f f f f f f 1.2.3

INCF f . d Increment f 1 00 1,nD df t f f f f f Z 1.2INCFSZ f. d Increment f. Skip if 0 1 12) C 'O 1111 df f f f f f f 1.2.3

IOR'·NF Cd Inclusive OR W w im f 1 00 C'100 df f f f f f f Z 1.2

MOVF f. d Mo\>e f 1 00 100e' df f f f f f f Z 1,2

M OV·· .'.F f Move'N to f1

00 OO QO I f f ! t f f fil<OP . No ooerauon 1 00 OOOD oxx o (01)0

RL= f. d Rotate Leftf through Carry 1 00 1101 df f E E f f f C 1,2

RR " f . d Rotate Rlgh: f through Carfy 1 0·) 1100 df f f f f f f C 1,2

SlB"'''''F f.d Subtract W from f 1 00 0010 df f f f f f E C.DC.l 1.2

S'IV:"PF f..d Swap nibbles in r 1 00 1110 df f f f f f E 1,2

XO~I;F r. d Exdusive OR VI/wl:h f 1 00 011D df f t f f f f Z 1,2

BIT·ORIENTED FILE REGISTER OPERATIONS

BCF f.b Bit Clear r 1 01 CObo pfff f Hf 1,2

8SF f . b Bit Set f 1 01 olbb bf f f f i f f 1.2

BTfSC L b Bit Test f, Skip if Clear 1 [2J 01 l obb bf f f ffff 3

BTFSS f . 1 l Bit Test t, Skip if Set 1 (2) 01 11bb PffE f f f f 3

LITERAL A ND CONTROL OPERATIONS

A D D L .. " V ~ Ad~ literal and W 1 11 l l l X l c kkk kkkk C,DC,l

A I \0 L '·""i <

AND lite 3' With" f' . '

1 11 1001 kkkk kkkk ZCALL 1 .; Call subroutine 2 10 ckkk kkkk kkkk

CLR.'NDT Clear V\,a:chOog T~mer 1 0'1 0000 011Q DI00 TOPO

GOTO 1i Go to address 2 10 1Jd:k kkkk kkkk

IORLV'; ~ Inclusive OR . 'iteralwith '."" 1 11 1000 kkkk J I ' . kkk Zr ·•. Ir)VL'·J I • ~ r''''o~e literal to '/,' 1 11 oox x kr...kk kkkk

RETFIE - RI:i:urn rrorn imerrIJ pt 2 C OO 0(1)0 0000 1001

RET_·••• ><: Re:u"n with 1i:eraln '1'1 2 11 OllO'. kkkk kk l c k

R~T.J R" - Re:urn from subrocane 2 00 0,)00 0000 1000

SLEEP . Go ';1 1 10 standl)Y Mode 1 00 oc o o 0110 0011 TOPD

SLSL"N k Subtract ..•'. frOM !rleral 1 11 iiox kkkk kkkk C,DC.l

XORLW ~ Excillsi'/e OR literal with V,,' 1 11 1010 kkkk kkkk Z

Note 1: wnen an 1 1 0 register J S~odlfled as J functton ()f itself:: e.·:;).,NOVE ' PORTS. 1), the value used Will be that ..•.lue oreser:

on the oins themselves. For example. if ~r,eoa:a latch is '1' for a p 'n configured as inpu and is driven 10\1• I)y an e.<t..:rnal

device, ~heoata Will be written bacK with a '0'.

2: If .rns instruction is executed on 1'e TMRO register (and, wr-ere applicable. 0 =1). the prescaler will oe cleared if

J ssigned to :he T.merO MOdule.

3: If .:>-ogramCounter (PC) is modffied or a conditional test is true. the mstrucuon requires two cycles. The second cycle is

executed as a J -!<)P

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Embedded Software Design 25