Upload
others
View
1
Download
0
Embed Size (px)
Citation preview
Zuhal Clarke, Infineon Bristol 10.10.2016 Page 1
Embedded Multi-Core Systems
for Mixed Criticality Applications
in dynamic and changeable
Real-time Environments
Artemis Technology Conference October 6, 2016
MADRID INFINEON (UK)
Zuhal Clarke
Zuhal Clarke, Infineon Bristol 10.10.2016 Page 2
CONTENT
EMC2 WP Partitioning
EMC2 Goals as concept
EMC2 Goals in Living Labs
Demonstration Platform Introduction
Platform Development Lifecycle
2
Zuhal Clarke, Infineon Bristol 10.10.2016 Page 3
HOW IT WORKS (As defined in EMC2 TA and CA)
3 set date Copyright © Infineon Technologies AG 2015. All rights reserved.
IFGB
WP 4
WP 6
D6.10
WP7
› 36 MM
› 157 MM
WP 13 / Dissemination-
exploitation
(10MM)
› Total : 203 MM (21.6 MM Subcontract )
Zuhal Clarke, Infineon Bristol 10.10.2016 Page 4
OBJECTIVES of INFINEON with EMC2
Problem: Early Mixed Critical Embedded system development
Systems are evolved into the “multi-core world”, software partitioning, resource availability, bottlenecks, integration and software debug become increasingly difficult problems to solve.
Solution:
1. System representation of pre-silicon device
1. Reflecting system complexity
2. Containing safety critical mechanisms
3. Allowing software development and execution
Use Emulation Platforms
Zuhal Clarke, Infineon Bristol 10.10.2016 Page 5
Emulation Platform Concept of Emulation Platforms
1. A hardware platform where the multicore system usage of the SOC device and complexity can be demonstrated in advance of a Silicon product. Avoiding high cost of error
2. Provide an accurate software target for application developers
This is achieved by the use of FPGA (Field Programmable Gate Array) technology
A virtual SOC platform that allows mixed critically hardware and software to be emulated in advance of commitment to manufacture
5
Zuhal Clarke, Infineon Bristol 10.10.2016 Page 6
Typical Virtual Platform
6
Zuhal Clarke, Infineon Bristol 10.10.2016 Page 7
Using Emulation Platforms resolve the following issues :
System configuration flexibility
A faster “Simulation” environment x100+ w.r.t RTL simulation
Real time behaviour demonstrated – Contention, Bottlenecks and system interfaces
Critical interactions between hardware and software validated
Early software development process – significant reduction is R+D costs
Significant Risk reduction in real time multicore platform development – integration into primary application
The results can be made available much earlier than the real hardware and will benefit from a low turnaround time
The simulation speeds orders of magnitude faster than RTL simulations
Debugging/monitoring capabilities greater than development boards.
An early start to the software development process.
7
Zuhal Clarke, Infineon Bristol 10.10.2016 Page 8
IFX LIVING LAB - EMC2 DEMONSTRATION GOALS
Demonstration of Heterogeneous Multiprocessor SOC Architecture
Development of safety critical ADAS Radar Processing Architecture
Validation Fault detection Hardware and Software Methodology
8
Zuhal Clarke, Infineon Bristol 10.10.2016 Page 9
EMC2 GENERIC HARDWARE TEMPLATE
9
External Memory Controller
Configurable
Redundancy
controller /
Checker
HPS
CPU
HPS
CPU
Configurable
Redundancy
controller /
Checker
LP
CPU
LP
CPU
Configurable
Redundancy
controller /
Checker
DSP
CPU
DSP
CPU
Co
nfig
ura
ble
In
terc
on
ne
cts
e.g
. b
usse
s w
ith
Co
nfig
ura
ble
Arb
itra
tio
n lo
gic
(RE-) Configurable
logic area for I/O
and or
data Processing
(FPGA)
DSP
DSP
DSP
Co
nfig
ura
ble
da
taflo
w
Inte
rco
nn
ect
I/O
Co
mp
on
en
ts
Multi Purpose Memory Blocks
Zuhal Clarke, Infineon Bristol 10.10.2016 Page 10
IFX Hardware / Software Application Mapping
1
0
External Memory Controller
Configurable
Redundancy
controller /
Checker
HPS
CPU
HPS
CPU
Configurable
Redundancy
controller /
Checker
LP
CPU
LP
CPU
Co
nfig
ura
ble
In
terc
on
ne
cts
e.g
. b
usse
s w
ith
Co
nfig
ura
ble
Arb
itra
tio
n lo
gic
(RE-) Configurable
logic area for I/O
and or
data Processing
(FPGA)
I/O
Co
mp
on
en
ts
Multi Purpose Memory Blocks
Tricore + FPGA Fault
Detection SW
Tricore + FPGA
Processing Configuration
SW Radar Processing
Accelerator HW
Radar Processing
Data Memory
Zuhal Clarke, Infineon Bristol 10.10.2016 Page 11
OVERVIEW OF FPGA PLATFORM
1
1
AURIX
TC29x/TC39x
ZYNC
Kintex
BUS
Bridge
RADAR
Playback
HSSL
(TC39X)Camera
Radar
EBU
HSSL
Clock
Distibution
PCI ETH HDMI
SPI
SPI
Power
Distribution
CAN
ETH
FLEX
GTM
QSPI
ASI L CC
ASIL D
QM
Vehicle Safety Goal
CAN
Zuhal Clarke, Infineon Bristol 10.10.2016 Page 12
HARDWARE UPGRADES
To use application boards to capture radar data in real time.
To replay radar & Visual data, captured from vehicles or fixed objects, under lab conditions
40MS/channel radar data at 16 bit/channel with up to 8 channels.
validating Radar processing upgrades against “Real world” data sets.
1
2
Zuhal Clarke, Infineon Bristol 10.10.2016 Page 13
HARDWARE VALIDATION
Firmware ensures configure connection to FPGA
Data sets are register sets are transferred to FPGA under control from Matlab
Data is processed by FPGA hardware units.
Matlab compares hardware results against Model results
1
3
Zuhal Clarke, Infineon Bristol 10.10.2016 Page 14
HARDWARE VALIDATION
1
4
Zuhal Clarke, Infineon Bristol 10.10.2016 Page 15
Safety Measures – Fault Injection & Detection
Firmware provide schedule for data sets for SPU processing.
Data sets ensure high level of coverage and fault sensitivity
CRC provides data and register paths for error detection
Chipscope Virtual I/O is used to model hardware ‘stuck at’ fault.
1
5
Zuhal Clarke, Infineon Bristol 10.10.2016 Page 16
FAULT INSERTION & DETECTION
1
6
Software
Debugger
Aurix
Microcontroller
Radar Data
Processing
FPGA
Control
Firmware
Chipscope
Fault Insertion
Fault log
Zuhal Clarke, Infineon Bristol 10.10.2016 Page 17
To support physical vehicle systems in development – at customer or partner site
Understanding risks in implementing and interfacing with real components
Build up a durable and realistic Test Environment and explore risks in verification and validation of system operation
Test real-time response of Safety Mechanisms and interference from non-critical applications
Built a Reference for Safety Performance Measures providing basis for certification
Exercise Safety Measures and feedback for Hardware Design Changes
Exercise Safety Measures and feedback for embedded Software Development
Speed up System SW development at the customer site prior to Silicon release
1
7
Conclusion