18
ELECTRONICS II VLSI DESIGN FALL 2013 LECTURE 4 INSTRUCTOR: L.M. HEAD, PhD ELECTRICAL & COMPUTER ENGINEERING ROWAN UNIVERSITY

ELECTRONICS II VLSI DESIGN FALL 2013 LECTURE 4 INSTRUCTOR: L.M. HEAD, PhD ELECTRICAL & COMPUTER ENGINEERING ROWAN UNIVERSITY

Embed Size (px)

Citation preview

Page 1: ELECTRONICS II VLSI DESIGN FALL 2013 LECTURE 4 INSTRUCTOR: L.M. HEAD, PhD ELECTRICAL & COMPUTER ENGINEERING ROWAN UNIVERSITY

ELECTRONICS II VLSI DESIGNFALL 2013

LECTURE 4INSTRUCTOR: L.M. HEAD, PhDELECTRICAL & COMPUTER ENGINEERINGROWAN UNIVERSITY

Page 2: ELECTRONICS II VLSI DESIGN FALL 2013 LECTURE 4 INSTRUCTOR: L.M. HEAD, PhD ELECTRICAL & COMPUTER ENGINEERING ROWAN UNIVERSITY

MOSFET Symbols

Page 3: ELECTRONICS II VLSI DESIGN FALL 2013 LECTURE 4 INSTRUCTOR: L.M. HEAD, PhD ELECTRICAL & COMPUTER ENGINEERING ROWAN UNIVERSITY

Cross-section used to identify capacitances.

Page 4: ELECTRONICS II VLSI DESIGN FALL 2013 LECTURE 4 INSTRUCTOR: L.M. HEAD, PhD ELECTRICAL & COMPUTER ENGINEERING ROWAN UNIVERSITY

Accumulation

Page 5: ELECTRONICS II VLSI DESIGN FALL 2013 LECTURE 4 INSTRUCTOR: L.M. HEAD, PhD ELECTRICAL & COMPUTER ENGINEERING ROWAN UNIVERSITY

Depletion – no channel

poly

SiO2

P-type substrate

GND

V << Vth

Depletion region

Page 6: ELECTRONICS II VLSI DESIGN FALL 2013 LECTURE 4 INSTRUCTOR: L.M. HEAD, PhD ELECTRICAL & COMPUTER ENGINEERING ROWAN UNIVERSITY

Depletion – sub threshold channel

Page 7: ELECTRONICS II VLSI DESIGN FALL 2013 LECTURE 4 INSTRUCTOR: L.M. HEAD, PhD ELECTRICAL & COMPUTER ENGINEERING ROWAN UNIVERSITY

Inversion

Page 8: ELECTRONICS II VLSI DESIGN FALL 2013 LECTURE 4 INSTRUCTOR: L.M. HEAD, PhD ELECTRICAL & COMPUTER ENGINEERING ROWAN UNIVERSITY

Capacitance to ground

Page 9: ELECTRONICS II VLSI DESIGN FALL 2013 LECTURE 4 INSTRUCTOR: L.M. HEAD, PhD ELECTRICAL & COMPUTER ENGINEERING ROWAN UNIVERSITY

MOSFET Capacitance Model

Page 10: ELECTRONICS II VLSI DESIGN FALL 2013 LECTURE 4 INSTRUCTOR: L.M. HEAD, PhD ELECTRICAL & COMPUTER ENGINEERING ROWAN UNIVERSITY

Threshold Voltage

Page 11: ELECTRONICS II VLSI DESIGN FALL 2013 LECTURE 4 INSTRUCTOR: L.M. HEAD, PhD ELECTRICAL & COMPUTER ENGINEERING ROWAN UNIVERSITY

Calculating the Threshold Voltage1. Develop the depletion region

2. Create a channel at the gate oxide/substrate interface

3. Account for any source to body voltage

4. Neutralize defect charge

5. Neutralize material dependent potential difference

'

'

ox

bBC C

QV Begin with the definition of voltage due

to a charge stored on a capacitor.

+Qb’ is the charge on the gate and -Qb’ is the charge under the gate oxide.

Page 12: ELECTRONICS II VLSI DESIGN FALL 2013 LECTURE 4 INSTRUCTOR: L.M. HEAD, PhD ELECTRICAL & COMPUTER ENGINEERING ROWAN UNIVERSITY

Calculating the Threshold Voltage

i

afp

a

fpssi

d

n

NkTV

where

qN

VVX

ln

2

From these equations:

fpsAsidAb VVqNXqNQ 2'

If the surface potential, Vs is equal to the electrostatic potential in the semiconductor bulk there is no charge stored in a depletion region. As Vs increases, the depletion region grows.

First, we determine the charge in the depletion region.

Page 13: ELECTRONICS II VLSI DESIGN FALL 2013 LECTURE 4 INSTRUCTOR: L.M. HEAD, PhD ELECTRICAL & COMPUTER ENGINEERING ROWAN UNIVERSITY

fpAsibo VqNQ 22'

Next, we determine the additional charge due to the channel.

Vs increases with an increase in VGS. When VS reaches -Vfp negative charge has accumulated at the oxide semiconductor interface. In fact, at that point the interface area (channel) is as n-type as the bulk semiconductor is p-type.

Taking into consideration any source to body potential:

If the body of the MOSFET is not tied to the source, the potential between the interface and the bulk is not only dependent upon VGS. Now the charge under the gate totals,

SBfpAsib VVqNQ 22'

Page 14: ELECTRONICS II VLSI DESIGN FALL 2013 LECTURE 4 INSTRUCTOR: L.M. HEAD, PhD ELECTRICAL & COMPUTER ENGINEERING ROWAN UNIVERSITY

CBox

bBC VV

C

QV

'

'

fpC VV 2fp

ox

bB VC

QV 2

'

'

The total potential across the gate-oxide capacitance:

Since the change in voltage to obtain the channel is:

Then*,

*Remember, Vfp is a negative number!

An additional source of charge is defects at the oxide interface:

fpox

ssbB V

C

QQV 2

'

''

Page 15: ELECTRONICS II VLSI DESIGN FALL 2013 LECTURE 4 INSTRUCTOR: L.M. HEAD, PhD ELECTRICAL & COMPUTER ENGINEERING ROWAN UNIVERSITY

And finally, there is the inherent potential difference between the gate and the substrate:

i

A

i

polyD

fpGms

n

N

q

kT

n

N

q

kT

VVV

lnln ,

Page 16: ELECTRONICS II VLSI DESIGN FALL 2013 LECTURE 4 INSTRUCTOR: L.M. HEAD, PhD ELECTRICAL & COMPUTER ENGINEERING ROWAN UNIVERSITY

fpSBfpox

Asi

ox

ssbofpms

ox

bbo

ox

ssbofpms

msfpox

ssbTHN

VVVC

Nq

C

QQVV

C

QQ

C

QQVV

VVC

QQV

222

2

2

2

''

''

'

''

'

''

'

''

Combining these components to get the final version of the threshold voltage:

fpSBfpTHNTHN

ox

Asi

ox

ssbofpmsTHN

VVVVV

C

Nq

C

QQVVV

22

2

2

0

'

'

''

0

Note error in equation 6.17

Page 17: ELECTRONICS II VLSI DESIGN FALL 2013 LECTURE 4 INSTRUCTOR: L.M. HEAD, PhD ELECTRICAL & COMPUTER ENGINEERING ROWAN UNIVERSITY

Now we come to the I-V Characteristics

Page 18: ELECTRONICS II VLSI DESIGN FALL 2013 LECTURE 4 INSTRUCTOR: L.M. HEAD, PhD ELECTRICAL & COMPUTER ENGINEERING ROWAN UNIVERSITY