Electronics for You Projects 2001

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2001Electronics For

Youissues

I D E A S

P R O J E C T S&&&EFYMore than 90 fully tested

and ready-to-useelectronics circuits

01V O L U M E

C o n t e n t s 2001JANUARY 2001

FEBRUARY 2001

CIRCUIT IDEAS

1) ELECTRONIC STARTER FOR SINGLE-PHASE MOTORS ------------------------------------------------------------- 7

2) MODEM 'ON'/'OFF' INDICATOR ------------------------------------------------------------------------------------- 8

3) TOUCH-SELECT AUDIO SOURCE ----------------------------------------------------------------------------------- 9

4) PRECISION ATTENUATOR WITH DIGITAL CONTROL -------------------------------------------------------------- 10

5) PRECISION AMPLIFIER WITH DIGITAL CONTROL---------------------------------------------------------------- 11

6) RANDOM NUMBER GENERATOR BASED GAME ------------------------------------------------------------------- 12

CONSTRUCTION PROJECTS

1) BUILD YOUR OWN PENTIUM III PC (PART-I) ------------------------------------------------------------------- 14

2) AUTOMATIC ROOM LIGHT CONTROLLER -------------------------------------------------------------------------- 21

CIRCUIT IDEAS

1) 9-LINE TELEPHONE SHARER ------------------------------------------------------------------------------------- 27

2) ELECTRONIC CARD LOCK SYSTEM -------------------------------------------------------------------------------- 28

3) PULSED OPERATION OF A CW LASER DIODE -------------------------------------------------------------------- 29

4) GENERATION OF 1-SEC. PULSES SPACED 5-SEC. APART -------------------------------------------------------- 31

5) HIGH-/LOW-VOLTAGE CUTOUT WITH TIMER --------------------------------------------------------------------- 32


1) BUILD YOUR OWN PENTIUM III PC (PART-II) ------------------------------------------------------------------ 34

2) INTELLIGENT WATER LEVEL CONTROLLER ----------------------------------------------------------------------- 40

3) A UNIQUE LIQUID LEVEL INDICATOR ---------------------------------------------------------------------------- 43

CIRCUIT IDEAS

1) AUTOMATIC HEAT DETECTOR ------------------------------------------------------------------------------------- 48

2) MUSICAL 'TOUCH' BELL ------------------------------------------------------------------------------------------- 49

3) NON-CONTACT LIQUID-LEVEL CONTROLLER --------------------------------------------------------------------- 50

4) AC MAINS PHASE-SEQUENCE INDICATOR ------------------------------------------------------------------------ 52

5) HIGH-POWER BICYCLE HORN ------------------------------------------------------------------------------------ 54

6) LUXURIOUS TOILET/BATHROOM FACILITY ---------------------------------------------------------------------- 55


1) INTERFACE YOUR PRINTER WITH 8085 MICROPROCESSOR ---------------------------------------------------- 58

2) MORSE PROCESSOR ----------------------------------------------------------------------------------------------- 63

CIRCUIT IDEAS

1) EEPROM W27C512 (WINBOND) ERASER ------------------------------------------------------------------------- 74

2) INTELLIGENT ELECTRONIC LOCK --------------------------------------------------------------------------------- 75

3) STABLE 455KHZ BFO FOR SSB RECEPTION ---------------------------------------------------------------------- 78

4) AUTO SHUT-OFF FOR CASSETTE PLAYERS AND AMPLIFIERS---------------------------------------------------- 81

5) HOUSE SECURITY SYSTEM ---------------------------------------------------------------------------------------- 84

6) SIMPLE WATER-LEVEL INDICATOR-CUM-ALARM ----------------------------------------------------------------- 87


1) ACCESS-CONTROL SYSTEM ---------------------------------------------------------------------------------------- 90

2) TELEPHONE LINE-INTERFACED GENERIC SWITCHING SYSTEM (PART-I) --------------------------------------- 87

APRIL 2001

MARCH 2001

CIRCUIT IDEAS

1) PRECISION INDUCTANCE AND CAPACITANCE METER ------------------------------------------------------------ 93

2) UNDER-/OVER-VOLTAGE BEEP FOR MANUAL STABILISER ------------------------------------------------------ 95

3) ULTRA-SENSITIVE SOLIDSTATE CLAP SWITCH ------------------------------------------------------------------- 97

4) 15-STEP DIGITAL POWER SUPPLY -------------------------------------------------------------------------------- 98

5) MICROPHONE FOR COMPUTER -----------------------------------------------------------------------------------100


1) PROGRAMMABLE MELODY GENERATOR (PART-I) ---------------------------------------------------------------102

2) TELEPHONE LINE-INTERFACED GENERIC SWITCHED SYSTEM (PART-II) --------------------------------------110

CIRCUIT IDEAS

1) VERSATILE ZENER DIODE TESTER -------------------------------------------------------------------------------117

2) DTMF PROXIMITY DETECTOR -------------------------------------------------------------------------------------119

3) STEPPER MOTOR CONTROL ---------------------------------------------------------------------------------------120

4) LOW-COST INTERCOM --------------------------------------------------------------------------------------------121

5) HIGH-POWER CAR BATTERY ELIMINATOR ----------------------------------------------------------------------122

6) AUTOMATIC PLANT IRRIGATOR ----------------------------------------------------------------------------------123


1) PROGRAMMABLE MELODY GENERATOR (PART-II) --------------------------------------------------------------125

2) AUTO CONTROL FOR 3-PHASE MOTORS -------------------------------------------------------------------------129

CIRCUIT IDEAS

1) PC-BASED DIAL CLOCK-CUM-ELECTRONIC ROULETTE ----------------------------------------------------------136

2) SIMPLE TELEPHONE RING TONE GENERATOR -------------------------------------------------------------------138

3) DUAL-INPUT HIGH-FIDELITY AUDIO MIXER -------------------------------------------------------------------139

4) ANTI-THEFT SECURITY FOR CAR AUDIOS -----------------------------------------------------------------------140

5) UNIPOLAR/BIPOLAR TRIANGULAR AND BIPOLAR SQUARE WAVE GENERATOR ------------------------------141


1) TELEPHONE REMOTE CONTROL ----------------------------------------------------------------------------------143

2) MICROCONTROLLER-BASED SCHOOL TIMER --------------------------------------------------------------------146

CIRCUIT IDEAS

1) LONG-RANGE CORDLESS BURGLAR ALARM ---------------------------------------------------------------------153

2) WATER-LEVEL CONTROLLER --------------------------------------------------------------------------------------154

3) INVISIBLE BROKEN WIRE DETECTOR ---------------------------------------------------------------------------156

4) PC-BASED MULTI-MODE LIGHT CHASER ------------------------------------------------------------------------157

5) FUSE STATUS INDICATORS FOR POWER-SUPPLIES -------------------------------------------------------------159


1) DIGITAL CAPACITANCE-CUM-FREQUENCY METER ---------------------------------------------------------------162

2) FLUID-LEVEL CONTROLLER WITH INDICATOR ------------------------------------------------------------------166

CIRCUIT IDEAS

1) A HIERARCHICAL PRIORITY ENCODER --------------------------------------------------------------------------171

2001C o n t e n t sMAY 2001

JUNE 2001

JULY 2001

AUGUST 2001

SEPTEMBER 2001

2) DIGITAL MAINS VOLTAGE INDICATOR ---------------------------------------------------------------------------173

3) ELECTRONIC DICE ------------------------------------------------------------------------------------------------175

4) LIGHT-OPERATED ORGAN ----------------------------------------------------------------------------------------177


1) MGMA-A MIGHTY GADGET WITH MULTIPLE APPLICATIONS ---------------------------------------------------179

2) TRAFFIC AND STREET LIGHT CONTROLLER ---------------------------------------------------------------------183

CIRCUIT IDEAS

1) DIGITAL FAN REGULATOR ----------------------------------------------------------------------------------------192

2) STEREO TAPE HEAD PREAMPLIFIER FOR PC SOUND CARD ----------------------------------------------------194

3) RUNNING LIGHTS AND RUNNING HOLES -----------------------------------------------------------------------195

4) HEART BEAT MONITOR -------------------------------------------------------------------------------------------197

5) 12V, 3A POWER SUPPLY -----------------------------------------------------------------------------------------198

6) A SIMPLE TRANSISTOR TESTER ---------------------------------------------------------------------------------199


1) LEAD-ACID BATTERY CHARGER WITH ACTIVE POWER CONTROL ----------------------------------------------201

2) MICROCONTROLLER-BASED DIGITAL CLOCK --------------------------------------------------------------------204

CIRCUIT IDEAS

1) SPELLER EFFECT SIGN DISPLAY ---------------------------------------------------------------------------------210

2) DARKROOM TIMER -----------------------------------------------------------------------------------------------211

3) LONG-RANGE TARGET SHOOTER ---------------------------------------------------------------------------------212

4) ACTIVE SHORTWAVE ANTENNA ----------------------------------------------------------------------------------214

5) POWER SUPPLY FOR WALKIE-TALKIE ---------------------------------------------------------------------------215

6) HIGH-PERFORMANCE INTERRUPTION DETECTOR ---------------------------------------------------------------216


1) AMPLITUDE MEASUREMET OF SUB-MICROSECOND PULSES ---------------------------------------------------218

2) AUTOMATIC SUBMERSIBLE PUMP CONTROLLER ----------------------------------------------------------------221

CIRCUIT IDEAS

1) DIGITAL RELAY TESTER FOR RAX AND MAX --------------------------------------------------------------------226

2) DECORATIVE SIGNBOARD ----------------------------------------------------------------------------------------228

3) OVERLOAD PROTECTOR WITH RESET BUTTON ------------------------------------------------------------------230

4) FASTEST FINGER FIRST INDICATOR -----------------------------------------------------------------------------231

5) CONDENSER MIC AUDIO AMPLIFIER ----------------------------------------------------------------------------232

6) SMOKE ALARM ---------------------------------------------------------------------------------------------------233


1) TRANSISTOR CURVE TRACER ------------------------------------------------------------------------------------235

2) TRIPPING-SEQUENCE RECORDER-CUM-INDICATOR -------------------------------------------------------------241

2001C o n t e n t s

OCTOBER 2001

NOVEMBER 2001

DECEMBER 2001

January

2001

Circuit Ideas

2001

C I R C U I T I D E A S

contact ratings of relay RL3 should be 10to 15 amperes.

Transformer X1 can be wound us-ing any suitable size CRGO core. (Onecan use a burntout transformer core as

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ELECTRONICS FOR YOU� ❚❚❚❚❚ � JANUARY 2001

S.C. DWIVEDI

A novel single-phase electronicstarter circuit meant for 0.5HPand 1HP motors is presented

here. It incorporates both overload andshort-circuit protections. A special cur-rent-sensing device has been added inthis starter to sense the current beingdrawn by the motor.

If the motor jams due to bearing fail-ure or defect in the pump or any otherreason, it would draw much higher cur-rent than its normal rated current. Thiswill be sensed by the current-sensingdevice, which will trip the circuit andprotect the motor. Some other reasonsfor the motor drawing higher currentare as follows:

(a) Windings damaged or short-cir-cuit between them.

(b) Shorting of motor terminals bymistake.

(c) Under voltage or single phasingoccuring in the mains supply source(normally, a 440V AC, 3-phase with neu-tral four-wire system).

The main components used in thecircuit comprise a specially wound sens-ing transformer X1, another locallyavailable step-down transformer X2,single-changeover relay RL1, twodouble-changeover relays (RL2 andRL3), and other discrete componentsshown in the figure. The mains supplyto the motor is routed in series withthe primary of transformer X1 via nor-mally-open contacts of relay RL3. Theprimary of transformer X1 is connectedin the neutral line.

To switch on the supply to the mo-tor, switch S1 is to be pressed momen-tarily, which causes the supply path tothe primary of transformer X2 to becompleted via N/C contacts of relay RL1.Relay RL2 gets energised due to theDC voltage developed across capacitorC2 via the bridge rectifier. Once therelay energises, its N/O contacts RL2(a)provide a short across switch S1 andsupply to the primary of transformerX2 becomes continuous, and hence re-

lay RL2 latches even if switch S1 is sub-sequently opened. The other N/O con-tacts RL2(b) of relay RL2, onenergisation, connect the voltage devel-oped across capacitor C2 to relay RL3,which thus energises and completes thesupply to the motor, as long as currentpassing through primary of transformerX1 is within limits (for a 1HP motor).

When the current drawn by motorexceeds the limit (approx. 5A), the volt-age developed across the secondary oftransformer X2 is sufficient to energiserelay RL1 and trip the supply to relaysRL2 and RL3, which was passing viathe N/C contact of relay RL1. As a re-sult, the supply to the motor also trips.

The contact rating for relays RL1and RL2 should be 5 amperes, while

SARAT CHANDRA DAS

well.) The primary comprises 30 to 31turns for use with 1HP motor and addi-tional eight turns, if you are using a0.5HP motor. Fuses F1 and F2 are kit-kat type. The ‘on’ pushbutton is nor-mally-‘off’ type, while ‘off’ pushbuttonS2 is of normally-‘on’ type. CapacitorsC1 and C2, apart from smoothing therectified output, provide necessary de-lay during energisation and de-energisation of relays. Diodes across re-lays are used for protection as free-wheeling diodes.

Starters for 0.5HP and 1HP motorsare not easily available in the market.Users are therefore compelled to use10-amp rated circuit breaker for suchmotors. A mechanical starter or autostarter would turn out to be costlierthan the circuit given here, which worksvery reliably. Parts used in this circuitare easily available in most of the localmarkets.


eration of the gadget. For this, first switchon the supply to the gadget and then
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S.C. DWIVEDI

Here is an interesting, low com-ponent-count, and easy-to-buildelectronic circuit for the

Internet surfers. This circuit, using twoLEDs, indicates the modem status, i.e.whether it is in use or not.

The incoming telephone line termi-nating on a master phone is shunted bya metal oxide varistor.

The circuit is configured around thepopular timer chip NE555N, which iswired as an astable multivibrator. Whenpower is applied to the circuit, theastable starts working as usual. How-ever, LEDs D2 and D3 connected to itsoutput pin 3 would not glow as transis-tor T1 is in off condition and hence re-sistor R4’s bottom end is hanging in highimpedance state.

However, when the modem is work-ing, voltage drop across preset VR1illuminates the LED inside the opto-coupler (IC2). As a result, transistorT1 gets sufficient base-bias through ac-

tivated transistor inside opto-couplervia resistor R3. Consequently, LEDs D1and D2 start blinking at the bistableIC1’s frequency determined by the val-

ues of resistors R1 and R2 and capaci-tor C1.

A 9V, 0.5A AC adapter can be usedto power the circuit. Finally, one minoradjustment is required for successful op-

switch ‘on’ the modem. Now adjust thewiper of preset VR1 very slowly until theLEDs start blinking. Memorise the wiperposition and fix it in this position using agood-quality glue/compound.

After construction, fix the completecircuit in a suitable and attractive cabi-net with one LED in its front panel. Keep

the whole unit near the modem and fitanother LED near the master telephonewith the label ‘Modem in Use’.

T.K. HAREENDRAN


input of power amplifier. This is indicated
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S.C. DWIVEDI

Often you need to connect out-put from more than one source(preamplifier) such as tape re-

corder/player and CD (compact disc)player to audio power amplifier. Thisneeds disconnecting/con-necting wires when youwant to change the source,which is quite cumber-some and irritating.

Here is a circuit thathelps you choose betweentwo stereo sources bysimple touch of your hand.This circuit is so compactthat it can be fixed withinthe audio power amplifiercabinet and can use thesame power supply source.

The circuit uses justtwo CMOS ICs and a fewother componenets. TheICs used are MC14551/CD4551 (quad 2-channel analogue multiplexer) andCD4011 (quad 2-input NAND gate). Whentouch-plate S1 is touched (its two platesare to be bridged using a fingertip), gate

by lighting of LED2.Pin 9 is the control pin of IC2. In the

circuit, the state of multiplexer switchesis shown with pin 9 ‘high’ (CD source se-lected). When pin 9 is pulled ‘low’, all theswitches within the multiplexer changeover to the alternate position to selecttape player as source.

EFY Lab note. Although one can con-nect pin 7 (VEE) of IC2 to ground, but for

operation with preamplifier signals goingabove and below ground level, one mustconnect it to a negative voltage (say, –1Vto –1.5V) to avoid distortion.

N1 output (IC1, pin 3) goes high whilethe output of gate N2 at pin 4 goes low.This causes selection of CD outputs beingconnected to the power amplifier input,which is indicated by lighting of LED1.

When touch-plate S2 is touched, theoutputs of gates N1 and N2 toggle. Thatis, IC2 pin 3 is pulled ‘low’ while its pin 4goes ‘high’. This results in selection of taperecorder outputs being connected to the

SARAVANAN J.


S.C. DWIVEDI The following design considerationsshould be kept in mind:

(a) Input: 500V max

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When instruments are designed,an analogue front-end is es-sential. Further, as most equip-

ment have digital or microcont-roller in-terface, the analogue circuit needs to havedigital control/access.

The circuit of a programmable attenu-ator with digital control is described here,where digital control can be a remote dipswitch, or CMOS logic outputs of a de-cade counter (having binary equivalentweight of 1, 2, 4, and 8, respectively), orI/O port of a microcontroller like 80C31.

The heart of this circuit is the popu-lar OP07 op-amp with ultra-low offset inthe inverting configuration. A dual, 4-channel CMOS analogue multiplexerswitch CD4052 enables the change ingain. An innovative feature of the circuitis that the ‘on’ resistance (around 100ohms) of CD4052 switch is bypassed sothat no error is introduced by its use.

Resistors R1 to R6 used in the circuitshould be of 0.1 per cent tolerance, 50ppm (parts per million) if you use 3½-

digit DPM, i.e. ±1999 counts (approx. 11bits). But for 4½-digit DPM (approx. 14bits), you may need to have trimpots (e.g.replace 1k-ohm resistor R6 by a fixed 900-ohm resistor in series with a 200-ohmtrimpot) to replace R3, R4, R5, and R6

Truth Table (Control input VS attenuation)X,Y (ON-switch (2) (1) GainPair) B A (Attenuation)X0,Y0 0 0 1/1000X1,Y1 0 1 1/100X2,Y2 1 0 1/10X3,Y3 1 1 1

gain selection resistors for proper calibra-tion to required accuracy. However, fortesting or trials, use 1per cent 100ppm MFR resistors. Theexpected errors will be around 1 per cent.

To keep parts count (hence cost) to aminimum, the common or ground is usedas the positive input terminal and oneend of resistor R1 as the negative. This isso because the op-amp inverts the polar-ity as it is used in inverting configura-tion. This does not matter as the equip-ment will be isolated by the power supplytransformer and all polarities are rela-tive. In case you want the common to bethe negative, you will have to add somestages (IC4 and IC5 circuitry shown inprecision amplifier circuit described later).

The OP07 pinout is based on stan-dard single op-amp 741. Any otherop-amp like CA3140, TLO71, or LF351can be used but with offset errors in ex-cess of 1 per cent, which is not tolerablein precision instrumentation.

The OP07 has equivalent ICs like

µA714 and LM607 having ultra-low off-set voltage (<100µV), low input biascurrent (<10nA), and high input imped-ance (>100M), which are the key require-ments for a good instrumentation op-ampfor use with DC inputs.

Since ¼W resistors can withstand upto 250V, resistors R1 and R2 in series areused for 1 meg-ohm with 500V (max) in-put limit. These resistors additionallylimit the input current as well. DiodesD1 and D2 clamp the voltage across in-put of op-amp to ±0.5V, thereby protect-ing the op-amp.

(b) OutputThe output can be connected to a

7107/7135-based DPM or any other ana-logue-to-digital converter or op-amp stage.Use a buffer at the output if the outputhas to be loaded by a load less than 1meg-ohm.

Use an inverting buffer if input leadshave to have polarity where ground is theinverting terminal. (For details, see nextcircuit.)

(c) CD4052 CMOS switchThe on-resistance (100-ohm approx.)

comes in series with the op-amp outputsource resistance, which produces no er-ror at output.

Caution. The circuit does not isolate,it only attenuates. When high voltage ispresent at its input, do not touch anypart of the circuit.

(d) Digital control options(i) A and B can be controlled by I/O

port of a microcontroller like 80C31 sothat the controller can control gain.

(ii) A and B can be given to counterslike 4029/4518 to scroll gain digitally.

(iii) A and B can be connected to DIPswitch.

(iv) A and B can be connected to athumbwheel switch.

Notes. 1. Digital input logic 0 is 0Vand logic 1 is 5V.

2. All resistors are metal film resis-tors (MFR) with 1% tolerance, unlessspecified otherwise.

3. C2 and C3 are ceramic disk capaci-tors of 0.1µF = 100n value.

ANANTHA NARAYAN


Gains greater than 100 may not bepractical because even at gain value of100 itself, a 100µV offset will work outto be around 10 mV at the output (100µVx 100). This can be trimmed using the

S.C. DWIVEDI
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puts are not loaded on measurement.The user can terminate the inputs withresistance of his choice (such as 10 meg-ohm or 1 meg-ohm) to avoid floating ofthe inputs when no measurement is be-ing made.

IC5 is used as an inverting buffer torestore polarity of the input while IC4is used as buffer at the output ofCD4052, because loading it by resistanceof value less than 1 meg-ohm will causean error. An alternative is to makeR7=R8=1 meg-ohm and do away withIC4, though this may not be an idealmethod.

offset null option in the OP07, connect-ing a trimpot between pins 1 and 8, andconnecting wiper to +5V supply rails.For better performance, use ICL7650(not pin-compatible) in place of OP07and use ±7.5V instead of ±5V supply.

Eight steps for gain or attenuationcan be added by using two CD4051 andpin 6 inhibit on CD4051/52. More stepscan be added by cascading manyCD4051, or CD4052, or CD4053 ICs, aspin 6 works like a chip select.

Some extended applications of thiscircuit are given below.

1. Error correction in transduceramplifiers by correcting gain.

2. Autoranging in DMM.3. Sensor selection or input type se-

lection in process control.4. Digitally preset power supplies or

electronic loads.5. Programmable precision mV or

mA sources.6. PC or microcontroller or micro-

processor based instruments.7. Data loggers and scanners.

Truth Table (Control Input vs Gain)X,Y (On-switch (2) (1) GainPair) B A (Av.)X0,Y0 0 0 1/10X1,Y1 0 1 1X2,Y2 1 0 10X3,Y3 1 1 100

This circuit is similar to the pre-ceding circuit of the attenuator.Gain of up to 100 can be

achieved in this configuration, which isuseful for signal conditioning of low out-put of transducers in millivolt range.

The gain selection resistors R3 toR6 can be selected by the user andcan be anywhere from 1 kilo-ohm to 1meg-ohm. Trimpots can be used for ob-taining any value of gain required bythe user. The resistor values shown inthe circuit are for decade gains suitablefor an autoranging DPM.

Resistor R1 and capacitor C1 reduceripple in the input and also snub tran-sients. Zeners Z1 and Z2 limit the inputto ±4.7V, while the input current is lim-ited by resistor R1. Capacitors C2 andC3 are the power supply decoupling ca-pacitors.

Op-amp IC1 is used to increase theinput impedance so that very low in-

ANANTHA NARAYAN


RUPANJANA

(CD4033 decade upcounter cum 7-segmentdecoder). In conjunction with three 7-seg-ment displays (DIS1 to DIS3), these form

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This electronic game is simulationof one-arm bandit game. Elec-tronics hobbyists will find it very

interesting. When toggle switch S1 isin ‘run’ position, all segments of 7-seg-ment displays (DIS1 through DIS3) willlight up. On turning toggle switch S1from ‘run’ to ‘stop’ position, displayeddigits will continue advancing and thefinal display is unpredictable. Thus thefinal number displayed in DIS1 throughDIS3 is of random nature. The speedwith which the number in 7-segmentdisplay keeps changing on flippingswitch S1 from ‘run’ to ‘stop’ conditionslowly decays before stopping with arandom number display.

To play this game, one has to obtainthree identical numbers in displaysDIS1 through DIS3. The contestantwould score 1 (one) point if he managesto get a final display of ‘000’, 2 pointsfor getting ‘111’ display, 3 points for‘222’,… and so on—up to ten points for‘999’. He should try to score maximumpossible points in fixed numbers of at-tempts (say, 20 to 25 attempts).

Apart from using this circuit asa game for entertainment, one can useit as random number generator forany other application as well. The de-cay time with the given componentvalues is around 15 seconds before thedisplay could stop at a final randomnumber.

The circuit comprises clock oscilla-tor built around NE555 timer IC4,three-stage clock pulse counter built us-ing three CD4033 ICs (IC1 to IC3), andthree 7-segment LED displays (DIS1 toDIS3).

In clock oscillator circuit, NE555timer IC4 is used in a similar way as afree-running astable multivibrator, theonly difference being the additional ca-pacitor C1 introduced between pin No.7 of IC4 and junction of resistors R22and R24. When toggle switch S1 is in‘run’ position, both terminals of capaci-

K. UDHAYA KUMARAN

tor C1 are shorted by switch S1 andtimer IC4 works as a free-runningastable multivibrator. The operating fre-quency is in the vicinity of 35 kHz,determined by the value of timing com-ponents.

When toggle switch S1 is flippedfrom ‘run’ to ‘stop’ position, capacitorC1 is introduced in the discharge pathof pin No. 7 of IC4 and junction of re-sistors R22 and R24. At the same time,capacitor C4 comes in parallel with tim-ing capacitor C3 to change the operat-ing frequency of the astable fromaround 35 kHz to around 65 Hz. Nowcapacitor C1 slowly starts charging asit is connected in the discharge path ofthe timing capacitors C3 and C4. Theclock frequency of IC4 gradually reducesand after 15 seconds, when capacitorC1 is sufficiently charged, the oscillat-

ing frequency gradually drops and fi-nally it stops oscillating. Thus, pin 3 ofIC4 becomes low.

Second part of the circuit comprisesthree cascaded ICs, IC1 through IC3

a 3-digit clock counter. The clock count-ing speed is dependant upon the clockpulse frequency of IC4. It is connected toclock input pin 1 of IC1 while chip enablepin 2 of IC1 to IC3 are held low. Thus allclock counter ICs advance by 1 for everypositive clock transition. Reset pin 15 ofall counter ICs is held low through resis-tor R25. Thus reset facility is not used inthis circuit.

Due to persistence of vision, one can-not distinguish 0-9 counting in DIS1 toDIS3 when the clock frequency is high.All 7-segment displays appear to showdigit 8, while the red LED1 remains litcontinuously, indicating clock counteris in running condition.

On sliding toggle switch S1 from‘run’ to ‘stop’ position, the countingspeed of individual digits falls immedi-ately due to the clock frequency chang-ing to around 65 Hz. Now, the count-ing speed will be 65 Hz for DIS3, 6.5Hz for DIS2, and 0.6 Hz for DIS1. Thisspeed of individual digit counting slowly

decays, until the counter stops andLED1 stops blinking, and the final count(random numbers) are displayed inDIS1, DIS2, and DIS3.

Construction

2001

C O N S T R U C T I O N

til it is required for installation. Whenit is taken out from the envelope, itshould be immediately placed on a suit-able grounded conductive surface. Themotherboard itself should be held fromedges and the person taking it out

N. KUNDRA

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K.C. BHASIN AND NEERAJ KUNDRA

T he procedure presented herewould enable you to assembleyour own multimedia personal

computer. It is assumed that you havea fundamental knowledge of how a PCfunctions and some basics of electron-ics. By way of tools you only needPhilips-head and flat-blade screwdriv-ers. A simple multimeter is the onlytest equipment that you would ever re-quire during assembly, for AC and DCvoltage measurement.

All the parts needed to assemble thismultimedia PC with processor speed of700 MHz are listed under Parts List.The cost of parts may vary from dealerto dealer and also with time. The totalcost of the listed parts at current pricelevel ranges from Rs 33,000 to Rs 37,000.

It is suggested to source these itemsfrom authorised dealers who would meettheir warranty obligations. We have alsomentioned the brand names of the partsthat we used during assembly of thebasic unit. It is, however, not necessaryto use identical makes, except, of course,the main processor and themotherboard, based on identical chipsetmentioned later in this article.

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Before starting the actual assembly ofthe PC system, the following precau-tions would help you to avoid any mis-hap during the assembly process:

• While the motherboard has to befitted at a fixed place inside the PC cabi-net, the locations of add-on cards (as andwhen used) and the drives (hard diskdrive, floppy disk drive, and CD-ROMdrive) within the drives’ bay of the cabi-net can be changed within certain lim-its. But it is better to place them faraway from each other. (Of course, the

length of the cable provided for inter-connections to the motherboard or add-on cards has to be taken into account, asthere must be some slack after these areinstalled and connected.) This will im-prove the cooling and re-duce the chances of electro-magnetic interference be-tween them.

• The motherboard con-tains sensitive components,which can be easily dam-aged by static electricity.Therefore the motherboardshould remain in its origi-nal antistatic envelope un-

should wear an antistatic wrist strapthat is properly grounded. In the ab-sence of a proper wrist strap, you maymake one on your own using a peeledoff multi-strand copper cable and groundit properly. Similar handling precau-tions are also required for DIMMS andcards.

• If you are using a motherboard dif-ferent from the one mentioned in the

The authors represent a combined team fromEFY and IT Solutions (India) Pvt Ltd, New Delhi Fig. 1: Block diagram of motherboard employing 810E chipset



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Processor• Full support for the Intel Pentium III and Celeron processors using PGA370 socket.• Supports 66MHz and 100MHz bus speed including all PGA370.• Supports 133MHz bus speed (810E chipset version only).VRM 8.2 (Voltage Regulator Modules) On-board• Flexible motherboard design with on-board VRM 8.2, easy to upgrade with future processors.System Memory• A total of two 168-pin DIMM sockets (3.3V SDRAM types).• Memory size up to 512MB.• Supports SDRAM at 66/100 (PC100) MHz.• Supports symmetrical and asymmetrical DRAM addressing.• Banks of different DRAM types and depths can be mixed.System BIOS• 4-Mbit Intel Firmware hub (with security feature).• PnP, APM, ATAPI, and Windows 95/98.• Full support of ACPI & DMI.• Auto-detects and supports LBA hard disks with capacities over 8.4 GB.• Easily upgradable by end-user.On-board I/O• Supports two PCI-enhanced IDEs PIO mode 3, mode 4, and ultra DMA 33/66 channels

(optional ultra DMA 66 cable). Twin headers for four IDE devices including IDE HDDs andCDROMs.

• One ECP/EPP parallel port (via a header).• Two 16550A UART parallel port (via a header).• One floppy port. Supports two FDDs of 360KB, 720KB, 1.2MB, 1.44MB, or 2.88MB (via a

header).• Four USB ports (via a header, optional).• PS/2 mouse port (via a header, optional).• AT keyboard port (factory option for PS/2 type).• Infrared (IrDA) support.Plug-and-play• Supports plug-and-play specification 1.1.• Plug-and-play for DOS, Windows 3.X, Windows 95, as well as Windows 98.• Fully steerable PCI interrupts.On-board VGA• Hardware motion compensation for S/W MPEG2 decode (DVD).• 3-D hyper pipelined architecture.• Full 2-D hardware acceleration.• 3-D graphics visual enhancements.• Dynamic display memory (DDM) or optional 4MB display cache (810DC100 or 810E chipset

version only).• Resolution up to 1,600x1,200.• Win 95 vxd, Win 98/NT5 mini-port drivers support.• VGA port (via a header).On-board AC97 Sound• Integrated AC97 controller with standard AC97 CODEC.• Direct Sound and Sound Blaster compatible.• Full-duplex 16-bit record and playback.• PnP and APM 1.2 support.• Win 95, 98, and NT drivers ready.• Line-in, line-out, mic-in and MIDI/game port.Power Management• Supports SMM, APM and ACPI.• Break switch for instant suspend/resume on system operations.• Energy star ‘Green PC’-compliant.• WAKE-ON-LAN (WOL) header support.• External modem ring-in wake-up support.Expansion Slots• One audio modem riser (AMR).• Four PCI bus master slots (ver 2.1 compliant).

parts list, modify the guidelines men-tioned here as per the directions given inthe user’s manual (which is supplied withthe motherboard you may be using), sincethere would be some differences betweenany two makes of the motherboard.

• Start the assembly only after go-ing through this article at least once.Only when you feel at ease, start theassembly of your machine as per theguidelines included in this article andthe applicable user’s manuals.

• Never try to insert a card in PCslots or try to plug/unplug a connectorwith power supply to the PC ‘on’.

• Ensure that the mains 3-pin socketor the socket on your stabiliser/UPSthat you would be using for connectionto the SMPS of the computer and/orthe monitor is correctly wired with ‘live’line on your right hand side. To findout which line is live (phase) and whichone is neutral, use your multimeter in250V AC or higher range. The live linewill show full voltage w.r.t. neutral pinand nearly the same voltage w.r.t. theground pin, while the neutral pin (w.r.t.ground pin) would/should show verylittle voltage (less than 10V AC). Else,the mains wiring has a problem thatneeds to be set right.

• Don’t drop any screw or other con-ducting material on your PC’smotherboard as that might cause short-ing of pins/tracks and consequent dam-age when you switch it ‘on’.

• Make sure that you have a large,flat surface area to work on. That willreduce the chances of small screws etcfalling and getting lost.

• While screwing components on tothe chassis, do not use excessive forceas that may damage the screws or theirgrooves/holes.

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Some points to be noted about thePentium III processor being used hereare:

• Intel’s Pentium III processors sup-port various clock speeds from 450MHzto 933 MHz. The one meant for desktopversion goes up to 1.13 GHz. (We areusing here a 700MHz version.)

• Integrates P6 dynamic executionarchitecture and a dual independent bus(DIB) architecture.

• Has a multi transaction system bus.• Incorporates Intel’s MMX media

enhancement technology.• Supports Internet streaming

single-instruction multiple data (SIMD)extensions.

• Compared to Pentium II, it has70 new instructions, enabling advanced3-D imaging, streaming audio and video,and speech recognition.

• Has a 32k (16k for instructions andanother 16k for data) as primary (level1) non-blocking cache for rapid access tomost heavily used data. In addition, it



has 512k unified, non-blocking (level 2)cache or 256k advanced transfer cacheintegrated on die, which runs at the corefrequency of the processor with very lowmemory access time.

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While the processor is the most impor-tant part of the motherboard, themotherboard itself is the most impor-tant part of the computer system. To-gether with the chipset, it forms thebrain of your computer.

The modern motherboards do awaywith the large number of controller chipsand cards that were used in the older XTand AT versions, such as clock genera-tor, bus controller, timer/counter, moni-tor/printer adopter, FDD and HDD con-trollers, multi-I/O or super IDE control-ler card, and DMA controller. All the func-tions performed by these controllers/cards (and others) are now performed byjust two or three chips and that too atmuch higher speed.

The motherboard based on Intel’s810/810E chipset (being used in thepresent system) combines the advantageof a multimedia (full-screen, full-motionvideo with realistic graphics) and en-hanced Internet performance at a bud-get price. With this motherboard, onedoes not need separate sound, video, orgraphics enhancement cards. A blockdiagram of a motherboard employing810E chipset is shown in Fig. 1.

Key features. The main features ofthe PC Partner motherboard used in thisproject are shown in the accompanyingbox. A layout diagram showing the rela-tive position of the jumpers, connectors,major components, PCI slots, and DIMMand CPU sockets is shown in Fig. 2.

Jumper settings. Positions of vari-ous jumpers within the motherboard areshown in Fig. 3. The jumper settingsfor enabling various functions are shownin Table I. Default settings are shownwith an asterisk mark. (Note. Leave allthese jumpers in their default settingpositions for the present project. The pro-cessor speed setting is to be done throughCMOS setup as indicated later.)

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Verifying components. First, carry outa physical check of all the items as per theparts list to ensure that there are no ap-

JP35, JP36 - On Board AC97 Codec Sound

JP35 JP36 Function1 1-2* 1 2-3* (S)# AC97 Sound Enable*

1 2-3 1 1-2 (P)# AC97 Sound Disable

TABLE I

JP1, JP2—System Bus Frequency

JP1 JP2 CPU Clock Speed1 Open 1 Open 133MHz (100MHz CPU run at 133MHz Front Side Bus)

1 Open 1 1-2 100MHz (66MHz CPU run at 100MHz Front Side Bus)

1 Close* 1 1-2* Auto*

Fig. 2: PC Partner motherboard layout diagram

JP15 - BIOS (Firm Ware Hub)

Boot Block Protect JP4 - CMOS Clear

JP15 Function JP4 Function1 Close* Unlocked* 1 1-2* Normal

1 Open Locked 1 2-3 CMOS Clear

JP34 - On Board Crystal PCI Sound (Optional)

JP34 Function

1 1-2* PCI Sound Enable*

1 2-3 PCI Sound Disable

JP29 - Keyboard Power On Select

JP29 Function1 1-2* Powered by +5V*

1 2-3 Powered by +5V Standby(Allows Keyboard Power On)

* Default settings

# P = Primary AMR,S = Secondary AMR



parent deficiencies and no signs of anyphysical damage, and the parts are cor-rect as indicated by the labels on the items/packages. For example, the Pentium pro-cessor pack should comprise Pentium IIIprocessor labeled 700MHz/100MHz sys-tem bus, fan/heat-sink assembly, and in-stallation manual with 3-year limited war-ranty. Similarly, ensure that the 64MBSDRAM DIMM bears the label (such asPC100) to indicate that it is compatiblewith 100MHz system bus speed.

Checking cabinet and its acces-sories. The AT mini tower PC cabinet

measures approx.180mm(width) x 330mm (height)x 360mm (depth). Thedrive bays comprise two133.35mm (5.25-inch) ex-posed, one 89mm (3.5-inch)exposed, and two 89mm(3.5-inch) internal bays.

It has 200W SMPS ofVESTA make pre-installed(+5V @16A, +12V @6A, -

5V @0.5A, and – 12V @0.5A). LEDs with2-pin SIP connectors are provided forpower ‘on’ (green and white twisted

wires), HDD (orange and white twistedwires) activity indication, and to resetpush switch (blue and white twistedwires), which are required to be con-nected to the appropriate pin pairs(Berg type) on the motherboard. (Pleaserefer Fig. 2 to spot the correspondingconnectors near JP34/JP4, but for thetime being, leave them alone.) An 8-ohm, 0.5W speaker (with black and redtwisted wires and 4-pin connector), togo into corresponding 4-pin speaker con-nector on motherboard, also forms partof the cabinet.

Checking SMPS. The control con-sole on the cabinet also has a DPDT push-button switch to switch on the mains(230V AC) to SMPS of the computer anda parallel-wired 3-pin AC socket onSMPS for connecting AC power to themonitor used with the PC. At this stage,slide the shielded connectors of the fourpower supply wires of the SMPS intothe corresponding connectors on theDPDT switch as per the diagram pro-vided on the SMPS case (top side). Thesame is reproduced in Fig. 4. The whiteand black wires have a return path viablue and brown wires, respectively, whenthe power supply switch is flipped ‘on’.Connect the 3-pin power cord providedwith the cabinet to the socket at the backof SMPS and plug 3-pin plug into thesocket of the mains supply or the UPS,as appropriate.

Switch on the SMPS. The fan blowerinside the SMPS should start running,

Fig. 3: Jumper positions within motherboard

Fig. 4: Power on/off switch wiring

Fig. 5: Installation of Pentium III processor in PGA 370 socket

(a)

(b)(c)

(d)

Fig. 6: DIMM installation

A

A



are also correct.Motherboard fitment. The chassis

on which motherboard is to be mountedcan be easily removed from the PC cabi-net. Unscrew it and gently slide it outfrom the main casing. Lay it flatly onthe antistatic workbench (properlygrounded conductive surface). Mark theside facing the keyboard connecter cut-out on the chassis.

All motherboards have standardmounting holes. The hardware suppliedcomprises plastic and metallicmotherboard retaining fasteners/screw-holders. Metal-type screw-holders arebetter as these have better strength andalso these ground the motherboard tothe chassis. You may use four metallicscrew-holders for the four corner holesin the motherboard, while the plasticfasteners may be used for the middleholes of the motherboard.

Before attempting fitment of themotherboard, align it on the chassissuch that the keyboard connector on themotherboard is towards the side markedearlier for this purpose. Now fit all thescrew-holders/fasteners, as discussedabove, on the chassis, opposite the holeson the motherboard, using Philipsscrews provided in the hardware packet.

Align themotherboard abovethe fasteners andpush it down, sothat the self-retain-ing heads of plasticfasteners pop outfrom the respectiveholes. For the me-tallic screw-holders,use Philips screwsto secure themotherboard to the

other, thisforms a 12-pinAT power sup-ply connectorwith orangewire (carryingpower goodsignal) ema-nating frompin 1.

The volt-ages on vari-ous pins ofthis joint 12-pin connectorwith theircolour codesare shown inTable II.Check the cor-rectness ofthese voltageswithin therange as givenin Table II.Then switchoff the powersupply andtake out the 3-

pin plug from the mains socket. If theAT power connector voltages are cor-rect, you can safely assume that volt-ages in all other power connectors [4-pin Molex, carrying +12V (yellow wire)followed by two black wires (ground) and+5V (red wire)] meant for various drives

TABLE IIIVGA– VGA Out Connector CN34*

Pin Signal Name Pin Signal Name1 Red signal 9 NC2 Green signal 10 GND3 Blue signal 11 NC4 NC 12 Display data channel data5 GND 13 Horizontal sync6 GND 14 Vertical sync7 GND 15 Display data channel clock8 GND*This connector is for the VGA display port. Connect aVGA or higher resolution display monitor to it.

TABLE IIAt Power Connector Pin Voltages

Pin Voltage Range Wire Pin Voltage Range WireColour Colour

1 *P. G. 4.5V (min) Orange 7 Ground - Black2 +5V +5%/-4% Red 8 Ground - Black3 +12V +5%/-4% Yellow 9 -5V +10%/-8% White4 -12V +10%/-9% Blue 10 +5V +5%/-4% Red5 Ground - Black 11 +5V +5%/-4% Red6 Ground - Black 12 +5V +5%/-4% Red*P. G. = Power good signal which is +5V (delayed, 100ms – 500ms).

indicating availability of +12V supplyto the fan. Now verify all DC outputs ofthe SMPS as follows.

There are two distinct 6-pin Molexfemale power connectors with projectionin the middle. If these are held suchthat all black wires are adjacent to each

PARTS LISTItem Description MakeAT cabinet with SMPS, power cord,power switch, reset switch, speaker,LEDs, complete with connectors andinstallation hardware packet. IMIL, ChennaiMotherboard with Intel’s 810chipset PC Partner, USA along withuser’s manual, CD (containingdrivers for onboard devices) andheaders for motherboard connectors.* (refer check-list) PC PartnerPentium PIII-700 Processor Intel64MB (PC 100)SDRAM (168-pin DIMM) AlphaHDD (hard disk drive) SeagateFDD (floppy disk drive) 3.5” SonyCD-ROM drive 52X with audio cable SamsungKeyboard LogitechMouse(3-button) LogitechColour Monitor 14” LGUSB connector bracket with 2 headers -*list of connectors/brackets forming part of motherboard.Header (connectors with cables) for HDD (40-pin twin) - oneHeader for FDD (34-pin twin) - oneHeader for PS/2 mouse - onePort bracket set with headers for:(a) VGA (15-pin ‘D’ connector ending into 16-pin FRC and

parallel port (25-pin ‘D’ ending into 26-pin FRC) - one(b) Com1 and Com2 (two 9-pin ‘D’ ending into 10-pin FRC) - two(c) Onboard AC97 sound codec (line-in, line-out, mic-in and

MIDI/game port ending into 26-pin FRC) - one

TABLE IV

Parallel-Port Connector CN6Pin Signal Name Pin Signal Name

1 Strobe- 14 AFD2 Data bit 0 15 Error3 Data bit 1 16 INIT4 Data bit 2 17 SLCTIN5 Data bit 3 18 GND6 Data bit 4 19 GND7 Data bit 5 20 GND8 Data bit 6 21 GND9 Data bit 7 22 GND10 ACK 23 GND11 Busy 24 GND12 PE 25 GND13 SLCT 26 GND



chassis firmly without using excessiveforce.

Pentium processor mounting (re-fer Fig. 5). The processor is to be fittedinto the PGA370 (pin grid array with370-pin recesses) socket, which is a ZIF(zero insertion force) socket. Take outthe processor and its heat sink fittedwith cooling fan and heat sink retainerclip ‘D’. Now proceed as follows:

1. Lift handle ‘A’ to its vertical posi-tion [refer Fig. 5(a)].

2. Align the processor pins with thesocket holes and insert the processorinto its socket [refer Fig. 5(b)].

3. With the processor in its socket,lower handle ‘A’ and bring it to its closed(horizontal) position [refer Fig. 5(c)].

4. Orient the heat sink (with fan ontop) such that the depression on oneside of the heat sink matches the corre-sponding projection on PGA370 socket,and place it (along with fan) over theprocessor [refer Fig. 5(c)].

5. On the PGA370 socket, there aretwo small projec-tions on oppositesides, in which theheat sink clip has tobe inserted. Whileit is fairly easy toinsert one side, it israther tricky to in-sert the left-outside as it needs tobe pulled down with

DIMM with the corresponding keys inthe socket.

3. Push the DIMM vertically down,inserting its bottom edge into thesocket.

4. Once seated properly, push DIMMdown from the top edge until the re-

considerable force to engage it into theprojection. You may use the flatscrewdriver tip to do this, but be care-ful that screwdriver does not slip anddamage the tracks on the motherboard[refer Fig. 5(d)].

6. Connect the 3-pin fan connectorto the corresponding connector CN17marked ‘CPU Fan’ on the motherboard.

DIMM installation (Fig. 6). Thereare two 168-pin SDRAM DIMM sockets

on the motherboard with socket 1marked ‘1’ and socket 2 left unmarked.The two sockets can together accept512MB SDRAM (i.e. up to 256 MB each).We propose to install a single 64MBDIMM, which isquite adequatefor current typeof applications. Itcan be insertedinto any of thetwo sockets andthe same will bea u t o m a t i c a l l ysuitably config-ured duringsetup. Removethe DIMM fromits anti-static en-velope, holding itby its edges. Pro-ceed as follows:

1. Using fin-gertips, push theretainer clips oneither side of theDIMM socketslightly awayfrom the socket.

2. Positionthe DIMM to beinstalled abovethe socket, align-ing the two smallnotches at thebottom edge of

TABLE VIICN7: USB Port

Pin Assignment1 VCC2 GND3 USBP1-4 USBP0+5 USBP1+6 USBP0-7 GND8 VCC

TABLE VCOM1/COM2– Serial Connectors CN4*, CN5*Pin Signal Name Pin Signal Name1 DCD 6 DSR2 SIN 7 RTS3 SOUT 8 CTS4 DTR 9 RI5 GND 10 NC*These connectors are for the serial portbracket. Both connectors have the same pin-outs.

TABLE VI

Audio & Game Port Pin Header CN341*

Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name

1 VCC 8 GND 15 NC 22 MIC-in2 VCC 9 XTD 16 VCC 23 NC3 SWC 10 GND 17 Line-out 24 GND4 SWA 11 SWB 18 Line-out 25 Line-in5 XTC 12 XTB 19 GND 26 Line-in6 XTA 13 MSIN 20 GND7 MSOUT 14 SWD 21 MIC-in

*This header is for the audio port bracket. It connects audio ports-stereo line-out, stereo line-inand microphone—and a game port (for a joystick or MIDI device) to your system.

TABLE VIII

IDE Connector Pin Definitions (J18, J19)Pin Function Pin Function

1 Reset IDE 2 GND3 Host data 7 4 Host data 85 Host data 6 6 Host data 97 Host data 5 8 Host data 109 Host data 4 10 Host data 1111 Host data 3 12 Host data 1213 Host data 2 14 Host data 1315 Host data 1 16 Host data 1417 Host data 0 18 Host data 1519 GND 20 Key21 DRQ3 22 GND23 I/O Write- 24 GND25 I/O Read- 26 GND27 IOCHRDY 28 BALE29 DACK3- 30 GND31 IRQ14 32 IOCS16-33 Addr 1 34 GND35 Addr 0 36 Addr 237 Chip select 0 38 Chip select 1-39 Activity 40 GND



reset switch, and the speaker), wouldbe completed after the motherboardchassis is screwed back into the PC case.

The cables to be connected to theFRC-type male connectors/headers onthe motherboard are listed below, andthe pin assignments are shown in thereferred tables. On the motherboard,normally, only start pin 1 is indicated.In an FRC connector, all odd numberpins are in one row while even numberpins are in the opposite row; pin 2 isopposite pin 1, pin 4 is opposite pin 3,and so on.

Pin 1 on the mating FRC female con-nector can be identified by an arrowmark over it. Ribbon cable wire goinginto pin 1 is of red (sometimes blue)colour. Some of the FRC connector pairs

have a notch and the corresponding pro-jection, which serves as a key so thatthey can go only the correct way. Thecables used for the drives have an addi-tional connector in the middle (for slavein case of HDD and drive B in case ofFDD, which will be explained later). Us-ing the tips given here, you can installthe motherboard end of the followingcables:

• 16-pin VGA connector CN34 (re-fer Table III).

• 26-pin parallel-port connector CN6(refer Table IV).

• 10-pin serial/com ports 1 and 2,CN4 and CN5 (refer Table V).

• 26-pin sound cable connector CN31(refer Table VI).

• 8-pin USB connector CN7 (referTable VII).

• 40-pin IDE-1 connector for HDD/CD-ROM drive CN1 (refer Table VIII).

• 34-pin FDD connector CN3 (referTable IX).

• 6-pin PS/2 mouse connector CN8(refer Table X).

tainer clips snap into place and theDIMM is firmly held into its position.

Cable set installation. While themotherboard chassis is still not replacedinto the case, you could install one ofthe ends of all the cables originatingfrom the motherboard. The installationof cables, which originated from SMPSand the control panel of the case (LEDs,

TABLE IXFloppy Connector Pin Definitions (JP26)Pin Function Pin Function

1 GND 2 FDHDIN3 GND 4 Reserved5 Key 6 FDEDIN7 GND 8 Index-9 GND 10 Morot enable11 GND 12 Drive select B-13 GND 14 Drive select A-15 GND 16 Motor enable17 GND 18 DIR-19 GND 20 STEP-21 GND 22 Write data-23 GND 24 Write gate-25 GND 26 Track 00-27 GND 28 Write protect-29 GND 30 Read data-31 GND 32 Side 1 select-33 GND 34 Diskette

TABLE XPS/2 Mouse Connector*

Pin Description Pin Description

1 Mouse data 2 NC3 Ground 4 +5V5 Mouse clock 6 NC*This connector is for the optional PS/2 mouseport bracket.

Stay tuned for the concluding part in next issue


ing resistor that keeps the IR LEDs,current within the required range.

IR detector modules. The IR detec-tor modules used in the circuit are com-monly available in the market. These

I & RUPANJANA

PARTS LIST

��

��S.C. DWIVED

ELECTRONICS FOR YOU� ❚❚❚❚❚ �JANUARY 2001

Usually, when we enter our roomin darkness, we find it difficultto locate the wall-mounted

switchboard to switch ‘on’ the light. For astranger, it is tougher still as he has noknowledge of the correct switch to beturned on. Here is a reliable circuit thattakes over the task of switching ‘on’ andswitching ‘off’ of the light(s) automaticallywhen somebody enters or leaves the roomduring darkness. This circuit has the fol-lowing salient features:

• It turns on the room light when-ever a person enters the room, providedthat the room light is insufficient. If morethan one person enters the room, say, oneafter the other, the light remains ‘on’.

• The light turns ‘off’ only when theroom is vacant, or, in other words, whenall the persons who entered the room haveleft.

• A 7-segment display shows the num-ber of persons currently inside the room.

• The circuit is resistant to noise anderrors since the detection is based on in-frared light beams.

• The circuit uses commonly avail-able components and is easy to build andtest.

The functional block diagram of thecircuit is shown in Fig.1. It comprises36kHz IR transmitter, two IR detectormodules, two monostable multivibrators,up/down-counter, 4-bit magnitude com-parator, 7-segment decoder display,light sensor, and relay driver.

Two pairs of IR transceivers areemployed in order to detect whetherthe person is entering or leaving theroom. When a person enters the room,IR detector 1 gets triggered, followedby triggering of IR detector 2. Con-versely, when a person leaves theroom, IR detector 2 gets triggered, fol-lowed by triggering of IR detector 1.

A priority detector circuit deter-mines which of the two detectors is

triggered first and then activates an up/down counter accordingly. The BCD out-put of the counter, at any time, repre-sents the number of persons inside theroom. The output of the up/down counteris decoded by 7-segment decoder/driverand displayed on 7-sement display. Si-multaneously, the output of counter iscompared by 4-bit magnitude compara-tor.

The output of comparator remainshigh as long as BCD output of counter isgreater than zero. A logic gate is used toinitiate energisation of a relay to switch‘on’ the light when comparator output ishigh and it is dark outside.

��

The detailed section-wise description ofthe circuit shown in Fig. 2 is as follows:

IR transmitter. The IR transmittercircuit consists of an astable multivibratorbuilt around NE555 timer IC1. The out-put of IC1 at pin 3 is a rectangular wave-form of around 36kHz frequency. This out-put is used to drive two IR LEDs, whichtransmit modulated IR light at 36kHz fre-quency. Modulating frequency of 36 kHzis used because the IR receiver modulesused in this circuit respond to IR signalsmodulated at 36kHz frequency. Themultivibrator frequency can be correctlyadjusted with the help of preset VR1 (10kilo-ohm). Resistor R3 is a current limit-

Fig. 1: Block diagram of automatic room light

Semiconductors:IC1, IC2, IC3 - NE555, timerIC4 - 74LS192, up/down decade

counterIC5 - 74LS85, 4-bit magnitude

comparator)IC6 - 7447, BCD to 7-segment

decoder/driverIC7 - MCT2E, opto-couplerIC8 - 7805, +5V regulatorIC9(N1-N4) - 74LS00, quad 2-input

NAND gateIC10(N5-N10) - 74LS14, hex schmitt

inverter gateT1, T2 - BC548, npn transistorT3 - SL100, npn transistorD1-D3 - IN4001, rectifier diodeIRLED1, IRLED2 - Infrared LED

Resistors (all ¼-watt, ±5% carbon, unlessstated otherwise):

R1 - 3.3-kilo-ohmR2 - 10-kilo-ohmR3 - 100-ohmR4, R5, R21 - 1.2-kilo-ohmR6, R7, R12 - 33-kilo-ohmR8, R9 - 180-kilo-ohmR10, R11 - 1-kilo-ohmR13-R19 - 470-ohmR20 - 100-kilo-ohmVR1 - 10-kilo-ohm presetCapacitors:C1 - 0.001µF, ceramic diskC2, C3, C4 - 0.01µF, ceramic diskC5, C6 - 4.7µF, 16V electrolyticC7, C8 - 10µF, 16V electrolyticC9 - 1µF, 16V electrolyticMiscellaneous:M1, M2 - IR sensor modulesDS1 - LT542 (common anode

display)RL1 - 12V, 200 ohm, 2 C/O.LDR1 - LDR (Dark resistance >

120 kilo-ohm)L1 - 230V, 100W electric bulb

- 12V power supply- Printed circuit board- IC sockets

REJO G. PAREKKATTU



have three terminals forVcc (+5V, here), ground,and the output signal,respectively. In the nor-mal state, the outputpin (pin 3) of this de-tector remains at highstate, and when an IRlight of correct modulat-ing frequency is de-tected, its output pingoes low. The pin con-figuration of the IRmodules may vary fromone manufacturer to theother. (Pin configura-tion of module TSOP1136 for 36 kHz usedby EFY is shown in Fig.2.) (Articles based onthe IR sensor modulehave been published inNov. 2000 and someother previous issues ofEFY. Readers may re-fer the same for moreinformation about themodule.)

Since the IR trans-mitter in this circuit iscontinuously ‘on’, emit-ting IR light, in the nor-mal condition, the out-put pins of both IR mod-ules will be at low state.Therefore transistors T1and T2 will remain cut-off. When a person en-

ters or leaves the room, the infrared lightbeams are interrupted one-by-one and theoutput of each IR sensor module, in turn,goes high, which results in conduction ofassociated transistors T1 and T2. Whichtransistor will turn ‘on’ first depends onwhether the person is entering or leavingthe room.

In the circuit, two NE555 timer ICs(IC2 and IC3) wired as monostablemultivibrators are used. The pulse widthof the output waveform (on time) for thesemultivibrators is fixed at about 0.9 sec-onds by suitably selecting the values forthe timing capacitors C5 and C6 in con-junction with their associated resistors R8and R9. These monostable multivibratorsget triggered when their trigger input pins(pin 2) go low. Thus the multivibratorsare triggered only when the IR lightbeams are interrupted. Although the out-put pulse width of both the multivibratorsis approximately the same, there is, how-ever, a phase difference corresponding tothe elapsed time between the successiveinterruptions of the IR beams. Refer tothe waveforms shown in timing diagramof Fig. 3.

Priority-detector logic circuit. Thepriority detector circuit uses three NANDgates, five inverter gates, and twodifferentiators. The timing diagram givenin Fig. 3 helps in understanding as tohow the priority-detector circuit detects aperson going out of the room.

At first the outputs from themonostable multivibrators are NANDedby gate N1 and its polarity is inverted

Fig. 3: Timing waveforms

Fig

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again by gate N7. At the same time, theoutputs of monostable IC3 and IC2 getdifferentiated by the capacitor-resistorcombinations of C7-R10 and C8-R11, re-spectively. Each differentiated output ispassed via Schmitt inverter pairs of N5-N6 and N10-N9 to convert the differenti-ated pulses into rectangular pulses. Therectangular pulses obtained at the out-put of gates N6 and N9 are again

NANDed with the output of gate N7 inNAND gates N2 and N3, respectively.The rectangular pulse at pin 4 of NANDgate N2 ends before the output of gateN7 goes high and hence the output ofNAND gate N2 stays high, while bothinputs to NAND gate N3 are simulta-neously high for the duration of rectan-gular output of gate N9. As a result, theoutput of gate N3 applied to countdown

clock pin 4 of IC4 causes the counter tocount down on its trailing edge (low-to-high transition) and the output count goesdown by one count.

Similarly, when a person enters theroom, pin 4 of counter IC4 remains high,while its pin 5 (count up) gets a low-going pulse resulting into counter outputadvancing by one count. Values of ca-pacitors C7 and C8 and resistors R10and R11 can be varied for optimum per-formance. (Lab note. The component val-ues have already been optimised andlogic circuit is suitably modified forhighly reliable performance of this partof the circuit, after considerable effort.)

Up/down counter. Up/down decadecounter 74LS192 (IC4) is used as thecounter. When the power is turned ‘on’,its outputs Q0 through Q3 are in the lowstate. Whenever a person enters theroom, a low-going pulse is applied at itscount-up pin 5, while its count-down pin4 is held at logic 1 and its output countadvances by one. Similarly, when the per-son leaves the room, a similar pulse isapplied at its countdown input (pin 4)while its countup pin 5 is held at logic 1and its output decreases by one. Thusthe 4-bit output always represents thenumber of persons still inside the room.The output of the decade counter is con-nected to 7-segment decoder/driver IC6(7447) that displays the number on com-mon-anode 7-segment LED display(LT542).

Magnitude comparator. The outputof the up/down counter is also applied to4-bit magnitude comparator that acts aszero detector, i.e. it detects whether thenumber of persons inside the room isgreater than zero or not. The 4-bit out-put of the decade counter is always com-pared with a reference 4-bit number(0000), and if a match occurs, the outputat pin 5 (P>Q) of the comparator goeslow to represent an ‘empty room’ condi-tion. In all other cases (when the num-ber of persons in the room is greaterthan zero), P>Q output will be at highstate. This output is given as one of theinputs to NAND gate N4 (followed byinverter gate N8). Thus, as long as theroom is not empty, one of the inputs toN4 gate will be high.

The second condition for the light toget switched ‘on’ is yet to be satisfied.Whether there is sufficient light in theroom or not is checked by the light sen-sor circuit.

Fig. 4: Actual-size, single-sided PCB layout for the circuit

Fig. 5: Component layout for PCB



Light sensor. The light sensor iswired around the opto-coupler MCT2E.The resistance of the LDR depends uponthe amount of light in the room. An LDRwith resistance below 5 kilo-ohm in nor-mal light and more than 120k resistancein darkness is required. When there issufficient ambient light, the transistor in-side the opto-coupler is turned ‘on’ andthe input of NAND gate (pin 3) is drivento low state. Thus the output of NANDgate remains at high state and that ofinverter gate N8 at low. However, whenthe light is insufficient, the resistance ofthe LDR increases, turning off the tran-sistor inside the opto-coupler. The sensi-tivity can be controlled by adding a high-valued variable resistance (about 680k)across the LDR.

When both conditions are satisfied(that is one or more persons are insidethe room and the ambient light is insuffi-cient), the output of NAND gate goes ‘low’and that of inverter gate N8 goes ‘high’to turn on transistor T3, therebyenergising relay RL1. A 230V, 100W elec-tric bulb is connected via the relay to the

AC mains. Once the relay gets energised,the LDR is effectively removed from thecircuit (since the LDR is connected to theN/C contact of the two pole relay) to pre-vent the flickering of the lamp with chang-ing resistance of the LDR.

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The full circuit, with the exception of theIR transmitter, can be assembled on asingle general-purpose PCB. However, anactual-size, single-sided PCB for the cir-cuit in Fig. 2 is shown in Fig. 4. The com-ponent layout for the PCB is shown inFig. 5.

The receiver-transmitter pairs areplaced about a metre apart as shown inFig. 6. The distance between the two sen-sors (receiver modules) is about 40 cm. Asteel pipe of 5mm diameter and 3cmlength can be placed in front of the IRmodule in order to improve its directiv-ity. After assembling the circuit, adjustpreset VR1 (10k) until pin 3 of both theIR sensor modules go high (5V). If thecircuit still does not function properly, ad-

just the distance between the sensors. Themetal cabinets of the IR modules must beconnected to ground.

Note that the circuit works with aregulated +5V supply, except the powersupply to the relay coil. The circuit hasno off-time memory, and so its working isinterrupted during power failure.

Another disadvantage is that the cir-cuit can count only up to 9. But it is quiteunusual to have more than nine peoplein a normal living room.

Take care about the IR sensor mod-ule pin connections. It may be damaged ifconnected wrongly. ❏

Fig. 6: Proposed layout of IR transmitterand receiver pairs

February

2001

Circuit Ideas

2001


EDIcalled subscriber. When the call is estab-lished, no ring-back tone is heard by the
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ELECTRONICS FOR YOU� ❚❚❚❚❚ �FEBRUARY 2001

S.C. DWIV

This circuit is able to handle nineindependent telephones (using asingle telephone line pair) lo-

cated at nine different locations, say,up to a distance of 100m from eachother, for receiving and making outgo-ing calls, while maintaining conversa-tion secrecy. This circuit is useful whena single telephone line is to be sharedby more members residing in differentrooms/apartments.

Normally, if one connects ninephones in parallel, ring signals are

heard in all the nine telephones (it isalso possible that the phones will notwork due to higher load), and out ofnine persons eight will find that the callis not for them. Further, one can over-hear others’ conversation, which is notdesirable. To overcome these problems,the circuit given here proves beneficial,as the ring is heard only in the desiredextension, say, extension number ‘1’.

For making use of this facility, thecalling subscriber is required to initiallydial the normal phone number of the

calling party. The calling subscriber hasthen to press the asterik (*) button onthe telephone to activate the tone mode(if the phone normally works in dial mode)and dial extension number, say, ‘1’, within10 seconds. (In case the calling subscriberfails to dial the required extension num-ber within 10 seconds, the line will bedisconnected automatically.) Also, if thedialed extension phone is not lifted within10 seconds, the ring-back tone will cease.

The ring signal on the main phoneline is detected by opto-coupler MCT-2E (IC1), which in turn activates the10-second ‘on timer’, formed by IC2(555), and energises relay RL10 (6V, 100-

ohm, 2 C/O). One of the ‘N/O’contacts of the relay has beenused to connect +6V rail to theprocessing circuitry and theother has been used to provide220-ohm loop resistance to de-energise the ringer relay intelephone exchange, to cut offthe ring.

When the caller dials theextension number (say, ‘1’) intone mode, tone receiverCM8870 (IC3) outputs code‘0001’, which is fed to the 4-bit BCD-to-10 line decimal de-coder IC4 (CD4028). The out-put of IC4 at its output pin14 (Q1) goes high andswitches on the SCR (TH-1)and associated relay RL1. Re-lay RL1, in turn, connects, viaits N/O contacts, the 50Hz ex-tension ring signal, derivedfrom the 230V AC mains, tothe line of telephone ‘1’. Thisring signal is available to tele-phone ‘1’ only, because halfof the signal is blocked by di-ode D1 and DIAC1 (which donot conduct below 35 volts).

As soon as phone ‘1’ islifted, the ring current in-creases and voltage dropacross R28 (220-ohm, 1/2W re-sistor) increases and operatesopto-coupler IC5 (MCT-2E).This in turn resets timer IC2causing:

(a) interruption of thepower supply for processingcircuitry as well as the ring

DHURJATI SINHA


TABLE IAppliance LDR2 LDR3 LDR4 LDR5no.

1 - * * *2 * - * *3 - - * *

RUPANJANA
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switch on the corresponding appliance(one out of 15).

The card used should be of opaqueplastic. It should be able to withstandsome heat from the bulb, even thoughthe appliance remains ‘on’ only for theperiod for which the card is in the slot.

The card has a triangular notch thatshows correct orientation/direction of in-sertion of card and prevents false opera-tion. LDRs can be placed in a line, orrandomly, to increase security.

The order in which holes should bepunched for each appliance is given in

Table I.Two illus-t r a t i o n s ,one eachfor card-2and card-5,are shownin the ac-company-ing figures.An eleva-tion andp l a n / t o pview of thegadget isalso shownin the fig-ures.

This circuit of electronic card locksystem is much simpler andcheaper than other similar cir-

cuits that have appeared in earlier issuesof EFY.

The circuit is configured around anaddressable 1 of 16 demultiplexerCD4514B (IC1). Any number in binaryform, when available at input pins 2, 3,21, and 22 (address pins A0 through A3),makes corresponding output go logic high,thus turning on the appliance through re-lay contacts. Up to 15 appliances can beswitched on/off (one at a time). OutputQ0 (pin 11) can be used for visual indica-tion, to show that circuit is active.

A 40W bulb illuminates LDR1 toLDR5 constantly. This pulls down basesof transistors T1 through T5 to ground.LDR1 ensures that card is properly in-serted into the card slot.

When the card is correctly inserted,it covers the hole/opening for LDR1 andthus blocks the light from falling on LDR1.As a result, transistor T1 conducts andextends positive supply to the collectorsof transistors T2 through T5. Then, de-pending upon the holes blocked/punchedin the inserted card, any combination ofemitters of transistors T2 through T5turns logic ‘high’ (transistors’ output cor-responding to blocked LDRs only goes

‘ h i g h ’ ) .These out-puts con-nected to ad-dress inputpins A0through A3of IC1

4 * * - *5 - * - *6 * - - *7 - - - *8 * * * -9 - * * -10 * - * -11 - - * -12 * * - -13 - * - -14 * - - -15 - - - -

- Blocked hole corresponding to selected bi-nary address.

* Punched holes corresponding to LDR po-sition on card

PRIYANK MUDGAL


S.C. DWIVEDI

its maximum amplitude). Above 3V, prob-ably population inversion is developedmuch above threshold, before the laser os-cillations build up into the cavity, and sowe observe the sharp peak in laser output

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Here a simple low-cost techniquefor converting a CW laser di-ode at 670 nm wavelength to

pulsed laser up to a frequency of 500 kHz.A low-power pulsed radiation source

is very important for any laboratory in-volved in optical pulsed systems—laser,pulsed discharges, optical communication,fibre-optic sensors, image processing,etc—where one is required to check thefrequency response of the detection sys-tem or optical simulation of an opticalsource or local networking using opticalfibre cable. Fast-speed LED offers the so-

lution for such requirements, but becauseof very low power and large divergence,its use remains limited. On the otherhand, a pulsed diode laser offers a verygood solution for this problem.

Commercial systems are usually ex-pensive. However, a CW diode laser oper-ating at 670 nm can easily be pulsed upto a frequency of 500kHz with low-costtechnique, using a function generator and

an inexpensive push-pull amplifier inter-face circuit. The block diagram of the sys-tem is shown in Fig. 1.

A 3mW CW diode laser at 670 nmwith voltage and current rating of 3V at100mA, respectively, is used. The source(a function generator) is capable of deliv-ering square pulses of 3V ampli-tude, which are amplified by acomplementary symmetry push-pull circuit shown in Fig. 2.

The output of the amplifieris connected to the diode laserfor pulsed operation. The laser

is focused onto aphotodiode termi-nated with 50-ohm resistor (Fig.1). The output ofphotodiode is dis-played on digitalstorage oscillo-s c o p eand it is

also connected to thePC for getting a hardcopy.

Up to a frequencyof around 20 kHz, thethreshold voltage forlaser oscillations isaround 2.4V. For fre-quencies greater than20 kHz, the thresholdfor laser oscillationsdepends on the operat-ing frequency and ishigher than 2.4V. Thebehaviour of laser pulses up to 10 kHz isnearly similar. Laser output at a typicalfrequency of 2 kHz is shown in Fig. 3, atvarious voltages (2.6V, 3.4V, and 4V). Theinput waveform ‘A’ is shown at the bot-tom of the figure.

For a driving pulse of about 3V (whichis the normal operating voltage for CWoperation), the laser pulse becomes flatafter a delay of approximately 40 µs (timetaken to build up the laser oscillations to

(for more details, refer Laser Fundamen-tals book by W. T. Silfvast, published byCambridge University Press), exponen-tially decaying to a steadystate valuewith a time constant depending on theinitial peak intensity and the carrier lifetime in the excited state. After the inputpulse is over, the oscillations die downwithin 5 µs.

Therefore above 3V, up to a frequency

of 10 kHz, the laser is operated in quasiCW mode. In the frequency range of 10kHz to 50 kHz, the laser output keeps onincreasing, even during the flat portion ofthe input current pulse, and falls down tozero during the off period of the drivingpulse. Fig. 4 shows the laser waveformsat 50 kHz, 100 kHz, 200 kHz, 300 kHz,and 500 kHz, respectively.

All these pulses were recorded ataround 4V. In this range of frequencies,

DR. ALIKA KHARE



the duration for which voltage is on/off isof the order of less than 5 µs, and so thedriving pulses switch off before the ter-mination of laser oscillations. Thereforethe laser output shows a modulation with

the DC component in it. Beyond 500 kHz,it is difficult to observe laser oscillationseven at voltages higher than 4V.

Lab note. Tests conducted at EFYusing laser diode of laser torch (rated

for <5mW) with identical inputs at 2 kHzdid not show any marked departure ofoutput waveform (square wave) from theinput square wave.


NA

ming of the 5-second and 1-second pulsewidth of respective sections.

When switch S2 is in position ‘a’ andswitch S1 is pressed momentarily, the out-put at pin 5 goes high for about 5 sec-onds. The trailing (falling) edge of this 5-second pulse is used to trigger the second
UPANJA
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R

This circuit using a dual-timerNE556 can produce 1Hz pulsesspaced 5 seconds apart, either

manually or automatically. IC NE556comprises two independent NE555 tim-ers in a single package. It is used toproduce two separate pulses of differ-ent pulse widths, where one pulseinitiates the activation of the secondpulse.

The first half of the NE556 is wiredfor 5-second pulse output. When slideswitch S2 is in position ‘a’, the first timeris set for manual operation, i.e. by press-

ing switch S1 momentarilyyou can generate a single pulse of 5-second duration. When switch S2 iskept in ‘b’ position, i.e. pins 6 and 2 areshorted, timer 1 in NE556 triggers byitself.

The output of the first timer is con-nected to trigger pin 8 of second timer,which, in turn, is connected to a poten-tial divider comprising resistors R4 andR5. Resistor R1, preset VR1, resistor R2,preset VR2, and capacitors C2 and C5are the components determining time pe-riod. Presets VR1 and VR2 permit trim-

PRAVEEN SHANKER timer via 0.1µF capacitor C6. This actionresults in momentarily pulling down ofpin 8 towards the ground potential, i.e.‘low’. (Otherwise pin 8 is at 1/2 Vcc andtriggers at/below 1/3 Vcc level.) When thesecond timer is triggered at the trailingedge of 5-second pulse, it generates a 1-second wide pulse.

When switch S2 is on position ‘b’,switch S1 is disconnected, while pin 6 isconnected to pin 2. When capacitor C ischarged, it is discharged through pin 2until it reaches 1/3Vcc potential, at whichit is retriggered since trigger pin 6 isalso connected here. Thus timer 1 isretriggered after every 5-second period(corresponding to 0.2Hz frequency). The

second timer is triggered as before toproduce a 1-second pulse in synchro-nism with the trailing edge of 5-sec-ond pulse.

This circuit is important wherevera pulse is needed at regular intervals;for instance, in ‘Versatile Digital Fre-quency Counter Cum Clock’ construc-tion project published in EFY Oct. ’97,one may use this circuit in place ofCD4060-based circuit. For the digitalclock function, however, pin 8 and 12are to be shorted after removal of0.1µF capacitor and 10-kilo-ohm resis-tors R4 and R5.


which is done using a variac.Further, the base voltage of transis-

tor T2 is adjusted with the help of pre-set VR2 so that it conducts up to thelower limit of the input supply and cutsoff when the input supply is less thanthis limit (say, 180V). As a result, tran-

S.C. DWIVEDI

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sistor T3 remains cut off (with its col-lector remaining high) until the mainssupply falls below the lower limit, caus-ing its collector voltage to fall. The col-lector of transistor T3 is connected tothe trigger point (pin 2) of IC1.

When the input is more than thelower limit, pin 2 of IC1 is nearly at+Vcc. In this condition the output ofIC1 is low, relay RL2 is de-energisedand power is supplied to the appliancethrough the N/C terminals of relay RL2.

If the mains supply is less than thelower limit, pin 2 of IC1 becomes mo-mentarily low (nearly ground potential)and thus the output of IC1 changes statefrom ‘low’ to ‘high’, resulting inenergisation of relay RL2. As a result,power to the load/appliance is cut off.

Now, capacitorC2 starts charg-ing through re-sistor R6 andpreset VR3.When the ca-pacitor chargesto (2/3)Vcc, IC1changes statefrom ‘high’ to‘low’. The valueof preset VR3may be so ad-justed that it

takes about one minute (or as desired)to charge capacitor C1 to (2/3)Vcc. Re-lay is now de-energised and the poweris supplied to the appliance if the mainssupply voltage has risen above the lowercut-off limit, otherwise the next cyclerepeats automatically.

One additional advantage of this cir-cuit is that both relays are de-energisedwhen the input AC mains voltage lieswithin the specified limit and the nor-mal supply is extended to the appliancevia the N/C contacts of both relays.

This inexpensive circuit can beconnected to an air-conditioner/fridge or to any other sophisti-

cated electrical appliance for its protec-tion. Generally, costly voltage stabilisersare used with such appliances for main-taining constant AC voltage. However,due to fluctuations in AC mains supply,a regular ‘click’ sound in the relays isheard. The frequent energisation/de-energisation of the relays leads to elec-trical noise and shortening of the life ofelectrical appliances and the relay/stabiliser itself. The costly yet fault-prone stabiliser may be replaced by thisinexpensive high-low cutout circuit with

timer.The circuit is so designed that relay

RL1 gets energised when the mains volt-age is above 270V. This causes resistorR8 to be inserted in series with the loadand thereby dropping most of the volt-age across it and limiting the currentthrough the appliance to a very lowvalue.

If the input AC mains is less than 180volts or so, the low-voltage cut-off circuitinterrupts the supply to the electricalappliance due to energisation of relay

RL2. After a preset time delay of oneminute (adjustable), it automatically triesagain. If the input AC mains supply isstill low, the power to the appliance isagain interrupted for another one minute,and so on, until the mains supply comeswithin limits (>180V AC). The AC mainssupply is resumed to appliance only whenit is above the lower limit.

When the input AC mains increasesbeyond 270 volts, preset VR1 is adjustedsuch that transistor T1 conducts andrelay RL1 energises and resistance R8gets connected in series with the elec-trical appliance. This 10-kilo-ohm, 20Wresistor produces a voltage drop of ap-

proximately 200V, with the fridge asload.

The value and wattage of resistorR8 may be suitably chosen according tothe electrical appliance to be used. It ispractically observed that after continu-ous use, the value of resistor R8 changeswith time, due to heating. So adjust-ment of preset VR1 is needed two tothree times in the beginning. But onceit attains a constant value, no furtheradjustment is required. This is the onlyadjustment required in the beginning,

DR D.K. KAUSHIK

Construction

2001


N. KUNDRA The HDD can now be installed atthe lowest closed (without any cutoutin front) position in the drive bay. Se-cure it like the other drives using fourPhilips screws.

• Completing the hardware in-

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� ��PART-II


K.C. BHASIN AND NEERAJ KUNDRA

• Installation of drives in drive’sbay. Before proceeding with the physi-cal installation of CD-ROM drive, harddisk drive, and floppy drive in thedrive’s bay, you have to plan their con-figuration. We propose to use only onefloppy drive. This drive will be config-ured as floppy drive ‘A’. The 34-pinfloppy drive cable end with twistedwires, emanating from CN3 on themotherboard, needs to be connected tofloppy drive (DS1 in Fig.7).

Let us configure the HDD as pri-mary master and CD-ROM drive as pri-mary slave using a single cable ema-nating from CN1 (IDE-1 header) on themotherboard (refer Fig. 8). (We couldalternatively configure CD-ROM driveas secondary master and connect it di-rectly to CN2 (IDE-2 connector) inmotherboard, using another 40-pincable/connector.)

The jumper on HDD should be usedto short pins 7 and 8 on the jumperblock at the rear of HDD (refer Fig. 9).Similarly, there is a jumper block atthe rear of CD-ROM drive with the pairsof pins marked as CS (cable select), SL(slave), and MA (master). Ensure thatjumper is used in the middle to selectthe slave mode for CD-ROM. The cableconnection arrangement for HDD andCD-ROM is shown in Fig. 8.

Before installation of drives, notedown pin-1 orientation/position of the34-/40-pin interface cable connectors onthe drives.

The CD-ROM drive may be installedin the topmost position for 13.33cm(5.25-inch) drive, after pushing out theplastic piece (used for protection) cov-ering the cutout in this drive’s bay. Alignit from the front side of the case to en-sure that it is flush with the cabinet’sexternal surface. Using four Philipsscrews (6-32 UNC) secure it in properhorizontal position. The screws should

stallation. After having completed theinstallation of drives and the cable setof the motherboard, install back the as-sembled motherboard chassis (complete

with its cable/connector set)into the PC cabinet andthen complete the cablingas follows.

You may start with ATpower supply connectors.By now you are familiarwith two 6-pin Molex con-nectors from SMPS usedfor powering the

motherboard (refer paragraph underheading ‘Checking SMPS’ in Part I).Take connecter with orange wire (PGsignal) first and align it over pin 1 ofPW1 connector on motherboard. Pro-jections on Molex connector of SMPSwould engage into corresponding holesin PW1 connector. Once you have en-gaged the connector in this fashion,make it vertical and then simply slideit down. It will snap into its position.(Be careful not to bend the pins andensure that you have not engaged thewrong pins.) Similarly, insert the other6-pin Molex connector in the adjacentpins of AT power connector. On in-

stallation, all black coloured wires willbe adjacent to each other.

Some of the connectors originatingfrom the motherboard (e.g. COM1,COM2, and VGA connectors) can be se-cured into the cutouts provided on thecase below the SMPS. Thus secure the‘D’ connectors for COM1, COM2, andVGA into the respective cutouts using

Philips screws. This saves theprecious space inside the PCcase and gives it an ethical look.

For accommodating thepanel/bracket for 25-pin ‘D’ con-nector of parallel port and PS/2mouse as well as audio panel/bracket, remove two of the cut-outs from the rear of the caseby just forcing them out withhands, and secure these brack-ets in the vacant positions us-ing Philips screws.

not be allowed to go more than 3.5 mminto the threaded holes.

Suitable cutout also exists in thedrive bay for installing the 8.9cm (3.5-inch) floppy drive. Before fitting, ensurethat drive door in the front opens down-ward (hinged towards top). For install-ing floppy drive follow the same proce-dure as used for fixing CD-ROM drive.

Fig. 7: Floppy drive cable for connecting up to two FDDs

Fig. 8: Connection of HDD and CD-ROM driveusing IDE-1 header



Now you may terminate the connec-tors originating from control panel onthe cabinet at the motherboard. Con-nect the loudspeaker connector to CN14,

power-on LED connector to CN12,HDD LED connector to CN13, and re-set switch connector to CN11. (Cor-rect orientation can be ensured bymatching the pin connected tocoloured (not white) wire to go intopin 1 of the connectors inmotherboard.)

Now connect the 40-pin middleconnector (in the ribbon cable) origi-nating from CN1 in the motherboardto CD-ROM drive and its end connec-tor to HDD, ensuring that pin 1 of

connector pairs correctly match. (Pro-jection/slot in the middle of connectorswill help you in proper orientation ofthe connectors, unless you try to force

it in with wrong orientation.)Follow it up by connecting the34-pin floppy drive end-connec-tor (at the end of twisted cable)to the interface connector offloppy drive. This header origi-nates from CN3 on themotherboard.

The 4-pin Molex-type powersupply connectors now remainto be connected to the drives.Ensure that rounded shoulderon the female connectors mate

correctly with the corresponding malepower connectors on CD-ROM drive andHDD. In all cases you will observe thatyellow wire (+12V) pin faces the PC casecover.

For FDD, use the 4-pin mini powersupply connector. This connector, if in-serted properly, will lock itself into po-sition. To take out this connector, youshould press the retaining lever withyour fingertip. Connect one of the 4-pinconnectors— CN24 or CN33 or CN32—to analogue audio output connector onCD-ROM drive, after correctly match-ing the ground pin ‘G’ marked over theanalogue audio connector on CD-ROMdrive (refer Fig. 10) and those of CN24or CN33 or CN32 as given in Table XI.

If you have followed all the tips re-ligiously, your hardware assembly iscomplete on closing the cover of the cabi-net using four to six Philips screws. Butbefore you do that, have a look again toensure that no loose wires are hangingaround. After closing the cover, you mayconnect the keyboard cable to the key-board connector, mouse cable to COM1connector, and amplified speakers’ ba-nana-type stereo jack into the line-outplug on the audio bracket.

Now that hardware assembly partof the basic unit is over, installation ofother cards, such as LAN card (for net-working), internal modem card (forInternet access), and TV tuner card, into

Fig. 9: Back-panel connector details of HDDand CD-ROM drives

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Continued

TABLE XIPin Assignment Internal Audio

Connector Internal Audio ConnectorCN25 : AUX-IN

Pin Assignment1 AUX-L2 GND3 GND4 AUX-R

CN24 : CD-INPin Assignment1 CD-L2 GND3 GND4 CD-R

CN33 : CD-INPin Assignment1 CD-R2 GND3 CD-L4 GND

CN32 : CD-INPin Assignment1 GND2 CD-L3 GND4 CD-R



the PCI slots, using the software driv-ers supplied with them, can be at-tempted subsequently.

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Eventually you will be using Windowsoperating system (say, Windows 98), andfor that you should be having MicrosoftWindows 98 installation CD. Use someother PC having Windows 98 operatingsystem to create a ‘startup disk’. Theidea is to have all important files, in-cluding system files, Fdisk.exe, andFormat.com files, in hand, so that youmay proceed with hardware partition-

ing and formatting of hard disk onceyou switch on your newly assembled PCfor the first time.

To make a startup disk, get a new

formatted 8.9cm (3.5-inch) floppy. Onthe working computer, click ‘start but-ton’, select settings, double click on icon‘add/remove programs’, select ‘startupdisk’, insert formatted floppy in floppydrive, and click over the ‘create disk’button seen on monitor’s screen.

The program would prompt you forinsertion of original Windows 98 CD inCD-ROM drive. Insert the same andclick on ‘OK’ button. Even if you do nothave the original CD, but have all pro-grams in Win98 directory in ‘C:’ drive,you can give the proper path and theappropriate programs will be copied tothe startup floppy disk.

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Switch on the newly assembled PC. Itperforms power-on-self-test (POST).During POST you will find ‘Num Lock’,‘Caps Lock’, and ‘Scroll Lock’ LEDsflashing. A single short beep duringPOST indicates that motherboard is‘OK’.

Certain messages will keep appear-ing on the screen of your monitor, in-cluding “ Press Del to enter CMOSsetup” . When this message appears,press ‘Del’ key to enter setup. TheCMOS Setup Utility screen appears onmonitor screen (refer screenshot 1).There are seven items on the left, whichcan be selected using arrow keys on yourkeyboard. On the right, it shows cer-tain options that are quite obvious andcan be interactively executed when re-quired.

Select the first item on the left,“Standard CMOS Features” , and pressenter to see its screen (refer screenshot2). Use arrow keys to move betweenthe items and ‘Page Up’ or ‘Page Down’key to edit or select the options. Youmay correct the date, including year andcentury, and the time to their current

values.You would notice from

screenshot 2 that during power up,the BIOS has identified the pri-mary master (Seagate’s 10GB harddisk ST310211A), 52X Samsung’sCD-ROM Drive SC-15, floppydrives, video, and RAM addressrange (including its breakdown).This latest Award BIOS 1984-2000does not contain ‘Auto Detect HardDisk’ as a separate utility in theCMOS setup options.

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Continued



To select any other screen/setup util-ity option, press ‘Esc’, select the nextitem from setup utility menu, and press‘Enter’. The next screenshot (screen shot3) pertains to ‘Advanced BIOS Features’.Here you may edit and change the first,second, and third boot devices to readCD-ROM, HDD-0, and floppy, respec-tively. This will enable you to boot/runthe computer from CD-ROM (if you havea Windows installation), CD, HDD (af-ter formatting and transferring the sys-tem files), or floppy drive (using thestartup floppy created earlier), in thatpriority.

Press ‘Esc’ to come back to the open-

ing screen. For the time being, skip utili-ties/screens 4 through 7 with their de-fault values. Select the last “Frequency/Voltage Control” menu item. Edit ‘CPUclock/spread spectrum’ item to read‘100MHz/On’. Thereafter press ‘Esc’ andselect ‘Save and Exit Setup’ or F10 key,and then ‘Y’ and ‘Enter’ for saving theedited BIOS selections.

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Assuming that you have Windows 98installation CD in CD-ROM drive, thePC will boot from the CD and start theWindows 98 setup program. Press func-

tion key ‘F3’ to come out of the setupprogram and come to the prompt‘D:\Win98>’. Type ‘Fdisk’ and press ‘En-ter’ for starting with the partitioning ofHDD. (Note. We could have used the‘start up’ floppy in Drive ‘A’ instead ofinserting Windows CD in CD-ROM driveand come to ‘A:\>’ prompt for runningthe ‘Fdisk’ program from ‘A’ drive, ifdesired.)

On pressing ‘Enter’ key, the follow-ing FDISK main menu appears:

Current fixed disk drive: 1Choose one of the following:1. Create DOS partition or logical

DOS drive2. Set active partition3. Delete partition or logical DOS

drive4. Display partition informationEnter choice: [ ]Press Esc to exit FDISKEnter choice 1 above and press ‘En-

ter’ key. The next menu on page 2 ap-pears as follows:

1. Create primary DOS partition?2. Create extended DOS partition?3. Create logical DOS partition?Type ‘1’ and press ‘Enter’ key. The

program verifies integrity of the diskand then displays.

Do you wish to use max. size for aprimary DOS partition and make it ac-tive. Y/N?

Type ‘N’ and press ‘Enter’. (Because,we propose to create two DOS parti-tions of equal size.) Once again the pro-gram verifies integrity of the disk andprompts you to enter/specify partitionin megabytes or percentage of diskspace. Type 50% and press ‘Enter’. Theprogram complies. Now press ‘Esc’ keyto return to the main FDISK menu.

Now enter choice 2. (The primaryDOS partition created earlier becomesactive.) The program will ask you toenter the number of partitions. As it iscurrently ‘1’ on ‘C’ drive, therefore type‘1’ and press ‘Enter’.

Again press ‘Esc’. (Do not press ‘Esc’key more than once, else it will comeout of FDISK.) Again you are led tomain FDISK menu.

Enter choice 1. You will come tomenu on page 2. Now enter choice 2 tocreate extended DOS partition. The pro-gram will again verify the integrity ofthe disk and show availability of 50% ofthe disk space for extended DOS parti-tion. Type 50% for extended DOS parti-

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tion and press ‘Enter’.Again press ‘Esc’ (only once). The

program will ask you to specify the diskspace for logical drive. Simply press ‘En-ter’ and then press ‘Esc’ to come backto the main FDISK menu. Choose op-tion 4 to display the information. Afterlooking at the partition information thatit has been correctly done, press ‘Esc’to come out. Press keysCTRL+ALT+DEL or RESET button forsettings to take effect. The PC will bootfrom CD-ROM drive as per settingsdone in the CMOS setup. On bootingyou will again come to the setup part ofWindows 98 program. Hence to comeout of it, press F3. Now your drives aredesignated as under:

C: First partition on hard diskD: Extended partition on hard diskE: CD-ROM driveNow you will be able to access CD-

ROM drive by typing ‘E:’. After theprompt ‘E:\>’, type ‘Format C:/S/U/V’and press ‘Enter’. (Here ‘C:’ refers todrive to be formatted, ‘S’ to system(transfer of system files to ‘C’ drive dur-ing formatting), ‘U’ to unconditional, and‘V’ to verification.) After formatting ‘C’drive, you will come back to the prompt‘E:\Win98>’. Type ‘setup’ and press ‘En-ter’ to install Windows 98 on ‘C’ drive.

As the program is interactive, keepanswering the questions logically.Choose ‘typical’ while selecting the Win-

dows version. Various messageslike ‘enter computer name’,workgroup, etc keep appearing,which you may reply suitably.Against ‘date/time zone’ selec-tion, choose India.

Computer will show theAgreement format that you arebound to accept. Hence click onthe appropriate button.

Before proceeding with theWindows installation, the pro-gram prompts you for enteringthe key number of Windows 98product, which accompanieseach original copy. You musttype the key number accu-rately. It will then copy theWindows 98 files to ‘C’ drive inWin98 directory. This will ob-viate use of Windows CD forcreating a startup file, when-ever required.

To format drive ‘D’, doubleclick on My Computer icon,

click the right button on drive D:, choose‘Format’, and in ‘Format D:’ menu box,choose full and click on ‘Start’ button.After completion of the formatting of‘D’ drive, it is accessible for read/writeoperations. This completes partitioningand formatting of the hard disk.

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• On-board VGA display driver.When the PC is running, insert themotherboard driver CD that came withthe motherboard (PCPartner driver’sCD, in our case) into CD-ROM drive.Select drive ‘E’, select ‘Intel ChipsetProducts’, 810, VGA , Win9X, andGraphics, in that order, and double clickon its ‘Setup.exe’ icon and follow theinstructions on screen. After finishing,shut down the PC as per Windows shut-down procedure and restart to allow thedrivers to take effect.

• On-board AC97 Codec sounddriver. Click on ‘Start’ button, selectsettings, select control panel, doubleclick on ‘System’ icon, click on ‘DeviceManager’, go to ‘Other Devices’, doubleclick on ‘PCI multimedia’, select ‘PCIAudio’, click on ‘Remove button’ (sincecompatible software drivers have not yetbeen installed to avoid conflicts), andthen click on ‘refresh’ button.

Go back to control panel and, clickon ‘Add new H/W’. A wizard guides you

through rest of the process, and in duecourse, a message “Found new hardware– PCI multimedia audio, display, soundvideo” appears. The program asks if youhave disk (drivers). Click the ‘Browse’button, select E:, ‘Intel Chipset Prod-ucts’, 810 , AC97 Sound, CS4299, Win98,in that order, and run ‘Setup’.

During the setup, when the programprompts you for selection of device,choose ‘Crystal Audio Codec’ and click‘OK’. Again during the course of driverinstallation for Crystal Audio Codec, theprogram will prompt you for location ofWindows 98 files, which you may browseand point towards C:\Win98 directoryor towards Windows CD as E:\Win98and click ‘OK’ button. After finishing,you may verify, via ‘Device Manager’(refer preceding para) by clicking on‘Sound, Video and Game controller’ icon,that ‘Crystal Audio Codec’ as also ‘Crys-tal Audio Codec with Game Device’ ap-pear under it. (A sound icon will con-currently appear on the bottom line ofyour desktop.)

• Intel Firmware Hub configu-ration. In ‘Device Manager’ under‘Other Devices’, an ‘Unknown Device’would still appear. This concerns ‘Intel’sFirmware Hub’. To correct this prob-lem, again go to 810 subdirectory onthe CD, double click on ‘INF_install’,and then on ‘Setup.exe’ within thatsubdirectory. A message “Found NewDevice – Intel Firmware Hub” appearson the screen. This device will be auto-matically configured when you followthe instructions appearing on the screenproperly. To confirm that there are nounknown devices now, open ‘DeviceManager’ and check all the items under‘Other Devices’.

With installation of drivers for on-board devices, hardware and softwareconfiguration of your multimedia PC iscomplete. Other secondary functionssuch as power management functions—APM (advanced power management) orACPI (advanced configuration andpower management interface)— can beincorporated later through CMOS‘Power Management Setup’ facility.Similarly, you can install Ethernet cardfor LAN and modem card for theInternet, fax, and e-mail accessibility viatelecom lines. A brief information onthese additional functions is given be-low.

• APM. APM caters to the PC to



enter an energy-saving standby mode.BIOS enables APM by default. It can beinitiated in the following ways:

1. By specifying time-out period inBIOS setup program.

2. By connecting a hardware sus-pend/resume switch to CN10 on themotherboard.

3. From ‘Suspend’ menu item in Win-dows.

• ACPI. ACPI provides direct con-trol to the operating system over thepower management as well as plug-‘n’-play functions. Features include:

1. Power management control of in-dividual devices, add-on cards, video dis-play, and HDD.

2. Methods for achieving less than30W operation in ‘Power-on SuspendSleeping State’ and less than 5W in ‘Sus-pend to Disk Sleeping State’.

3. A soft-off feature to power off thePC.

4. Support for multiple wake-upevents for the PC to resume normal op-eration.

5. Support for front-panel power and‘sleep’ mode switch.

• Ethernetcard for LAN.Ethernet cardscapable of run-ning at 10Mbps to100Mbps, of dif-ferent makes suchas Intel, Real Tek,Mercury and Dax,as Ethernet PCIadapter are avail-able in the mar-ket.

Each cardcomes with a bracket, driver diskette,and user manual. The bracket wouldhave an LED and RJ-45 jack. This jackis used for running a twisted-pairunshielded cable (max. length 100metres) between the card and the hub/concentrator (10Base-T or 100Base-Tx)to which other computer’s LAN cardsare similarly connected. Once the cableis connected to the hub, the LED onEthernet card would light up. Beforeinstalling, remove a cutout opposite thePCI slot to make space for the bracketof Ethernet card. When you install the

card, the power to the PC should be‘off’.

When you switch ‘on’ the computer,it automatically detects its presence and‘New Hardware Wizard’ appears on thescreen to guide you through the instal-lation process. It asks for location ofthe drivers. The driver’s floppy can beinserted in ‘A’ drive and path can beindicated. You can then proceed fur-ther, as per instructions appearingon the screen, to complete its installa-tion.

• Modem. 56kbps PnP (plug-‘n’-playcompatible) and Windows 95/98 compat-ible internal modem cards are availablefrom different manufacturers for instal-lation in any of the PCI slots. The mo-dem card will have a telephone line jackfor connection of telephone line fromwall socket, a parallel phone jack forconnecting a telephone set, and Mic andspeaker jacks for external mic andspeakers for use with voicemail andspeakerphone facilities, respectively.

For installing the drivers, the pro-cedure would be similar to that usedfor installation of the Ethernet card. ❏


the intelligent digital liquid level con-troller circuit presented here. It has thefollowing features:

• It can automatically switch on thepump when the tank is empty andswitch it off when the tank becomes full.DI

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ELECTRONICS FOR YOU� ❚❚❚❚❚ � FEBRUARY 2001

In coming years, the drinking wateris going to be one of the scarce com-modities. This would partly be at-

tributable to our mismanagement of wa-ter supply and its wastage. In normalhouseholds, where pumps are used tofill the overhead tanks (OHT), it is usu-ally observed that people switch on thepump and forget to switch it off even

when the tank has become full. As aresult, water keeps overflowing until thehousehold people notice the overflowand switch the pump off. As the OHT,in general, is kept on the topmost floor,it is not quite convenient to go up fre-quently and see the water level in theOHT.

This problem can be solved by using

• It can check the ground tank(sump tank) water level from which thewater is pumped into the overhead tank(OHT). If the sump tank water level isbelow the predetermined level, the unitswitches off the pump to protect thepump from dry-run, even though theoverhead tank may be completelyempty.

• It includes under- and over-volt-age cutout to switch off the pump if thevoltage is not within specified low(200V) and high (250V) limits.

• It includes a circuit for digital dis-

Fig. 1: Circuit diagram of water level controller

S.C. DWIVE

SADHAN CHANDRA DAS



play of the overhead tank level to indi-cate water levels 0 through 4 as perpositions of the tips of the sensors in-side the overhead tank.

• The sensors used in this projecthave a lifetime of more than five years.

Digital display circuit (referFig. 1.) This circuit comprises a quad2-input XOR gate IC1 (CD4030) for sumoutputs, decimal to BCD code converterusing diode matrix of diodes D3 throughD7, a BCD to 7-segment decoder/driverIC2 (74LS47), and common-anode type7-segment display LTS 542R.

When only the tip of sensor probe

(cathode) No. 1 is intouch with the water,the voltage at pin 3 ofIC1 becomes logic high(i.e. +5V), and hencevoltage at line No. 1(L-1) also becomeshigh. Now due to con-duction of diode D3,the BCD code 0001 (Q3Q2 Q1 Q0) is gener-

ated and con-verted toequivalent 7-segment codeby IC2(74LS47) todisplay thedecimal digit‘1’.

Similarly,when the tipsof the both sen-sors 1 and 2are in touchwith water, thevoltage at pin 3becomes logic

low (0V) while the voltages at pin 4 andline 2 (L-2) become logic high (i.e. +5V).Now due to conduction of diode D6, thecorresponding BCD code 0010 is gener-ated and decimal digit 2 is displayed onthe 7-segment display.

When the tank is completely empty,the outputs of all XOR gates of IC1 arelow and the display shows decimal digit0. In this way the display circuit worksto show decimal digits 0 through 4, cor-responding to the level of the water, asdefined by the position of the sensorsat different heights. Here the resistorsR9 through R12 and R19 through R21

have been used for passive pull-down.Controller circuit. The controller

circuit is built around three quad 2-in-put NOR ICs (IC3 through IC5) toswitch the pump motor on or off whencertain conditions are fulfilled. The con-ditions to be met for switching-on/run-ning of the pump are:

1. The mains supply should bewithin certain ‘low’ and ‘high’ cut-off lim-its (say between 200V AC and 250V AC).

2. The water level in the sump(ground tank) is above certain optimumlevel (2' in Fig. 1).

3. Water in the overhead tank (OHT)is below the minimum level.

Once all the above-mentioned threeconditions are satisfied, the pump mo-tor would start running. The corre-sponding logic level at point A will below (point B will also be low automati-cally – not being in touch with the liq-uid), point C will also be low and pointD will be high.

Once running, the pump will con-tinue to run even when the water risesabove the minimum level in the OHT(i.e. when point A subsequently goeshigh), provided the first condition is stillfully satisfied and the water level inthe sump has not fallen below that ofsensor 1'. It will stop only when eitherthe maximum specified level in the OHThas been reached or the water level inthe sump has fallen below sensor 1' po-sition.

Here the NOR gate pairs of N2 andN3, and N6 and N7, form NOR-latches.When the ground tank (sump) waterlevel is above the defined level 2', thevoltage at pin 11 of gate N6 is low. Sodiode D12 cannot conduct. Also, if themains voltage is within acceptable lim-its of 200-250V, the voltage at outputpin 3 of gate N12 is high and the volt-age at collector of transistor T2 is low.Diodes D8 and D11 are thus cut off. Sothe voltage at input pin 8 of gate N4 ispulled down to logic low level by pas-sive pull-down resistor R18 (56 kilo-ohm).

Now if overhead tank is empty, i.e.water level is below level 1, voltagestates at input pins 1 of gate N2, andpins 12 and 13 of gate N1, are pulleddown to logic low by passive pull-downresistors R13 and R14 respectively.Hence voltages at output pin 11 of gateN1 and input pin 5 of gate N3 becomelogic high to force the output at pin 4 of

Fig. 2: Power supply

Fig. 3: Construction details of probes for mineral water

Fig. 4: Construction details of probes for non-conducting liquids



gate N3 to be latched low. This logiclevel will not change until voltages atinput pins 5 and 6 of gate N3 becomelow (0V) and voltage at pin 1 of gate N2goes high (+5V). Since both inputs ofgate N4 are low, hence its output at pin10 goes logic high to drive transistor T1into conduction. Relay RL1 is thusenergised and the pump motor isswitched ‘on’.

The water level of the overhead tankstarts rising. When the water levelreaches the tip of the topmost sensor 5,voltage at pin 1 of gate N2 goes high.

Already, the voltage levels at pin 11 ofgate N1 and input pin 5 of gate N3 arelow. So the voltages at output pin 4 ofgate N3 and input pin 9 of gate N4 be-come logic high to turn the output pin10 of gate 4 to logic low level. Thusrelay RL1 is de-energised, to switch thepump off.

When line voltage is within thespecified limits and ground water levelgoes below the defined level 1', the volt-age at output pin 11 of gate N6 becomeslogic high to make diode D12 conduct.As a result, the voltage at pin 8 of gate

N4 becomes logic high to make its out-put pin 10 go low. Transistor T1 is cutoff and the relay is kept disabled, eventhough the overhead tank is fully empty.The relay will be enabled only when thewater level in the sump tank is abovelevel 2'.

When the ground tank water levelis above level 2' but the line voltage isout of range, gate N12 output pin 3 goeslow to cut off transistor T2, making di-ode D11 conduct. In this state the out-put of gate N6 and the output of gateN2 become logic low. Although diodeD12 does not conduct, diode D11 con-ducts and the output of gate N4 goeslow to cut off transistor T1. This dis-ables relay RL1 and the pump remains

PARTS LIST1Semiconductors:IC1 - CD4030 quad 2-input XOR

gateIC2 - 74LS47 BCD to 7-segment

decoder/driverIC3-IC5 - CD4001 quad 2-input NOR

gateIC6 - LM7812 regulator 12-voltIC7 - LM7805 regulator 5-voltT1-T2 - SL100 npn transistorD1-D15,D17-D20 - 1N4001 rectifier diodeD16 - Red LEDDIS1 - LTS542R 7-segment com-

mon anode displayResistors (all ¼-watt, ±5% carbon, unlessstated otherwise):R1-R8 - 33-kilo-ohmR9-R18 - 56-kilo-ohmR19-R21 - 1.5-kilo-ohmR22, R24 - 2.2-kilo-ohmR23 - 1.2-kilo-ohmR25 - 1-kilo-ohmR26, R27 - 220-kilo-ohmR28-R34 - 330-ohmVR1, VR2 - 100-kilo-ohm presetCapacitors:C1-C4, C7 - 0.01µF ceramic discC5 - 470µF, 35V DC electrolyticC6 - 2200µF, 35V DC electrolyticC8,C9 - 10µF, 25V DC electrolyticMiscellaneous:RL1 - 12V, 200-ohm 2 C/O relayX1 - 230V AC primary to

(a) 0-15V, 750 mA, and(b) 0-12V, 100 mA secondarytransformer

S1 - Push-to-on buttonS2 - On/Off switch

- IC sockets- Heat sinks for regulator ICs- SS304, 5mm dia. stainless

steel rod for anode and 3mmdia. for all cathodes - of ap-propriate length

- Multi-core feed wire

Fig. 5: Actual-size, single-sided PCB for water level controller

Fig. 6: Component layout for the PCB


off, even though the overhead tank iscompletely empty.

Here two cathode sensors for sens-ing ground tank water level have beenused instead of one, to provide somehysteresis in the system. When groundwater level is below level 1', the outputof gate N6 becomes logic high (5V).When water level is above level 2', theoutput of gate N6 is logic low (0V). Ifthe water level is in between levels 1'and 2', there is no change of state atoutput of gate N6, i.e. output remainsat the last/previous state.

Power supply (Fig. 2). The powersupply circuit consists of step-downtransformer X1 (having two secondar-ies with ratings of 12V, 100 mA and15V, 750 mA), a bridge rectifier (usingfour 1N4001 diodes), a capacitor of 2200µF for filtering purpose, regulator IC7812 for feeding the anode probes aswell as relay RL1, and regulator IC 7805for feeding regulated +5V supply to all

digital ICs, LEDs, and 7-segment dis-play. The 12V secondary is used for sam-pling the mains. One of its terminals isgrounded while its other terminal,marked ‘G’, is connected to point ‘G’ ofhigh/low cutout circuit in Fig. 1. Theother secondary rated at 15V, 750 mAis used for deriving the regulated DCsupplies required for operation of thecircuit.

Construction of sensors (Fig. 3).The highlight of the circuit are its elec-trodes (Fig. 3) used for mineral/conduc-tive water, which are made of stainlesssteel (grade SS-304) rods. These elec-trodes have a life span of more than fiveyears. Anode is a rod of 5 mm diameterand each of the cathodes is of 3 mmdiameter, as shown in the figure.

The cathodes and the anode shouldbe long enough so that their solderedterminals are not in contact with water,even when the tank is full. The jointsshould be covered with insulation in such

a way that rain water does not come incontact with the soldered joints. Onehas to use orthophosphoric acid or zinc-chloride to make a soldered joint be-tween stainless steel and conducting partof the flexible feed wire.

The distance between the anode andthe cathodes should not be more than 60cm. Arrangement should be made in sucha way that no electrode touches theother.

The circuit can also be used for non-conductive liquids such as pure distilledwater by using floats in conjunction withmicro switches, as shown in Fig. 4. Thisarrangement can be used for distilledwater plants, research laboratories, andfor other nonconductive liquid level sens-ing applications.

An actual-size, single-sided PCB forthe circuits in Figs 1 and 2 is shown inFig. 5, and the component layout isshown in Fig. 6.

PARTS LIST2Semiconductors:IC1-IC3 - CD 4030 quad 2-input X-OR

gateIC4 - 74LS47 BCD to 7-segment

decoder/driverRUPANJANA

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Aseparate alternative circuit of aunique liquid level indicatorto provide a display in terms of

the percentage of full-scale level in OHTis shown in Fig. 7. It can either be usedto replace the digital display circuit in-cluded in Fig. 1 (by simply connectingthe 10% and 100% sensor probes of Fig.7, additionally, to points marked ‘A’ and‘B’ respectively in Fig. 1, apart from con-nection of +5V and +12V supplies andground points) or it can be used in con-junction with an audio alarm unit shownin Fig. 8 and the power supply circuitin Fig. 2 independantly.

The latter configuration can be usedwhen you do not desire to have auto-matic control for switching the pumpmotor on and off but need only to be

warned when water reaches 100% andalso when its level drops to 10% so thatyou may manually switch the pump mo-tor on or off, as the case may be.

This level indicator can show the dis-crete levels in percentage from 0 to100% with 10% resolution. An audioalarm circuit has been incorporated togenerate audio alarm when the tanklevel reaches 100% and also when thelevel drops to 10%. The input to theaudio alarm circuit (Fig. 8) is tappedfrom line-1 and line-10 representing10% and 100% levels respectively inFig. 7.

If, in place of displaying the liquidlevel in percentage, one wants to dis-play only the digits 0 through 10, then7-segment display DIS1 and LEDs

IC5 - UM66 melody generatorDIS1-DIS3 - LTS 542 common anode

7-segment displayT1, T3, T4 - SL100 npn transistorT2 - BC 108 npn transistorD1-D16,D21, D22 - 1N4001 rectifier diodeZD1 - 3.1 volt zener diodeLED1-LED4 - Red LEDResistors (all ¼-watt, ±5% carbon, unlessstated otherwise):R1 - 3.3-kilo-ohmR2-R5 - 1.5-kilo-ohmR6-R24 - 330-ohmR25-R34 - 56-kilo-ohmR35-R44 - 33-kilo-ohmR45 - 100-kilo-ohmR46 - 2.7-kilo-ohmR47, R48 - 680-ohmCapacitor:C1 - 100µF, 25V electrolyticMiscellaneous:LS - 8-ohms speaker 7.5 cm dia

- SS 304, 5 mm dia and 3mmdia stainless steel rods of ap-propriate length for anodeand cathodes respectively.

- Multi-core feed wire

SADHAN CHANDRA DAS



(LED1 through LED4) for ‘%’ symbol canbe removed. This circuit can be usedfor premises which have overhead tanksand the water supply is provided by mu-nicipalities or corporations etc.

Display circuit. The basic elementsof the circuit, as shown in Fig. 7, com-prise three quad 2-input XOR gates (IC1through IC3) to get only the sum out-puts, a hardwired decimal-to-BCD con-verter (using diodes D1 through D16),and a 74LS47 BCD-to-7-segment de-

coder/driver(IC4). Whenthe tip ofsensor-1 is intouch withthe water,the line (L-1)connected topin 3 of IC1(CD 4030)goes to logic1 state(+5V).

W h e nthe tips of sensors 1 and 2 both touchthe water, pin 3 of IC1 goes to logic 0(0V), while line L-2 connected to pin 4of IC1 becomes high (+5V). Thus whichone of the lines (L-1 through L-10) willbe at logic 1 would depend on whichlast sensor (counted from bottom of thetank) is in touch with the water. If thetank is totally empty, all the lines, L-1through L-10, would be at logic 0.

These lines (L-1 through L-10) rep-resent the decimal numbers 1 through

10. If line L-1 is at logic 1, BCD code0001 is generated due to conduction ofdiode D9 only. Similarly, if line L-3 isat logic 1, BCD code 0011 is generateddue to conduction of diodes D6 andD16.

The voltages, corresponding to theirBCD codes, are fed to the inputs of IC74LS47 (7-segment decoder/driver) todrive 7-segment display DIS2. When lineL-10 is high, display DIS3 is driven bytransistor T1 (SL100) for decimal num-ber 1.

Since all the time the unit place digitof the percentage display is 0, the cath-odes of corresponding segments of DIS1have been permanently connected to0V (ground) through current-limitingresistors of 330 ohms each. In this waythe circuit displays 0 to 100 per centof liquid level with 10 per cent resolu-tion.

One may or may not use diode D1.In this circuit the resistors of 56-kilo-ohm are connected across the inputs ofXOR gates and ground, while resistors

Fig. 7: Unique liquid level indicator

Fig. 8: Audio alarm unit



from R2 to R5 have beenused for passive pull-down action.

Audio alarm unit.Fig. 8 shows the circuitfor audio alarm. Thebase of transistor T2(BC108) is connected tothe terminals of lines L-10 and L-1 via diodesD21 and D22 respec-tively and a common re-sistor of 100-kilo-ohm.

When water touchesthe topmost sensorprobe, transistor T2 con-ducts and transistor T3is cut off. As a result3.1V developed acrosszener ZD1 becomesavailable across pins 1and 2 of melody genera-tor IC7 (UM66). Theamplified musical alarmis heard from thespeaker.

When the tank is nei-ther 100% full nor it isabove 10% (but less than20%), transistor T2 cutsoff while transistor T3is saturated to makethe voltage across pins 1and 2 of IC7 at almost0V, and hence no soundis produced by the unit.

A separate parts listand actual-size PCB lay-out as well as componentlayout (Figs 9 and 10 re-spectively) are includedafter integrating thepower supply of Fig. 2with liquid level indica-tor circuit of Fig. 7 andaudio alarm unit ofFig. 8. ❏

Fig. 9: Actual-size, single-sided PCB for the unique liquid level indicator

Fig. 10: Component layout for the above PCB

March

2001

Circuit Ideas

2001


lay is in energised state. LED1, con-nected in series with 68-ohm resistor
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ELECTRONICS FOR YOU� ❚❚❚❚❚ �MARCH 2001

S.C. DWIVEDI

sound from UM3561. Resistor R4 in se-ries with a 3V zener is used to providethe 3V supply to UM3561 when the re-

SUKANT KUMAR BEHARAR1 across resistor R4, glows when thesiren is on.

To test the working of the cir-cuit, bring a burning matchstickclose to transistor T1 (BC109),which causes the resistance of itsemitter-collector junction to go lowdue to a rise in temperature and itstarts conducting. Simultaneously,

transistor T2also conducts be-cause its base isconnected to thecollector of tran-sistor T1. As aresult, relay RL1energises andswitches on thesiren circuit toproduce loudsound of a fire-brigade siren.

Lab note.We have added a

table to enable readers to obtain all pos-sible sound effects by returning pins 1and 2 as suggested in the table.

Pin Designation Sound EffectSEL1 SEL2No Connection No Connection Police Siren+3V No Connection Fire Engine SirenGround No Connection Ambulance SirenDo not care +3V Machine Gun

This circuit uses a complementarypair comprising npn metallictransistor T1 (BC109) and pnp

germanium transistor T2 (AC188) to de-tect heat (due to outbreak of fire, etc)in the vicinity and energise a siren. Thecollector of transistor T1 is connectedto the base of transistor T2, while thecollector of transistor T2 is connectedto relay RL1.

The second part of the circuit com-prises popular IC UM3561 (a siren andmachine-gun sound generator IC), whichcan produce the sound of a fire-brigadesiren. Pin numbers 5 and 6 of the ICare connected to the +3V supply whenthe relay is in energised state, whereaspin 2 is grounded. A resistor (R2) con-nected across pins 7 and 8 is used to fixthe frequency of the inbuilt oscillator.The output is available from pin 3.

Two transistors BC147 (T3) andBEL187 (T4) are connected inDarlington configuration to amplify the


IVEDI

ing. Simultaneously, the emitter-baserjunction of transistor BC558 also starts
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S.C. DW

Here is a musical call bell thatcan be operated by just bridg-ing the gap between the touch-

plates with one’s fingertips. Thus thereis no need for a mechanical ‘on’/‘off’switch because the touch-plates act asa switch. Other features include low costand low power consumption. The bellcan work on 1.5V or 3V, using one ortwo pencil cells, and can be used inhomes and offices.

Two transistors are used for sens-ing the finger touch and switchingon a melody IC. Transistor BC148 isnpn type while transistor BC558 is pnptype.

The emitter of transistor BC148 isshorted to the ground, while that oftransistor BC558 is connected to thepositive terminal. The collector of tran-sistor BC148 is connected to the base ofBC558. The base of BC148 is connectedto the washer (as shown in the figure).

The collector of BC558 is connected topin 2 of musical IC UM66, and pin 3 ofIC UM66 is shorted to the ground. Theoutput from pin 1 is connected to a tran-sistor amplifier comprising BEL187transistor for feeding the loudspeaker.One end of 2.2-mega-ohm resistor R1is connected to the positive rail and the

other to a screw (as shown in the fig-ure). The complete circuit is connectedto a single pencil cell of 1.5V.

When the touch-plate gap is bridgedwith a finger, the emitter-collector junc-tion of transistor BC148 starts conduct-

SUKANT KUMAR BEHARAconducting. As a result, the collector oftransistor BC558 is pulled towards thepositive rail, which thus activates melodygenerator IC1 (UM66). The output ofIC1 is amplified by transistor BEL187and fed to the speaker. So we hear amusical note just by touching the touchpoints.

The washer’s inner diameter shouldbe 1 to 2 mm greater than that of thescrewhead. The washer could be fixed in

the position by using an adhesive, whilethe screw can be easily driven in awooden piece used for mounting thetouch-plate. The use of brass washer andscrew is recommended for easy solder-ability.


IVEDI

stable multivibrator wired around thecommon 555 timer IC. It can be set orreset by the closure of reed switches.The output of the multivibrator drivesthe relay, which controls the AC mains

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EFY readers are quite familiarwith liquid-level controllers. Butthe one presented here is dif-

ferent. Usually, transducers using elec-

tric conduction, or variation in resis-tance or capacitance principle, are em-ployed for level sensing.

In conduction type of sensors, theelectric current passes through the liq-uid. The corrosion of contacts is a ma-jor problem while using DC excitation.The cost and the size are the two re-strictive factors in using AC excitation.Further, passing current through theliquid in combustive environments is not

permissible.In resistance type sensors, the re-

sistance is altered through some me-chanical arrangement, which means a

large operatingforce is re-quired, whichmay be a prob-lem in smalltanks. In ca-pacitive trans-ducer type, thec o n s t r u c t i o ncost is high.

In thepresent project,an easy but ef-fective liquid-level controlleris presented us-ing the mag-

netic principle. It is non-contact typeand hence can be used in almost all ap-plications, irrespective of whether theliquid is conductive or not. Two reedswitches (with glass enclosure) and aring magnet (normally used in loud-speakers) form the sensor unit. The reedswitches used are normally-open typeand they close when placed (and ori-ented properly) in a magnetic field.

The electronic circuit is a simple bi-

S.C. DW supply to the pump motor or any othercontroller (such as a solenoid-operatedvalve).

The reed switches are connected asshown in the figure. These are put in aclosed (non-conductive) tube, which isthen placed in the tank. The ferrite ringmagnet is put inside the float, and it

moves up and down along thetube depending upon thelevel of the liquid in the tank.

When the level of the liq-uid in the tank is low, themagnet comes closer to reedswitch S2. As a result, switchS2 is closed and the bistablemultivibrator sets. This ac-tuates the relay, therebystarting the pump to fill thetank. The level of the liquidin the tank starts increasing.

When the level of the liq-uid in the tank is highenough, the ring magnetcomes close to reed switch

S1, and it closes. The bistablemultivibrator now resets and the pumpis switched off. This process is repeatedand the tank gets filled automatically.

Switches S1’ and S2’ are used fortesting the circuit or when the reedswitches are non-functional. A neon bulbis used to indicate the presence of theAC supply in the plug. An optionalpiezobuzzer is used to raise an audible

R.G. THIAGARAJ KUMAR



alarm when the relay energises.If you desire to display the level of

the liquid in the tank, additional reedswitches would need to be placed insidethe tube at different levels (say, 1/4th, 1/2, 3/4th, and near-overflow level). They

can be connected between the LEDs andthe supply via current-limiting resistorsfor level indication. The LEDs can bearranged in a model tank diagramprinted on the front panel of the con-troller. The LED corresponding to the

level of the liquid in the tank would glowin this arrangement.

The selection of float material is to bedone carefully to avoid chemical reac-tion and/or pollution of the liquid. Teflonfloats are suitable for most applications.


DWIVEDI

the second part of the circuit.The three phases (R, Y, and B) are

brought to an artificial neutral at the junc-tions of resistors R17 through R19 (each22 kilo-ohm, 2-watt) to serve as the com-mon reference. As stated earlier, for agiven phase sequence, when phase R is
.C.
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specified fashion, as shown in the figure.The second part comprises the phase-se-quence detector followed by phase-se-quence sensor operated flip-flop and LEDswitching transistors.

The astablemultivibratorsection providesclock pulses inthe 10 to1000Hz range tothe decadecounter and theLED array sec-tion. The LEDsare grouped intotwo parts toform two dis-

tinctive indicators. Thesetwo groups are successivelydriven by Q0 to Q4 and Q5 to Q9 outputsof IC1. Only one of the two groups’ LEDswill turn on sequentially, depending onwhich of the two transistors (transistorT3 or transistor T4) is on, which, in turn,is dependent upon the phase sequence ofthe three-phase supply. This becomesclear from the following explanation of

S

M.K. CHANDRA MOULEESWARANat its negative-going zero, phase B is nega-tive. So data-input pin 5 of the flip-flop(IC2) is logic ‘high’ (due to non-conduc-tion of transistor T5). Meanwhile, clock-input pin 3 of the flip-flop goes from lowto high due to phase R (refer waveformsfor condition 1, as observed by EFY Lab).The ‘high’ at data pin appears at the Q

output (pin 1) while Q output remains‘low’ as long as the phase sequence isclockwise. Therefore the Q output drivestransistor T3 to extend the ground pathfor green LEDs D1 through D10 to showa clockwise-rotating LED ring.

When any of the two phases gets in-terchanged (say, after a maintenance

Amains phase-sequence indicatorserves as a hand-tool in checking electrical wiring, especially the

wiring of three-phase AC motors.The basic idea of the circuit is that

when any (say, Y) of the three phases(RYB), taken as a reference phase, is atnegative-going zero voltage, its leadingphase (say, R) is positive while its lag-ging phase (B) is negative, and thesestates can be easily verified.

The circuit comprises two main parts.The first part comprises transistorisedmultivibrator, decade counter-cum-LEDdriver, and LED arrays arranged in a



work at the power-house or repair/replace-ment of a 3-phase transformer), the con-ditions are reversed (refer waveform for

condition 2, as observed byEFY Lab), and Q become‘high’ and red LEDs D11through D20 are switchedon (sequentially) by tran-sistor T4 to show ananticlockwise-rotating ring.

While testing for thephase sequence, there is noneed to keep the device onfor a long time. A push-to-on read switch can be usedduring the phase-sequencetesting. If the device is to

be used for long periods, use a high-capac-ity battery in place of PP3 battery. Alsoreplace 2W resistors R17 to R19 with 5W

fusible-type resistors.The frequency of the astable

multivibrator is unimportant, except thatthe speed of the LED ring must be easilyvisible. Zener diodes ZD1 and ZD2 areused for protection of transistors T5 andT6, respectively.

Precautions. 1. Never use an ACmains adaptor-type power supply in placeof the battery.

2. Correctly position LEDs D1through D20 in the ring for its properviewing.

3. Assemble resistors R11 to R19 onthe PCB at a slightly elevated level usingceramic beads for proper dissipation ofheat.


disk to pin 5 of IC1 and the other endto pin 8 of IC1 through a 1/4W, 1-kilo-
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S.C. DWIVEDI

An interesting circuit of a bicyclehorn based on a popular, low-cost telecom ringer chip is de-

scribed here. This circuit can be pow-ered using the bicycle dynamo supplyand does not require batteries, whichneed to be replaced frequently.

The section comprising diodes (D1and D2) and capacitors (C1 and C2)forms a half-wave voltage-doubler cir-cuit. The output of the voltage doubleris fed to capacitor C3 via resistor R1.The maximum DC supply that can beapplied to the input terminals of IC1 is28V. Therefore zener diode ZD1 is addedto the circuit for protection and voltageregulation.

The remainder of the circuit is thetone generator based on IC1 (KA2411).The dual-tone output signal from pin 8of IC1 is fed to the primary of transfor-mer X1 (same as used in transistor ra-dios) via capacitor C6. The secondary ofX1 is connected to a loudspeaker directly.

In case you are interested in con-

necting a piezoceramic element in placeof the loudspeaker, remove capacitor C6,transformer X1, and the loudspeaker.Connect one end of the piezoceramic

ohm resistor.IC1 KA2411 is also available in COB

style, with the same pin configuration.

Both packages work equally well. How-ever, to get the best results with theCOB package, change values of resis-tors R2 through R4 to 330-kilo-ohm, ca-pacitor C4 to 0.47µF, 63V electrolytic(positive end to pin 3 of IC1), and C5 to0.005µF, 63V.

This bicycle horn project can also beused as a telephone extra ringer by justremoving all components on the left sideof capacitor C3 and connecting the cir-cuit shown in Fig. 2 to the terminals ofcapacitor C3.

T.K. HAREENDRAN


with doors kept open, a parallel on/offswitch is included on the switchboardto bypass the relay contacts and manu-ally control the switching on/off of thelight and exhaust fan. (This is the ser-vice mode.) In this case, the music re-

S.C. DWIVEDI
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Aged persons in the house andguests often fumble whilesearching for the toilet and

bathroom switches at night. Also, veryfew of us take care to switch off thelights of toilets/bathrooms after usingthem. The circuit given here helps toovercome both the problems.

The figure shows two symmetricalcircuits (one each for toilet and bath-room) sharing common power supplyand a melody generator-cum-audiowarning unit. The reed switches S1 andS2 are of normally-open type, operatedby permanent magnets appropriatelyfixed to the doors of bathroom and toi-let, respectively. When the doors ofbathroom and toilet are closed, the reedswitches are also closed, and vice versa.(Door is assumed in closed conditionwith nobody inside bathroom/toilet, i.e.reed switch is activated.)

The operational features of the cir-cuit are:

mains on as long as the door remainsopen. In case of failure of the unit, thesame on/off switch can be used as usualuntil the circuit is repaired.

• Due to battery backup facility,even with power failure, when a personis inside, the door status is maintained.However, the lamp and fan will be ononly on mains resumption.

• Also, when a person leaves theroom during power failure, with doorclosed, the lamp and fan are kept off onresumption of power. (Intelligent-mode!)

• However, the circuit can be fooledby opening and closing the door within10 seconds, without entering inside. Inthis case, the lamp and fan will con-tinue to be on and would require re-opening and closing of the door to bringthe circuit to order.

This problem can be prevented tosome extent by using a hydraulic dooropener, which would approximately take10 seconds to close the opened door. Adelay period of 10 seconds is deliber-ately chosen for letting the person in-side the toilet/bathroom in normal case!

IC1 is a dual positive edge-triggered‘D’ type flip-flop. IC1(a) gets triggered

Fig. 1

• Lamp and exhaust fan areswitched on when the door is opened.

• Soft music is played continuouslyuntil the door is closed from inside/out-side.

• With a person inside the room,lamp and fan remain on, until the dooris reopened. They go off when the dooris reopened.

• Visual indication of whether thetoilet/bathroom is occupied/vacant isgiven by two bicolour LEDs fixed on apanel, which may be fitted near the doorwith corresponding ‘toilet’/’bathroom’ la-bels on them. Here the LED colour turnsfrom ‘green’ to ‘red’ if the room getsoccupied, and vice-versa.

• If the door is opened once, andnot closed back within 10 seconds, thelamp and fan are automatically switchedoff, thus conserving electricity. But themusic remains on as a reminder thatthe door is not closed.

• For cleaning of bathroom/toilet

A.R. GIDWANI


when bathroom door (and switch S1) isopened and hence IC1(b) toggles, as Qoutput of IC1(a) is connected to clockinput pin of IC1(b). As a result, relayRL1 energises through transistor T3,thereby switching on the lamp and ex-haust fan. (Please refer to Fig. 2, theseparate wiring diagram of lamp andexhaust fan via the N/O contacts of therelay.) Simultaneously, pin 2 (Q) ofIC1(a) goes low, switching transistor T5‘on’, which switches on melody genera-tor IC4, letting out a sweet audio tunevia transistor T6 and loudspeaker.

In normal condition, when someoneopens the bathroom door and gets insidewithin preset time of IC3(a) (10 secondshere), and closes the door from inside,the music stops with lamp and fan ‘on’.Now, in case someone opens the doorbefore or after use, and forgets to shutit, the lamp and exhaust fan are switchedoff after 10 seconds but the music re-mains ‘on’ as a reminder that the door isto be closed. This happens due to monomultivibrator (MMV) IC3(a), which re-sets pin 10 of IC1(b) through transistorT1 after 10 seconds. (This period can beadjusted by varying the values of resis-tor R11 and/or capacitor C7.)

It should be noted here that al-

though IC3 is used as ‘MMV’, it is trig-gered here with a positive pulse throughits pin 4 (reset pin) rather than its pin6 (trigger pin). This arrangement makesit unique for setting and resetting IC3through pin 4, and resetting IC1(a)through pin 5 of IC3 and transistor T1.

Battery backup facility ensuresmemory backup during power failure.Power supply uses a normal 2-diode full-wave rectifier circuit, which needs nofurther explanation. The purpose of us-ing bi-colour LED1 and LED2 is that,initially when the door is closed theseemit green light— as the green LED partgets the supply via resistor R15— to in-dicate that bathroom/toilet is vacant.When bathroom/toilet is occupied, tran-sistor T3/T4 conduct to light up the redLED part as well.

Melody generator IC4 (UM66) isswitched on through diodes D3/D4 andtransistor T5, which conducts whenIC1(a) pin 2 or IC2(a) pin 2 goes low.When transistor T5 conducts, zener ZD1breaks down and supplies regulated3.9V to IC4, to produce a melodious tunevia transistor T6 and the speaker.

As most toilets and bathrooms are‘attached’ nowadays, only a single cir-cuit is required, and the circuit can bewired on a general-purpose veroboard.

A small modification of the circuit,by adding additional SPST switch S3,as shown in Fig. 2, needs to be doneinside the wooden switchboard box. Thispermits the user to operate the lampand fan during cleaning of the toilet orfor bypassing the circuit, when bath-room or toilet undergo repair work.

Fig. 2


Construction

2001


be printed and stores them in an inter-nal buffer. When the printer detects acarriage return (0dH), it prints out thefirst row of characters from the printerbuffer. When the printer detects a sec-

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�� JANA


RUPAN

SHAILA GHANTI

It is very convenient to interface aprinter to print 8085 programs.Here a simple hardware interface

circuit with its driver software is de-scribed that would enable students totake printout of the 8085 programs inhexadecimal codes along with theirmemory locations in the format:

XXXX DD,where XXXX is the 4-bit hexadecimaladdress and DD is 2-bit hexadecimaldata.

For most types of printers, the datato be printed is sent to the printer asASCII characters on eight parallel lines.The printer receives the characters to

ond carriage return, it prints out thesecond row of characters. The processcontinues until the desired charactersare printed.

Transfer of ASCIIcodes from the micro-processor to a printerneeds to be done ona handshake basis be-cause the micropro-cessor can send char-acters much fasterthan the printer can

print them.The printermust in someway let the mi-croprocessorknow that itsbuffer is full,and it cannotaccept anymore charac-ters until itprints outsome of the al-ready storedcharacters. Acommon stan-dard for inter-facing withparallel print-ers is theCentronics in-terface.

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C e n t r o n i c sprinters usu-ally have a 36-pin interfaceconnector. Thepin assign-ments of thes i g n i f i c a n tpins ofCentronics in-terface connec-tor, used inthis project,

TABLE IPin Assignments of Centronics

Interface ConnectorPin no. Signal Direction2 Data bit 0 (D0) In3 Data bit 1 (D1) In4 Data bit 2 (D2) In5 Data bit 3 (D3) In6 Data bit 4 (D4) In7 Data bit 5 (D5) In8 Data bit 6 (D6) In9 Data bit 7 (D0) In

1 Strobe (STR) In14 Auto Feed (AF) In36 Device Select (DSL) In31 Initialise (INIT) In

11 Busy (BSY) Out13 Select (SEL) Out32 Error (ERR) Out12 Paper end (PE) Out19 to30, 33 Ground —

Fig. 2: System’s block diagram

Fig. 3: Schematic diagram of the printer interface circuit

Fig. 1: Timing diagram



7112 XCHG 1B Exchange DE with HL pair so thatHL is initialised to starting memorylocation of the program to be printed.

7113 LXI D 2A20 11 Initialise memory locations to store7114 20 ASCII codes of the program.7115 2A7116 MOV A,H 7C To get the ASCII codes of addresses7117 CALL 70FC CD of memory location of the program to7118 FC be printed using the subroutine.7119 71711A MOV A,H 7C711B CALL7100 CD711C 00711D 71711E MOV A,L 7D711F CALL 70FC CD7120 FC7121 707122 MOV A,L 7D7123 CALL 7100 CD7124 007125 717126 MOV A,M 7E To get the ASCII codes of the7127 CALL 70FC CD contents of the program to be7128 FC printed using the subroutine.7129 70712A MOV A,M 7E712B CALL 7100 CD712C 00712D 71712E INX H 23 Increment pointer to mem. location.712F MOV A,M 7E Move contents of mem. into acc.7130 CPI CF FE Whether it is end of the program.7131 CF7132 JNZ 7116 C2 If not, start executing from 7116.7133 167134 717135 MVI A,43 3E If it is end of the program,7136 43 transfer the code for CF.7137 STAX D 127138 INX D 137139 MVI A, 46 3E713A 46713B STAX D 12713C DCX D 1B713D LXI H 2A20 21 Initialise mem. pointer to block713E 20 (2A20) where ASCII codes of charac-713F 2A ters to be printed are stored.7140 MVI A, 82 3E Initialise 8255.7141 827142 OUT 0B D3 Write control word in control register7143 0B of 8255.7144 MVI A, 0B 3E Reset printer.7145 0B7146 OUT 0B D37147 0B7148 CALL 7200 CD Delay for a few microseconds.7149 00714A 72714B MVI A,05 3E Send SELECT signal.714C 05714D OUT 0B D3714E 0B714F IN 09 DB Read the status of printer to find7150 09 out whether the printer is selected.7151 ANI 02 E67152 027153 CPI 02 FE7154 027155 JNZ 714F C2 If printer is not selected, again read7156 4F the status of printer

Memory Instructions Code Commentslocation


7157 717158 MVI B,04 06 Else counter of 4 is initialised in B7159 04 register to print 4 digits of memory715A CALL 7220 CD address (use subroutine to transfer715B 20 data to printer in polling mode).715C 72715D INX H 23 Get next memory location715E DCR B 05 Check whether 4 characters are715F JNZ 715A C2 transferred.7160 5A7161 717162 MVI A, 20 3E Send the (20) blank space to printer7163 207164 OUT 08 D37165 087166 MVI A,09 3E To generate STROBE pulse to printer7167 097168 OUT 0B D37169 0B716A MVI A,08 3E716B 08716C OUT 0B D3716D 0B716E MVI C,02 0E Counter of 2 is initialised in C register716F 02 to print 2 codes.7170 CALL 7220 CD Use subroutine to transfer data.7171 20 in polling mode.7172 727173 INX H 23 Get next memory location7174 DCR C 0D Check whether 4 characters are7175 JNZ 7170 C2 transferred.7176 707177 717178 MVI A, 0A 3E Send LF code to printer.7179 0A717A OUT 08 D3717B 08717C MVI A,0D 3E Send CR code to printer.717D 0D717E OUT 08 D3717F 087180 MVI A,09 3E7181 097182 OUT 0B D37183 0B7184 MVI A,08 3E7185 087186 OUT 0B D37187 MOV A,E 7B Check wheter the full program7188 XRA L Ad codes are transferred to printer7189 JNZ 7158 C2 If not, continue to transfer next718A 58 codes.718B 71718C MOV A,D 7A718D XRA H AC718E JNZ 7158 C2 Else, stop executing the program.718F 587190 717191 RST 1 CF

Subroutine for converting hexadecimal to ASCII codes70FC RRC 0F Rotate right 4 times to get 4 MSB.70FD RRC 0F70FE RRC 0F70FF RRC 0F7100 ANI 0F E6 Mask 4 LSBs7101 0F7102 CPI 0A FE Compare with 0A7103 0A7104 JC 7109 DA If it is less than 0A,7105 C6

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7106 707107 ADI 07 C6 Add 07 to data7108 077109 ADI 30 C6 Else add 30H to data to convert data710A 30 into ASCII code.710B STAX D 12710C INX D 13710D RET C9

Subroutine to transfer data in polling mode:7220 MVI A 09 3E To generate the STROBE signal7221 097222 OUT 0B D37223 0B7224 IN 09 DB Find whether the printer is not BUSY7225 097226 ANI 01 E67227 017228 CPI 00 FE7229 00722A JNZ 7224 C2722B 24722C 72722D MOV A,M 7E Get the ASCII code from memory

722E OUT 08 D3 location, send the data to printer to722F 08 print.7230 MVI A,08 3E Send the strobe pulse with min7231 08 0.5µs duration.7232 OUT 0B D37233 0B7234 MVI A,09 3E7235 097236 OUT 0B D37237 0B7238 MVI A,08 3E7239 08723A OUT 0B D3723B 0B723C RET C9

Subroutine for delay:7200 MVI C, FF 0E Load C register with data FF.7201 FF7202 DCR C 0D Decrement the contents of C reg.7203 JNZ 7202 C2 If the contents of C is not zero, go to7204 02 7202.7205 727206 RET C9

9000 310095 LXI SP,9500H ;Initialise stack pointer9003 11209D LXI D,9D20H ;Store location where9006 EB XCHG ;data to be printed starts

;into register pair DE9007 11209A LXI D,9A20H ;Location where ASCII900A 7C X1: MOV A,H ;conversion of data is

;stored900B CDFC90 CALL 90FCH ;Convert addresses of900E 7C MOV A,H ;mem. locations of data900F CD0091 CALL 9100H ;to be printed into ASCII9012 7D MOV A,L9013 CDFC90 CALL 90FCH9016 7D MOV A,L9017 CD0091 CALL 9100H901A 7E MOV A,M ;Convert data to be901B CDFC90 CALL 90FCH ;printed into ASCII901E 7E MOV A,M901F CD0091 CALL 9100H9022 23 INX H9023 7E MOV A,M9024 FECF CPI CFH ;End of data?9026 C20A90 JNZ X19029 3E43 MVI A,43H ;ASCII code of C902B 12 STAX D902C 13 INX D902D 3E46 MVI A,46H ;ASCII code of F902F 12 STAX D9030 1B DCX D9031 21209A LXI H,9A20H ;Initialise mem. pointer

;to start of ASCII codes9034 3E82 MVI A,82H ;Initialise 82559036 D30B OUT 0BH9038 3E30 MVI A,30H ;Initialise Printer903A D30A OUT 0AH903C 3E10 MVI A,10H903E D30A OUT 0AH9040 CD0092 CALL 9200H ;Call delay9043 3E30 MVI A,30H9045 D30A OUT 0AH9047 3E02 MVI A,02H ;ASCII code for start of

;text

Addr. Hex code Label Mnemonics Remarks Addr. Hex code Label Mnemonics Remarks9049 D308 OUT 08H904B CD5092 CALL 9250H ;Call status904E CD7092 CALL 9270H ;Call strobe9051 0604 X4: MVI B,04H ;Counter of 4 for printing9053 CD2492 X2: CALL 9224H ;four digits of addresses9056 23 INX H ;of memory location9057 05 DCR B9058 C25390 JNZ X2905B 3E20 MVI A,20H ;Send blank space to

;printer905D D308 OUT 08H905F CD5092 CALL 9250H ;Call status9062 CD7092 CALL 9270H ;Call strobe9065 0602 MVI B,02H ;Counter of 2 for printing9067 CD2492 X3: CALL 9224H ;two digits of data906A 23 INX H906B 05 DCR B906C C26790 JNZ X3906F CD9092 CALL 9290H ;Call LFCR9072 7B MOV A,E ;Check whether all data9073 AD XRA L ;has been transfered for

;printing9074 C25190 JNZ X49077 7A MOV A,D9078 AC XRA H9079 C25190 JNZ X4907C 3E03 MVI A,03H ;ASCII code for end of

;text907E D308 OUT 08H9080 CD5092 CALL 9250H ;Call status9083 CD7092 CALL 9270H ;Call strobe9086 3E04 MVI A,04H ;ASCII code for end of9088 D308 OUT 08H ;transmission908A CD5092 CALL 9250H ;Call status908D CD7092 CALL 9270H ;Call strobe9090 76 HLT

;Subroutine for converting hex to ASCII90FC 0F RRC ;Rotate four times to get

;MSB90FD 0F RRC

��"��" ��!��"��



Addr. Hex code Label Mnemonics Remarks

90FE 0F RRC90FF 0F RRC9100 E60F ANI 0FH ;Mask four bits of LSB9102 FE0A CPI 0AH9104 DA0991 JC X59107 C607 ADI 07H9109 C630 X5: ADI 30H910B 12 STAX D910C 13 INX D910D C9 RET

;Output Subroutine9224 7E MOV A,M ;Output one byte of data9225 D308 OUT 08H9227 CD5092 CALL 9250H ;Call status922A CD7092 CALL 9270H ;Call strobe922D C9 RET

;Delay Subroutine9200 C5 PUSH B9201 06FF MVI B,FFH9203 0EFF X7: MVI C,FFH9205 0D X6: DCR C9206 C20592 JNZ X69209 05 DCR B920A C20392 JNZ X7920D C1 POP B920E C9 RET

;Status Subroutine9250 C5 PUSH B9251 06FF X9: MVI B,FFH9253 0EFF X8: MVI C,FFH9255 DB09 IN 09H ;In port B9257 E60F ANI 0FH ;Compare with 06H9259 FE06 CPI 06H

Addr. Hex code Label Mnemonics Remarks

925B CA6692 JZ X11925E 0D DCR C925F C25392 JNZ X89262 05 DCR B9263 C25192 JNZ X99266 C1 X11: POP B9267 C9 RET

;Strobe subroutine9270 3E20 MVI A,20H9272 D30A OUT 0AH9274 C5 PUSH B9275 0EFF MVI C,FFH9277 0D X10: DCR C9278 C27792 JNZ X10927B C1 POP B927C 3E30 MVI A,30H927E D30A OUT 0AH9280 C9 RET

;Line feed and Carriage return Subroutine9290 3E20 MVI A,20H ;ASCII code for Space9292 D308 OUT 08H9294 CD5092 CALL 9250H ;Call status9297 CD7092 CALL 9270H ;Call strobe929A 3E0A MVI A,0AH ;ASCII code for Line feed929C D308 OUT 08H929E CD5092 CALL 9250H ;Call status92A1 CD7092 CALL 9270H ;Call strobe92A4 3E0D MVI A,0DH ;ASCII code for Carriage

;Return92A6 D308 OUT 08H92A8 CD5092 CALL 9250H ;Call status92AB CD7092 CALL 9270H ;Call strobe92AE C9 RET

are given in Table I.Fig. 1 shows the timing waveforms

for transferring data characters to theprinter using the basic handshake sig-nals. Assuming that the printer hasbeen initialised, first check the busysignal pin to see if the printer is readyto receive data. If this signal is low

(not busy), send anASCII code on theeight parallel datalines. After at least 0.5µs, assert the STROBEsignal low to tell theprinter that a charac-

ter has been sent. The strobe signalgoing low causes the printer to assertits BUSY signal high. After a minimumtime of 0.5 µs, the strobe signal can beraised high again. Note that the datamust be held valid on the data lines forat least 0.5 µs after the strobe signal ismade high. When the printer is ready

to receive the next character, the BUSYsignal will be low. The process contin-ues.

The 8085 microprocessor is inter-faced to the printer through 8255 pro-grammable peripheral interface deviceas shown in the block diagram (Fig. 2)

and the detailed interface dia-gram (Fig. 3). One end of thecable, which is used for connect-ing 8255 to the printer, shouldnormally have a 26-pin FRC con-nector to meet with the corre-sponding connector on the kit,and the other end should have a36-pin male Centronics connec-tor to go into the correspondingconnector on the printer.

Port A of 8255 is used fortransferring the data to the

printer. Port B is used for checking thestatus signals coming from the printer.Port C is used for sending the controlsignals required to activate the printer.The interface signals between 8255 andthe printer should be connected asshown in Table I.

(EFY Lab note. The maximum cur-

TABLE IIPort B of 8255—(Input) Status Signals

Cent. pin no. 12 32 13 11Signal PE ERR SEL BSY CommentsData B3 B2 B1 B0

0 1 1 0 =06H (status OK)

}

TABLE IIIPort C of 8255—(Output) Control Signals

Cent. pin no. NU 14 31 1 NU 36 NU NUSignal AF INIT STR DSL CommentsData C7 C6 C5 C4 C3 C2 C1 C0

X 0 1 1 X 0 X XX 0 0 1 X 0 X X

X 0 1 1 X 0 X XX 0 1 0 X 0 X X

X 0 1 1 X 0 X XNU=Not Used

=30H printer=10H initiali-long delay sation=30H=20H

strobeShort delay=30H

}



rent that an 8255 output pin can sourceand sink is limited to 400 µA and 2.5mA, respectively. To enhance this capa-bility, open-collector hex buffers/drivers7407 shown in Fig. 3 were used for alloutput port pins. For input port pins,there is no danger of overloading, andhence these pins were connected directlyfrom the printer to the kit.)

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During initialisation, some memory lo-cations are kept aside to store the ASCIIequivalent of the characters that are tobe printed. This is followed by configu-ration (initialisation) of 8255 by send-ing the mode control word to its controlregister. To initialise the printer, first

Fig. 4: Actual-size, single-sided PCB forthe printer interface circuit

send initialisation (INIT*) pulse for afew microseconds. Then send the selectsignal (DSL*) to select the printer. Readthe status to find out whether theprinter is selected and the BUSY signalis low. Now send the ASCII characterto print the character, followed by theSTROBE* pulse for 0.5 µs. The processcontinues till the end of the program.The end of the program is indicated us-ing RST1 (CFH).

The starting location of the programto be printed should be stored in D andE registers. The eight MSBs and eightLSBs of memory location should bestored in D register and E register, re-spectively. The complete software pro-gram is given (page 46) with commentsas necessary.

(EFY Lab note. The original pro-gram was tried many times, but we didnot succeed. Finally, the program wasextensively modified and successfullyrun using Epson 9-pin printer. The pro-gram, along with Tables II and III show-ing the status and control signals thathave been used in program implemen-tation, is included (page 47) for the ben-efit of readers, who may try both theprograms, if desired.)Address map of devices used:RAM locations used: 9000H to 92AEH (70FCHonwards used by author)PORT A (output) : 08HPORT B (input) : 09HPORT C (output) : 0AHControl word register : 0BHImportant memory locations :Stack pointer initialised : 9500HData to be printed is stored at : 9D20H onwardASCII conversion of data to be printed startsat: 9A20H. Data to end with CFH as the lastbyte.

The actual-size, single-sided PCBlayout of the printer interface circuitand the component layout are shown inFigs 4 and 5, respectively. ❏


PARTS LISTSemiconductors:IC1, IC2 - 7407 hex buffer/driver (open-

collector type)Resistors (all ¼-watt, ±5% carbon, unlessstated otherwise):R1-R12 - 1-kilo-ohm (or use one-/two-

resistor networks)Miscellaneous:

- Centronics connector andcable


RUPANJANA ��

The circuit is configured around the ba-
��

M orse code, introduced bySamuel Morse, is still useduniversally even though bet-

ter modes of communication are nowavailable. Following are the main rea-sons for its preference over other meansof communication:

1. It enables communication withdistant stations, using low-power trans-mitters.

2. It avoids the problems of regionalaccents and pronunciation.

3. It has the ability to override noiseas it occupies only a fraction of the band-width required for a radio telephonysignal.

The circuit presented here convertstext intothe corre-s p o n d i n gM o r s ecode, andvice versa.The high-light ofthis circuitis that itcan inter-pret Morses i g n a l sava i lab lein the formof soundfrom hamradio orany othersource. Itis veryuseful fornot onlyl e a r n i n gbut alsofor trans-

sic 8085 microprocessor. For simplify-ing the overall design, a programmablekeyboard/display interface 8279 chip hasbeen used, which relieves the micropro-cessor from scanning the keyboard anddisplay. Here, 25 keys, including SHIFTand CNTL keys, and six 7-segment com-

TABLE IIAddress Distribution

Device AddressEPROM 0000 to 03FFRAM 1000 to 17FF8279: Command Port 21 Data Port 20

Lookup TableChr/ Address Hexcode Ch/ Address Hexcode Ch/ Address Hexcodeword word word0 0300 3F AA 0E 00 J 034C 1E A9 03 00 . 03B4 80 99 39 001 0304 06 A9 0E 00 K 0350 70 E6 00 00 , 03B8 04 5A 3A 002 0308 5B A5 0E 00 L 0354 38 59 03 00 ; 03BC 84 66 36 003 030C 4F 95 0E 00 M 0358 55 3A 00 00 ? 03C0 D3 A5 35 004 0310 66 55 0E 00 035C 46 – 03C4 08 56 39 005 0314 6D 55 0D 00 03C8 00 3F 00 006 0318 7D 56 0D 00 N 0380 54 36 00 00 EOM* 03CC 0F 99 0D 007 031C 07 5A 0D 00 O 0384 5C EA 00 00 WAIT* 03D0 7E 59 0D 008 0320 7F 6A 0D 00 P 0388 73 69 03 00 BT* 03D4 49 56 0E 009 0324 6F AA 0D 00 Q 038C 67 9A 03 00 SK* 03D8 4F 95 39 00A 0328 77 39 00 00 R 0390 50 D9 00 00 SELECt 03DC 6D 79 38 79B 032C 7C 56 03 00 S 0394 6D D5 00 00

trAnSt03E0 39 78 78 50

C 0330 39 66 03 00 T 0398 78 0E 00 00 03E4 77 54 6D 78D 0334 5E D6 00 00 U 039C 3E E5 00 00 M oVEr 03E8 55 00 5C 2AE 0338 79 0D 00 00 V 03A0 2A 95 03 00 rECEIE 03EC 79 50 50 79F 033C 71 65 03 00 W 03A4 6A E9 00 00 03F0 39 79 30 79G 0340 3D DA 00 00 X 03A8 52 96 03 00 SEtUP 03F4 6D 79 78 3EH 0344 76 55 03 00 Y 03AC 6E A6 03 00 03F8 73 00 00 00I 0348 30 35 00 00 Z 03B0 4B 5A 03 00 03FC 00 00 00 00

*Notes: 1. EOM=End of message= 2. WAIT=3. BT=Sentence separation= 4. SK=End of work=

TABLE IV

mission and reception of Morse code. Itcan find application in ham radio, te-legraphy, etc.

JUNOMON ABRAHAM

TABLE I7-segment Display

TABLE IIIDATA FORMAT IN SCAN KEY BOARD MODE(FOR ANALYSING RETURNED HEX CODE)



m o n - c a t h o d echaracter dis-plays are used.Though 7-seg-ment displaysare not suitablefor alphanu-meric charac-ters, these havebeen used herewith some com-promise for re-ducing the over-all cost. (Note.The use of dot-matrix LCD dis-play avoids thedifficulty in dis-playing charac-ters in 7-seg-ment format.One can go fora microcont-roller design, ifneeded.) The 7-segment displaypattern em-ployed for dif-ferent charac-ters is shown inTable I.

Two hard-ware inter-rupts, RST5.5and RST6.5, areused for readingthe key entries.These aredriven by theIRQ line fromthe keyboard/display inter-face IC 8279.

A buffer(IC8) is con-nected at thedisplay outputof 8279 to drivethe 7-segmentdisplays. Theencoded scanlines (SL2 -SL0) are de-coded by an oc-tal decoder74LS138 (IC9),whose outputsdrive the com-mon cathode ofdisplays via

Fig. 1: S

chematic circuit of M

orse processor



PARTS LISTSemiconductors:IC1 - 8085A microprocessorIC2 - 74LS373 octal D-type latchesIC3 - 6116 RAM (2 kB)IC4 - 27C32 EPROM (4 kB)IC5 - 8279 keyboard/display

decoderIC6, IC9 - 74LS138 3-bit binary decoderIC7 - 74LS123 retriggerable

monostable multivibratorIC8 - 74LS244 octal bus driverIC10 - 7805 +5 volt regulatorT1 - BC548 npn transistorT2 - BC549 npn transistorT3-T8 - BC558 pnp transistorD1 - 1N4148 switching diodeLED1 - LEDDIS1-DIS6 - LTS543 common-cathode

displayResistors (all ¼-watt, ±5% carbon, unlessstated otherwise):R1 - 68-kilo-ohmR2 - 3.3-kilo-ohmR3 - 2.2-kilo-ohmR4 - 5.6-kilo-ohmR5 - 1-mega-ohmR6 - 15-kilo-ohmR7, R8 - 1-kilo-ohmR9-R16 - 68-ohmR17-R22 - 220-ohmR23 - 180-ohmVR1 - 2.2-kilo-ohm presetVR2 - 100-ohm presetCapacitors:C1 - 2.2µF, 16V electrolyticC2, C4, C6 - 0.1µF ceramic discC3 - 10µF, 16V electrolyticC5 - 0.001µF ceramic discC7 - 10pF ceramic discMiscellaneous:PZ1 - Piezo buzzerMIC - Condenser microphoneS1-S26 - Tactile switches for keyboardXTAL - 6.144 MHz crystal

Fig. 2: Actual-size, single-sided PCB for the Morse processor

transistor switches. The keys are wiredin such a way that these can be repre-sented by the seven higher order bits ofthe keyboard data.

Morse signals in the form of soundare converted to microprocessor-compat-ible signals. The arrangement comprisescondenser microphone, preamplifier,and retriggerable monostablemultivibrator 74LS123 (IC7). The out-put of IC7 drives SID pin of 8085 and itis in ‘high’ logic state when a sound isdetected by the microphone. The sensi-tivity of the amplifier can be adjustedby preset VR2.

The converted Morse code drives apiezo buzzer via a transistor connectedat the SOD line of 8085 microprocessor.Intensity of the sound can be controlledby potentiometer VR1.

The firmware is stored in 27C32 (4kEPROM— only 1 kB is needed for the




program). RAM 6116 stores the key-board entries and also acts as a stack.One can enter/store a maximum of ap-proximately 1,750 characters in theRAM. This is adequate for normal ap-plications. In case one needs to storelengthy text, one should use a larger-capacity RAM. Battery backup may beused for avoiding loss of data due topower failure. The low-level address/data lines of 8085 are demultiplexedusing an octal transparent latch IC74LS373.

The address bits A12 and A13 aredecoded by IC6 to generate chip select(CS) signals for various ICs. The ad-dress map of devices is indicated inTable II.

��

The software driver routines for the cir-cuit, along with their Assembly languagecode, are listed in Appendix A. Basi-cally, the following functions are per-formed by the software program:

(a) Initialisation of the peripherals.(b) Reading the depressed key data

and its storage in RAM.(c) Writing data into the display

RAM in 8279.(d) Generation of Morse code.(e) Recognition of Morse code from

its sound.(f) Giving proper messages at ap-

propriate time.Since Morse code is a time-depen-

dent code, the program contains manyjump instructions. The program hasbeen made interactive and user-friendly.The firmware is divided into the follow-ing modules: (a) booting, (b) keyboard,(c) transmit, (d) receive, (e) play, and(f) lookup table.

The logic of the program can be gen-erally understood from the Assemblylanguage listing given in Appendix A. Abrief description of each module is, how-ever, given below:

(a) Booting. This section initialisesstack pointer 8279 and the interrupts.It also fixes default speed for Morsecode. It is the first module executedwhen you switch on the power supply.

(b) Keyboard. When a key ispressed, IRQ pin of 8279 interrupts8085. The ISR (interrupt service rou-tine) reads the keyboard data and, ifneeded, does some manipulations. It alsodisplays the entered characters in the



Booting0000 31FF17 LXI SP,17FFH Initialise stack pointer0003 3E10 MVI A,10H Initialise 82790005 D321 OUT 21H0007 3E40 MVI A,40H0009 D321 OUT 21H000B 3E0D MVI A,0DH000D 30 SIM Activating RST6.5000E 325017 STA 1750H Updating mode and

position data0011 211D00 LXI H,001DH0014 225117 SHLD 1751H0017 21246C LXI H,6C24H Fixing default setup001A 227017 SHLD 1770H001D 11DC03 LXI D,03DCH0020 CDE000 CALL DISPLAY Display ‘SELECt’0023 FB EI0024 76 HLT Halt

RST 5.5002C C3F700 JMP 00F7H Go to ISR of RST5.5

RST 6.50034 DB20 IN 20H Reading keyboard data

from IC 82790036 F5 PUSH PSW Store it in the stack0037 FE8A CPI 8AH Checking CNTL+

RECEIVE key0039 CA0002 JZ RECEIVE003C FE8C CPI 8CH Checking CNTL+

TRANSMIT key003E CA8001 JZ KEYBOARD0041 FE84 CPI 84H Checking CNTL+PLAY

key0043 CAD001 JZ PLAY0046 FE86 CPI 86H Checking CNTL+

CONTINUE key0048 CAD501 JZ 01D5H004B FE98 CPI 98H Checking CNTL+

CLEAR key004D C26000 JNZ 0060H0050 210010 LXI H,1000H Clearing the RAM0053 36C8 MVI M,C8H0055 23 INX H0056 7C MOV A,H0057 FE17 CPI 17H0059 DA5300 JC 0053H005C 2A5117 LHLD 1751H Return to mode from005F E9 PCHL where clearing action

is called0060 FE8E CPI 8EH Checking CNTL+

SETUP key0062 C27700 JNZ 0077H0065 3E0E MVI A,0EH Activating RST5.50067 30 SIM0068 11F403 LXI D,03F4H006B CDE000 CALL DISPLAY Display the message

‘SEtUP’006E FB EI006F 76 HLT0070 3E0D MVI A,0DH Activating RST6.50072 30 SIM0073 2A5117 LHLD 1751H0076 E9 PCHL Return to mode from

where setup action iscalled

0077 3A5017 LDA 1750H The following CNTL007A B7 ORA A key functions are only

for TRANSMIT mode007B CA8000 JZ 0080H Checking whether we

were in the TRANSMITmode

007E FB EI007F 76 HLT0080 F1 POP PSW Getting key closuredata

which is stored in stack

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Addr. Opcode Label Mnemonics Comments0081 FE92 CPI 92H Checking CNTL+�key0083 C28900 JNZ 0089H0086 2B DCX H Shifting the characters0087 2B DCX H right by one place0088 C9 RET0089 FE90 CPI 90H Checking CNTL+�key008B C8 RZ Shifting the characters

by one place008C FE80 CPI 80H Checking CNTL+TABR

key008E C29600 JNZ 0096H0091 110500 LXI D,0005H Shifting the characters

left by six places0094 19 DAD D0095 C9 RET0096 FE82 CPI 82H Checking CNTL+TABL

key0098 C2A000 JNZ 00A0H009B 11F9FF LXI D,FFF9H Shifting the characters

right by six places009E 19 DAD D009F C9 RET00A0 FE88 CPI 88H Checking CNTL+

START key00A2 CA1001 JZ TRANSMIT00A5 FE96 CPI 96H Checking CNTL+DEL

key00A7 C2BA00 JNZ 00BAH00AA E5 PUSH H00AB 46 MOV B,M Delete one character in

the left most position ofthe display

00AC 2B DCX H00AD 70 MOV M,B00AE 23 INX H00AF 23 INX H00B0 7C MOV A,H00B1 FE17 CPI 17H00B3 DAAB00 JC 00ABH00B6 E1 POP H00B7 2B DCX H00B8 2B DCX H00B9 C9 RET00BA FE94 CPI 94H Checking CNTL+INS

key00BC C2D100 JNZ 00D1H00BF 2B DCX H Inserting a space for

adding character00C0 E5 PUSH H00C1 46 MOV B,M00C2 36C8 MVI M,C8H00C4 23 INX H00C5 7E MOV A,M00C6 70 MOV M,B00C7 47 MOV B,A00C8 7C MOV A,H00C9 FE17 CPI 17H00CB DAC400 JC 00C4H00CE E1 POP H00CF 2B DCX H00D0 C9 RET00D1 FE7F CPI 7FH Checking whether key

data is valid character00D3 D2CF00 JNC 00CFH00D6 07 RLC00D7 77 MOV M,A Enter it into the RAM00D8 C9 RET Return

DISPLAY SUBROUTINE:00E0 0E06 DISPLAY: MVI C,06H Display six characters

taken from lookup table00E2 1A LDAX D Lookup table is pointed

to by DE -reg pair00E3 D320 OUT 20H00E5 13 INX D00E6 0D DCR C00E7 C2E200 JNZ 00E2H

Addr. Opcode Label Mnemonics Comments



00EA CDC001 CALL DELAY2 Wait for some time00ED CDC001 CALL DELAY200F0 C9 RET Return

VECTOR RST 5.500F7 DB20 IN 20H Reading key closure

data from 827900F9 E63F ANI 3FH00FB 07 RLC00FC 327017 STA 1770H Storing dot value00FF 47 MOV B,A0100 80 ADD B0101 80 ADD B0102 327117 STA 1771H Storing dash value0105 C9 RET Return

TRANSMIT SUBROUTINE:0110 31FF17 TRANSMIT: LXI SP,17FFH0113 7C MOV A,H0114 FE17 CPI 17H Checking end of mem.0116 D2B301 JNC 01B3H0119 1603 MVI D,03H011B 5E MOV E,M011C 1A LDAX D011D D320 OUT 20H Display character in

the RAM011F F3 DI0120 E5 PUSH H0121 0E04 MVI C,04H Morse code generation0123 13 INX D0124 1A LDAX D0125 F5 PUSH PSW0126 217017 LXI H,1770H0129 E603 ANI 03H012B FE01 CPI 01H012D CA4801 JZ 0148H0130 23 INX H0131 FE02 CPI 02H0133 CA4801 JZ 0148H0136 FE03 CPI 03H0138 CA5901 JZ 0159H013B F1 POP PSW013C E1 POP H013D FB EI013E 7E MOV A,M013F 23 INX H0140 FECC CPI CCH Checking end of

message character ‘]’0142 C21001 JNZ 0110H0145 C3B301 JMP 01B3H0148 3ECD MVI A,CDH Setting SOD line014A 30 SIM014B 46 MOV B,M014C CD7001 CALL DELAY1 Waiting014F 05 DCR B0150 C24C01 JNZ 014CH0153 3E4D MVI A,4DH Resetting SOD line0155 30 SIM0156 217017 LXI H,1770H0159 46 MOV B,M015A CD7001 CALL DELAY1 Waiting015D 05 DCR B015E C25A01 JNZ 015AH0161 F1 POP PSW0162 0F RRC0163 0F RRC0164 0D DCR C0165 C22501 JNZ 0125H0168 C32101 JMP 0121H

DELAY1 SUBROUTINE:0170 E5 DELAY1: PUSH H Executing these

instructions requireapproximately

0171 21CF01 LXI H,01CFH 3 msec0174 2B DCX H0175 7C MOV A,H0176 B5 ORA L0177 C27401 JNZ 0174H

Addr. Opcode Label Mnemonics Comments Addr. Opcode Label Mnemonics Comments

017A E1 POP H017B C9 RET

KEYBOARD SUBROUTINE:0180 AF KEYBOARD:XRA A Updating mode and

positing data0181 325017 STA 1750H0184 218001 LXI H,0180H0187 225117 SHLD 1751H018A 11E203 LXI D,03E2H Displaying message018D CDE000 CALL DISPLAY ‘trAnSt’ for indicating

the TRANSMIT mode0190 31FF17 LXI SP,17FFH0193 210610 LXI H,1006H Entering keyboard data

to the RAM0196 11FBFF LXI D,FFFBH0199 19 DAD D019A 0E06 MVI C,06H019C 1603 MVI D,03H019E 5E MOV E,M019F 1A LDAX D01A0 D320 OUT 20H01A2 23 INX H01A3 0D DCR C01A4 C29E01 JNZ 019EH01A7 7C MOV A,H01A8 FE17 CPI 17H Checking end of mem.01AA DAB301 JC 01B3H01AD 11E803 LXI D,03E8H01B0 CDE000 CALL DISPLAY If mem. is over display

‘MoVEr’01B3 FB EI01B4 76 HLT01B5 C39601 JMP 0196H

DELAY2 SUBROUTINE:01C0 0E9F DELAY2: MVI C,9FH Wait approximately

400 msec01C2 CD7001 CALL DELAY101C5 0D DCR C01C6 C2C201 JNZ 01C2H01C9 C9 RET

PLAY SUBROUTINE:01D0 1603 PLAY: MVI D,03H01D2 210510 LXI H,1005H01D5 F3 DI01D6 23 INX H01D7 7C MOV A,H01D8 FE17 CPI 17H Checking end of mem.01DA D2EB01 JNC 01EBH01DD 5E MOV E,M01DE 1A LDAX D01DF D320 OUT 20H Displaying data in RAM01E1 CDC001 CALL DELAY2 Wait for some time01E4 FB EI01E5 7E MOV A,M01E6 FECC CPI CCH Checking end of mem.

symbol ‘]’01E8 C2D501 JNZ 01D5H01EB C3B301 JMP 01B3H Go to keyboard module

RECEIVE SUBROUTINE:0200 3EFF RECEIVE: MVI A,FFH Updating mode and

position data0202 325017 STA 1750H0205 210002 LXI H,0200H0208 225117 SHLD 1751H020B 11EE03 LXI D,03EEH020E CDE000 CALL DISPLAY Display message

‘rECEIE’0211 11FA03 LXI D,03FAH0214 CDE000 CALL DISPLAY Clear the display0217 FB EI0218 110510 LXI D,1005H Morse code aquisition021B 13 INX D021C D5 PUSH D021D 218117 LXI H,1781H0220 3600 MVI M,00H



0222 2B DCX H0223 E5 PUSH H0224 0E00 MVI C,00H0226 1E04 MVI E,04H0228 61 MOV H,C0229 0600 MVI B,00H022B CD7001 CALL DELAY1022E 04 INR B022F 20 RIM Reading the SID pin0230 07 RLC0231 DA2B02 JC 022BH0234 24 INR H0235 3A7117 LDA 1771H0238 BC CMP H Checking for the space

between characters0239 DA6602 JC 0266H023C 78 MOV A,B023D FE02 CPI 02H023F DA2902 JC 0229H0242 2600 MVI H,00H0244 1640 MVI D,40H0246 3A7117 LDA 1771H0249 0F RRC024A B8 CMP B Checking for dot and

dash024B D25702 JNC 0257H024E 7A MOV A,D024F 07 RLC0250 57 MOV D,A0251 00 NOP0252 00 NOP0253 00 NOP0254 00 NOP0255 00 NOP0256 00 NOP0257 79 MOV A,C Constructing morse

code data0258 0F RRC0259 0F RRC025A B2 ORA D025B 4F MOV C,A025C 1D DCR E025D C22902 JNZ 0229H0260 E1 POP H0261 71 MOV M,C0262 23 INX H0263 C32302 JMP 0223H0266 79 MOV A,C0267 0F RRC0268 0F RRC0269 F6C0 ORI C0H026B 1D DCR E026C CA7402 JZ 0274H026F 0F RRC0270 0F RRC0271 C36B02 JMP 026BH0274 E1 POP H0275 77 MOV M,A

Addr. Opcode Label Mnemonics Comments Addr. Opcode Label Mnemonics Comments

0276 0638 MVI B,38H Comparing obtained0278 21FD02 LXI H,02FDH morse code data with

lookup data027B 3A8017 LDA 1780H027E 23 INX H027F 23 INX H0280 23 INX H0281 23 INX H0282 05 DCR B0283 C29102 JNZ 0291H If given morse code is

invalid, display ‘y’0286 FE04 CPI 04H0288 DA1D02 JC 021DH028B 215C03 LXI H,035CH028E C39F02 JMP 029FH0291 BE CMP M0292 C27B02 JNZ 027BH0295 3A8117 LDA 1781H0298 23 INX H0299 BE CMP M029A 2B DCX H029B C27B02 JNZ 027BH029E 2B DCX H029F D1 POP D02A0 7A MOV A,D02A1 FE17 CPI 17H Checking end of mem.02A3 D2D102 JNC 02D1H02A6 7E MOV A,M02A7 D320 OUT 20H Display the character02A9 7D MOV A,L Store data, correspond-02AA 12 STAX D ing to displayed charac-

ter, in the RAM02AB 0600 MVI B,00H02AD 217017 LXI H,1770H02B0 7E MOV A,M02B1 07 RLC02B2 23 INX H02B3 86 ADD M02B4 D2B802 JNC 02B8H02B7 04 INR B02B8 4F MOV C,A02B9 0B DCX B02BA CD7001 CALL DELAY102BD 20 RIM02BE 07 RLC02BF DA1B02 JC 021BH Check for space between02C2 78 MOV A,B words02C3 B1 ORA C02C4 C2B902 JNZ 02B9H02C7 AF XRA A02C8 D320 OUT 20H Giving space in display02CA 13 INX D02CB 3EC8 MVI A,C8H02CD 12 STAX D Store the space data

in the RAM02CE C31B02 JMP 021BH Repeat the process02D1 76 HLT Halt

7-segment display. (Table III has beenincluded by EFY for ready reference bythe readers to know the hex data gener-ated by 8279 when any key is eitherpressed alone or in combination withSHIFT or CNTL key.)

(c) Transmit. This module convertseach character in the RAM to its corre-sponding Morse code signals which areoutput through the SOD line. The speedof transmission or words per minute de-pends on the value entered in the setupmenu.

(d) Receive. The acquisition ofMorse code is done by checking the pres-

ence of sound with time. This modulecontinuously monitors the SID pin of8085 microprocessor, where the sound-converted logic level (depending onwhether the sound is present or not) isavailable. It compares this logic levelwith a prefixed time value and accord-ingly decides whether the sound wasdue to dot or dash. Moreover, it dis-plays characters corresponding to theentered Morse code.

(e) Display. This module displayscharacters in the moving display for-mat as per the entered message. Thespeed of movement is fixed to approxi-

mately three characters per second.(f) Lookup table (Table IV). This

is a block of data, which contains the 7-segment data for every character andthe data needed for Morse code genera-tion or reception. Each character takesfour EPROM locations. The first loca-tion indicates the 7-segment data, whilethe second and third locations hold theMorse code data. The fourth location isunused. (EFY note. We have includedTable IV showing the hex data gener-ated by depression of any key alone orin combination with SHIFT or CNTLkeys, for ready reference by the readers.



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Before going to the operating procedure,we have to know the functions of keysassociated with CNTL key.

CNTL+SETUP (8EH). The defaultspeed is initialised for approximately 5words/minute. If you want to changethis setting, you can do so by using thiscontrol key combination. When youpress this combination, the message‘SEtUP’ is displayed. Here you can en-ter any one of the characters rangingfrom ‘1’ through ‘9’ and ‘A’ through ‘K’to change the speed. Note that the mini-mum speed is associated with ‘K’ andthe maximum with ‘1’.

CNTL+CLEAR (98H). It clears theRAM content.

CNTL+PLAY (84). CNTL+PLAY isused for displaying the RAM content inmoving format. You can interrupt anyprocess by pressing any control key thathas no function.

CNTL+CONT (86). It is used forcontinuing the play operation if it wereinterrupted.

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1. Switch on the power supply. A mes-sage ‘SELECt’ will be displayed. By de-pressing the appropriate key, you canselect any one of the following modes:(a) transmit, (b) receive, (c) setup, (d)play, (e) continue, and (f) clear.

2. Press CNTL+TRANSMIT keys forentering into the transmit mode. A mes-sage ‘trAnSt’ appears for a second, af-ter which you can enter your message.

3. At the end of the message youhave to enter ‘]’ symbol (by pressingSHIFT+] keys, i.e. 66H) for invoking themicroprocessor.

4. By the use of arrow keys (� or �)or by TAB (TAB R or TAB L) keys, setthe location in the message at which thetransmission is to start. If you want totransmit the message from beginning,depress CNTL+TRANSMIT keys againfor getting into the first character.

5. Press CNTL+START keys for get-ting Morse code of the message.

6. You can go to any other mode byselecting the corresponding mode beforefinishing the transmission or later.

7. For entering into the receivemode, press the CNTL+RECEIVE keys.You will see the ‘rECEIE’ message forone second.

8. Generate Morse code using abuzzer, voice, or some other source (suchas ham radio and recorded tape).

9. The acceptance of sound will beindicated by LED1 for duration of ‘Dit’/’Dash’. If LED does not light, adjust theposition of microphone or change thegain of the amplifier using potmeterVR2.

10. The converted data can be re-played by pressing the CNTL+PLAYkeys.

Note 1. The clear and setup control

keys can be used, at any time, if needed.

�#$-%�+,%�#$

PCB designed particularly for this cir-cuit (as given in Fig. 2, with componentlayout shown in Fig. 3) is needed formaking this circuit. IC bases are pre-ferred for fixing the ICs. For continu-ous operation, provide a heat sink forthe regulator IC. Since this circuit isbased on time comparison, it is neces-sary to use the correct frequency crys-tal (6.144 MHz).

EFY Note. Although the circuit hasbeen fully tested using the given firm-ware, elaboration of certain software in-structions, requested from the author,is still awaited. These clarification,when received, will be suitably publishedin a coming issue.

April

2001

Circuit Ideas

2001


S.C. DWIVEDI

plication of 5V DC to reset pin 15, andthe output at pin 3 (Q0) goes high. Thishigh output is shifted to the next output

��

��

ELECTRONICS FOR YOU� ❚❚❚❚❚ �APRIL 2001

EPROMs (electrically erasablePROMs) are generally erased byultraviolet rays, and it takes half

an hour or so to erase the data in anERPOM. Nowadays a special EEPROMfrom Winbond is available in the market,which is being used in telecommunica-tion due to its low cost.

The simple, low-cost circuit presentedhere takes only 100 ms to erase old pro-grams electrically. The programming volt-age VPP for the mentioned IC is 12.7V,unlike the 28xxxx series EEPROMs thatcan be written to or read like a RAM, insitu. Multiple ICs connected in parallel

can be erased simultaneously using thegiven circuit.

The circuit requires 15V to 20V DC.Timer IC3 (LM555) is used for genera-tion of clock pulses of 200 millisecond timeperiod with an ‘on’ time of 100 millisec-onds. Pulse time is achieved by using pre-

sets VR1 and VR2 and capacitor C1. The‘on’/‘off’ time of pulse may be set with thehelp of an oscilloscope or by taking ap-propriate values of presets VR1 and VR2(in-circuit resistances) and capacitor C1using the following relationship:

On time=0.69VR1xC1=Off Time=0.69VR2xC1=100 milliseconds

IC1 (7812) and IC2 (7805) are voltageregulator ICs that are used to obtain regu-lated 14V DC and 5V DC, respectively,required for operation of the circuit. Theclock with time period of 200 millisecondsis fed to IC4 (CD4017). In this IC, theoutput is available successively only at

one of the output pins with a delay of 200milliseconds when reset pin 15 is low. The14V DC is made available via transistorsT1 and T2 to pins 22 and 24 of IC5(27C512, which is the IC under erasure).

As soon as push-to-on switch S1 ispressed momentarily, it resets IC4 by ap-

pin with the successive clock pulse re-ceived at pin 14.

Q5 output from pin 1 of IC4 is in-verted using transistor T3 and is given tochip-enable pin 20 of IC5, when 14V DCis already available at pins 22 and 24 ofIC5. All address pins, except pin 24 (A9),are set low and all data pins (11 through13 and 15 through 19) are at high level(+5V). Then pins 22 and 24 are pulsedlow for 100 milliseconds. Immediately alldata (cells) are set high. (Data output ishigh only in erased condition.)

At the end when Q9 output of IC4goes high, transistor T4 conducts, pullingits collector low. LED1 glows to indicatecompletion of erasure. Simultaneously, pin4 of timer IC3 is taken low to stop gen-eration of further clock pulses until IC4

is reset.Insert the next IC to be erased in IC5

socket (preferably use a ZIF socket) andreset IC4 by pushing switch S1 momen-tarily. It takes only 100 milliseconds toerase the EEPROM IC.

J.P. SHARMA


sections for one minute when disableswitch S6 (or any other switch shuntedacross its terminal) is momentarilypressed.

During idle state, capacitor C1 is in

S.C. DWIVEDI
��
��


This intelligent electronic lock cir-cuit is built using transistorsonly. To open this electronic lock,

one has to press tactile switches S1through S4 sequentially. For deceptionyou may annotate these switches withdifferent numbers on the control panel/keypad.

For example, if you want to use tenswitches on the keypad marked ‘0’

through ‘9’, use any four arbitrary num-bers out of these for switches S1 throughS4, and the remaining six numbers maybe annotated on the leftover six switches,which may be wired in parallel to disableswitch S6 (shown in the figure). Whenfour password digits in ‘0’ through ‘9’ aremixed with the remaining six digits con-nected across disable switch terminals,energisation of relay RL1 by unauthorisedperson is prevented. For authorised per-sons, a 4-digit password number is easyto remember.

To energise relay RL1, one has topress switches S1 through S4 sequentiallywithin six seconds, making sure that eachof the switch is kept depressed for a du-

discharged condition and the voltageacross it is less than 4.7 volts. Thus ze-ner diode ZD5 and transistor T1 are innon-conduction state. As a result, the col-lector voltage of transistor T1 is suffi-ciently high to forward bias transistor T2.Consequently, +12V is extended to se-quential switching and relay latch-up sec-tions.

When disable switch is momentarilydepressed, capacitor C1 charges upthrough resistor R1 and the voltage avail-able across C1 becomes greater than 4.7volts. Thus zener diode ZD5 and transis-

tor T1 start conducting and thecollector voltage of transistor T1is pulled low. As a result, tran-sistor T2 stops conducting andthus cuts off positive supply volt-age to sequential switching andrelay latch-up sections.

Thereafter, capacitor C1starts discharging slowlythrough zener diode D1 andtransistor T1. It takes approxi-mately one minute to dischargeto a sufficiently low level to cut-off transistor T1, and switch ontransistor T2, for resuming sup-ply to sequential switching andrelay latch-up sections; and un-til then the circuit does not ac-cept any code.

The sequential switchingsection comprises transistors T3through T5, zener diodes ZD1

through ZD3, tactile switches S1 throughS4, and timing capacitors C2 through C4.In this three-stage electronic switch, thethree transistors are connected in seriesto extend positive voltage available at theemitter of transistor T2 to the relay latch-up circuit for energising relay RL1.

When tactile switches S1 through S3are activated, timing capacitors C2, C3,and C4 are charged through resistors R3,R5, and R7, respectively. Timing capaci-tor C2 is discharged through resistor R4,zener diode ZD1, and transistor T3; tim-ing capacitor C3 through resistor R6, ze-ner diode ZD2, and transistor T4; andtiming capacitor C4 through zener diodeZD3 and transistor T5 only. The indi-

K. UDHAYA KUMARAN

ration of 0.75 second to 1.25 seconds. Therelay will not operate if ‘on’ time dura-tion of each tactile switch (S1 throughS4) is less than 0.75 second or more than1.25 seconds. This would amount to re-jection of the code.

A special feature of this circuit is thatpressing of any switch wired across dis-able switch (S6) will lead to disabling ofthe whole electronic lock circuit for about

one minute. Even if one enters the cor-rect 4-digit password number within oneminute after a ‘disable’ operation, relayRL1 won’t get energised. So if anyunauthorised person keeps trying differ-ent permutations of numbers in quicksuccessions for energisation of relay RL1,he is not likely to succeed. To that ex-tent, this electronic lock circuit is fool-proof.

This electronic lock circuit comprisesdisabling, sequential switching, and relaylatch-up sections.

The disabling section comprises zenerdiode ZD5 and transistors T1 and T2. Itsfunction is to cut off positive supply tosequential switching and relay latch-up



vidual timing capacitors are chosen insuch a way that the time taken to dis-charge capacitor C2 below 4.7 volts is 6seconds, 3 seconds for C3, and 1.5 sec-onds for C4.

Thus while activating tactile switchesS1 through S3 sequentially, transistor T3will be in conduction for 6 seconds, tran-sistor T4 for 3 seconds, and transistor T5for 1.5 seconds.

The positive voltage from the emitterof transistor T2 is extended to tactileswitch S4 only for 1.5 seconds. Thus onehas to activate S4 tactile switch within1.5 seconds to energise relay RL1. Theminimum time required to keep switchS4 depressed is around 1 second.

For sequential switching transistorsT3 through T5, the minimum time forwhich the corresponding switches (S1through S3) are to be kept depressed is0.75 seconds to 1.25 seconds. If one oper-ates these switches for less than 0.75 sec-

onds, timing capacitors C2 through C4may not get charged sufficiently. As a con-sequence, these capacitors will dischargeearlier and any one of transistors T3through T5 may fail to conduct before ac-tivating tactile switch S4. Thus sequen-tial switching of the three transistors willnot be achieved and hence it will not bepossible to energise relay RL1 in such asituation.

A similar situation arises if one keepseach of the mentioned tactile switches de-pressed for more than 1.5 seconds. Whenthe total time taken to activate switchesS1 through S4 is greater than six sec-onds, transistor T3 stops conducting dueto time lapse. Sequential switching is thusnot achieved and it is not possible toenergise relay RL1.

The latch-up relay circuit is builtaround transistors T6 through T8, zenerdiode ZD4, and capacitor C5.

In idle state, with relay RL1 in de-

energised condition, capacitor C5 is in dis-charged condition and zener diode ZD4and transistors T7, T8, and T6 in non-conduction state.

However, on correct operation of se-quential switches S1 through S4, capaci-tor C5 is charged through resistor R9 andthe voltage across it rises above 4.7 volts.Now zener diode ZD4 as well as transis-tors T7, T8, and T6 start conducting andrelay RL1 is energised. Due to conduc-tion of transistor T6, capacitor C5 remainsin charged condition and the relay is incontinuously energised condition.

Now if you activate reset switch S5momentarily, capacitor C5 is immediatelydischarged through resistor R8 and thevoltage across it falls below 4.7 volts. Thuszener diode ZD4 and transistors T7, T8,and T6 stop conducting again and relayRL1 de-energises.


RF acts like a carrier and the signal iswell resolved.

The BFO circuit comprises transistors

SUNIL KUMAR
��
��


Most Indian amateur radio op-erators prefer to operate onSSB (single sideband) and CW

because these carry the signal over a longdistance for a given transmitter power.Broadcast receivers are not meant to di-

rectly receive Morse code transmission onSSB and CW. Short-wave listeners requiresome arrangement to receive the same.One such arrangement comprises a simpleIF BFO (beat frequency oscillator), whichis an RF oscillator of conventional type.

The output of BFO is heterodynedto beat with another frequency toobtain a resultant frequency (dif-ference of the two frequencies) ly-ing in the audio range (about 1kHz).

BFO can be used to get an au-dio note from CW reception andalso to resolve SSB signals. An SSBsignal is transmitted without car-rier signal. In ordinary receivers,it does not produce speech with suf-ficient clarity. When BFO signal isheterodyned with SSB signal, this

T1 and T2, which are connected in astraightforward two-stage, direct-coupled,common-emitter configuration. The inputand output are in phase and positive feed-back between the two is provided by ce-ramic filter CF1. A significant amount offeedback is provided only at the operat-ing frequency of the filter, which is 455kHz. So the circuit oscillates at this fre-quency. The ceramic filter gives good fre-quency stability and requires no adjust-ment in order to produce the correct fre-quency. This BFO is meant for single-sideband reception only.

There is no need to connect BFO toreceiver. Tune your BC receiver to anySSB signal, and then on keeping BFO justclose to it, you may notice some hissingnoise in your receiver. Match BFO fre-quency to your receiver’s IF, which maybe between 452 and 460 kHz, until youget clear sound. If the BFO signal is toostrong, increase the distance betweenBFO and receiver.

D. PRABAHARAN


tween the noise and the signal. ResistorR4 offers feedback resistance to controlthe gain of the opamp. By increasing ordecreasing the value of resistor R4, thegain can be increased or decreased, re-spectively. The preset time delay of timer

MAR

��

�� SUNIL KU


H ere are two simple, low-cost cir-cuits that can be used to shutoff the mains supply to any au-

dio or video equipment (such as tape re-corder, CD player, and amplifier). Thesecircuits are helpful to those in the habitof falling asleep with their music systemon.

The circuits will also protect the equip-ment from getting damaged due to high-voltage spikes whenever there is a re-sumption of power after a break. This ispossible because the equipment will getswitched off automatically under such con-ditions but will not get switched on auto-matically on resumption of mains supply.

The circuit in Fig. 1 can be used toshut off any cassette player that has areliable auto-stop mechanism. Wheneverswitch S1 is pressed momentarily, it ex-tends the supply to the step-down trans-former of the tape recorder and chargescapacitor C1 through diode D1. This, inturn, makes transistor T1 conduct andenergise relay RL1 to provide a parallelpath to switch S1, so that supply to thestep-down transformer continues evenwhen switch S1 is released.

When any button on the cassetteplayer is pressed, the capacitor chargesthrough diode D2. This ensures conduc-tion of transistor T1 and thus the conti-nuity of operation of cassette player. How-ever, whenever the auto-stop mechanismfunctions at the end of a tape, the leafswitch gets opened. This cuts the charg-ing path for the capacitor and it startsdischarging slowly. After about oneminute, the relay opens and interruptsmain power to the transformer. The timedelay can be increased by increasing thevalue of capacitor C1.

If the appliance used is a two-in-onetype (e.g. cassette player-cum-radio), justconnect another diode in parallel with di-odes D1 and D2 to provide an additionalpath for charging capacitor C1 via thetape-to-radio changeover switch, so thatwhen radio is played the relay does not

interrupt the power supply.The other circuit, shown in Fig. 2,

functions on the basis of the signal re-ceived from preamp of the appliance used.In this circuit, opamp µA741 is wired ininverting opamp configuration. It ampli-fies the signal received from the preamp.Timer NE555 is used to provide the nec-essary time delay of about one minute.

Preset VR1 is used to control the sen-sitivity of the circuit to differentiate be-

NE555 (which is about one minute) canbe increased by increasing the valueof C4.

Initial energisation of relay RL2 andcharging of capacitor C4 take place ondepression of switch S3 in the same man-ner as charging of capacitor C1 (refer Fig.1) on depression of switch S1. As a re-sult, pins 2 and 6 of NE555 go high andthe output of timer goes low to switch offmains supply from the relay to step-downtransformer X2 of the appliance. Bleederresistor R6 is used to discharge capacitorC4. Now if signals are received from the

ARTHUR LOUIS



preamplifier, these are amplified by 741and fed to the base of transistor T2, whichkeeps capacitor C4 charged through re-sistor R5. When there is no signal, T2will not conduct and the capacitor slowlydischarges through R6. The output of 555goes high to switch off the relay and thus

the mains supply to transformer X2.Switch S2 can be depressed momentarilyif the device needs to be manuallyswitched off.

Note. The 12V supply should be pro-vided to the circuit from the equipment’spower supply. Opamp 741 should be

driven from the preamplifier of the gad-get used, and not from its power ampli-fier output. Switches S1 and S2 are 2-pole push-to-on switches. These can alsobe fabricated from 2-pole on-off switches,which are widely used in cassette play-ers, by removing the latch pin from them.


nected at the output.UMAR
��

Here is a low-cost, invisible lasercircuit to protect your housefrom thieves or trespassers. A

laser pointer torch, which is easily avail-able in the market, can be used to oper-ate this device.

The block diagram of the unit shownin Fig. 1 depicts the overall arrangementfor providing security to a house. A lasertorch powered by 3V power-supply is used

for generating a laser beam.A combination of plain mir-rors M1 through M6 is usedto direct the laser beamaround the house to form anet. The laser beam is di-rected to finally fall on anLDR that forms part of thereceiver unit as shown in Fig.2. Any interruption of the

beam by a thief/trespasser will re-sult intoenergisation ofthe alarm. The3V power-supplycircuit is a con-ventional full-wave rectifier-fil-ter circuit. Anyalarm unit thatoperates on 230VAC can be con-

The receiver unit comprises two iden-tical step-down transformers (X1 and X2),two 6V relays (RL1 and RL2), an LDR, atransistor, and a few other passive com-

ponents. When switches S1 and S2 areactivated, transformer X1, followed by afull-wave rectifier and smoothing capaci-tor C1, drives relay RL1 through the la-ser switch.

The laser beam should be aimed con-tinuously on LDR. As long as the laserbeam falls on LDR, transistor T1 remainsforward biased and relay RL1 is thus inenergised condition. When a personcrosses the line of laser beam, relay RL1turns off and transformer X2 getsenergised to provide a parallel path acrossN/C contact and the pole of relay RL1.In this condition, the laser beam will haveno effect on LDR and the alarm will con-tinue to operate as long as switch S2 ison.

When the torch is switched on, thepointed laser beam is reflected from a defi-nite point/place on the periphery of thehouse. Making use of a set of properlyoriented mirrors one can form an invis-ible net of laser rays as shown in theblock diagram. The final ray should fallon LDR of the circuit.

Note. LDR should be kept in a longpipe to protect it from other sources oflight, and its total distance from thesource may be kept limited to 500 metres.The total cost of the circuit, including thelaser torch, is Rs 400 or less.

SUNIL K

MALAY BANERJEE


��

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S.C. DWIVEDI

This water-level indicator-cum-alarm circuit is configured aroundthe well-known CMOS input-com-

patible, 7-channel IC ULN2004Darlington array.

As the water level rises in the tank,it comes in contact with probes P1 throughP7 and thereby makes pins 7 through 1high, sequentially. As a result, the corre-sponding output pins 10 through 16 golow one after the other, and LED1through LED7 light up in that order.

When water comes in contact with thefinal probe P7, it results in sounding ofthe piezo-buzzer connected to output pin

PRADEEP G.

16 along with LED7.

Construction

2001


Data latches. There are six datalatches formed from three CD4508 ICs

��


RUPANJANA

The easy-to-construct access control(code lock) circuit presented hereincorporates the following unique

features:(a) Many people can use the same sys-

tem with their own unique 6-digit code.(b) A single-digit system code has been

included, which is common to all users ofthe system. It can be easily changed withthe help of DIP switches.

��

The block diagram of the system shownin Fig. 1 provides an overall view of itscomposition and working. A 16-digit key-pad is used for sequentially entering sixHex numbers, which are decoded by thekeyboard encoder into their equivalent bi-nary numbers and stored in separate datalatches in binary form.

The first three Hex numbers are usedas an address for an EPROM, which storesa predetermined code at prefixed addressesallocated to separate users or used forseparate purposes. The code data outputfrom EPROM (one byte/two nibbles) at aspecified address is compared with thenext two keyboard entries in two 4-bitcomparators that are cascaded together.

The resultant outputs of these twocomparators are connected to the nextcomparator stage, in which the last key-board digit (i.e. sixth Hex digit) is com-pared with the system code selected by

(IC2 through IC4). Each CD4508 containstwo completely independent 4-bit datalatches having a common power supply.The 6-digit code is stored in these latches.

The 4-bit data bus originating fromthe output of IC1 is connected to datainput pins of all the six latches in paral-lel. For example, pin 17 (QA) of IC1 isconnected to the corresponding pins 4 and16 of all the latches as the LSB of 4-bitbinary output from IC1. Initially, pin 3 of

DIP switch.If any one or more of the six consecu-

tive keyboard-entered digits do not con-form to the predetermined code, an alarmgenerator sounds the alarm to indicatewrong code. If the result of final compari-son of all the six digits is correct, a monomultivibrator, serving as lock driver foropening/closing a lock, gets activated fora fixed preset duration.

The detailed description of individualunits, as shown in Fig. 2, is as follows:

Keyboard and keyboard encoder.The keyboard consists of 16 push-to-ontype keys in a 4x4 matrix format. It canbe made using data switches or one canuse membrane-type keyboard at some ex-tra cost. The keys should be numbered inHex as shown in the figure.

The encoder is built around 74C922(IC1), which is a 16-key keyboard encoder.It generates a 4-bit binary number corre-sponding to the key pressed; for example,shorting pin 1 (R1) with pin 11 (C1) gen-erates the binary equivalent of digit ‘0’.

Whenever a key is pressed, the signalgenerated by this encoder IC is availableas logic ‘high’ output at pin 12 and isused to activate a piezo-buzzer (PZ1) viatransistor T1 (BC547). The continuoustone of PZ1 indicates that a key is pressed.The key-pressed signal is also used tostore data in the latches.

The output from pin 12 is connectedto pin 13 of IC5 (CD4017 counter) for

clocking at itstrailing edge.On each clock-ing, counter IC5advances by onecount andthereby storesdata in separatedata latches oneafter the other.IC1 also holdsthe last numberat its outputpins.

BHASKAR BANERJEE

Fig. 1: Block diagram of the access-control system

PARTS LISTSemiconductors:IC1 - 74C922 16-key encoderIC2-IC4 - CD4508 dual 4-bit latchIC5 - CD4017 decade counterIC6 - 27C32 EPROMIC7-IC9 - CD4063 4-bit magnitude

comparatorIC10 - CD4528 dual retriggerable

monostableIC11 - NE555 timerIC12 - CD4069 Hex inverterT1-T4 - BC547 npn transistorT5 - SL100 npn transistorT6 - 2P4M SCRD1, D2, D4 - 1N4148 switching diodeD3 - 1N4007 rectifier diodeLED1-LED3 - Red LEDLED4 - Green LEDResistors (¼-watt ±5% carbon, unless statedotherwise)R1, R3, R4,R15, - 10-kilo-ohmR2, R5, R8,R21, R22 - 4.7-kilo-ohmR6 - 18-kilo-ohmR7 - 10-mega-ohmR9 - 2.2-mega-ohmR10, R11,R17-R20 - 1-kilo-ohmR12-R14 - 470-ohmR16 - 47-kilo-ohmR23 - 47-ohmCapacitors:C1, C7, C8,C12 - 0.1µF ceramic discC2 - 2.2µF, 25V electrolyticC3, C5, C6,C9, C10 - 22µF, 25V electrolyticC4, C13 - 47µF, 25V electrolyticC11 - 470µF, 25V electrolyticMiscellaneous:S1 - Push-to-on switchS2 - Push-to-off switch

- 4x4 keyboard matrixPZ1 - Continuous tone-type piezo-

buzzerRL1 - 9V, 200-ohm, 1 C/O relayS3 - 4-way DIP switch

- Regulated 5V power supplyetc



IC5 providesa high outputto ‘clear’ and‘store’ pins 1and 2 of IC2A,thereby clear-ing its 4-bitregister.

When akey ispressed, theequivalent bi-nary code ispresent atdata inputpins of all thelatches. Onreleasing thekey, pin 12 ofIC1 changesits state from‘high’ to ‘low’,thereby gen-erating therequired clockpulse for IC5.This clockingmakes pins 3and 2 of IC5low and high,respectively,causing thebinary datacorrespondingto the firstHex digit key-board entry tobe stored andavailable atthe output ofIC2A.

Similarly,when the sec-ond key ispressed, newdata is storedin IC2B with-out affectingthe previouslystored data inIC2A. Theoutputs fromfirst threedata latchesare connectedto addresspins ofE P R O M27C32 (IC6).The outputsF

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from fourth and fifth data latches are con-nected to two 4-bit magnitude compara-tors IC7 and IC8 (CD4063), and the out-put from sixth data latch is connected toa similar 4-bit magnitude comparator IC9for further processing.

The memory. All 8-bit codes, exceptthe 4-bit system code, are stored at dif-ferent locations (addresses) in the EPROM(IC6). Out of the six Hex digits, first fivedigits are used as personalised code, andout of these five digits, the first three areused to form an address for EPROM.

The leftmost digit of the code is theMSD (most significant digit) and the thirddigit from left is the LSD (least signifi-

cant digit) of the 12-bit wide address forIC6. The fourth and fifth digits from leftare to be the same as the data stored inIC6 (beforehand) at that particular ad-dress. Thus, when a code is entered viathe keyboard, the fourth and fifth digitsare compared with the data stored at theaddress formed by the first three digits.(The EPROM can be programmed withthe help of ‘Manual EPROM Programmer’,and may be replaced by an EEPROM forbetter reliability.)

Code comparator. There are three4-bit comparators (IC7 through IC9) usedin the circuit, which are cascaded togetherto form a 12-bit comparator. Comparators

Fig. 3: Actual-size, single-sided PCB layout for access-control system



IC7 and IC8 compare the 8-bit data out-put of EPROM with the correspondingfourth and fifth digits entered via the key-board and stored in latches IC3B and IC4A.

While IC7 compares the upper 4-bitoutput of IC6 with the contents of IC3B(i.e. the fourth digit from left), IC8 com-pares the lower 4-bit output of IC6 withthe contents of IC4A (i.e. the fifth digitfrom left). Similarly, IC9 compares thelast digit (i.e. the contents of IC4B) withthe code entered/formed by 4-way DIPswitch S3 (marked A through D), whichis referred to here as the system code.This system code digit can be changedfrom time to time.

The result of the comparison by thethree comparators is finally available fromIC9. If the entered code matches with thestored data, pin 6 of IC9 goes high, indi-cating a correct code. Otherwise, eitherof pins 5 and 7 goes high depending uponthe magnitude of the data. Pins 5 and 7are connected together via diodes D1 andD2 and used as the trigger for alarm cir-cuit. The outputs from IC9 are availableonly after entering the last digit.

Alarm generator. The alarm genera-tor is built around a 555 timer (IC11).The logic ‘high’ output from pin 5 or pin 7of IC9 triggers the SCR and applies Vccsupply to IC 555 to make it oscillate. The

output from pin 3 of IC11 is used to drivetransistor T2 (BC547) to generate a long-duration alarm tone from PZ1.

A common buzzer is used for key-pressaudio indicator and alarm generator tokeep the cost low. The output from pin 3of timer also drives LED2, which flashesat the output frequency of the astable os-cillator.

MMV and lock driver. When a validcode is entered, pin 6 of IC9 becomes highand triggers monostable multivibratorCD4528 (IC10) via transistor T3. On trig-gering, pin 6 of IC10 becomes high andremains in that state for a predeterminedtime period. The output at pin 6 of IC10drives transistor T5 (SL100) to operaterelay RL1. When the system is locked,red LED1 glows, and when it is unlocked,green LED4 glows.

The other half of IC10 is used to keepthe keyboard activated for a predeter-mined time. The keyboard is activated bypressing switch S1. This feature improvesthe security of the system.

��

Data input/output pins are to be connectedwith utmost care because improper con-nection will force the system to work un-predictably. Also, care should be takenwhile using IC1, as it is quite costly. Thepoints marked Vcc should be connectedto the power supply directly.

The system can be built on a general-purpose PCB or a veroboard. A single-sided PCB layout for the circuit is, how-ever, shown in Fig. 3, with its componentlayout shown in Fig. 4.

��

Initially, when IC1 is disabled by IC10,no code can be entered. To activate thekeyboard, press switch S1 momentarily.This will activate the keyboard fora predetermined time. The code shouldbe entered within this time. Using the4-way DIP switch S3, the system codecan be changed at any time for extra se-curity.

If wrong code is entered, the buzzersounds alarm and the red LED startsflashing. In this case, you can reset thecircuit by a momentary depression ofswitch S2. It is to be noted that no dis-play unit is used, to keep the code secret.But if you still prefer to have one, thesame could be included. ❏



VEDI

1100 binary), respectively. Thus you canselect any one of the hundred devices,divided into ten groups, to be switchedon/off, as desired—one at a time.

The interface and control unit(Fig. 2). This unit performs the followingfunctions:

��

�� PART I


S.C. DWI

Quite a few projects using DTMF-to-BCD decoder ASIC MT 8870/KT 3170 have appeared in EFY

during the past few years. The projectpresented here also uses the same ASIC,but it is used here as part of a circuit inwhich a fairly advanced switching logicwith adequate foolproofing and authenti-cation is implemented. The major featuresof this circuit are:

• Programmable password protectionover a public network

• Foolproof mechanisms for eventssuch as time-out delays, incorrect pass-word, and power-on initialisation

• Expandable designThe primary objective of this circuit

is to make a fairly low-cost device for con-trolling up to a hundred householdswitches remotely over any public/privatetelephone network.

��

The block diagram of the system is shownin Fig. 1. It consists of the following threeunits:

1. The interface and control unit2. The authentication unit3. The main device selection and

switching circuit

The interface and control unit pro-vides control signals and BCD data to theother two units. It handles interfacingwith the telephone line and also gener-ates control signals for hanging up (HUP)and a universal reset pulse, which is usedby the authentication circuit for its op-eration. Its design may be altered toachieve connectivity to another network,which is capable of providing certain con-trol and data signal sequences.

The authentication unit stores fourpresettable digits of code data andcompares the same against the 4-digitDTMF code sent via the telephone linesbefore the time-out occurs. If the 4-digitcode is found valid, the authenticationunit issues an authorisation signal tothe main device selection and switchingunit. However if an incorrect passwordis entered, the device terminates thecall by returning to the off-hook condi-tion.

The fifth DTMF digit determines theaddress of the group to be selected, whilethe sixth digit determines the device num-ber that is to be selected within thatgroup. The selected device can be switchedon or switched off by a momentary de-pression of the telephone keypad switchesmarked * (code1011 binary) and # (code

• Detects an incoming call. Counts upto a programmable number of rings andthen simulates handset off-cradle condi-tion.

• Once off-hook, it must decode DTMFsignals on the telephone line within a fixedtime and generate appropriate BCDdata and StD pulse for indicating a validdata condition. The positive edge of thisStD pulse is used for subsequent opera-tions.

• Generates a universal Reset signalthat includes a time-out and a power-on-reset. This Reset signal is an active lowpulse of programmable duration.

• Generates a hang-up (HUP) signalon expiry of the time-out and uses thissignal internally to take the device off-line.

When a call arrives, a 75-80V AC ringsignal is available on the lines. This ringsignal is coupled to optocoupler Opto-1(MCT2E) via DC blocking capacitor C1and current-limiting resistor R1. LED1serves as a ring indicator and as an anti-parallel diode to the in-built LED of theoptocoupler for working with AC ring sig-nal. The output of optocoupler triggerstimer IC1, which is configured as amonostable retriggerable flip-flop to pro-vide a pulse output to be used as a clockfor decade counter IC2 (CD4017) with de-coded outputs.

The pulse-width of monostable shouldbe slightly greater than 0.6 second to en-sure that the pulse does not terminateduring the 0.2-second pause between apair of ring signals of 0.4-second dura-

Fig. 1: Block diagram of telephone line-interfaced generic switching system

AJAY SUBRAMANIAN AND NAYANTARA BHATNAGAR



tion. Thus the monostable produces onepulse for each ring (in fact, a pair), whichclocks CD4017 counter.

IC2 will freeze after counting a pre-programmed number of rings. This num-ber is determined by its output pin whichis tied to its pin 13. In Fig. 2 pin 9 (O8

output) is shorted to pin 13. Thus countof IC2 is frozen at the beginning of theeighth ring.

The first pulse from IC1 also triggersthe first stage of monostable multivibrator74123 (IC5), which causes the Reset out-put to go high. As a result, CD4017 (IC2)is enabled (which was otherwise reset,when no ring signal was present). Also,the authentication circuit is enabled toreceive BCD data and control signals, asand when generated by CM8870 (IC4).

If the preset count is reached and

the call has not been an-swered yet (local tele-phone handset still oncradle), the counter (IC2)is frozen and ‘D’ flip-flop(IC3A) is set. This acti-vates relay RL1 thatplaces a 220-ohm loadacross the lines to simu-late handset off-cradlecondition and also en-ables CM8870 (IC4) byapplying a ‘low’ at its in-hibit (active high) pin 5.This causes the ring sig-nal, in turn, to be takenoff the telephone lines(by telephone exchange)and establish a connec-tion (analogous to thematurity of a call). Thecircuit is now ready toreceive signals from theremote-end telephone.

In case the call is an-swered from the localtelephone before the pre-set count of IC2 isreached, the ring ceasesas the local telephone isin off-hook condition.Since there is no otherway of re-triggering IC5,a time-out eventually oc-curs and the devicereinitialises all units au-tomatically. The device isalso protected against ac-tivation by dialing froma parallel phone instru-ment, since the ring sig-nal is necessary to powerup the ASIC MT8870 (af-ter a pre-programmednumber of rings).

CM8870 (IC4) gener-ates an StD pulse when-ever fresh data islatched onto its outputs.This signal is used as a

‘data valid’ gate wherever appropriate.Also, when a key is pressed, an ESt (Earlysteering) pulse is generated at its pin 16,which lasts till the key is pressed. ThisESt pulse is used for clocking IC12B inthe authentication and control unit andretriggering monostable multivibrator74123 (IC5), extending the duration ofReset pulse. This ensures that the cir-cuit will operate as long as the user

Fig. 2: C

ircuit diagram of the interface and control unit



presses keys within preset time intervals,or else a time-out is decreed and the de-vice is reset.

The resetting process includes hang-up (HUP) state, clearing the authentica-tion circuit status, and consequentlydeactivating the main switching circuit,

thus restoring the device to its initialstate. (The flip-flops, which control de-vices in the main device selection andswitching unit, are allowed to retain theirstates.)

If the time-out period expires, the Re-set pulse falls and the falling edge is

used to trigger the sec-ond stage of monostablemultivibrator 74123(IC5). The complementedoutput 2Q of the secondstage of IC5 is a HUP(hang-up) signal thatclears relay driver flip-flop 74LS74 (IC3A), thuscausing the device tohang up, and inhibit IC4.It resets CD4017 (IC2)counter that counts thenumber of rings. Also, asa Reset pulse goes low, itresets the authorisationcircuit.

The additional cir-cuitry around the input ofIC4 protects inbuilt op-amp input terminalswithin the chip.

The power-on-resetcircuit comprises resistorR5 and capacitor C10. Itresets the device whenpower to the circuit isswitched on. Since it islow for some time afterpower is switched on, itresets the flip-flop (IC3A)and decade counterCD4017 (IC2). Fig. 4shows the relative timingwaveforms pertaining tothis unit.

LED2 through LED5are used to show theBCD output for theDTMF code receivedover the telephone lines(decoded after relay RL1has energised).

The authenticationunit (Fig. 3). This cir-cuit receives BCD dataand StD control signalinitially. It outputsauthorisation (Auth) sig-nal only when the correctsecurity code has beenentered. Control pulsescan reach the ‘main

switching unit’ only when this signal islow (implying that authentication of thefour digit code sent over the telephonelines has been verified).

Note that when a wrong code is re-ceived, IC9A clocks IC9B and a low islatched by IC9B. As a result the Q2 out-

Fig

. 3:

The

aut

hent

icat

ion

unit

circ

uit

diag

ram



Fig. 4: Signal waveforms of the interface and control unit

Fig. 5: Method of programming code usingDIP switches

off cradle simulation circuit is deactivated.Also since the Reset signal is low, all otherunits are initialised. This feature ensuresthat a denial-of-service attack (whereinunauthorised agents engage the systemand thus prevent authorised users fromusing it) is discouraged.

However, if correct codes are entered,each time when a StD pulse arrives, itclocks CD4017 (IC13) counter so that thenext word is applied at the input of thecomparator. The result of the current com-parison (high) is latched into the first ‘D’flip-flop (IC9A).

When the user presses all four keysin the correct sequence, the first flip-flopalways latches a high and the secondflip-flop is never clocked. At the end ofthe sequence, when the last digit is com-pared and the result is latched, O4 out-put of CD4017 (IC13) goes high, and asa result, IC12A is clocked and latchesa ‘high’ at its Q output and the input toinverter gate IC11E and ‘D2’ pin of flip-flop IC12B goes high. Simultaneously, sig-nal at the output of gate IC11E goes low.This low signal at pin 12 of IC10D ANDgate disables the gate from accepting anyfurther StD pulses. So the authentica-tion unit is bypassed and subsequent BCDdata and StD pulses are transmitted tothe main switching unit. The ESt pulseassociated with fifth BCD data, latchesthe high signal at D2 input of IC12 to itsQ2 output, while its Q2 output (Auth)goes low to activate the main device se-lection and switching unit at the start offifth code.

When the Reset signal goes high,the output of inverter gate IC11F goeslow. This enables IC13 (CD4017) again bytaking its MR pin low. At the same time,the high ‘Preset’ signal at both the flip-flops (IC9A and IC9B) keeps them enabled.

When the code is not entered withinpreset period, the Reset signal goes lowon expiry of the time-out period, the cir-cuit again goes back to its initial state bytaking the preset pin on the flip-flops(IC9A and 9B) low and MR pin of CD4017(IC13) high. Simultaneously, IC12A iscleared (its Q output goes low). As a re-sult, Auth output goes high and themain device selection and switchingcircuit is initialised and deactivated.Since the initialised state is maintainedas long as the Reset signal is low, anypossibility of noise triggering is elimi-nated.

To be continued….

As soon as the device establishes acall (i.e. relay RL1 energises after apreprogrammed number of rings), the au-thentication unit (and not the main de-vice selection and control unit) is acti-vated due to a high Reset pulse that isgenerated as soon as the ring arrives andalso on every pressing of a key due to(ESt) signal from IC4 via OR gate (IC7A),which triggers IC5.

Now the caller is expected to enterthe 4-digit password sequence from theremote telephone set in DTMF mode. Ini-tially, only the first word (nibble) of thearray of tri-state buffer drivers (ICs74LS244) is enabled by O0 output of IC13(CD4017). As a result, the first 4-bitprogrammed word is applied to the ‘P’inputs of 4-bit comparator IC 74LS85(IC8). LED7 through LED10 indicate thepreset data present at ‘P’ inputs of thecomparator. The other 4-bit ‘Q’ inputsfor comparison are obtained from theBCD output decoded by IC4 upon press-ing a DTMF telephone key at the remoteend. This comparator result is availableat pin 6 of IC8 before the arrival of StDpulse.

On the arrival of StD pulse, the out-put of the comparator is latched into ‘D’flip-flop (IC9A). Initially, both flip-flops(IC9A and 9B) are set, as explained ear-lier. So the ‘CLK’ input of the second flip-flop (IC9B) is low.

If at any instant, a low is latched intothe first flip-flop IC9A (as a result of afailed match between the preset code andthe code entered via the remote telephoneset), the second flip-flop (IC9B) is clocked,and it latches a low at its Q output. Thisresets decade counter IC13 via inverterIC11F. The Q2 output of IC9B is nor-mally low. But when a wrong password isentered, this output goes high. As a re-sult, transistor T2 (2N2222) of the inter-face and control unit, grounds the power-on-reset capacitor C10, as stated earlier.Thus the unauthorized call is terminatedwhen the CLR signal (from the output ofIC6A) is activated. As a result, IC2 andIC3A are reset (asynchronously) and the

put of IC9B goes high and saturates tran-sistor T2 in the interface and control unitand thereby shunts capacitor C10 toground, thus simulating a power-on-re-set condition. As a consequence CLR sig-nal (at output of IC6A) is activated andthe line interface circuit is initialised.Also, since the monoshot IC5 is cleared,Reset goes low (active) and resets theauthentication unit also. When the Au-thentication unit is initialised, IC9A and9B are set, which causes Q2 output ofIC9 to be reset, and thus transistor T2 iscut off again. Capacitor C10 now chargesthrough resistor R5 as it did when thecircuit was initially switched on.

The Reset signal is initially low. As aresult, this circuit is in its initialised state,wherein IC13 (CD4017) is reset and ICs9A and 9B (7474) are set (i.e. their Qoutputs are high and Q outputs are low).Also, IC12A has its CLR pin low and itis in reset state with its Q pin low. Asstated earlier, the Auth signal is initiallyhigh.

The password consisting of four 4-bitwords is applied at the input pins D0_0through D0_3 to D3_0 through D3_3 of74LS244 ICs 15 and 14 respectively asshown in Fig. 3. These words may be pro-grammed using thumbwheel switches orarrays of DIP switches with pull-down re-sistors as shown in Fig. 5.

May

2001

Circuit Ideas

2001


the capacitance value is given by the re-lationship C=Tx10–3 while the inductorvalue is given by the relationshipL=Tx103. The time period (1/frequency)of timer 555 (IC2) is adjusted for 1 msand 1 µs in ‘b1’ and ‘b2’ positions, respec-AR
UM
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� � ��

ELECTRONICS FOR YOU� ❚❚❚❚❚ �MAY 2001

This circuit for measurement of in-ductance and capacitance can beused to test whether the values

of inductors and capacitors quoted by themanufacturer are correct.

The principle used in the circuit isbased on the transient voltages producedacross inductors and capacitors connectedas series R-L and R-C networks, respec-tively, across a constant voltage source.The time constant for R-C and R-L net-works is given by the relationships t=RxCand L/R, respectively, where resistance Ris in ohms, capacitance C in Farads, in-ductance L in Henries, and time t in sec-onds.

The voltageacross capacitorin R-C networkrises exponen-tially to 0.632 ofthe applied volt-age and voltageacross inductor inR-L network de-grades exponen-tially to 0.368 ofthe applied volt-age in one RxCand one L/R time(referred to astime constant Tof the combina-tion), respec-tively.

When the in-ductor/capacitorunder test is con-nected across ter-minals A and Bshown in the cir-cuit, it is dis-charged throughthe normally-closed contacts oftwo-way push-to-on/off switch S1.

When switch S1 is pushed, the capacitor’svoltage begins to grow (or the inductor’svoltage begins to drop). Simultaneously,the output of timer 555 IC, which is wiredas an astable multivibrator, is passedthrough NOR gates N1 and N2 and ap-plied to the counter circuit.

When the time constant (one CxR orone L/R, as the case may be) reaches,gate N2 is inhibited as its pin 2 goes highand the counter circuit freezes. Modeswitch S2 is to be kept in position ‘a1’ forcapacitance measurement and in position‘a2’ for inductance measurement.

As series resistance R1 is 1 kilo-ohm,

tively, of the range switch. The values ofcapacitors and inductors covered in eachrange, together with displayed values, areshown in the table.

From the table it is obvious that thiscircuit can measure capacitance from 1nF to 9,999 µF and inductance from 1mH to 9999 H. While presets VR1 andVR2 are to be adjusted for the in-circuitvalue of 1.717 kilo-ohm each, the in-cir-cuit value of preset VR3 is close to 4.7kilo-ohm. If a regulated +5V is not used,the measurement of capacitance and in-ductance will be imprecise.

Given below are some importantpoints to be taken care of:

1. The position of mode-select switchS2 and range-select switch S3 should bechanged before switch S1 is pressed.

2. If the circuit is allowed to function

SUNIL K

P. THANGAVEL



until it displays a constant value, themaximum time taken for measurementwill be 10 seconds.

3. When mode-select switch S2 is inposition a1, capacitances can be measured,

and when it isin position a2,inductancescan be mea-sured.

4. Whenrange-selectswitch S3 is inposition ‘b1’,the output of555 IC willhave a timeperiod of 1 ms

(frequency = 1 kHz), and when it is inposition ‘b2’, the output of 555 IC willhave a time period of 1 µs. (EFY lab note.The guaranteed frequency of NE555 islimited to 500 kHz, and hence it may not

be possible to get 1µs period. One maytherefore use a 2nF capacitor to get aperiod of 2 µs and multiply the displayedvalue by 2, in b2 range.)

5. Use a breadboard for connectinginductors or capacitors across terminalsA and B.

6. Using both the ranges for measur-ing an inductor or capacitor enables oneto obtain the accurate value. For example,a 4.7µF capacitor will display only 4 µFwhen measured in range b1 , while in b2range it will display 4700 nF (or 4.7 µF).

7. Don’t press switch S1 before insert-ing the capacitor or the inductor betweenterminals A and B.

TABLE555 IC Capacitance Inductance DisplayedTime period range range value

C=Tx10– 3 L=Tx103

1 ms When T=1 ms, When T=1 ms, L=1H Capacitance in(Switch S3 in C=1 µF When T=9999 ms, µF and inductanceposition b1) When T= L=9999 H in H

9999 ms,C=9999 µF

1 µs When T=1 µs, When T=1 µs, Capacitance in nF(Switch S3 in C=1 nF L=1 mH and inductanceposition b2) When T=9999 µs, When T=9999 µs, in mH

C=9999 nF L=9.999H=9.999 µF =9999 mH


UMAR

used to sense high or low voltage in thiscircuit.

Transistor T1 in conjunction with ze-ner diode ZD1 and preset VR1 is used to

��

��


SUNIL K

Manual stabilisers are still popu-lar because of their simple con-struction, low cost, and high re-

liability due to the absence of any relayswhile covering a wide range of mains ACvoltages compared to that handled by au-tomatic voltage stabilisers. These are usedmostly in homes and in business centresfor loads such as lighting, TV, and fridge,and in certain areas where the mains ACvoltage fluctuates between very low (dur-ing peak hours) and abnormally high (dur-ing non-peak hours).

Some manual stabilisers available inthe market incorporate the high-voltage

auto-cut-off facility to turn off the loadwhen the output voltage of manualstabiliser exceeds a certain preset highvoltage limit. The output voltage may be-come high due to the rise in AC mainsvoltage or due to improper selection bythe rotary switch on manual stabiliser.

One of the major disadvantage of us-ing a manual stabiliser in areas with awide range of voltage fluctuations is thatone has to keep a watch on the manualstabiliser’s output voltage that is displayedon a voltmeter and keep changing thesame using its rotary switch. Or else, theoutput voltage may reach the preset auto-cut-off limit to switch off the load withoutthe user’s knowledge. To turn on the loadagain, one has to readjust the stabiliservoltage using its rotary switch. Such op-

eration is very irritating and inconvenientfor the user.

This under-/over-voltage audio alarmcircuit designed as an add-on circuit forthe existing manual stabilisers overcomesthe above problem. Whenever thestabiliser’s output voltage falls below apreset low-level voltage or rises above apreset high-level voltage, it produces dif-ferent beep sounds for ‘high’ and ‘low’ volt-age levels—short-duration beeps withshort intervals between successive beepsfor ‘high’ voltage level and slightly longer-duration beeps with longer interval be-tween successive beeps for ‘low’ voltage

level. By using these two different typesof beep sounds one can readily readjustthe stabiliser’s AC voltage output with thehelp of the rotary switch. There is no needof frequently checking voltmeter reading.

It is advisable to preset the high-levelvoltage 10V to 20V less than the requiredhigh-voltage limit for auto-cut-off opera-tion. Similarly, for low level one may pre-set low-level AC voltage 20V to 30V aboveminimum operating voltage for a givenload.

The primary winding terminals ofstep-down transformer X1 are connectedto the output terminals of the manualstabiliser. Thus, 9V DC available acrosscapacitor C1 will vary in accordance withthe voltage available at the output termi-nals of the manual stabiliser, which is

sense and adjust the high-voltage levelfor beep indication. Similarly, transistorT2 along with zener ZD2 and preset VR2is used to sense and adjust low voltagelevel for beep indication.

When the DC voltage across capaci-tor C1 rises above the preset high-levelvoltage or falls below the preset low-levelvoltage, the collector of transistor T2 be-comes high due to non-conduction of tran-sistor T2, in either case. However, if theDC voltage sampled across C1 is withinthe preset high- and low-level voltage,transistor T2 conducts and its collectorvoltage gets pulled to the ground level.These changes in the collector voltage oftransistor T2 are used to start or stoposcillations in the astable multivibratorcircuit that is built around transistors T3

and T4. The collectorof transistor T4 is con-nected to the base ofbuzzer driver transis-tor T5 through resis-tor R8. Thus when thecollector voltage oftransistor T4 goeshigh, the buzzersounds. Preset VR3 isused to control thevolume of buzzersound.

In normal condi-tion, the DC voltage sampled across ca-pacitor C1 is within the permissible win-dow voltage zone. The base of transistorT3 is pulled low due to conduction of di-ode D2 and transistor T2. As a result,capacitor C2 is discharged. The astablemultivibrator stops oscillating and tran-sistor T4 starts conducting because tran-sistor T3 is in cut-off state. No beep soundis heard in the buzzer due to conductionof transistor T4 and non-conduction oftransistor T5.

When the DC voltage across capaci-tor C1 goes above or below the windowvoltage level, transistor T2 is cut off. Itscollector voltage goes high and diode D2stops conducting. Thus there is no dis-charge path for capacitor C2 through di-ode D2. The astable multivibrator starts

K. UDHAYA KUMARAN



oscillating. The time period for which thebeep is heard and the time interval be-tween two successive beeps are achievedwith the help of the DC supply voltage,which is low during low-level voltage sam-pling and high during high-level voltage

sampling. The time taken for chargingcapacitors C2 and C3 is less when the DCvoltage is high and slightly greater whenthe DC voltage is low for astablemultivibrator operation. Thus during low-level voltage sensing the buzzer beeps for

longer duration with longer interval be-tween successive beeps compared to thatduring high-voltage level sensing.

This circuit can be added to any ex-isting stabiliser (automatic or manual) orUPS to monitor its performance.


MAR

the 555 timer (IC1).The output of IC1 is used as a clock

for decade counter 4017 (IC2) that is wiredas a divide-by-two counter. For each suc-

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�� SUNIL KU


PRADEEP G.

Here is the circuit of a highly sen-sitive clap switch that can beoperated from a distance of up

to 10 metres from the microphone.Signals picked up by the microphone

are amplified by transistors T1, T2, and

T3. Diode D1 detects clap signals and theresulting positive voltage is applied to thebase of transistor T4. The output fromtransistor T4 is further amplified by tran-sistor T5, whose output is used to triggera monostable multivibrator wired around

cessive clap, transistor T6 conducts andcuts off alternately. As a result, for eachclap signal, the lamp is either switched‘on’ or ‘off’.

Triac 8T44A (or ST044) can drive loadof up to 4-amp rating. The 12V DC foroperation of the circuit is directly derivedfrom the mains using rectifier diode D2,current-limiting resistor R16, and 12V ze-ner ZD1 shunted by filter capacitor C7.


ing resistor across the relay contacts getsconnected to the circuit.

The table shows the theoretical out-
��

RUPANJANA

Here is a simple circuit to obtainvariable DC voltage from 1.25Vto 15.19V in reasonably small

steps as shown in the table. The inputvoltage may lie anywhere between 20V

and 35V.The first section of the circuit com-

prises a digital up-down counter builtaround IC1— a quad 2-input NANDschmitt trigger (4093), followed byIC2— a binary up-down counter (4029).Two gates of IC 4093 are used to gen-erate up-down logic using push but-tons S1 and S2, respectively, while theother two gates form an oscillator toprovide clock pulses to IC2 (4029). Thefrequency of oscillations can be variedby changing the value of capacitor C1or preset VR1.

IC2 receives clock pulses from the os-cillator and produces a sequential binaryoutput. As long as its pin 5 is low, thecounter continues to count at the risingedge of each clock pulse, but stops count-ing as soon as its pin 5 is brought to logic1.

Logic 1 at pin 10 makes the counterto count upwards, while logic 0 makes itcount downwards. Therefore the countercounts up by closing switch S1 and counts

put for various digital input combinations.The measured output is nearly equal tothe theoretically calculated output acrossregulator IC3 (LM317). The output volt-age is governed by the following relation-ship as long as the input-to-output differ-ential is greater than or equal to 2.5V:

Vout = 1.25(1+R2'/R1')Where, R1' = R15 = 270 ohms (fixed)

and R2' = R11 + R12 + R13 + R14= 220 + 470 + 820 +1500 ohms= 3,010 ohms (with all relays

energised)One can use either the binary

weighted LED display as indicated byLED1 through LED4 in the circuit or a74LS154 IC in conjunction with LED5through LED20 to indicate one of the 16selected voltage steps of Table I. The in-put for IC4 is to be tapped from points

down by closing switch S2.The output of counter IC2 is used to

realise a digitally variable resistor. Thissection consists of four N/O reed relaysthat need just about 5mA current for their

operation. (EFY lab note. The originalcircuit containing quad bilateral switchIC 4066 has been replaced by reed relaysoperated by transistorised switches be-cause of unreliable operation of theformer.) The switching action is performedusing BC548 transistors. External resis-tors are connected in parallel with thereed relay contacts. If particular relay con-tacts are opened by the control input atthe base of a transistor, the correspond-

NAVEEN THARIYAN



TABLEBinary Equivalent LED4 LED3 LED2 LED1output dec no. R14 (W) R13 (W) R12 (W) R11 (W) R2' (W) Vout (V)0000 0 Shorted Shorted Shorted Shorted 0 1.250001 1 Shorted Shorted Shorted 220 220 2.270010 2 Shorted Shorted 470 Shorted 470 3.430011 3 Shorted Shorted 470 220 690 4.440100 4 Shorted 820 Shorted Shorted 820 5.050101 5 Shorted 820 Shorted 220 1040 6.060110 6 Shorted 820 470 Shorted 1290 7.220111 7 Shorted 820 470 220 1510 8.241000 8 1500 Shorted Shorted Shorted 1500 8.191001 9 1500 Shorted Shorted 220 1720 9.211010 10 1500 Shorted 470 Shorted 1970 10.371011 11 1500 Shorted 470 220 2190 11.391100 12 1500 820 Shorted Shorted 2390 11.991101 13 1500 820 Shorted 220 2540 13.011110 14 1500 820 470 Shorted 2790 14.171111 15 1500 820 470 220 3010 15.19

marked ‘A’ through ‘D’ in the figure. Thisarrangement can be used to replace theLED arrangement at points A, B, C, andD. This 74LS154 IC is a decoder/demultiplexer that senses the output ofIC2 and accordingly activates only one ofits 16 outputs in accordance with the

sets itself, and hence the output at pins6, 11, 14, and 12 is equivalent to binaryzero, i.e. ‘0000’. The corresponding DCoutput of the circuit is minimum (1.25V).As count-up switch S1 is pressed, thebinary count of IC2 increases and theoutput starts increasing too. At the high-est count output of 1111, the output volt-age is 15.19V (assuming the in-circuit re-sistance of preset VR2 as zero). PresetVR2 can be used for trimming the outputvoltage as desired. To decrease the out-put voltage within the range of 1.25V to15.2V, count-down switch S2 is to be de-pressed.

Notes. 1. When relay contacts acrossa particular resistor are opened, the cor-responding LED glows.

2. The output voltages are shown as-suming the in-circuit resistance of presetVR2 as zero. Thus when the in-circuit re-sistance of preset VR2 is not zero, theoutput voltage will be higher than thatindicated here.

count value. LEDs at the output of thisIC can be arranged in a circular way alongside the corresponding voltages.

��

When the power is switched on, IC2 re-


S.C. DWIVEDI

the help of a multimeter, find out thepositive terminal out of the three wires.

There exists a potential difference of4V or so between the positive and groundterminals. The third terminal will obvi-

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Buying a microphone for a com-puter is costly. Especially whenthere is a need to have two mi-

crophones—one for modem and anotherfor sound card—or if the present micro-phone is not working properly and needsto be replaced, you are likely to feel theburden of extra cost. Here is a low-costmicrophone circuit that comes within yourbudget.

All sound cards and modems have a

socket for microphone that is in compat-ible with stereo jack pins. The stereo sockettakes condenser microphone asinput and provides the neces-sary positive voltage for a con-denser microphone. Beforebuilding the full circuit, con-nect three wires to the jackpin,switch on the computer, andinsert the jack pins; into thesocket of the sound card. With

ously be for the signal input. The positiveterminal is used for biasing the condensermicrophone. After identifying all the ter-minals, connect them as shown in the ac-companying circuit diagram.

VYJESH M.V.

Construction

2001


RUPANJANA

half notes. So each octave has twelvenotes. On a piano keyboard, black keysin between white keys produce the aver-age frequency of adjacent keys. Forexample, ‘SA’ has a frequency of 595Hz and ‘RE’ has a frequency of 668 Hz.When a black key in between them is

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� �� - PART I


Anumber of melody generator cir-cuits based on chips like UM3481,UM3482, UM34815A, UM66, etc

have appeared in EFY. All these UMCchips contain preprogrammed maskedROM and are not field-programmable assuch.

Here is the detailed design of a typi-cal melody generator circuit using differ-ent types of memories, including EPROM,RAM, and ROM (hard-wired).

As soon as the power is switched onto UMXX series melody generators, a tuneis heard, which stops after a while. Whena switch on the melody generator ispressed, the second tune is heard. If thechip is capable of producing twelve tunes,each successive depression of the switchresults in a new tune being played. Afterthe twelfth tune has been played, the nextdepression of the switch causes the firsttune to repeat, and so on. The circuit pre-sented here can be programmed exactlythe same way.

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Generally, an electronic organ or piano isplayed with both hands. Now imagineplaying a 32-key organ with a singlefinger. In that case, only one key canbe pressed at a time and hence only onenote can be heard. Considering that thetime taken by the finger to move fromone key to another is very short, the re-

quired notes can be played properly andhence the tune can be heard. The notescan also have breaks in between. Thisfeature can be explained by consideringfive notes written in the following twoways:

1. SA RE GA MA PA2. SA---RE GA---MA PAIn the first case the notes are con-

tinuous. In the second case there arebreaks (no sound), indicated by ‘—’ for astipulated amount of time, in betweenSA and RE as well as GA and MA. Eachof the circuits explained in this projectincorporates the break (no sound) fea-ture.

You should make sure that you haveaccess to a musician before attemptingany of the circuits. In addition, you wouldneed a computer and a frequency meteror a digital multimeter. The computer isrequired to test the tunes, i.e. to makesure that the given notes match the tuneof a given song.

A brief on music from the softwarearticle ‘Generation of Indian Classical Mu-sic on a Microprocessor’ by Prof. V.V.Athani, published in April ’94 issue ofEFY, is as follows:

“Taking into account only one elec-tronic organ (piano), the number of notesin music are only seven—SA RE GA MAPA DHA NI. But these basic notes aredivided into three octaves (refer Fig. 4),where each octave also has notes called

pressed, a frequency of 631.5 Hz is pro-duced. These black keys are called half-note keys.”

Here we have selected a total of 28notes, including all notes from the middleoctave, eleven notes from upper octave,and a few from the lower octave. All the28 notes with their respective frequen-cies are given in Table I.

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Before moving to the software program,let us see how the notes for a tune canbe obtained. Give your musician thesong for which you need notes. Writethose notes in terms of SA RE GA etc,making sure that all the notes of thetune lie within the range of the 28 notesgiven in Table I. No sound in betweenthe notes, including its duration, asalso the duration of each particularnote, should be taken into account. Forexample, if in a tune the time period ofa note SA is 500 ms and that of RE 1500ms, the two notes can be written asSA RE RE RE. Similarly, no soundin between can be written as SA RE-RE-SA.

The notes so obtained have to be con-verted into data characters. This can bedone directly by using Table I; for ex-ample, SA-RE RE GA---MA can be writ-ten as C-E E G---H.

Execute the program (refer Appendix‘A’ for the source code of the program)and enter the delay value (say, 300). Nowenter the first line of the tune and press‘Enter’ key. The tune can be heard. This

tune can be repeatedby pressing ‘R’. If thistune needs to bechanged, or a new tuneis to be entered, pressany key. In this way allthe lines in a tune aretested line by line. Af-ter testing all the lines,enter all the lines of thetune once again and re-check the tunes untilFig. 1: Block diagram of EPROM-/RAM-based melody generator

VYJESH M.V.



you are satisfied. Press‘E’ to quit the program.Now convert the tunes(data characters) tohexadecimal values us-ing Table I. These hexa-decimal values are to beentered into EPROM/RAM at consecutive lo-cations to get the tune.

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Since most parts of thecircuits for EPROM- andRAM-based melody gen-erators are similar, themain circuits for bothversions have been in-tegrated in Fig. 2. Rel-evant changes havebeen described appropri-ately.

The common blockdiagram for EPROM-and RAM-based melodygenerators is shown inFig. 1. A low-frequencyoscillator followed by abinary counter is used togenerate the addressesfor EPROM/RAM.

In the case ofEPROM, thepreprogrammed dataoutput is directlycoupled to two 1-of-16decoders (one for uppernibble and the other forlower nibble of data).

However, in RAMbased-circuit, a key-board is deployed at thetime of writing the dataat specified locations(addresses) into theRAM. Thereafter thekeyboard is detachedand data output pins areconnected to two 1-of-16decoders, as in EPROM-based circuit. Only 28outputs (out of 32 out-puts) of the two decod-ers, with each repre-senting a unique note,are used in conjunctionwith individual presetsto control the oscillator’sF

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frequency and thus the resulting soundfrom the loudspeaker.

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In Fig. 2, NE555 timer (IC1) is wired inastable mode, which provides clock pulsesfor the 12-stage binary counter CD4040(IC2). In the EPROM version, jumper J1is used to permanently short pin 3 of IC1and pin 10 of IC2, while there is no needto operate push-to-on switches S2 and S3and you can leave them open (i.e. in offstate).

An 8-bit, 4k EPROM 2732 is used forIC3. Since its pin 21 isaddress A11, switch S6 isto be kept in position ‘a’to connect it to O11 out-put of IC2. When clockpulses are fed to IC2, itstarts counting up fromits reset state (all outputszero). The binary outputsof IC2 serve as the ad-dress for memory loca-tions in the EPROM,where the data for thenotes is stored. For theEPROM version, the pinsof connector K2(F) are tobe kept shorted to thecorresponding pins ofconnector K3(M). Suffixes

‘F’ and ‘M’ within pa-rentheses indicate fe-male and male connec-tors, respectively.

Data bits of thelower nibble (D0through D3) are con-nected from EPROM tothe address pins of 1-of-16 decoder IC4(CD4514) and those ofthe higher nibble (D4through D7) to the ad-dress pins of another 1-of-16 decoder IC5(CD4514).

The ‘Hex value’ col-umn in Table I indi-cates that either thelower nibble or the up-per nibble, or bothnibbles, of stored hexdata in memory will al-ways be zero. It meansthat at least one of thetwo CD4514 (IC4 and

IC5) will have binary 0000 at its addressinput. The Q0 output of these ICs is notused for generating any note. The hexdata 00 (i.e. 0000 0000) is, in fact, usedfor no sound. Similarly, hex values 01(0000 0001) and 10 (0001 0000) are used

Fig. 3: Tone oscillator

Fig. 4: Piano keyboard

Fig. 5: Flowchart ofdoorbell

for ‘Reset’ and ‘Stop-clock’ functions.The remaining 14 outputs from each

of the two CD4514 (IC4 and IC5) areused together for generating one of the 28notes corresponding to the hex datastored and the output from a specificmemory location. The Q2 to Q15 outputsof IC4 and IC5 are connected via diodesD101 (and preset VR101) through diodeD128 (and preset VR 128), respectively, tothe tone oscillator circuit built aroundtimer NE555 (IC101), as shown in Fig. 3.(EFY lab note. The numbering of diodesand other components of this circuit hasbeen done for convenience.)

IC101 is wired with presets to forman oscillator. At any time, only one ofdiodes D101 to D128, depending on thecurrent note selected via EPROM’s ad-dressed location, will be forward biasedand its corresponding preset will form partof the oscillator circuit. Each preset is ad-justed to a value (refer Table I) to obtainthe frequency corresponding to the se-lected note.

No sound (00 hex). Breaks are nec-essary in between the notes to make atune sound perfect. The break period,termed as ‘no sound,’ is obtained by out-putting hex value 00 from the EPROM.During this input to the two 1-of-16 de-coder ICs (IC4 and IC5), the Q0 outputs

Fig. 6: Actual-size single-sided PCB-1 layout for circuit of Fig. 2



of both decoder ICs go high.Since Q0 outputs are not connected

to the tone oscillator circuit (or anywhereelse), no note or sound is produced forhex value 00, and there is only timeelapse. ‘No sound’ code is used as breakbetween the notes.

Reset (01 hex). When the data out-put of EPROM corresponds to 01 (hex),Q1 output of IC4 goes high. Since Q1 out-put of IC4 is connected to MR (masterreset) pin 11 of counter IC2 via resistor-capacitor network R2-C3, IC2 is resetwhen data 01 hex appears at the outputof EPROM.

Stop-clock signal (10 hex). Whenthe data output of EPROM correspondsto 10 (hex), Q1 output of IC5 goes high,which after inversion by NAND gate N1is applied to pin 4 of IC1 via normally-closed contacts of push-to-off switch S1.As a result, IC1 stops oscillating and pro-ducing clock pulses. The active ‘high’ Q1output of IC5 is therefore referred to asstop-clock signal in this circuit. Pushingswitch S1 at this stage removes logic ‘high’

input fromNAND gateN1 and theclock oscilla-tor starts os-cillating.

The flowchart for ad o o r b e l lgiven in Fig.5 shows theorder inwhich thedata is en-tered/read.First, thedata per-taining tothe firsttune isstored. Onceall the notes( inc ludingbreaks/ ‘nosound’ peri-ods) for thefirst tuneare stored, as top -c lockdata (10hex) isstored at theend of tune-1 that stops

after the first tune. Now on pressingpush-to-off switch S1 momentarily, theclock advances to start the second tune(tune-2). Thus each tune is made to endwith 10 hex code for stop signal. Whenall tunes of the doorbell are exhausted,the last stop-clock data is followed by areset data (01 hex), so that one goes tothe start of tune-1 (on reset), and the cyclerepeats.

For instance, the hexadecimal valueof ‘SA’ is 70H (refer Table I) or binary0111 0000, which means that binary dataat the input of IC4 and IC5 is 0000 and0111, respectively. As a result, only Q7output of IC5 goes high. This outputbrings the associated preset resistor tunedto the frequency of SA (595 Hz) into theoscillator circuit. Simultaneously, data0000 at the input pins of IC4 causes itsQ0 pin to go high. But since Q0 is leftopen, there is no effect.

Similarly, when binary data corre-sponding to note SA❚ (05 hex) is outputby the EPROM, Q5 of IC4 and Q0 of IC5go high. The Q5 output of IC4 brings

PARTS LIST(Common to EPROM, RAM and ROM)

Semiconductors:IC101 - NE555 timerIC201 - 7805 +5V regulatorD101-D128 - 1N4007 rectifier diodeD201-D204 - 1N4001 rectifier diodeResistors (¼-watt ±5% carbon, unless other-wise stated)R101 - 5-kilo-ohmVR101-VR128 - Refer Table IVR129 - 10-kilo-ohm presetCapacitors:C101 - 0.1µF ceramic discC102 - 0.22µF ceramic discC103 - 10µF, 12V electrolyticC201 - 100µF, 25V electrolyticC202 - 1000µF, 16V electrolyticMiscellaneous:LS101 - 8-ohm, 4W loudspeakerX201 - 230V AC primary to 0-6V,

500mA sec. transformer(for EPROM and ROM)

Semiconductors:IC1 - NE555 timerIC2 - CD4040 counterIC3 - (1) 2732 EPROM

- (2) 6116 RAMIC4, IC5 - CD4514 1-of-16 decoderIC6 - CD4011 quad NAND gateT1-T8 - BC547 npn transistorD1-D64 - 1N4007 rectifier diodeLED1-LED20 - Red LEDResistors (¼-watt ±5% carbon, unless other-wise stated)R1, R7 - 10-kilo-ohmR2 - 22-kilo-ohmR3, R8 - 470-ohmR4 - 1-mega-ohmR5, R9-R16 - 1-kilo-ohmR6 - 2.2-kilo-ohmR17, R18 - 100-ohmR19 - 330-ohmVR1 - 100-kilo-ohm presetCapacitors:C1 - 22µF, 12V electrolyticC2 - 0.1µF ceramic discC3 - 0.01µF ceramic discC4 - 0.22µF ceramic discMiscellaneous:S1 - Push-to-off switchS2-S5 - Push-to-on switchS6 - SPDT switchJ1, J2 - JumperK1-K5 - Connectors

into circuit the corresponding preset tunedto the frequency of SA❚ (1190 Hz). TheQ0 output of IC5 has no effect, as Q0 isopen. In this way both the ICs (IC4 andIC5) function in accordance with data attheir inputs to produce the correspondingnotes.

Power supply. The circuit shown inFig. 11 is used to obtain the regulated 5VDC using IC 7805.

Fig. 7: Actual-size single-sided PCB-2 layout for circuit of Figs 3 and 11



The actual-size, single-sided PCB lay-outs for the circuits of Figs 2 and 3(common for EPROM and RAM versionsof the melody generator) are shown inFigs 6 (PCB-1) and 7 (PCB-2), respectively.The component layouts for PCBs of Figs 6and 7 are shown in Figs 8 and 9, respec-tively. The power supply circuit (Fig. 11)has also been integrated in PCB-2.

This circuit can be used as a door-bell, or even as a car-reverse horn. Theflow chart for car-reverse horn is shownin Fig. 12. The necessary connections areshown in Fig. 13. When the circuit is usedas a car-reverse horn, data flows fromthe next address location to where itstopped earlier.

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Connections to join the two PCBs shouldbe made only after the adjustment of pre-sets on PCB-2 using any of the followingthree procedures:

Using frequency meter. Assemble allthe components of PCB-2. Connect a probeto the Vcc using a crocodile clip at theother end. Switch on the 5V power supplyand connect the output from the toneoscillator on the PCB to the frequencymeter. Now connect the probe to the an-ode of diode D101 and adjust preset resis-

in the circuit diagram of Fig. 3, but ad-justing the variable resistors to lower val-ues in the table may be very tedious.

Any method may be used to adjustall the variable resistors. But after play-ing a tune, it may be felt that the tunedoesn’t sound proper, even if it soundedright with computer. The reason can bethat the resistors were not properly tunedor it may be due to minute imperfectionsin output voltages from IC4 and IC5.These imperfections can be overcome byreadjusting the resistors by the methodgiven below.

The imperfections can only be ad-justed when data from the EPROM isheard. But, the notes of a tune will notbe in an increasing frequency sequence.The sequence should be PA❚, dha❚, ----- to----- DHA❚, ni❚. To do this, include at leasttwo sets of sequence data from Table Iwith 2-3 bytes of gap in between succes-sive sequences, after all the tunes, asshown in the flowchart of Fig. 10. Thismethod of readjustment is used only toprevent disconnection of PCB of Fig. 7from PCB of Fig. 6 and tuning the resis-tors again and again.

Remove jumpers J1 and J2. Switchon the power supply. Press switch S4 toprovide clock pulses for IC2. Say, if theEPROM contains 10 tunes, after the tenthtune release S4. Now keep pressing S2momentarily until the first note of thesequence (PA

❚) sounds. Now connect the

frequency meter at the speaker terminals(disconnect speaker if necessary) and ad-just VR101 if the value of the frequencymeter reading is not consistent with thevalue in the Table I. Press S2 again toadjust VR102, and so on. After the read-justment process insert jumpers J1 andJ2 and press S3 to reset IC2.

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The only difference between the EPROM-and RAM-based circuits is the use ofRAM chip in place of EPROM and a key-board for programming the RAM in RAM-based circuits. Besides, an LED panel isused for displaying the selected RAM ad-dress.

Switch S2 is used to manually pro-vide clock pulses to IC2. Similarly, switchS3 is used to manually reset IC2 beforeand after programming. Both switches (S2and S3) are integrated into Fig. 2. Theconnector K1 in between IC2 and IC3 isused to connect to K5(M) connecter along

tor VR101 for 446 Hz (refer Table I).In this way all the variable resistors areadjusted one by one by connecting +5Vfrom the probe to the corresponding di-odes.

With the help of a musician. Youcan seek the help of a musician if youdon’t have access to a frequency meter ora digital multimeter. Connect the outputfrom the tone oscillator to the speakerand switch on the power supply. First,choose the main notes in the middle oc-tave. Connect the probe to the respectivediode of SA and tell the musician toadjust the variable resistor to the fre-quency of SA. Now connect the probeto the respective diode of RE and adjustthe variable resistor to the frequencyof RE, and so on. After adjusting mainnotes, adjust half notes. (In Table I,music notes shown in small letters arehalf notes.) This method will be success-ful only if the musician is well trained inmusic.

Using digital multimeter. First, as-semble only preset resistors VR101through VR128. Now adjust the variableresistors to their respective values (shownin column 6 of Table I) using a digitalmultimeter. Use the variable resistors withmaximum value as given in column 7 ofTable I. You can also use the values shown

Fig. 8: Component layout for PCB-1



with the associated LEDs as shown inFig. 14. EPROM 2732(IC3) is replaced with an8-bit, 2k SRAM (6116).Pin 21 of 6116 is WE(write enable – activelow). Switch S6 is to bekept in position ‘b’ whileworking with RAM.

At the time of writ-ing (programming) datainto the RAM, there isno connection betweenconnectors K2(F) andK3(M). Also, jumper J1is removed. To programthe RAM, K4(M) is to bemated with K2(F). Afterprogramming is over,K2(F) is connected toK3(M).

IC6 (CD4011) con-tains four NAND gates,of which NAND gate N1is used for stop-clock sig-nals. It functions in the

same man-ner as in anE P R O M -based cir-cuit. The in-puts of N1are shortedand con-nected tothe groundvia resistorR7. So theoutput of N1b e c o m e shigh, whichkeeps IC1oscillating.

After as top -c lock( a c t i v e‘high’) signalappears atthe input ofNAND gateN1, its out-put goeslow. Whenswitch S1 ispressed, theoutput of N1goes highand IC1starts oscil-lating again.

Gates N2 and N3 are used to provide readand write logic for RAM. In read condi-tion, the output of N3 is at logic 0 be-

cause its inputs are at logic 1. Press-ing of switch S5 provides ‘write’condition, since the output of gate N3is at logic 1 and that of gate N2 atlogic 0.

LED connector. A separate maleconnector K5(M) is fabricated withLEDs as shown in Fig. 14. This con-nector should be connected to K1(F).

The LEDs indicateaddresses ofmemory locations ofRAM. Glowing ofLED1 throughLED11 togethermeans that lastRAM location is be-ing addressed. (Weare using a 2kBRAM.)

Keyboard. Thecircuit diagram ofkeyboard is shownin Fig. 15. Male con-nector K4(M) shouldbe connected toK2(F) during pro-gramming. Thecircles shown with

the corresponding hex values are simplemetallic contacts (or tabs) that avoidthe use of a large number of switches.To enter the hex data, the probe istouched to the corresponding metallic con-tact tab.

The keyboard can be easily wired us-ing a general-purpose board. To test thekeyboard after wiring, connect point ‘A’to the ground via a 100-ohm resistor (R18)as shown in Fig. 15. Now touch each andevery tab one by one using the metallicprobe and verify that the data shown bythe LEDs (LED13 through LED20) is con-sistent with the hex value shown on thetab/circle. After checking, disconnect re-sistor R18.

Connector K3 shouldbe soldered to the PCBby using a ribbon cableof adequate length, sothat it could be easilyconnected to K2(F) afterprogramming. The out-puts from IC4 and IC5go to preset-array partof the tone oscillator.Wiring is done similar tothat in an EPROM ver-sion.

Fig. 10: Flowchart for re-adjustment

Fig. 12: Flow chartof car-reverse horn

Fig. 13: Wiring connections for car-reverse horn


Fig. 11: Power supply



TABLE IMusic Frequency Data Hex Variable Variable Maximumnote of music character value resistor resistor value of

note (preset) in-circuit variable(Hz) number value (ohm) resistor

Lower octave

PA❚ 446 1 20 VR101 8274 10kdha❚ 472 2 30 VR102 7740 10kDHA❚ 500 3 40 VR103 7230 10kni❚ 530 A 50 VR104 6744 10kNI❚ 561 B 60 VR105 6288 10k

Middle octave

SA 595 C 70 VR106 5850 10kre 630 D 80 VR107 5445 10kRE 668 E 90 VR108 5055 10kga 707 F A0 VR109 4698 5kGA 749 G B0 VR110 4356 5kMA 794 H C0 VR111 4029 5kma 841 I D0 VR112 3726 5kPA 891 J E0 VR113 3438 5kdha 944 K F0 VR114 3165 5kDHA 1000 L 02 VR115 2910 5kni 1062 M 03 VR116 2655 5kNI 1120 N 04 VR117 2445 5k

Upper octave

SA❚ 1190 O 05 VR118 2220 5kre❚ 1260 P 06 VR119 2016 5kRE❚ 1335 Q 07 VR120 1824 2kga❚ 1414 R 08 VR121 1644 2kGA❚ 1498 S 09 VR122 1473 2kMA❚ 1588 T 0A VR123 1308 2kma❚ 1682 U 0B VR124 1158 2kPA❚ 1782 V 0C VR125 1014 2kdha❚ 1888 W 0D VR126 876 1kDHA❚ 2002 X 0E VR127 747 1kni❚ 2122 Y 0F VR128 624 1k

no sound — — 00 — — —

Reset � 01Stop-clock � 10

Program-ming. ConnectLED connectorK5(M) to K1(F)and keyboardc o n n e c t o rK4(M) toK2(F). Pressswitch S3 mo-mentarily toreset IC2. NoLED glows onthe LED con-nector, indicat-ing the initialaddress aszero. Nowtouch the tabmarked ‘00’with the probe.

Press S5 momentarily and lift the probe.Glowing of no LED on the keyboard indi-cates that ‘00’ is entered in the initialmemory location. (It is good to enter ‘00’in the first memory location.)

Now get the hex dump values of thetunes. Press switch S2 to go to the nextmemory location, indicated by LED1 (cor-responding to address line A0), on theLED connector strip. Touch the appropri-ate tab with the probe to enter the corre-sponding hexadecimal value at memorylocation 1. Press switch S5 and lift theprobe. The data entered into memory lo-cation 1 is shown by keyboard LEDs inbinary form.

Hex data values (refer Table I) aresuch that any of the four LEDs corre-

Fig. 14: LED indicatorcircuit

Fig. 15: Keyboard and probe for programming RAM



#include <stdio.h>#include <dos.h>#include <stdlib.h>#include <conio.h>#include <ctype.h>void play(char *str,int d);void main(){int f,d=200;char ch1[180],ch2;clrscr();printf(“\n Enter delay value:” );scanf(“%d” ,&d);while(1){printf(“\n enter tune :” );scanf(“%s” ,&ch1);play(ch1,d);a:ch2=getch();if (tolower(ch2)==’r’){ play(ch1,d);goto a;}if (tolower(ch2)==’e’)exit(0);

}}void play(char *str,int d){int i=0;while(str[i]!=’\0'){switch(str[i]){case’1':sound(446);break;case’2':sound(472);break;case’3':sound(500);break;case’A’:sound(530);break;case’B’:sound(561);break;case’C’:sound(595);break;case’D’:sound(630);break;case’E’:sound(668);break;

case’F’:sound(707);break;case’G’:sound(749);break;case’H’:sound(794);break;case’I’:sound(841);break;case’J’:sound(891);break;case’K’:sound(944);break;case’L’:sound(1000);break;case’M’:sound(1062);break;case’N’:sound(1120);break;case’O’:sound(1190);break;case’P’:sound(1260);break;case’Q’:sound(1335);break;case’R’:sound(1414);

break;case’S’:sound(1498);break;case’T’:sound(1588);break;case’U’:sound(1682);break;case’V’:sound(1782);break;case’W’:sound(1888);break;case’X’:sound(2002);break;case’Y’:sound(2122);break;case’-’:nosound();break;}delay(d);i++;}nosound();}

Appendix ‘A’

sponding to either D0 through D3 bits orD4 through D7 bits would glow to showthe data entered. So it is easy to identifywhether the data entered is correct ornot. If necessary, make a table of binarydata along with corresponding hex val-ues.

After entering all the tunes, discon-nect keyboard from K2(F) and connectK3(M) to K2(F). Now connect externaljumper J1 as shown in the circuit dia-gram.

Switch S4 across jumper J1 terminals (Stay tuned for the next issue)

is not necessary but it may prove useful ifany readjustment of variable resistors isneeded (as in the case of EPROM), or forchecking each and every tune one by one.

The programming steps aresummarised as below:

1. Press switch S3.2. Touch tab 00 with the probe.3. Press and release switch S5.4. Lift the probe.5. Press S2 to go to the next memory

location.6. Repeat from step 2 onwards for the

next hex value programming.7. After last data is entered, press S3.8. Keep S4 pressed to check all the

tunes that have been entered.9. Connect jumper J1 if all tunes are

entered.The data table (Table I), writing of

musical notes, conversion of notes to hexvalues, preset-array alignment, and flowcharts for door-bell and car-reverse tuneare also applicable for the RAM version.


VEDI

PARTS LISTSemiconductors:IC1 - NE555 timerIC2, IC13, IC25 - CD4017 decade counterIC3, IC9, IC12,IC21, IC22 - 7474 dual ‘D’ flip-flopsIC4 - MT8870 DTMF decoderIC5 - 74123 dual retriggerable

DWI

��

�� PART II


S.C.

AJAY SUBRAMANIAN AND NAYANTARA BHATNAGAR

In Part I we had covered the inter-face and control unit and the au-thentication unit. Before we proceed

with the description of the next unit (maindevice selection and switching unit) shownin the block diagram of Fig. 1, the follow-ing modifications may be incorporated inPart I:

1. In the interface unit (Fig. 2), re-place 2-input AND gate IC6A (7408) witha 3-input AND gate (7411) and connectReset signal from pin 13 of IC5 (1Q) tothe third input of the new 3-input ANDgate. This modification has been done sothat when Reset signal is low (active), nopart of the circuit is active. All ICs willbe asynchronously reset. To avoid any con-fusion, change in the input connections ofIC6A AND gate is shown in Fig. 6.

2. In the authentication circuit (Fig.3), CLR2* pin 13 of IC12B is to be discon-nected from +5V rail and joined with

CLR1 pin 1 of IC12A, so that authentica-tion signal AUTH is deactivated on sys-tem reset.

Main device selection and switch-ing unit (Fig. 7). This circuit receivesStD control signal after a successful au-thentication of the four-digit code by theauthentication unit. The AUTH and itsinverse AUTH signals available on codeauthentication are used in this circuit forenabling various chips such as IC23 andIC24 (74LS195), IC25 (CD4017), IC27through IC29 (74LS154), and StD gateIC19C (7408).

A combinational logic circuit, compris-ing three 3-input NOR gates inside 7427(IC16) and two inverter gates (IC17B and17C) of 7404, has been used to discrimi-nate between an address (numeric digit)and a switching signal (‘*’ for ‘on’ and ‘#’for ‘off’). DTMF digit switches 1 through9 and 0 (0 on the telephone keypad stands

for decimal 10 and the de-coded output fromMT8870 is the equivalentbinary number 1010) gen-erate a logic-1, R_EN(register enable) signal,while keys marked ‘*’ and‘#’ generate a logic-1,S_EN (switching enable)signal. Thus this combi-national logic differenti-ates between register en-able (R_EN) and deviceswitching enable (S_EN)signals. The R_EN andS_EN outputs for variouskey depressions of thetelephone keypad areshown in Truth Table.

The combinationallogic circuit is followedFig. 6: Modification

monostable multivibratorIC6 - *7411 triple 3-input AND

gatesIC7 - 7432 quad OR gatesIC8 - 74LS85 4-bit magnitude

comparatorIC10, IC19 - 7408 quad 2-input AND

gatesIC11, IC17 - 7404 hex invertersIC14, IC15 - 74LS244 octal buffers/line

driversIC16 - 7427 triple 3-input gatesIC18 - 7400 quad 2-input NAND

gatesIC20 - 74125 quad bus buffersIC23, IC24 - 74195 4-bit parallel access

shift registersIC26 - 7414 hex Schmitt invertersIC27-IC29 - 74LS154 4-line to 16-line

decodersOpto-1 - MCT2E opto-couplerT1,T2 - 2N2222 npn transistorD1,D2 - 1N4001 rectifier diodeD3, D4 - 1N4148 switching diodeZD1, ZD2 - Zener diode 5.1VLED1-LED10 - Red LEDsResistors (1/4W ± 5% carbon, unless speci-fied otherwise)R1, R2, R5, R29 - 10-kilo-ohmR3, R12, R30 - 100-kilo-ohmR4 - 220-ohmR6-R9 - 51-kilo-ohmR10 - 39-kilo-ohmR11 - 56-kilo-ohmR13 - 330-kilo-ohmR14-R18 - 1.2-kilo-ohmR19 - 20-kilo-ohmR20, R27, R28 - 1-mega-ohmR21-R24,R31-R34 - 470-ohmR25,R26 - 1-kilo-ohmR31-R34 - 4.7-kilo-ohmCapacitors:C1 - 0.47µF, 160V polyesterC2,C4-C6 - 0.01µF ceramic discC3, C9, C13 - 10µF, 16V electrolyticC7, C8, C14 - 0.1µF ceramic discC10 - 100µF, 16V electrolyticC11, C12 - 47µF, 16V electrolyticMiscellaneous:Xtal - 3.57946MHz quartz crystalRL1 - Relay 6V, 100-ohm, 1 C/O

- 5V, 1A regulated powersupply

- Berg stick/FRC connectors- Ribbon cable etc.

*Note. IC 7408 is replaced with 7411 (referFig. 6).



Fig. 7: M

ain device selection and switching unit



by the RCLK and SCLK generation cir-cuitry comprising ICs 18, 19, 25, and 26,which allows the following functions tobe performed:

• After AUTH signal at Q (pin 8 ofIC12B in Fig. 3) goes low (active), onecan select a group and a device withinthe selected group by next two DTMFswitch depressions on the telephone key-pad, while a third key depression of ‘*’ or‘#’ results into switching ‘on’ or ‘off’ of thedesired device.

• Multiple devices can be switchedon/off one after the other, onceauthorisation signal AUTH becomes ac-tive (low) without a system reset.

• The system can be reset after orbefore switching ‘on’/‘off’ of the desireddevice with the help of remote telephonekeypad. This feature can also be used foravoiding switching on/off of a device ifthe user perceives that he has selected awrong device.

When R_EN signal is logic 1, IC25(CD4017) is clocked at the leading edgeof StD pulse, while one of the 74LS195registers (IC23 or IC24, as enabled byone of the Q outputs of IC25) is latchedat the trailing edge of the delayed Stdpulse (RCLK) as indicated by the direc-tion of arrow on RCLK pulse in Fig. 7.The resistor-capacitor combinations R26-C11 and R25-C12 wired around Schmittinverter gates A through D of IC26 (7414)provide the necessary delay for reliablelatching of the data in IC23 and IC24.Resistors R27 and R28 across capacitorsC11 and C12, respectively, serve as bleed-ers for discharging the respective capaci-tors.

When S_EN signal is logic 1, clockingof 7474 ‘D’ flip-flops via active 74LS125gates occurs corresponding to the leadingedge of Std (SCLK) pulses, while the trail-ing edge resets IC25 via capacitor C14, toenable receiving of fresh group and de-vice selection data.

(EFY note. The circuit comprisingIC25 and IC26 includes some modifica-tions by EFY Lab to improve the timingof RCLK and SCLK for reliable operationof the RCLK and SCLK generation partof the circuit.)

Group selection. When any of DTMFnumeric keys 1 through 9 and 0 on theremote telephone keypad is depressed im-mediately after AUTH signal goes activelow, R_EN signal goes to logic 1 (whileS_EN is logic 0). As a result, Std pulsepassing through NAND gates IC18B andFig. 9: Actual-size, single-sided PCB for the circuit in Fig. 7

Fig. 8: Actual-size, single-sided PCB for the circuits in Figs 2 and 3



IC18C clocks IC25 with its leading edge.IC25 is in reset condition before code au-thentication due to ‘high’ AUTH signal,and its Q0 (pin 3) is ‘high’. On clocking,shifting of ‘high’ state from Q0 to Q1 (pin2) enables AND gate IC19B, while ANDgate IC19 is still disabled. Thus the trail-ing edge of RCLK passes through IC19Bto latch the MT8870-decoded data corre-sponding to the mentioned numeric keydepression, which is available at the in-put of group select register IC24, at itsoutput. This is the group select address.

The group select address is appliedto the address lines of 4-line-to-16-linedecoder IC29 (group selector). In the nor-mal telephone keypad, we use only tennumeric keys (1 through 9 and 0) andhence only ten outputs (Y1 through Y10)are available from IC29. The other sixoutputs Y0 and Y11 through Y15 are notused. Thus we can select any of thegroups 1 through 10 via outputs markedY1 through Y10 of IC29.

The output corresponding to the ad-dress present at IC29’s input pins goeslow (active). This low (active) output se-lects/enables another IC 74LS154 repre-senting the corresponding group. (Pleasenote that this is only a demo versioncircuit, wherein only two groups, out often possible groups, can be accessed us-ing IC27 and IC28. Pin 19 of IC27 andIC28 can be connected to any of the groupselect pins Y1 through Y10 of IC29, asdesired. Once connected, the specificgroup numbers will get allocated to IC27and IC28.)

Device selection within the se-lected group. The next DTMF numberkey depression (i.e. the sixth afterenergisation of relay RL1 or the secondafter the 4-digit authentication code)causes shifting of ‘high’ on pin 2 (Q1) ofIC25 to pin 4 (Q2) in synchronism withthe leading edge of StD pulse clockingIC25. As a result, AND gate IC19A isenabled while AND gate IC19B is dis-abled.

The trailing edge of delayed StD pulse(RCLK) causes the data corresponding tothe mentioned numeric key to be latchedat the output of device select registerIC23. This device select address is ap-plied to address input pins of all groupICs (IC27 and IC28, here) in parallel.However, since only one group IC is inselected condition (as explained earlier),the device control output correspondingto the device select address present atFig. 11: Component layout for PCB-2




Switching on oroff refers to Q out-put of the corre-sponding ‘D’ flip-flop(7474) going high orlow, respectively.You may suitablyuse the flip-flop out-puts to energise a re-lay or fire a triac orcontrol the corre-sponding device/de-vices.

If you press anynumber key (1

through 9 or 0) instead of ‘*’ or ‘#’ key onthe DTMF keypad, IC25 will receive aclock pulse via AND gates IC18B andIC18C, and the ‘high’ state will shift fromQ2 to Q3 (pin 7 of IC25). Since Q3 outputis coupled to the baseof transistor T2 via diode D4, it will re-sult into a system reset (as explainedin Part I). A system reset implies thatyou have to redial the local telephonenumber from remote telephone. When re-lay RL1 again energises, redial the four-digit authentication code, followed bygroup select, device select, and switch on(*) or switch off (#) codes, as explainedearlier.

Thus, after dialing two digits identi-fying the group and the device within thatgroup, if we press a third numeric digitinstead of ‘*’ or ‘#’ on the remote tele-phone keypad, a system reset can beachieved remotely. This feature can alsobe utilised to bypass switching operationif the user realises that he has selected awrong group/device.

Operation summary. The entire op-eration can be summarised as below:

• Using the remote telephone key-pad, dial the local number of thetelephone to which the circuit is con-nected.

• If the local handset is lifted beforethe programmed number of rings, a nor-mal conversation can ensue.

• If the handset is not lifted beforethe programmed number of rings, waitfor simulated off-hook status of the localtelephone handset (indicating energisationof relay RL1).

• Now dial the four digits of the pre-set authentication code in a proper se-quence from the remote keypad withinthe preset duration. A system reset willoccur in case the 4-digit code is notdialed within the preset duration or

the code used is wrong, which causesde-energisation of the relay and createsconditions similar to on-hook state ofthe local telephone handset. So you willhave to repeat all steps from the begin-ning.

• If the 4-digit authentication codematches the preset code, you can dial thenext two digits identifying the group andthe device within that group selected forthe purpose of switching on or off (or evenas a dummy operation for the purpose offorcing a system reset).

• Dialing ‘*’ from the remote tele-phone keypad will result into switchingon of the selected device, while dialing ‘#’will result into switching off of the se-lected device. (Dialing any number, 1through 9 or 0, causes a system reset.Relay RL1 will be de-energised, and youwill have to restart from the initial step.)You can proceed with the same procedureto switch on/off the next selected device.The procedure can be repeated for anynumber of devices (one-at-a-time) with-out affecting the status of non-selecteddevices.

Testing. It is recommended that thecircuit be built in stages, verifying properoperation at each stage. The main switch-ing circuit may be assembled convention-ally, with logic operation tested at vari-ous points. The authentication circuit isalso self-contained and may be assembledand debugged independently.

However, care must be taken whileassembling the interface and control unit.The ASIC must be assembled first andtested for proper operation and output lev-els, followed by rigging and testing ofmonostable multivibrators in the 74123.The ring pulse generator and decadecounter, CD4017, comes next. Finally, in-terface connections between the variouscircuits should be made after verifyingthe proper functioning of each circuit inisolation.

A single-sided PCB for the circuits inFigs 2 and 3, and including modificationreferred in Fig. 6, is shown in Fig. 8,while another single-sided PCB for thecircuit in Fig. 7 is shown in Fig. 9. Thecomponent layouts for both the PCBs aregiven in Figs 10 and 11, respectively.Suitable connectors are provided to en-able isolation and joining of individualcircuits using jumpers/connectors, foreasy testing and fault analysis during as-sembly. ❏

Truth Table for Device Selection and SwitchingKeypad Decoded data input Switch and registerKey from MT8870 enable outputsNo. D3 D2 D1 D0 S_EN R_EN1 0 0 0 1 0 12 0 0 1 0 0 13 0 0 1 1 0 14 0 1 0 0 0 15 0 1 0 1 0 16 0 1 1 0 0 17 0 1 1 1 0 18 1 0 0 0 0 19 1 0 0 1 0 10(10) 1 0 1 0 0 1* (11) 1 0 1 1 1 0#(12) 1 1 0 0 1 0

the active group input is pulled low. Thisactive low output is used as the controlsignal for a corresponding tri-state gateof 74LS125 (IC20).

We have shown only four gates, outof possible 100, in this circuit. The out-put pins of tri-state gates are connectedto the clock inputs of the corresponding‘D’ flip-flops (only four out of possible 100are shown). The clock pins of IC21 andIC22 have been pulled high to avoid anynoise triggering when tri-state buffers arein high-impedance state.

Switching the selected device. Onlyone device corresponding to the digit inthe registers— IC24 for group address andIC23 for device address— is enabled to beaffected by the signal (‘*’ or ‘#’) as theseventh (or the third after authentica-tion) code. On pressing DTMF keypadswitch ‘*’ or ‘#’, the selected device isswitched on or switched off depending onthe key pressed. D0 bit of the decodedswitching signals ‘*’ and ‘#’ is appliedto data pins of all 7474 flip-flops inparallel. Only the data correspondingto the selected device gets clocked viathe corresponding tri-state gate of74LS125.

The Q2 output of IC25 is still highwhen SCLK is generated and, as a re-sult, AND gate IC18D is enabled to al-low application of SCLK to all 74LS125gates on depression of either ‘*’ or ‘#’ onthe remote keypad. Switching takes placeat the trailing edge of SCLK pulse, whilethe trailing edge of SCLK pulse causesresetting of IC25, thereby creating condi-tions that were unavailable just beforethe previous group selection. Subse-quently, you can select any other (or thesame) group and any other (or the same)device. You can switch on or off the se-lected device by following the same pro-cedure.

June

2001

Circuit Ideas

2001


operation. In quick-test mode, you canperform a rough check of zener diode’s
��
ELECTRONICS FOR YOU� ❚❚❚❚❚ �JUNE 2001

Zener diodes available in the mar-ket are specified according to theirbreakdown voltage as well as tol-

erance. The tolerance may vary from 5per cent to 20 per cent. The circuit of aversatile zener diode tester presented hereenables you to verify the specified break-down voltage and tolerance values. In ad-dition, you can check the dynamic imped-ance of a zener diode.

The dynamic imped-ance characteristics of azener diode determineas to how well the ze-ner diode regulates itsown breakdown voltage.Thus this circuit can beused to compare the dy-namic impedance char-acteristics of zener di-odes from a lot and seg-regate/categorise themaccordingly.

For full-fledged ze-ner diode testing youwill have to refer to the manufacturer’sdatasheet to check zener diode parameterssuch as zener voltage, power, and cur-rent (maximum/nominal) ratings. In ad-dition, temperature coefficient and dy-namic impedance have also to be checkedif zener diode is to be used for criticalfunctions such as voltage reference for

breakdown voltage up to 47 volts. In qual-ity-test mode, you can check dynamic im-pedance characteristic for zener diodesfrom 3.3V to 120V.

Commonly available step-down trans-formers X1 and X2 (230V AC primary to9V AC, 750 mA sec. each) are connectedback-to-back as shown in the figure. Abridge rectifier followed by filter capaci-tor C1 converts the output from X2 trans-former to DC. Neon lamp L1 indicatesthe presence of higher DC voltage (220Vapproximately) across capacitor C1, whichis used to test various zener diode valuesfrom 3.3V to 120V.

An advantage of using this high-volt-age circuit is that the current gets re-stricted to a low value. It delivers only 3mA (approx.) when testing zener diodeswith higher breakdown values (e.g. 120Vzener diode), but while testing zener di-odes of low breakdown values, such as3.3V, it delivers a current slightly above20 mA. Such power-supply characteris-tics suit our requirement, as stated ear-lier. Since a small current is used for test-ing of zener diodes, there is no danger ofzener diodes getting damaged during test-ing using the dynamic impedance method.

Before using the circuit, check DC volt-age across test terminals A and B withoutconnecting any zener diode and then fliptoggle switch S2 to quick-test position. DCvoltage available across terminals A andB will be around 200V DC. Now put toggleswitch to quality-test position. DC voltagecan now be adjusted from 6V DC to 200VDC (approx.) with the help of potentiom-eter VR1. After these preliminary checks,the circuit is ready for operation.

To test zener diode by quick-testmethod, connect zener diode across termi-

digital voltmeters, control systems, andprecision power-supply circuits. However,for a common hobbyist it is not necessaryto check zener diodes critically, and onlychecking its dynamic impedance charac-teristic is sufficient.

Dynamic impedance implies the de-gree of change in a zener diode’s voltagewith the change in current. Expressed inohms, it equals the small change in zener

voltage divided by the correspondingchange in zener current (centered aroundthe test current figure prescribed indatasheets by manufacturers). Fromdatasheets it is observed that test cur-rent value is high for low-voltage zenerdiodes and low for higher-voltage zenerdiodes. However, the dynamic impedancevalue will be low for low-voltage zenerdiodes and vice versa for higher-voltagezener diodes.

To test 3.3V to 120V zener diodes bythe practical dynamic impedance method,you need to have a variable voltage (0 toabove 120V) and current (1 mA to 150mA) supply source. Designing this type ofpower supply is quite complicated and isprone to damage if excess current isdrawn accidentally.

The zener diode tester circuit pre-sented here has been designed consider-ing the above factors. It is capable of test-ing zener diodes of breakdown voltage rat-ings of upto 120V and wattage ratings of250 mW, 400 mW, 500 mW, and 1W.

The circuit can be deployed in quick-test mode as also in quality-test mode of

SUNIL KUMARK. UDHAYA KUMARAN

TABLE IIMinimum and Maximum Test Current

ValuesZener diode values IT(min) IT(max)3.3V to 12V 10mA 15mA13V to 27V 5mA 10mA30V to 43V 2mA 5mA47V to 75V 1.5mA 3mA82V to 120V 1mA 2mANote: Zener diode power rating is 1 watt.

TABLE IMinimum and Maximum Test Current

ValuesZener diode values IT(min) IT(max)3.3V to 4.3V 10mA 15mA4.7V to 18V 5mA 10mA20V to 39V 2mA 4mANote: Zener diode power ratings are 250 mW,400 mW, and 500 mW.



nals A and B and flip switch S1 to ‘on’position. Note down DC voltage in digitalmultimeter M2, which is the rough break-down voltage. In quick-test method youcan test zener diode values up to 47 voltssafely. For higher-value zener diodes youwill have to increase the value of resistorR3 suitably. If zener diode presents a short,digital multimeter M2 will read ‘0’ volts.

To perform quality test on the samezener diode, turn switch S1 ‘off’ and re-move zener diode from across terminals Aand B. Now turn switch S1 ‘on’ and adjustpotentiometer VR1 to obtain DC voltage(on digital multimeter) across terminals A

and B equal to the one found during quicktest method. Now keep potentiometer VR2in mid position and connect zener diodeacross terminals A and B.

(Note. Before testing zener diode, re-fer Table I and Table II for the minimumtest current (ITmin) and maximum testcurrent (ITmax) required for various ze-ner diode values, depending upon theirwattage rating.)

Test current is adjusted using poten-tiometer VR2 and measured using meterM1 (A 0-25mA analogue milliamperemeter or a 0-20mA digital multimeter canbe used.)

Now adjust potentiometer VR2 andnote down changes in zener voltage dur-ing ITmin and ITmax conditions. If the re-quired current is not available, increaseDC voltage by adjusting potentiometerVR1 suitably. While changing test currentfrom ITmin to ITmax, the voltage variationacross zener diode should be less than 1volt for lower-value zener diodes and afew volts for higher-value zener diodes. Avoltage variation of more than this valueindicates that zener diode is not properlyregulating. When comparing zener diodesof same values, the zeners showing lessvoltage deviation would regulate better.


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ADTMF-based IR transmitter andreceiver pair can be used to realise a proximity detector. The circuit

presented here enables you to detect anyobject capable of reflecting the IR beamand moving in front of the IR LED photo-detector pair up to a distance of about 12cm from it.

The circuit uses the commonly avail-able telephony ICs such as dial-tone gen-erator 91214B/91215B (IC1) and DTMFdecoder CM8870 (IC2) in conjunction withinfrared LED (IR LED1), photodiode D1,and other components as shown in thefigure. A properly regulated 5V DC powersupply is required for operation of the cir-cuit.

The transmitter part is configuredaround dialer IC1. Its row 1 (pin 15) and

column 1 (pin 12) get connected togethervia transistor T2 after a power-on delay(determined by capacitor C1 and resis-tors R1 and R16 in the base circuit of thetransistor) to generate DTMF tone (com-bination of 697 Hz and 1209 Hz) corre-sponding to keypad digit “1” continuously.

LED 2 is used to indicate the tone

output from IC3. This tone output is am-plified by Darlington transistor pair of T3and T4 to drive IR LED1 via variable re-sistor VR1 in series with fixed 10-ohmresistor R14. Thus IR LED1 producestone-modulated IR light. Variable resis-tor VR1 controls the emission level to varythe transmission range. LED 3 indicatesthat transmission is taking place.

A part of modulated IR light signaltransmitted by IR LED1, after reflection

from an object, falls on photodetector di-ode D1. (The photodetector is to beshielded from direct IR light transmis-sion path of IR LED1 by using any opaquepartition so that it receives only the re-flected IR light.) On detection of the sig-nal by photodetector, it is coupled toDTMF decoder IC2 through emitter-fol-lower transistor T1.

When the valid tone pair is detectedby the decoder, its StD pin 15 (shorted toTOE pin 10) goes ‘high’. The detection of

the object in proximity of IR transmitter-receiver combination is indicated byLED1. The active-high logic output pulse(terminated at connector CON1, in thefigure) can be used to switch on/off anydevice (such as a siren via a latch andrelay driver) or it can be used to clock acounter, etc.

This DTMF proximity detector findsapplications in burglar alarms, objectcounter and tachometers, etc.

RUPANJANAK.S. SANKAR


AR

first flip-flop and CLR pins of the otherthree flip-flops goes active ‘low’ (becauseof the power-on-reset circuit formed by
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SUNIL KUM

JAYDIP APPASAHEB DHOLE

A simple, low-cost hardwired stepper motor control circuit that canbe used in low-power applications,

such as moving toys etc is presented here.The circuit comprises a 555 timer IC

configured as an astable multivibratorwith approx. 1Hz frequency. The fre-quency is determined from the followingrelationship:

Frequency = 1/T = 1.45/(RA + 2RB)CWhere RA = RB = R2 = R3 = 4.7 kilo-ohmand C = C2 = 100 µF.

The output of timer is used as clockfor two 7474 dual ‘D’ flip-flops (IC2 andIC3) configured as a ring counter. Whenpower is initially switched on, only thefirst flip-flop is set (i.e. Q output at pin 5of IC2 will be at logic ‘1’) and the otherthree flip-flops are reset (i.e. their Q out-puts will be at logic ‘0’). On receipt of aclock pulse, the logic ‘1’ output of the firstflip-flop gets shifted to the second flip-flop (pin 9 of IC2). Thus with every clockpulse, the logic ‘1’ output keeps shiftingin a ring fashion.

Q outputs of all the four flip-flops areamplified by Darlington transistor arrays

inside ULN2003 (IC4) and connected tothe stepper motor windings marked ‘A’through ‘D’ in the figure. The common

point of the winding is connected to +12VDC supply, which is also connected to pin9 of ULN2003. The colour code used forthe windings is shown in the figure.

When the power is switched on, thecontrol signal connected to SET pin of the

R1-C1 combination) to set the first flip-flop and reset the remaining three flip-flops. On reset, Q1 of IC2 goes ‘high’ whileall other Q outputs go ‘low’. External re-set can be activated by pressing the resetswitch. By pressing the reset switch, you

can stop the stepper motor. On releasingthe reset switch, the stepper motor againstarts moving further in the same direc-tion.


SUNIL KUMAR
��

components in addition to condenser mi-crophone and low-wattage speaker (referFig. 1). The complete unit can be made

on a general-pur-pose veroboard.

The micro-phone signals areamplified by atwo-stage transis-tor amplifier,while the speakeris driven throughan audio outputtransformer (similarto the one used intransistor radios).When ring button(push-to-on switchS1) is pressed, ca-

pacitor C3 gets connected between thebase of transistor T2 and the top end ofprimary winding of audio output trans-former. As a result, the amplifier circuit

wired around transistor T2 gets convertedinto a Hartley oscillator and produces anaudible tone for call-bell.

To build a two-way intercom set, maketwo identical units with the speaker ofeach circuit installed near the other unitas shown in Fig. 2.

PRADEEP G.

The intercom circuit described hereuses two transistors, an audiotransformer, and a few passive


cuit is added. If the output voltage ex-ceeds 15V due to some reason such ascomponent failure, the SCR fires becauseof the breakdown of zener ZD2. Once SCRfires, it presents a short-circuit across the

UMAR

��

��


To operate car audio (or video) sys-tem from household 230V ACmains supply, you need a DC

adaptor. DC adaptors available in themarket are generally costly and supplyan unregulated DC. To overcome theseproblems, an economical and reliable cir-cuit of a high-power, regulated DC adap-tor using reasonably low number of com-ponents is presented here.

Transformer X1 steps down 230V ACmains supply to around 30V AC, which isthen rectified by a bridge rectifier com-prising 5406 rectifier diodes D1 throughD4. The rectified pulsating DC issmoothed by two 4700µF filter capacitorsC1 and C2.

The next part of the circuit is a se-ries-transistor regulator circuit realisedusing high-power transistor 2N3773 (T1).Fixed-base reference for the transistor istaken from the output pin of 3-pin regu-lator IC1 (LM 7806). The normal outputof IC1 is raised to about 13.8 volts bysuitably biasing its common terminal bycomponents ZD1 and LED1. This simplearrangement provides good, stable volt-

unregulated DC supply, resulting in theblowing of fuse F1 instantly. This offersguaranteed protection to the equipment

connected and to thecircuit itself.

This circuit canbe assembled using asmall general-pur-pose PCB. A good-quality heat-sink isrequired for transis-tor T1. Enclose thecomplete circuit in a

readymade big adaptor cabinet as shownin the figure.

SUNIL K

T.K. HAREENDRAN

age reference at a low cost. LED1 alsoworks as an output indicator.

Finally, a crowbar-type protection cir-


the water. LED1 glows up as the water
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S.C. DWIVEDIPRIYANK MUDGAL

The circuit presented here watersyour plants regularly when youare out for a vacation.

The circuit comprises a sensor partbuilt using only one op-amp (N1) of quadop-amp IC LM324. Op-amp N1 is config-ured here as a comparator. Two stiff cop-per wires are inserted in the soil contain-ing plants. As long as the soil is wet, con-ductivity is maintained and the circuit re-mains off.

When the soildries out, the resis-tance between thecopper wires (sensorprobes A and B) in-creases. If the resis-tance increases be-yond a preset limit,output pin 1 of op-ampN1 goes ‘low’. Thistriggers timer IC2(NE 555) configuredas a monostablemultivibrator. As a re-sult, relay RL1 is ac-tivated for a presettime. The water pump starts immediatelyto supply water to the plants.

As soon as the soil becomes suffi-

ciently wet, the resistance between sen-sor probes decreases rapidly. This causespin 1 of op-amp N1 to go ‘high’. LED1glows to indicate the presence of adequatewater in the soil. The threshold point atwhich the output of op-amp N1 goes ‘low’can be changed with the help of presetVR1.

To arrange the circuit, insert copperwires in the soil to a depth of about 2 cm,keeping them 3 cm apart. When the soil

gets dried, adjust VR1 towards groundrail until LED1 turns off and relay RL1is energised. The motor starts pumping

reaches the probes.For small areas a small pump such

as the one used in air coolers is able topump enough water within 5 to 6 sec-onds. The timing components for IC2 areselected accordingly. The timing can bevaried with the help of preset VR2.

The circuit is more effective indoorsif one intends to use it for long periods.This is because the water from reservoir(bucket, etc) evaporates rapidly if it iskept in the open. For regulating the flowof water, either a tap can be used or oneend of a rubber pipe can be blocked us-ing M-seal compound, with holes punc-

tured along its length to water severalplants.

Construction

2001


RUPANJANA

‘Stop-clock’ and ‘Reset’ functions) are tobe strapped (shorted) together for connec-tion to the corresponding input points ofthe ‘variable-resistor array and tone os-

��

� �� - PART II


VYJESH M.V.

Part I of this article dealt with thedesign of EPROM and RAM ver-sions of a programmable melody

generator. In this concluding part we shallstudy a programmable melody generatorusing home-brewed ROM.

There were only a few differences be-tween the circuits of RAM- and EPROM-based programmable melody generatorsand as such we could integrate the com-mon portion of the two circuits into asingle schematic/PCB design. However,the circuit of a ROM-based programmablemelody generator is totally a new one.The ROM, as stated earlier, is home-builtusing discrete components, which can beused for storage of 100 bits (100 notes).The block diagram of the ROM-basedmelody generator is shown in Fig. 16.

Note that the last block comprisingvariable resistor array is identical to thatused in EPROM/RAM version (refer Fig.3 in Part I of the article). The power-supply circuit shown in Fig. 11 can alsobe used for ROM-based melody genera-tor. Thus PCB and component layoutsshown in Figs 7 and 9 can be used with-out any modification in this system.

��

The circuit diagram of ROM-based melodygenerator is shown in Fig. 17. Here timerNE 555 (IC1) is wired as an astablemultivibrator. The output pulses from IC1are used as clock for decade counterCD4017 (IC2). The ten sequential outputsfrom IC2 are applied to npn BC547 tran-sistors T1 through T10.

Similarly, the outputs from anothersimilar decade counter IC3 are connectedto pnp BC558 transistors T11 throughT110 via inverter gates N1 through N10of IC3 and IC4 (CD4069). Each of these100 transistors (T11 through T110)provides one bit for one note. The out-puts are taken from the collectors oftransistors and connected to the ‘variable-resistor array and tone oscillator’ circuit.(Note: Collectors of transistors represent-ing identical notes are shorted together.)

As in the previous circuits of RAM-and EPROM-based melody generators,here also ‘Stop-clock’ and ‘Reset’ signalsare made available. You may programany/all of the hundred transistors T11through T110 for 28 notes as well as forthe ‘Stop-clock’ and ‘Reset’ functions. How-ever, both ‘Stop-clock’ and ‘Reset’ func-

tions are optional, depending upon thenumber of tunes and number of notes.For ‘Stop-clock’ function, the output froma transistor is applied to inverter N11whose output is connected to reset pin 4of IC1. Similarly, for ‘Reset’ function, theoutput from a transistor is applied to pins15 of IC3 and IC4.

The collectors of transistors pro-grammed for each specific note (including

cillator’ circuit, while the ‘Stop-clock’ and‘Reset’ lines are to be connected as shownin Fig. 17.

We can have a maximum of 30 out-put lines (28 forthe notes and twofor ‘Stop-clock’and ‘Reset’ func-tions) from the100-transistor ar-ray. TransistorsT1 through T10are used to switch

on Vcc to transistors T11 through T110.

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Initially, when power is switched ‘on’ tothe circuit, IC2 and IC3 are in Reset con-dition. So only pin 3 (Q0) of IC2 and IC3will be at ‘high’ logic. These high outputsare applied to the base of transistor T1and the input of inverter N1. As a result,

PARTS LISTSemiconductors:IC1 - NE555 timerIC2, IC3 - CD4017 decade counterIC4, IC5 - CD4069 hex invertersT1-T10 - BC547 npn transistorT11-T110 - BC558 pnp transistorResistors (¼-watt ±5% carbon, unless other-wise stated)R1 - 10-kilo-ohmR2 - 100-kilo-ohmR3 - 680-ohmR4 - 1-mega-ohmR5 - 1-kilo-ohmR6 - 68-ohmCapacitors:C1 - 2.2µF, 12V electrolyticC2, C3 - 0.01µ ceramic discMiscellaneous:S1 - Push-to-off switch*Parts List of tone oscillator and power sup-ply is given in Part I of the article (publishedin May issue).

Fig. 16: Block diagram of ROM-based melody generator



transistor T1 is switched on and +5V Vccis available at the emitter of transistorT1. This potential is extended to the emit-ters of T11, T21, T31,… , T91 and T101.Simultaneously, the output of inverter N1will be at logic ‘0’, which is applied to thebases of pnp transistors T11 through T20.

Since transistor T11 is the only tran-sistor that has both Vcc at its emitterand nearly 0V at its base simultaneously,it gets forward biased and its collector ispulled toward its emitter voltage (Vcc).

Thus initially, on powering the circuit,transistor T11 is activated and its collec-tor goes high.

The initial state lasts for a fewseconds and as soon as IC1 generates aclock pulse (which is applied to the clockpin of IC2), Q1 (pin 2) of IC2 goes ‘high’and pin 3 goes ‘low’, while no change takesplace in IC3. Now transistor T2 isswitched on.

Since the base of transistor T12 is atlow potential, the positive voltage will be

available at its collector. Thus transistorsT11 through T20 will be switched on andoff sequentially with the arrival of eachnew clock pulse.

At the beginning of tenth pulse, thecarry-output pulse from pin 12 of IC2 isapplied to clock pin 14 of IC3. Now pin 3(Q0) of IC2 and pin 2 (Q1) of IC3 go ‘high’.Therefore, transistors T21 through T30are now switched ‘on’ and ‘off’ in a se-quential fashion. In this way one out of100 transistors is switched ‘on’ sequen-

Fig. 17: Schematic diagram of ROM-based melody generator



tially to produce an output to drive the‘resistor-array tone oscillator’ according tothe tune data. Thus when power isswitched on, the tune is produced.

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The PCB design should ideally be double-sided for such types of transistor arrays.However to keep the cost down, we haveincluded only a single-sided PCB layout,which is shown in Fig. 18 with its compo-nent layout in Fig. 19.

First, assemble transistors T11through T110. Solder the transistors, leav-ing a length from the PCB. Now take athin, bare wire and connect the emitterleads of transistors T11, T21... T91 andT101 together from the components side.Similarly connect emitters of other rowsof transistors. Suitable pads for the pur-pose have been provided on the PCB.

Similarly the collectrors of transis-tors T1 through T10 may be connectedtogether using bare wire from the com-ponents side. Now assemble all the re-

maining components.

��!�� !

In this circuit, programming means hardwiring. You should have a lot of patienceto do all the hard wiring. No hexadecimalvalues are required. Before starting withthe wiring, label diodes D101 throughD128 of ‘variable resistor array oscillator’PCB (Fig. 7 and 9 in Part 1) in terms oftheir respective notes i.e. label D101 asPA❚, D102 as dha❚, ..., D128 as NI

❚, and so

on.Now starting from transistor T11 con-

nect the transistor outputs (refer PCB ofFig. 18) to diodes D101 through D128 ac-cording to the tune note that each tran-sistor (T11 through T110) sequentiallyrepresents. Extreme care should be takenwhile wiring, because if any error occurs,it will be very tedious to find out.

Let us consider the example of fivenotes ‘SA RE— GA SA PA’. In this caseprogramming can be done as under:

ConnectT11�SA�D6T12�RE�D8T13�NO connection, leave open (be-

cause the data is no sound)T14�GA�D10T15�SA�D6 (Again to D6)T16�PA�D13Reset. With this circuit a maximum of

100 notes are feasible. However if all notesare not utilised, Reset is necessary afterthe last utilised note. Because if the totalnumber of notes is less than 98, for ex-ample, 86, then after 86th note there are 14more bits to reach for an automatic resetto occur. (The circuit automatically resetsitself after 100th bit.) So there is a big delayfor the tune to get repeated. To skip thedelay, we use Reset. For this, the outputfrom the next transistor after the last noteis connected to point marked ‘RESET’ onPCB. When the pulse appears at pin 15 ofIC2 and IC3, the circuit resets.

Stop-clock. Stop-clock is used whenmore than one tune is to be programmed.If the clock is to be stopped, say, after the1st tune, we use stop-clock. For this, the





Fig. 20: Flow chartfor repetitive playingof 99 notes (singletune)

output from thenext transistor afterthe last note of thetune is connected tothe stop-clock pointin the PCB. Pleaserefer to flow chartsof Fig. 20 and 21,which showoccurance of auto-matic reset and useof stop-clock and re-

set functions.Housing. There is a

lot of wiring in betweenthe ROM circuit of Fig.17 and the resistor-arrayoscillator. So the enclo-sure must have enoughspace for all the wires tofit properly without get-ting detached from thePCB while installing.[EFY note. To overcomethis problem to some ex-tent, a 28-pin (16+12)SIP connector (with pinsprojecting towards bothsides of the PCB) may beused. This will obviate

the need to run loose wires between ROMPCB and variable-resistor array oscilla-tor PCB. Wires originating from the col-lectors of the transistor array may be con-nected to one side of the connector onROM PCB itself and a ribbon cable with28-pin SIP connector on both sides canbe used between the two PCBs.] ❏

Fig. 21: Flowchart forrepetitiveplaying of anumber oftunes


PARTS LISTSemiconductors:IC1-IC3 - MCT2E optocoupler

S.C. DWIVEDI

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Induction motors widely used in work-shops, irrigation pump sets, etc re-quire a 3-phase supply. Normally,

these motors are connected to 3-phasesupply from electricity boards using ther-mal bimetal relays and relay contactors.Thermal relays protect the motor fromoverload. Relay coils having hold-on con-tacts with push-to-‘on’ and push-to-‘off’switches are used for activating and de-activating the relay contacts.

Single-phasing, line dropout, and re-verse phasing are harmful for 3-phase mo-tors. In the event of line dropout and single-phasing, the motor draws a heavy currentfrom the existing phases, and during phasereversal the motor simply rotates in re-verse direction. Further, an operator (at-tendant) for switching ‘on’/‘off’ the motoris always not possible, especially when themotor has to be operated round the clock.Also the protection provided by the ther-mal relay in the starter assembly is inad-equate, since it involves some delay in ac-tivation. Thus some damage to the wind-ings of the motor can take place, especiallyif overload conditions occur frequently.

The circuit presented here incorpo-rates the following features to overcomeall the above-mentioned problems:

• Electronic sensing of phase sequence

with under-frequency cut-out.• Current sensing for single-phasing

prevention.• Current sensing for overload cut-

out.• Automatic starting/tripping.• Programmable timer with battery

backup to count the motor’s run time.• Latching circuit to prevent the mo-

tor from frequently starting and tripping.• Easy operation with just two

switches for time set and reset.The phase-sequence detector protects

the motor before starting, while the cur-rent-sensing circuit protects it during run-ning. This double protection makes themotor operation really safe.

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The schematic circuit diagram of induc-tion motor controller is shown in Fig. 1.

3-Phase sequence checker. The volt-age from each of the three phases is con-nected to optocouplers IC1 through IC3via rectifier diodes D1 through D3. Theoutputs from the optocouplers are half-wave rectified DC pulses with a phase dif-ference of 120° (during the conduction pe-riod of diodes), which are applied to a posi-tive-edge-triggered, dual JK flip-flop IC4.

When the red phase rises, the outputof IC1 goes from ‘low’ to ‘high’, resultingin clearing of both flip-flops FF1 and FF2through 0.1µF capacitor C1. While the redphase is still ‘high’, the yellow phase rises,

resulting in theoutput of IC2 going‘high’ and provid-ing a clock pulse toFF1. As a result, Qoutput of FF1 goes

TABLE IIMotor Core Core Primary SecondaryHP size area Max SWG Turns SWG Turns(Max) amps6 17 0.25 10 14 14 38 17020 23 0.56 22 11 9 38 110

TABLE IPhase sequence Signal OK LED RL1Correct On OnIncorrect Off Off

IC4 - CD4027 J-K flip-flopIC5, IC6 - NE555 timerIC7, IC9, IC10 - CD4017 decade counterIC8 - CD4060 14-stage counter

and oscillatorIC11 - 7805 5V regulatorD1-D30 - 1N4007 rectifier diodeZD1, ZD2 - 3.3V zener diodeLED1-LED4 - Red LEDResistors (1/4W ± 5% carbon, unless speci-fied otherwise)R1-R3 - 100-kilo-ohm, 0.5 wattR4-R6, R16,R18-R23, R25,R30, R31, R38,R47, R49 - 4.7-kilo-ohmR7, R24 - 27-kilo-ohmR8-R10 R17,R26, R29, R32,R37, R39, R43,R44, R46, R48,R51-R53 - 10-kilo-ohmR11, R28, R34 - 1-kilo-ohmR12 - 220-kilo-ohmR13, R41 - 1-mega-ohmR14, R35, R36,R45, R50 - 470-ohmR15 - 470-ohm, 0.5 wattR27 - 180-kilo-ohmR33 - 2.2-kilo-ohmR40 - 22-kilo-ohmR42 - 82-kilo-ohmVR1 - 4.7-kilo-ohm presetVR2 - 47-kilo-ohm presetCapacitors:C1-C3, C6,C13 - 0.1 ceramic diskC4, C7, C11, C17- 100µF, 63V electrolyticC5, C14-C16,C18, C19 - 10µF, 25V electrolyticC8, C10, C12 - 47µF, 25V electrolyticC9 - 1000µF, 63V electrolyticMiscellaneous:X1-X3 - Current-sensing trans-

formersX4 - 0-230V AC primary to

12V-0-12V, 500mAsecondary transformer

S1 - ‘On’/‘off’ switchS2 - SPDT switchS3 - 7-way rotary switch

- 1.5V X4 battery- Starter assembly- Cabinet

D. DINESH



‘low’ (since J1 input of FF1 is already‘high’ when the clock pulse arrives atCLK1 pin). Now, when the blue phaserises, the output of IC3 goes ‘high’, while

the output of IC2 is already ‘high’, result-ing in the output Q of FF2 going ‘low’.

The above process repeats once dur-ing each 50Hz cycle. If Q outputs of both

FF1 and FF2 are ‘low’, the phase sequenceis correct and both diodes D28 and D29are in blocking mode. The base of tran-sistor T1 is pulled towards ground via re-

Fig. 1: Schematic diagram of auto control for 3-phase motor



sistor R11 and transistor T1 starts con-ducting. As a result, IC5 is triggered andhence ‘sequence OK’ LED connected topin 3 of IC5 via resistor R14, glows.

IC5 is a popular 555 timer wired as aretriggerable monoshot. Its time periodis set at 25 milliseconds (approx.). If themonoshot is not retriggered within 25 mil-liseconds, the ‘sequence OK’ signal goes‘low’. The circuit operates smoothly at fre-

quencies up to 42 Hz.If any of the phase fails, the phase

sequence is disturbed, resulting in the out-put of IC5 going ‘low’ and ‘sequence OK’LED goes ‘off’. The LED status in relationto the phase sequence is shown in Table I.The output of IC5 is also used for drivingrelay RL1 via transistor T2 (SL100).

Normally-open (N/O) contacts of re-lay RL1 are wired in series with ‘off’

switch of starter assembly as shownin the Fig. 1. Thus when phase se-quence is correct and the frequency isabove 42 Hz, the relay is in energisedstate and it is feasible to switch onthe starter by momentary energisationof relay RL2, whose N/O contacts arewired in parallel with the ‘on’ switchof starter assembly.

Auto-starter and current-sens-ing circuit. As soon as the phase se-quence is detected to be correct (asexplained in the previous section), theoutput of IC5 goes ‘high’. This output,via resistor R15, is used to reset IC7and enable IC6, besides acting as aclock for decade counter IC10.

IC6 is an NE555 timer wired inastable mode to provide clock pulsesto decade counter CD4017 (IC7). Even-tually, when Q8 output of CD4017(IC7) goes ‘high’, relay RL2 energisesthrough transistor T9 (SL100). N/Ocontacts of RL2 are connected across‘on’ switch of starter assembly, asstated earlier and the starter’s relaycoil energises. The next clock pulse toIC7 deactivates relay RL2, but starterremains in ‘on’ state due to hold-oncontact (the fourth contact of contactorin starter assembly). When Q9 (pin 11)of IC7 goes ‘high’, its CK pin 14 ismuted due to conduction of transistorT8 (which pulls it to ground) to pre-vent further counting. The Q9 outputof IC7 is also used in the motor ‘on’/‘off ’ timer circuit, explained later.

The supply to starter is connectedthrough primaries of three small cur-rent transformers used for sensingthe load in each phase. These trans-formers can be constructed using com-mon EI laminations generally used for

power transformers. Core number 23 or17 may be employed as per details givenin Table II.

The secondaries of these transformersare connected to the current-sensing cir-cuit wired around transistors T3 throughT5. If any phase goes ‘off’, it cuts off thecorresponding transistor and thereby pro-vides forward bias to transistor T6.

The outputs of transistors T3 through




T5 are wired-OR via diodes D15, D16, andD17. Any excessive increase in load cur-rent (overload) results in forward biasingof transistor T7. The excess current limitcan be set with the help of preset VR1.

The conduction of transistors T6 and/or T7 causes their common collector junc-tions to be pulled low. This ‘low’ signal iscoupled to transistor T2 via diode D30.As a result, relay RL1 deactivates to trip

the starter and thus stop the inductionmotor. The above conditions aresummarised in Table III.

Motor on/off counter and latch.Frequent start and stop operations sub-ject the motor to lot of fatigue due toheavy currents, which may damage themotor. In this circuit, automatic restart-ing of motor is limited to three attemptsfor each power ‘on’, by using another de-

cade counter CD4017 (IC10). It moni-tors each ‘on-off ’ cycle of the motor byadvancing the count of decade counterby one on every start.

The clock for IC10 is obtained fromthe output of IC5 via resistor R15. Thispoint i.e. the junction of resistor R15and diode D30 is also used as supplypoint for transistors T6, T7, T12 andT13 as also for reset pin of timer IC6.On the third start, pin 7 (Q3) goes ‘high’and transistor T13 gets forward biased.As a result, CK pin 14 of IC10 is pulledlow to stop any further clock to thedecade counter, which thus gets latchedand LED3 glows to indicate the latchedstate of the counter. Simultaneously,this ‘low’ signal causes transistor T2 tocut off and de-energise relay RL1. Thusthe motor cannot restart automaticallyand only complete resumption of powercan reset the latch.

Motor on-off timer. A timer is pro-vided to run the motor for a predeter-mined time. It counts run time of themotor and thereafter switches off themotor automatically. The signal frompin 11 (Q9) of IC7 is connected to thebase of transistor T11 via resistor R38(as referred in ‘auto-starter and curre-sensing circuit’). Thus the collector oftransistor T11 goes ‘low’ to activate theoscillator circuit of CD4060 (IC8), whilethe motor is running. Prior to that, theoscillator circuit of CD4060 was inac-tive because its pin 11 was at logic ‘1’,being connected to +ve rails via resis-tors R39, R40 and diode D22. The fre-quency of oscillation is set by R-C net-work comprising 47µF capacitor C8 andresistor R42 in series with preset VR2.

A timing of either 30 minutes or 60minutes can be selected with the help

of switch S2 for the output of ‘on’/‘off’ timerto go from ‘low’ to ‘high’ state.The outputfrom the pole of switch S2 is connected tothe clock input of decade counter IC9. Theoutputs of IC9 go ‘high’ sequentially after30/60-minute time intervals, depending onthe selection made via switch S2. Thusmultiples of 30-/60-minute basic timingcan be selected with the help of 7-wayrotary switch S3. (The 7-way rotary switch




may be substituted with decade thumb-wheel switch, if desired.)

The output available at the pole ofrotary switch S3 goes ‘high’ after the se-lected duration to forward bias transistorT12, which, in turn, causes de-energisation of relay RL1. Also, whenthe selected run time is over, the oscilla-tor of IC8 (CD4060) gets inhibited becauseoscillator pin 11 of IC8 goes ‘high’ due to

the feedback from the pole of switch S3via resistor R43 and diode D23. LED1glows to indicate that run time is over.To restart the motor, IC8 and IC9 can bemanually reset by closing and then open-ing switch S1. The timer may be bypassedby keeping switch S1 closed.

The timer section requires very low

power in standby modeand is powered by four1.5V cells as standbysupply. A battery-lowindicator is provided towarn the user aboutthe low battery condi-tion.

Power supply.The normal DC powersupply for the circuitis provided by a smallstep-down transformerX4 connected between R (red) phaseand neutral, followed by rectifier andfilter capacitor. The unregulated volt-age is used for operation of the relays,while the 5V regulated supply is usedfor the remaining circuit.

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An actual-size, single-sided PCB for themotor controller circuit of Fig. 1 is shownin Fig. 2, with its component layout shownin Fig. 3. It is recommended to use basesfor ICs.

Before connecting the circuit to starterassembly, a bench test is required for theadjustment of timer. Apply 3-phase powerto the circuit. Observe pin 3 of IC5

(NE555), which should go‘high’, provided the sequenceis correct. Else, interchangeany two phase wires. As ‘se-quence OK’ signal at pin 3 ofIC5 goes ‘high’, relay RL1energises and IC6 (IC555) isactivated. As a result, relayRL2 energises after a delayof 15 seconds for one second.

Now adjust preset VR2such that 30-minute-durationpulse train (time period 60minutes) is available at pin

14 of IC8 (CD4060). Flip switch S2 to 30-minute position. Select the required runtime using rotary switch S3. On comple-tion of the selected run time, ‘time over’LED should glow and the timer shouldstop. Relay RL1 should de-energise.

After resetting the timer with the helpof switch S1, relay RL1 should energise

TABLE IIITruth Table of Current Sensing Circuit

Phase R Phase Y Phase B T6 T7 RL1(ON) (ON) (ON) R.B. R.B. Energised(ON) (ON) (OFF) F.B. R.B. De-energised(ON) (OFF) (OFF) F.B. R.B. De-energised(OFF) (OFF) (ON) F.B. R.B. De-energised(OFF) (ON) (OFF) F.B. R.B. De-energised(ON) (OFF) (ON) F.B. R.B. De-energised(OFF) (ON) (ON) F.B. R.B. De-energisedIn case of overloadingin any phase — X F.B. De-energisedNote: R.B. = Reverse bias; F.B. = Forward bias; X = Don’t care

Fig. 4: Layout of cabinet for mountingtransformer relays and the PCB

Fig. 5: Creation of virtual neutral from 3-phaes 3-wiressystem

once again. Then after a delay of 15 sec-onds, relay RL2 should again energise forone second. Now short momentarily pin14 of counter CD4017 (IC10) to groundthrice. On the third touching, Q3 of IC10will go ‘high’ and LED3 will glow, fol-lowed by de-energisation of relay RL1. Themains should be interrupted completelyto reset IC10.

Current transformers X1 through X3,step-down transformer X4, and relays RL1and RL2 may be mounted side by side ina compact box as shown in Fig. 4. ThePCB may be mounted over the transform-ers and relays using insulated spacers.Current transformers are to be connectedbefore the starter relay contacts.

Over-current adjustment can be doneonly after connecting the load. Connectall the wires to the starter point and theload. Keep wiper contact of VR1 towardsground side and switch on the 3-phasesupply. Relay RL1 activates. After 5 sec-onds, relay RL2 also activates and themotor starts running. Now slide the wiperof VR1 and mark the position just beforethe motor trips. (Remember that suchtrips will be counted by latching counter.)

Caution. Some parts of this circuitcontain live 3-phase voltages. So avoidtouching the circuit with bare hands.

Note. In the case of non-availabilityof neutral terminal, assembler a circuitas shown in Fig. 5. Connect ‘N’ markedwire (shown in Fig. 1) to two more trans-formers X5 and X6 that are identical toX4. The secondaries of these transform-ers (X5 and X6) are kept open, while thesecondary of X4 is connected to the power-supply circuit as shown in Fig. 1. ❏

July

2001

Circuit Ideas

2001


low to light the corresponding LED.

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ELECTRONICS FOR YOU� ❚❚❚❚❚ �JULY 2001

This hardware-cum-software projectis meant to control hardwarethrough software. The hardware

using LEDs to simulate both dial clockand electronic roulette is rather simple.

Of the two 4-line-to-16-line decodersused in the circuit, the first (IC1) drives‘hour LEDs’ and the other (IC2) drives‘minute LEDs’. These decoders are inter-faced directly to the PC’s printer port pro-vided on its backside.

Data output lines D0 to D3 (pins 2through 5 of 25-pin ‘D’ connector) of the

printer port are connected to four addressinputs of the decoder used for minute dis-play, while data output lines D4 to D7(pins 6 through 9) are connected to fourdata inputs of the decoder used for hourdisplay.

Since the outputs of these decodersare active-low, the positive terminals ofLEDs are made common. This obviatesthe need to use additional inverters. Inaccordance with 4-bit binary address atinputs A through D of decoders, only oneof the 16 outputs at a time goes active-

Since a dial clock requires only 12LEDs, only 12 of 16 outputs of 74154 de-coders are used in this circuit. Only the

minute decoder (IC2) is used for electronicroulette.

The dial clock and electronic roulettefunctions, which can be selected via thesoftware program, are explained below:

Dial clock. When dial clock is se-lected, system time is displayed on theLED panel. The hour-indicating LEDglows continuously, while minute-indicat-ing LED blinks for each odd second (i.e.1, 3, 5,.… , and so on). The clock incorpo-rates hourly chime and alarm setting fea-tures. Chime and alarm sound can be dis-tinguished from the duration for which itwill sound.

Electronic roulette. Roulette is agame of chance that basically comprisesa circular wheel divided into a number ofsectors that are numbered serially and apointer. There exists a relative motion be-tween the pointer and the wheel. The ro-tation is initiated by mechanical means.The wheel is allowed to stop itself andthe number indicated by the pointer de-cides the winner.

This game can also be arranged elec-tronically by using sequential runninglights, which will simulate the rotatingwheel, and making them to stop at ran-dom position. The chance of a number tobe winner is 1 out of 12 in the PC-basedelectronic roulette explained here. Thesoftware for dial clock and electronic rou-lette is written in ‘C’ language.

For simulation of dial clock, the soft-ware uses gettime () function to read timefrom the computer, which is then stored

VIJAYA KUMAR P.RUPANJANA



plied by 16 to write the binary equivalentof hour into data pins D5 to D7.

Outportb (0x0378,ho*16+mn);Simulation of roulette wheel is quite

simple. The software uses a decimal num-ber (1 through 13) generator whose bi-nary equivalents are written into datapins D0 to D4 of the parallel port usingoutputb () function. The roulette can bereset by initialising decimal number gen-erator that simulates running lights.

The decimal number generator can be

#include <stdio.h>#include <dos.h>#include <stdlib.h>#define PORT 0x0378main(){ int k=0;clrscr();gotoxy(30,10);printf(“1.(D)ial Clock\n”);gotoxy(30,12);printf(“2.(R)un Electronic Roulette \n”);gotoxy(30,14);printf(“3.(E)xit\n”);do{k=getch();k=toupper(k);if(k==‘D’){Aclock(0,0,0);}if(k==‘R’){Roulet();}}while(k!=‘E’);clrscr();printf(“By Vijaya kumar.P,3rd Sem,E&C, K.V.G.C.E,Sullia\n”);printf(“Dedicated to Father of Electricity Michael Faraday who is my favorite Scientist.\n”);exit(0);}Aclock(int shor,int smin,int ssec){int ho,sc,mn,mnt,k,i=0;struct time tim;clrscr();do{gettime(&tim);gotoxy(30,8);ho=tim.ti_hour;mn=tim.ti_min;sc=tim.ti_sec;mnt=mn;if(ho>12)

{ho=ho-12;}if(ho==0){ho=12;}i=sc % 2;mn=mn*i; /*Making minute LED to blink*/mn=mn/5;outportb(PORT,ho*16+mn);printf(“hour:min:sec = %02d:%02d:%02d\n”, ho,mnt,sc);gotoxy(30,10);printf(“1.(G)oto MAIN MENU\n”);gotoxy(30,12);printf(“2.(S)et Alaram\n”);if(shor==ho&&smin==mnt&&ssec==sc){alarm(15);}if(mnt==0&&sc==0){alarm(1);}if(bioskey(1)) /* To check Whether any key is pressed */k=getch();k=toupper(k);if(k==‘S’){setala();}}while(k!=‘G’);{outportb(PORT,0);main();}}setala() /*Function to set Alarm*/{int hrs,mns,scs;clrscr();printf(“Enter hour\n”);scanf(“%d” ,&hrs);printf(“Enter Minute\n”);scanf(“%d” ,&mns);printf(“Enter seconds\n”);

scanf(“%d” ,&scs);Aclock(hrs,mns,scs);}alarm(int beps) /*Function to produce beeping sound*/{int i;for(i=0;i<beps;i++){sound(1500);delay(100);nosound();delay(100);}}Roulet()/*Function for Roulette Wheel*/{int i,k=0;clrscr();gotoxy(30,10);printf(“1.Press any key to Reset\n”);gotoxy(30,12);printf(“2.(P)lay\n”);gotoxy(30,14);printf(“3.(G)oto MAIN MENU\n”);k=getch();k=toupper(k);do{for(i=1;i<13;i++)/* To generate decimal number from 1 to 12*/{if(bioskey(1))k=getch();k=toupper(k);if(k==’P’)break;outportb(PORT,i);/*outputting binary equivalents of ithrough Data pins of LPT port*/delay(50);}}while(k!=’G’);outportb(PORT,0);main();}

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stopped at random for play. The speed ofrunning can be adjusted by using delay ()function. The delay time has to be se-lected appropriately, as it should not beeither too low or too high. Keeping thedelay time very low is undesirable, sinceit will cause continuous glowing of LEDs.Similarly, a very high delay time is alsoundesirable, since the player can stop thewheel at his winning position.

in a variable. This time is written intothe parallel-port as 8-bit binary numberby using outportb () function. To makeminute-indicating LED to blink, minutevariable is multiplied by (second % 2).The multiplication result comes out to be1 for odd seconds and 0 for even seconds.

i=sc%2;mn=mn*i;The binary equivalent of minute vari-

able is written into data pins D0 to D4 ofthe parallel-port. Hour variable is multi-


caded in such a way that the positive volt-age available at the emitter of transistorT1 is extended to the collector of transis-tor T3 when the outputs of all the three

SUNIL KUMAR
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Here is a simple telephone ringtone generator circuit designedusing only a few components. It

produces simulated telephone ring toneand needs only DC voltage (4.5V DC to12V DC). One may use this circuit in or-dinary intercom or phone-type intercom.

The sound is quite loud when this circuitis operated on +12V DC power supply.However, the volume of ring sound is ad-justable.

The commonly available 14-stage bi-nary ripple counter with built-in oscilla-

tor (CMOS IC CD4060B) is used to gen-erate three types of pulses, which areavailable from pin 1 (O11), pin 3 (O13), andpin 14 (O7), respectively. Preset VR1 isadjusted to obtain 0.3125Hz pulses (1.6-second ‘low’ followed by 1.6-second ‘high’)at pin 3 of IC1. At the same time, pulsesavailable from pin 1 will be of 1.25 Hz

(0.4-second ‘low’, 0.4-second ‘high’) and 20Hz at pin 14. The three output pins ofIC1 are connected to base terminals oftransistors T1, T2, and T3 through resis-tors R1, R2, and R3, respectively.

Transistors T1 through T3 are cas-

stages are low. As a result, transistorsT1 through T3 are forward biased for 0.4,1.6, and 0.025 seconds, respectively andreverse biased for similar durations.

Using a built-in oscillator-type piezo-buzzer produces around 1kHz tone. In thiscircuit, the piezo-buzzer is turned ‘on’ and‘off’ at 20 Hz for ring tone sound by tran-sistor T3. 20Hz pulses are available atthe collector of transistor T3 for 0.4-sec-ond duration. After a time interval of 0.4

second, 20Hzpulses becomeagain avail-able for an-other 0.4-sec-ond duration.This is fol-lowed by twoseconds of no-sound inter-val. Thereaf-ter the pulsepattern re-

peats itself.Refer the figure that indicates wave-

forms available at various points includ-ing the collector of transistor T3. PresetVR2 can be used for adjusting the ampli-tude of the ring tone.

K. UDHAYA KUMARAN, VU3GTH


IL KUMAR

Higher input impedance may be obtainedby substituting higher-resistance potenti-ometers, but this will lead to the pickupof stray signals.

The current drain of this circuit at 6V
SUN
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T he circuit described here is basedon the superior characteristics ofdual-gate MOSFET (metal-oxide

semiconductor field-effect transistor). Itexhibits a very high input impedance thatlends for good sensitivity and very lessloading of the input signal source. Lowcross-modulation characteristic leads tominimal distortion of the output with re-spect to the input signals. Also, theMOSFET offers low feedback capacitanceand high transconductance. All these ad-vantages make the MOSFET the most ef-fective for high-quality mixer and con-verter applications.

This dual-input audio frequency mixercircuit employs a single dual-gateMOSFET 3N200. One may, however, sub-stitute it with any other dual-gateMOSFET such as 3N187 and BF966. (Itis to be noted that BF966 is not gate-protected and hence calls for suitable pre-caution in handling it.)

The audio frequency (AF) input fromthe first channel (CH1) is applied ongate 1 (G1) of the MOSFET through 500-kilo-ohm potentiometer VR1. The AF in-put from the second channel (CH2) is ap-plied on gate 2 (G2) of the MOSFETthrough another 500-kilo-ohm potentiom-eter VR2. Potentiometers VR1 and VR2serve as gain controls for the mixer in-

puts.Gate 1 receives the negative bias re-

sulting from the voltage developed by thecurrent passing through resistor R1 thatis in series with the source. Gate 2 re-ceives the positive bias produced acrossresistor R3 by the voltage divider formedby resistors R3 and R4.

The mixed common output signal de-

veloped across drain load resistor R2 iscoupled to the output through capacitorC5. This output can be, in turn, fed toany audio amplifier system for furtheramplification.

The input impedance at each signalinput is approximately 500 kilo-ohm,which is determined largely by the resis-tance of potentiometers VR1 and VR2.

DC is less than 3 mA. The open-circuitvoltage gain is 10 for each channel. Themaximum amplitude of input signals atgates G1 and G2 is 0.1V RMS. Signals ofhigher amplitudes are reduced by the ad-justment of potentiometers VR1 and VR2,hence evading the output signal peak-clip-ping. The corresponding output signal am-plitude is 1V RMS.

The entire circuit can be built on ageneral-purpose PCB or veroboard. The

complete assemblyis shielded using ametal container.The two input jacksshould be fixed onthe opposite sides ofthe containeragainst the outputjack.

This simple cir-cuit can be utilisedfor various combina-tions of devices atthe input end. A few

examples are two microphones, two au-dio players, or one audio player and onemicrophone, etc.

Note. Adequate precautions should betaken to prevent the destruction ofMOSFET due to static electricity. The useof a grounded tip for the soldering iron isrecommended.

PRASAD J.


S.C. DWIVEDI

mately 5 seconds as ‘on’ and 5 seconds as‘off’ time.

Gate N4, with its associated compo-nents, forms a self-testing circuit. Nor-mally, both of its inputs are in ‘high’ state.However, when one switches off the igni-

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T his small circuit, based on popu-lar CMOS NAND chip CD4093,can be effectively used for protect-

ing your expensive car audio systemagainst theft.

When 12V DC from the car battery is

applied to the gadget (as indicated byLED1) through switch S1, the circuit goesinto standby mode. LED insideoptocoupler IC1 is lit as its cathode ter-minal is grounded via the car audio (am-plifier) body. As a result, the output atpin 3 of gate N1 goes low and disablesthe rest of the circuit.

Whenever an attempt is made to re-move the car audio from its mounting bycutting its connecting wires, theoptocoupler immediately turns off, as itsLED cathode terminal is hanging. As aresult, the oscillator circuit built around

gates N2 and N3 is enabled and it con-trols the ‘on’/‘off’ timings of the relay viatransistor T2. (Relay contacts can be usedto energise an emergency beeper, indica-tor, car horns, etc, as desired.)

Different values of capacitor C2 givedifferent ‘on’/‘off’ timings for relay RL1 tobe ‘on’/‘off’. With 100µF we get approxi-

tion key, the supply to the car audio isalso disconnected. Thus the output of gateN4 jumps to a ‘high’ state and it providesa differentiated short pulse to forward biastransistor T1 for a short duration. (Thecombination of capacitor C1 and resistorR5 acts as the differentiating circuit.)

As a result, buzzer in the collectorterminal of T1 beeps for a short duration

to announce thatthe security cir-cuit is intact.This ‘on’ periodof buzzer can bevaried by chang-ing the values ofcapacitor C1and/or resistorR5.

After con-struction, fix theLED and buzzerin dashboard asper your re-quirement andhide switch S1

in a suitable location. Then connect leadA to the body of car stereo (not to thebody of vehicle) and lead B to its positivelead terminal. Take power supply for thecircuit from the car battery directly.

Caution. This design is meant for caraudios with negative ground only.

T.K. HAREENDRAN


S.C. DWIVEDI

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T he circuit given here is capable ofgenerating unipolar and bipolartriangular waves as well as bipo-

lar square waves. In unipolar mode, theoutput frequency is double that ofbipolar mode (using identical componentvalues).

When switch S1 is closed, the circuitgenerates bipolar triangular as wellas bipolar square waves, and when switchS1 is open, it generates unipolar triangu-lar and bipolar square waves—both hav-

ing double the frequency in the firstcase.

Op-amp 301 acting as a com-parator produces bipolar squarewave with output swinging between+Vcc and –V EE. The square waveoutput is fed to op-amp 741 that isconfigured as an integrator to pro-duce a triangular waveform.

Figs 2 and 3 show the wave-forms with switch S1 in closed andopen positions, respectively, using

0.047µF ca-pacitor C andi n - c i r c u i tvalue of presetVR1 as 28kilo-ohm. Thecircuit is ca-pable of work-ing on a fewhertz toaround 250kHz.

YOGESH KATARIA

Construction

2001


the relays, press ‘*’ and then press keyfor digit 8. A musical note is heard, whichindicates that all the relays have beenswitched ‘off’. Keep the handset on cradle.

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SUNIL KUMAR
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JUNOMON ABRAHAM

T elephone remote control impliescontrol of devices at a remotelocation via a circuit interfaced to

the remote telephone line/device by dial-ing specific DTMF (dual-tone multi-fre-quency) digits from a local telephone. Thetelephone remote control system describedhere has the following features:

1. It can control multiple channels/relays.

2. It provides you feedback when thecircuit is in energised state and also sendsan acknowledgement indicating actionw.r.t. the switching ‘on’ of each requestedrelay and switching ‘off’ of all relays (to-gether).

3. It can selectively switch ‘on’ any oneor more relays one after the other andswitch ‘off’ all relays simultaneously.

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Instead of straightway proceeding withthe circuit description, we shall start withthe operation as this would help us inunderstanding the circuit better. The op-eration is as follows:

1. From the local telephone, dial the

number of theremote tele-phone towhich the cir-cuit is con-nected. In ashort whileyou will heara musicalnote indicat-ing that thecircuit con-nected to theremote tele-phone is ac-tive.

2. Now ifyou want toswitch ‘on’ aparticular re-l a y / d e v i c e ,press ‘*’ but-ton on thet e l e p h o n ekeypad fol-lowed by anyone of digits 1to 7 corre-sponding tothe device/re-lay numberthat you de-sire to switch‘on’. Theswitching ‘on’of the relaywill be ac-knowledged/indicated by amusical note.Now you maykeep thehandset onthe cradle.

3. If youwant toswitch ‘off’

At the remote telephone end, the ringingsignal is detected by a high-input-imped-

TABLE I(A)Input Output

A2 A1 A0 Qn = addressedL L L Q0L L H Q1L H L Q2L H H Q3H L L Q4H L H Q5H H L Q6H H H Q7

TABLE I(B)WR R Q Q

Addressed un-addressedL L = DATA holdL H = DATA LH L hold holdH H L LH = High; L = Low

Fig. 1: S

chematic diagram

of the telephone remote control



open-collector type, the output pin hasbeen pulled towards Vcc via 10-kilo-ohm

ance op-amp CA3140E that is wired as acomparator. Since this op-amp output is

resistor R21. IC2 (NE556) com-prises two timers (NE555 type) thathave been configured asmonostables.

When a ring is detected by IC1,its output triggers one of the tim-ers in IC 556. The output of thetimer after inversion by one of theNAND gates of IC3 (CD4011), en-ables IC4 (CD4060) by taking itsreset pin 12 ‘low’. (IC4 is an oscil-lator-cum-14-bit binary counter.) Asa result, IC4 starts counting whenthe ring signal strikes the input ofthe circuit.

After some time, decided by thesetting of preset VR3, Q12 outputof IC4 goes ‘high’. This outputcoupled to pin 8 of a NAND gateinside IC3 will enable it. The de-tected ring signal (if the ring sig-nal is still persisting) applied to pin9 of the same NAND gate (afterinversion by another NAND gate)will pass through it to trigger thesecond monostable inside IC2(NE556) as well as IC5 (NE555),which is again wired as amonostable. This arrangementavoids the circuit from being trig-gered by any transients or false ringsignals on the telephone line.

The output of the secondmonostable of IC2, available at itspin 9, drives transistor T2 andshunts the telephone line with 220-ohm resistor (R20). As a result, thetelephone line voltage drops toaround 10 to 12 volts. This isequivalent to the lifting of the tele-phone handset of the remote tele-phone. As mentioned earlier, bothIC5 and the second monostable ofIC2 are triggered simultaneously.The output of monostable IC5 startsmelody generator IC6 (UM66) andthe musical note obtained from itis coupled to the telephone line.This informs the caller that the re-mote circuit is in energised state.

As the remote circuit is in energisedcondition, the next step for the operator

Fig. 2: Actualsize, single-sided PCB for the circuit




PARTS LISTSemiconductors:IC1 - CA3140E op-ampIC2 - NE556 dual timerIC3 - CD4011 quad NAND gateIC4 - CD4060 14-stage counter/

oscillatorIC5 - NE555 timerIC6 - UM66 melody generatorIC7 - CM8870 DTMF-decoderIC8 - CD4099 8-bit addressable

latchIC9 - 7805 regulator +5VT1 - BC548 npn transistorT2-T9 - BC547 npn transistor (only

T2 and T6 shown)LED1, LED2 - Green LEDLED3 - Yellow LEDLED4 - Red LEDD1, D2 - 1N4148 switching diodeD3-D10 - 1N4007 rectifier diode (only

D3 and D4 shown)Resistors (all ¼-watt, ±5% carbon, unlessotherwise stated)R1, R16, R17 - 150-kilo-ohmR2, R21 - 10-kilo-ohmR3 - 33-kilo-ohmR4 - 680-kilo-ohmR5 - 560-ohmR6, R10 - 22-kilo-ohmR7 - 1-mega-ohmR8, R15 - 390-ohmR9, R12 - 15-kilo-ohmR11 - 270-ohmR13, R14 - 3.3k-kilo-ohmR18 - 330-kilo-ohmR19, R22-R27 - 4.7-kilo-ohm (R22-R27 not

shown in the figure)R20 - 220-ohmVR1 - 10-kilo-ohm presetVR2 - 1-mega-ohm presetVR3 - 220-kilo-ohm presetVR4 - 470-kilo-ohm presetCapacitor:C1 - 0.22µF ceramic diskC2 - 220µF, 10V electrolyticC3 - 100µF, 10V electrolyticC4, C5, C8 - 0.01µF ceramic diskC6, C11, C12 - 0.1µF ceramic diskC7 - 10µF, 10V electrolyticC9 - 0.02µF ceramic diskC10 - 0.47µF, 100V polyesterMiscellaneous:XTAL - 3.58MHz crystalRL1-RL7 - 6V, 150-ohm 1C/O relay

(only RL4 shown)

at local telephone is to press the ‘*’ but-ton, which makes the local telephone tooperate in the tone-dialing mode. The dig-its that are pressed after pressing the ‘*’button are converted to DTMF tones.

The tone is decoded by IC7 and itsthree LSBs (covering binary equivalentof decimal digits 0 through 7) are con-nected to the address inputs, while theMSB line is connected to reset pin 2 ofIC8 (CD4099, an 8-bit addressable latch).When a valid DTMF tone is detected atthe input of IC7, its pin 15 goes ‘high’ toenable IC8 after inversion by NAND gateof IC2. At the same time, it triggers IC5for informing the caller that his key-pressis accepted.

Numbers 1 to 7 on the local keypadcause latching of the corresponding re-lays, while number 8 causes reset opera-tion, which means that we can switch ‘on’seven relays independently one by one andswitch ‘off’ all relays simultaneously bypressing number 8. The output of IC8drives the relays via the relay driver tran-sistor. Truth tables I(A) and I(B) ofCD4099 indicate relay operation.

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1. Connect the circuit to the telephoneline.

2. Adjust preset VR1 so that the ring-ing pulse causes LED1 to flicker. For bet-ter performance, set the voltage at pin 3of IC1 at approximately 2 volts.

3. The time required to activate/energise the circuit is adjusted by presetVR3 with the help of LED2.

4. The time available for remoteswitching action can be set by preset VR2with the help of LED4. Indirectly, the set-ting of preset VR2 determines the chargethat will have to be paid to the telecomdepartment.

5. The period of the musical note canbe controlled by the adjustment of VR4with the help of LED3. ❏


A

PARTS LISTSemiconductors:IC1 - 68HC705JIACP

microcontroller

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RUPANJAN

U.B. MUJUMDAR

The basic requirements of a real-time programmable timer gener-ally used in schools and colleges

for sounding the bell on time are:• Precise time base for time keep-

ing.• Read/write memory for storing the

bell timings.• LCD or LED display for display-

ing real time as well as other data tomake the instrument user-friendly.

• Keys for data entry.• Electromechanical relay to oper-

ate the bell.We are describing here a sophisti-

cated, yet economical, school timerbased on Motorola’s 20-pinMC68HC705J1A microcontroller.

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The pin assignments and main featuresof the microcontroller are shown inFig.1 and the Box, respectively. Thecomplete system is divided into foursections, namely, the time keeping sec-tion, the input section (keyboard), theoutput (display, indicators, and relaydriving) section, and power supply andbattery backup.

The time-keeping section. Accu-rate time-keeping depends on theaccuracy of time base used for drivingthe microcontroller. In this project, the

microcontroller is driven by AT-cut par-allel resonant crystal oscillator that isexpected to provide a very stable clock.A 3.2768MHz crystal provides a timebase to the controller. The frequency(fosc) of the oscillator is internally di-vided by 2 to get the operating fre-quency (fop). This high-frequency clocksource is used to control the sequenc-ing of CPU instructions.

Timer. The basic function of a timeris the measurement or generationof time-dependant events. Timers usu-ally measure time relative to the inter-nal clock of the microcontroller. TheMC68HC705J1A has a 15-stage ripplecounter preceeded by a pre-scaler thatdivides the internal clock signal by 4.

This provides the timing reference fortimer functions.

The programmable timer status andcontrol register (TSCR) is used for de-ciding the interrupt rate. It can be pro-grammed to give interrupts after every16,384, 3,2768, 65,536, or 131,072 clockcycles. In Table I, the control word isset to provide the interrupts after ev-ery 16,384 cycles. For a 32,768MHzcrystal, the interrupt period willbe 10 ms. Thus, timer interrupts willbe generated after every 10 ms (100Hz). That is, 100 interrupts will make1 second.

Now time-keeping becomes verysimple. As we are having a precise1-second time count, a real-time clockcan be easily built.

The MC68HC705J1A has a 64 byteRAM that is used for data storage. Realtime (in terms of seconds, minutes,

IC2 - CD4532 8-bit priorityencoder

IC3 - 74LS138 3-line to 8-linedecoder

IC4 - 74LS47 BCD-to-7-segmentdecoder/driver

T1-T3 - BC547/BC147 npntransistor

T4-T7 - 2N2907 pnp transistorD1- D7 - 1N4007 diodeZD1 - 5.6V, 0.5watt zenerResistors (¼-watt, ±5% carbon, unless statedotherwise)R1 - 210-ohm, 0.5 wattR2 - 27-ohmR3, R12-R14,R24-R27 - 1-kilo-ohmR4-R8 - 100-kilo-ohmR9 -R11,R23,R29 - 10-kilo-ohmR15-R22 - 47-ohmR28 - 10-mega-ohmCapacitors:C1 - 350µF, 25V electrolyticC2, C3 - 1µF, 16V electrolyticC4, C5 - 27pF ceramic diskC6 - 0.1µF ceramic diskMiscellaneous:S1-S5 - Push-to-on switch (key)S6 - On/off switchPZ1 - Piezo buzzerRL1 - Relay 12V, 300-ohm, 1C/OXTAL - 3.2768MHz AT-cut crystalX1 - 230V AC primary to 12V-

0-12V, 500mA secondarytransformer

DIS.1-DIS.4 - LTS542 common-anodedisplay

- 4 x 1.2V Ni-Cd cells

Fig. 1: MC68HC705J1A pin assignment

Main features of MC68H705JIA• 14 bidirectional input/output (I/O) lines.

(All the bidirectional port pins are programmable as inputs or outputs.)• 10mA sink capability on four I/O pins (PA0-PA3).• 1,240 bytes of OTPROM, including eight bytes for user vectors.• 64 bytes of user RAM.• Memory-mapped I/O registers.• Fully static operation with no minimum clock speed.• Power-saving stop, halt, wait, and data-retention modes.• Illegal address reset.• A wide supply voltage range from – 0.3 to 7 volts.• Up to 4.0MHz internal operating frequency at 5 volts.• 15-stage multifunction timer, consisting of an 8-bit timer with 7-bit pre-scaler.• On-chip oscillator connections for crystal, ceramic resonator, and external clock.



hours, days of a month, and months)is stored in this RAM. Thus an accu-rate real-time clock is generated.

The input section. For setting thereal-time clock and storing operatingtimes, the timer requires to be pro-grammed externally. Data is fed us-ing the keyboard.

Press-to-on type keys are inter-faced to the microcontroller using an8-bit priority encoder CD4532. This en-coder detects the key-press operationand generates the equivalent 3-bit bi-nary data. Its truth table is shown inTable II. The priority encoder is in-terfaced to port A of themicrocontroller.

Various keys used in the timer,along with their functions, are de-scribed below:

Time (4): For setting real time inminutes and hours.

Bell (5): For setting the bell’s op-erating timings.

Digit Advance (6): Data setting isdone digitwise (hour’s digit followedby minute’s digit). The Digit Advancekey shifts the decimal point to theright.

Store (7): For storing the data (realtime or bell time).

Delete (3): For deleting a particu-lar bell timing.

Here, the figures within parenthe-ses indicate the decimal equivalentsof 3-bit binary data from the keyboard.

Set and run modes. Data settingis possible only in set mode. Set modeor run mode can be selected by toggleswitch S6. By using a lock switch forS6, the timer can be protected fromunauthorised data entry/storage.

In run mode if you press ‘Bell’ keyonce, the display shows the bell’s vari-ous operating timings one after theother, in the same order in whichthese had been previously stored. Incase you want to discontinue seeingall the bell timings, you may press‘Time’ key at any stage to revert backto the display of real time.

The output section. Seven-seg-Fig

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ment displays are used for data dis-play. As LEDs are brighter, these havebeen used in the system. There are twotechniques for driving the displays: (i)driving each display using a separatedriver (like 74LS47 or CD4511) and (ii)using multiplexed displays.

The first technique works well, butpractically it has two problems: it usesa large number of IC packages and con-sumes a fairly large amount of current.By using multiplexed display both theproblems can be solved. In multiplex-ing, only one input is displayed at anygiven instant. But if you chop or alterinputs fast enough, your eyes see theresult as a continuous display. WithLEDs, only one digit is lighted up at atime. This saves a lot of power andalso components, making the systemeconomical.

Generally, displays are refreshed ata frequency of 50 to 150 Hz. Here, dis-plays are refreshed at a frequency of100 Hz (after every 10 ms). The dis-play-refreshing program is an interruptservice routine program. BCD-to-7-seg-ment decoder/driver 74LS47, along withtransistor 2N2907, and 3-line-to-8-linedecoder 74LS138 are used for drivingcommon-anode displays.

In multiplexed display, the currentthrough the segments is doubled toincrease the display’s brightness.74LS47 is rated for sinking a currentof up to 24 mA. As the current persistsfor a very small time in multiplexeddisplay, it is peaky and can be as highas 40 mA per segment.

The decimal point is controlledindividually by transistor BC547,as 74LS47 does not support the deci-mal point. PA0 and PA1 bits of portA are used for controlling the electro-mechanical relay and buzzer, respec-tively.

Power supplyand battery backup.The microcontrollerand the associated ICpackages require a5V DC supply, whilethe relay and thebuzzer require 12VDC supply. A simplerectifier along withzener diode-regulatedpower supply is used.The microcontroller isfed through a bat-

tery-backed power supply, so that inthe case of power failure the function-ing of the controller’s timer section isnot affected. During power failure thetimer is taken to ‘low power’ mode(called ‘wait’ mode). In this mode thecontroller draws a very small current.So small Ni-Cd batteries can provide agood backup.

A simple diode-resistance (27-ohm,1/4-watt) charger maintains the chargeof the battery at proper charging rate.

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Motorola offers Integrated DevelopmentEnvironment (IDE) software for pro-gramming its microcontroller and com-plete development of the system.The development board comes withEditor, Assembler, and Programmersoftware to support Motorola’s deviceprogrammer and software simulator.The ICS05JW in-circuit simulatoralong with development board (pod)forms a complete simulator andnon-real-time I/O emulator for simu-lating, programming, and debuggingcode for a MC68HC705J1A/KJ1 familydevice.

When you connect the pod to yourhost computer and target hardware,you can use the actual inputs andoutputs of the target system duringsimulation of the code. You canalso use the ISC05JW software to editand assemble the code in standalonemode, without input/output to/from pod.The pod (MC68HC705J1CS) can be in-terfaced to any Windows 3.x- or Win-dows 95-based IBM computer using se-rial port.

The software for the timer has beenso developed that the system becomesas user-friendly as possible. The mainconstraint is read/write memory (RAM)

Fig. 3: Power supply circuit for the school timer



space. As mentioned earlier, themicrocontroller has only 64 byte RAM.About twenty bell operating timings arerequired to be stored. So the efficientuse of RAM becomes essential.

The software rou-tines for the timer,along with their As-sembly languagecodes, are listed in afolder. (Note: Thisfolder, containingsource code (.asm) andlisting file (.lst) willform part of the EFY-CD provided with theAugust issue. As filesare quite large, it isnot feasible to includethem here.) Basically,the following func-tions are performedby the software pro-gram:

1. Initialisation ofports and the timer.

2. Reading of key-pressed data.

3. Storing of realtime and bell timings.

4. Comparison ofreal time and belltime. If the twomatch, the bell rings.

5. Display of data.6. Time-keeping.For a user-friendly

system, the associatedsoftware is required to perform manydata manipulation tricks and internalbranching. The operation and logic canbe understood from the Assembly lan-guage listings. The software is mainly

TABLE ITimer Status and Control Register (TSCR)

Bit 7 6 5 4 3 2 1 0

Signal TOF RTIF TOIE RTIE TOFR RTIFR RTI RTOReset 0 0 0 0 0 0 1 1TOF: Timer overflow flag RTIF: Real-time interrupt flagRTIE: Real-time interrupt enable RTI and RTO: Real-time interrupt select bit.

RTI RTO Interrupt period0 0 fop ÷ 214 For 3.2768MHz crystal0 1 fop ÷ 215 Frequency of operation (fop)1 0 fop ÷ 216 = 3.2768x106/2 = 1.638x106MHz1 1 fop ÷ 217 For RTI=RTO=0

Interrupt period = 10ms (100Hz)

divided into the following modules:Keyboard. When a key is pressed,

CD4532 sends the corresponding data.After reading the data, the controllerdecides on the action. ‘Set/ Run’ key(S6) is connected to port PA4.

Bell. This part of the program isused for displaying the bell operatingtimings stored in the RAM. The oper-ating timings are displayed one by onewith a delay of 5 seconds between twoconsecutive timings.

Set. The real time and bell timingsare stored using this part of the soft-ware. Data is entered digitwise; for ex-ample, 08:30 a.m. will be stored as 0,followed by 8, followed by 3, and finally0. Data is stored in 24-hour format.

Data fed from the keyboard is con-verted into equivalent hex and storedin RAM. Any particular operating tim-ing can be deleted from the memoryusing ‘Delete’ key, provided the timingis already stored in the memory.

Run. Here the real time is com-pared with bell operating time. If thetwo match, the relay is operated.

DataCon. This part of the softwareis used for finding out the decimalequivalent of hex data. Themicrocontroller manipulates the hexdata and converts it into BCD formatfor display.

Timer. The timer of themicrocontroller is initialised to give aninterrupt after every 10 ms. A real-time clock is generated using the inter-rupt. Also the display is refreshed dur-ing the interrupt service routine.

For real-time systems batterybackup is very essential, because powerfailure affects the time keeping. In in-terrupt service routine, the availabilityof power supply is checked. If the poweris available, displays are refreshed andthe timer operates normally. However,during the power-failure period, dis-plays are off and system is taken to‘low power’ mode. In this mode onlythe timer part of the microcontrollerremains activated while operations ofall other peripherals are suspended.

Fig. 4: Actual-size single-sided PCB for the circuits in Figs 1 and 2



This considerably reduces the powerconsumption. When the supply gets re-stored, the controller starts operatingin normal fashion.

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When the power is switched on, thedisplay shows 12.00. Two settings arerequired in the timer: (a) setting of realtime and (b) setting of bell operatingtimings. For setting real-time clock‘Time’ key is used, while for settingbell timings ‘Bell’ key is used.

Storing of real time. To store realtime, say, 05:35 p.m., flip ‘Run’/’Set’key (S6) to set mode. The display willshow ‘0.000’. Press ‘Time’ key. Further

pressing of ‘Time’ key will incrementthe data, like 0.000, 1.000, 2.000, andthereafter it will repeat 0.000, etc.To select the digit, press ‘Digit Ad-vance’. This stores the present digitand the next digit is selected as indi-cated by the decimal pointer. Data isstored in 24-hour format. The time to

be stored is 17.35, ofwhich the first digitwill be 1.000. Thesecond, third, andfourth digits can bestored in similarfashion. After thefourth digit, press‘Digit Advance’ keyonce more. The dis-play will show 1735(with no decimal).Now press ‘Store’ tostore the data.

Storing of belltimings. The proce-dure to store bell op-erating timings issimilar to that of set-ting real time. Theonly difference is thathere data is changedby ‘Bell’ key in placeof ‘Time’ key. Anynumber of bell tim-ings (<20) can bestored in the samefashion. If the num-ber of bell operatingtimings exceeds 20,the timer will not ac-cept any new belltiming until one of

the previously stored timings is deleted.Deletion of bell operating tim-

ings. For deleting a particular timing,first store this timing using the stepsgiven above. Then press ‘Delete’ key todelete the specific data from the memory.

Display of real time. If ‘Run’/’Set’key is taken to run mode, real timewill be displayed.

Checking of bell operating times.For checking the bell operating times,press bell key in ‘Run’ mode only. Thestored bell operating timings will be dis-played one by one with a delay of 5seconds between two consecutive tim-ings.

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There are two ways to program theEPROM/OTPROM (one-time program-mable ROM):

1. Manipulate the control bits in theEPROM programming register to pro-gram the EPROM/OTPROM on a byte-by-byte basis.

2. Program the EPROM/OTPROMwith Motorola’s MC68HC705J in-circuitsimulator.

The author has used the secondmethod for programming the OTPROM.(EFY note. Readers who wish toacquire a Pod for 705KJ1/J1Amicrocontrollers, along with the re-quired software, may contact VinayChaddha at [email protected].)

An actual-size, single-sided PCBfor the circuits in Figs 2 and 3 is shownin Fig. 4, with its component layoutshown in Fig. 5.

❏ Fig. 5: Component layout for the PCB

TABLE IITruth Table for Priority Encoder CD4532

Keys E1 D7 D6 D5 D4 D3 D2 D1 D0 Q2 Q1 Q0

Store 1 1 X X X X X X X 1 1 1Digit Adv. 1 0 1 X X X X X X 1 1 0Bell 1 0 0 1 X X X X X 1 0 1Time 1 0 0 0 1 X X X X 1 0 0Delete 1 0 0 0 0 1 X X X 0 1 1

August

2001

Circuit Ideas

2001


DI

the role of an electronic switch.When the infrared beam is inter-

rupted, the output of the receiver modulegoes ‘high’ to apply a forward bias to the

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ELECTRONICS FOR YOU� ❚❚❚❚❚ �AUGUST 2001

S.C. DWIVE

This long-range cordless burglaralarm circuit makes use of acordless telephone (CLT) unit with

paging facility and a few low-cost discretecomponents. The circuit is so simple thateven a novice can easily construct it with-out any difficulty.

When the ‘page’ button on a CLT ispressed and held in that position, thehandset starts beeping to indicate thatsomebody is calling. This function is usedhere to build the gadget. The system con-sists of three sub-assemblies:

1. Wireless beeper. The handset ofthe CLT.

2. Infrared transmitter. A numberof IR transmitter circuits based on the

well-known 555 chip have been publishedearlier in EFY. Just select one circuit witha modulating frequency of 36 to 38 kHzand assemble it on a veroboard. After that,enclose it in a proper cabinet. (EFY note.A typical IR transmitter circuit used dur-ing testing is shown in Fig. 1.)

3. Infrared receiver-cum-controlunit. The circuit diagram of this unit isshown in Fig. 2. Front end of this block isSharp’s GP1U561X integrated infrared re-ceiver module (or TK1836/TSOP1836 from Temic/Telefunken, etc). This mod-ule can demodulate 36kHzmodulated IR beam to pro-duce an active-similar ‘low’output. You may also useany other module, providedit has an active-‘low’ output.The modulated IR beamfrom the transmitter is re-ceived by the receiver mod-ule and its output at pin 2goes ‘low’. The rest of the cir-cuit is in sleep mode as itdoes not get power for its op-eration. The SCR here plays

base of transistor T1. As a result, the gateof SCR gets sufficient forward bias to con-duct (and latch). The astable multivibratorbuilt around IC1 starts working to con-trol the ‘on’/‘off’ relay timings. Diode D1prevents the relay from latching and di-ode D2 works as a free-wheeling diode.

Normally open (N/O) contacts of therelay are used to close the ‘page’ buttoncontacts until the circuit is reset by press-ing push-to-off switch S1 (N/C type). Onemay replace switch S1 with a key-lockswitch to avoid its unauthorised opera-tion. The astable circuit helps the hand-set user to distinguish between a normal

paging call and an intrusion warningalarm.

After construction, fix the trans-mitter and receiver modules at oppo-site sides in the door frame as shownin Fig. 3. Carefully open the CLT andsolder two wires to the ‘page’ buttonterminals with their free ends con-nected to the relay contacts (N/O). Nowyour cordless burglar alarm with awireless monitoring range of about 500metres (actual range is based on theCLT’s paging range) is ready to detectan intruder.

EFY note. The author has success-fully tested his prototype with the fol-lowing CLT makes:

1. Panasonic KX-T 3611 BH (madein Japan)

2. Panaphone WT-3990 (made inChina)

3. Citizen JRT-5400 (made in India)

T.K. HAREENDRAN

Fig. 2

Fig. 3

Fig. 1


MAR ter level touches probe L in the overhead
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SUNIL KU

I n most houses, water is first storedin an underground tank (UGT) andfrom there it is pumped up to the

overhead tank (OHT) located on the roof.People generally switch on the pumpwhen their taps go dry and switch off thepump when the overhead tank starts over-flowing. This results in the unnecessarywastage and sometimes non-availabilityof water in the case of emergency.

The simple circuit presented heremakes this system automatic, i.e. itswitches on the pump when the waterlevel in the overhead tank goes low andswitches it off as soon as the water levelreaches a pre-determined level. It alsoprevents ‘dry run’ of the pump in casethe level in the underground tank goesbelow the suction level.

In the figure, the common probes con-necting the underground tank and theoverhead tank to +9V supply are marked‘C’. The other probe in underground tank,which is slightly above the ‘dry run’ level,is marked ‘S’. The low-level and high-levelprobes in the overhead tank are marked‘L’ and ‘H’, respectively.

When there is enough water in theunderground tank, probes C and S areconnected through water. As a result,

transistor T1 gets forward biased andstarts conducting. This, in turn, switchestransistor T2 on. Initially, when the over-head tank is empty, transistors T3 andT5 are in cut-off state and hence pnp tran-

sistors T4 and T6 get for-ward biased via resistorsR5 and R6, respectively.

As all series-con-nected transistors T2,T4, and T6 are forwardbiased, they conduct toenergise relay RL1(which is also connectedin series with transistorsT2, T4, and T6). Thusthe supply to the pumpmotor gets completed viathe lower set of relaycontacts (assuming thatswitch S2 is on) and thepump starts filling theoverhead tank.

Once the relay hasenergised, transistor T6is bypassed via the up-per set of contacts of therelay. As soon as the wa-

tank, transistor T5 gets forward biasedand starts conducting. This, in turn, re-verse biases transistor T6, which then cutsoff. But since transistor T6 is bypassedthrough the relay contacts, the pump con-tinues to run. The level of water contin-ues to rise.

When the water level touches probe

H, transistor T3 gets forward biased andstarts conducting. This causes reverse bi-asing of transistor T4 and it gets cut off.As a result, the relay de-energises andthe pump stops. Transistors T4 and T6will be turned on again only when thewater level drops below the position of Lprobe.

Presets VR1, VR2, and VR3 are to beadjusted in such a way that transistorsT1, T3, and T5 are turned on when thewater level touches probe pairs C-S, C-H,and C-L, respectively. Resistor R4 ensuresthat transistor T2 is ‘off’ in the absenceof any base voltage. Similarly, resistorsR5 and R6 ensure that transistors T4 andT6 are ‘on’ in the absence of any basevoltage. Switches S1 and S2 can be usedto switch on and switch off, respectively,the pump manually.

You can make and install probes onyour own as per the requirement and fa-cilities available. However, we are describ-

JOYDEEP KUMAR CHAKRABORTY



ing here how the probes were made forthis prototype.

The author used a piece of non-me-tallic conduit pipe (generally used for do-mestic wiring) slightly longer than thedepth of the overhead tank. The commonwire C goes up to the end of the pipe

through the conduit. The wire for probesL and H goes along with the conduit fromthe outside and enters the conduit throughtwo small holes bored into it as shown inFig. 2.

Care has to be taken to ensure thatprobes H and L do not touch wire C di-

rectly. Insulation of wires is to be removedfrom the points shown. The same arrange-ment can be followed for the undergroundtank also. To avoid any false triggeringdue to interference, a shielded wire maybe used.


S.C. DWIVEDI

For audio-visual indication, one mayuse a small buzzer (usually built insidequartz alarm time pieces) in parallel withone small (3mm) LCD in place of LED1and resistor R5. In such a case, the cur-

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P ortable loads such as video cam-eras, halogen flood lights, elec-trical irons, hand drillers, grind-

ers, and cutters are powered by connect-ing long 2- or 3-core cables to the mainsplug. Due to prolonged usage, the powercord wires are subjected to mechanicalstrain and stress, which can lead to in-ternal snapping of wires at any point. Insuch a case most people go for replacingthe core/cable, as finding the exact loca-

tion of a broken wire is difficult. In 3-corecables, it appears almost impossible to de-tect a broken wire and the point of breakwithout physically disturbing all the threewires that are concealed in a PVC jacket.

The circuit presented here can easilyand quickly detect a broken/faulty wireand its breakage point in 1-core, 2-core,and 3-core cables without physically dis-turbing wires. It is built using hex in-verter CMOS CD4069. Gates N3 and N4are used as a pulse generator that oscil-lates at around 1000 Hz in audio range.

The frequency is determined by timingcomponents comprising resistors R3 andR4, and capacitor C1. Gates N1 and N2are used to sense the presence of 230V ACfield around the live wire and buffer weakAC voltage picked from the test probe.The voltage at output pin 10 of gate N2can enable or inhibit the oscillator circuit.

When the test probe is away from anyhigh-voltage AC field, output pin 10 ofgate N2 remains low. As a result, diode

D3 conducts and inhibitsthe oscillator circuit fromoscillating. Simulta-neously, the output of gateN3 at pin 6 goes ‘low’ tocut off transistor T1. As aresult, LED1 goes off.When the test probe ismoved closer to 230V AC,50Hz mains live wire, dur-ing every positive half-cycle, output pin 10 of gateN2 goes high.

Thus during everypositive half-cycle of themains frequency, the os-cillator circuit is allowed

to oscillate at around 1 kHz, making redLED (LED1) to blink. (Due to the persis-tence of vision, the LED appears to beglowing continuously.) This type of blink-ing reduces consumption of the currentfrom button cells used for power supply.

A 3V DC supply is sufficient for pow-ering the whole circuit. AG13 or LR44type button cells, which are also used in-side laser pointers or in LED-based conti-nuity testers, can be used for the circuit.The circuit consumes 3 mA during thesensing of AC mains voltage.

rent consumption of the circuit will bearound 7 mA. Alternatively, one may usetwo 1.5V R6- or AA-type batteries. Usingthis gadget, one can also quickly detectfused small filament bulbs in serial loopspowered by 230V AC mains.

The whole circuit can be accommo-dated in a small PVC pipe and used as ahandy broken-wire detector. Before detect-ing broken faulty wires, take out any con-nected load and find out the faulty wirefirst by continuity method using any mul-timeter or continuity tester. Then connect230V AC mains live wire at one end ofthe faulty wire, leaving the other end free.Connect neutral terminal of the mainsAC to the remaining wires at one end.However, if any of the remaining wires isalso found to be faulty, then both ends ofthese wires are connected to neutral. Forsingle-wire testing, connecting neutralonly to the live wire at one end is suffi-cient to detect the breakage point.

In this circuit, a 5cm (2-inch) long,thick, single-strand wire is used as thetest probe. To detect the breakage point,turn on switch S1 and slowly move thetest probe closer to the faulty wire, begin-ning with the input point of the live wireand proceeding towards its other end.LED1 starts glowing during the presenceof AC voltage in faulty wire. When thebreakage point is reached, LED1 immedi-ately extinguishes due to the non-avail-ability of mains AC voltage. The pointwhere LED1 is turned off is the exactbroken-wire point.

While testing a broken 3-core roundedcable wire, bend the probe’s edge in theform of ‘J’ to increase its sensitivity andmove the bent edge of the test probe closerover the cable. During testing avoid anystrong electric field close to the circuit toavoid false detection.

K. UDHAYA KUMARAN, VU3GTH


RUPANJANA

TABLE IPin Configuration

Pin Description1 *Strobe2 Data bit 0

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For those who want to use their PCfor various electronic functions,here is a circuit that converts a

PC to a multi-mode light chaser. The ad-vantage of this light chaser over otherlight chasers is that users can define theirown patterns (designs) of running lightsby altering the source program that re-quires a simple hardware. The programgiven here produces 24 different patternsof running light.

The circuit shown in Fig. 1 is mainlyused to physically isolate the PC hard-ware from the mains supply and to makeit capable of driving 230V loads. The PC’sparallel port (LPT1) provided on its backis used to interface with the circuit. LPT

with a 25-core cable. Instead of connect-ing 230V bulbs you can connect small6.2V miniature lamps, which are easilyavailable in electrical shops. Connections

are shown in Fig. 3. While using6.2V miniature lamps, 50 miniaturelamps must be connected in seriesand the net combination of 50 bulbsin series should be connected toeach channel (channel 1 throughchannel 8).

Since LEDs require very smallcurrent, parallel ports can directlydrive LEDs. Software can be testedusing simple hardware as shown inFig. 2.

C language provides a built-inoutportb() function to output binarydata to a hardware port. To under-stand this, let us consider the fol-lowing program:#include <dos.h>main(){int i;printf(“Input a decimal number”);scanf (“%d”,&i);outportb() (0x0378,i);}

The above program is used tooutput a binary equivalent of thedecimal number entered. Scanf func-tion is used to take the input deci-mal number from the keyboard. Theoutportb() function directly outputsthe binary equivalent of the decimalnumber to LPT1 (Port ID is 0x0378).

port is terminated in a 25-pin ‘D’ typefemale connector. Its pin configuration isshown in Table I.

Triacs are used to drive 230V bulbs.Triac BT136 used here can take up a loadof up to 800 watts. If you want to drivehigher loads, BT136 (4A) can be replacedwith triacs of higher current ratings, likeBT139 (16A). Since we are using triacs todrive 230V bulbs, the mains supply wouldalso appear on the PC. Optocouplers havebeen used to isolate the PC from 230Vmains supply.

The circuit can be assembled on ageneral-purpose dotted PCB and can belinked to the PC’s LPT port (female) us-ing a 25-pin male ‘D’ type connector along

3 Data bit 14 Data bit 25 Data bit 36 Data bit 47 Data bit 58 Data bit 69 Data bit 710 Acknowledge11 *Busy12 Paper end13 Select14 *Auto feed15 Error16 Initialise17 *Select input18-25 Ground

Note: *indicates that pins are internally(hardware) inverted.

VIJAYA KUMAR P.



For example, if the number entered is 15,its binary equivalent 00001111 is writteninto data pins D0 to D7 of the parallelport.

To understand the logic of multi-modelight chaser, first consider the followingsimple sequential running light program:#include <stdio.h>#include <dos.h>#include <math.h>

main(){int temp=0,i,ch,PORT = 0x0378;printf(“Press x to exit” );run:for(i=0;i<8;i++){tempb=pow(2,i);outportb(PORT,temp); /* outputs BINARY no. to LPT1 */delay(2000); /*using delay to control speed */if(bioskey(1))/*To check whether any key is pressed */ch=getch();ch=toupper(ch);if(ch==’X’){

exit(0);}}goto run;}

In the above program, ‘for’ loop is usedto increment ‘i’ in steps of 1 up to 7. Asthese values of ‘i’ get substituted intemp=pow(2,i), numbers temp= 20=1, 21=2,22 =4, 23=8, 24=16, 25=32, 26=64, and 27=128

are generated. The outportb() function isused to write binary equivalents of 1, 2,4, 8, 16, 32, 64, and 128 to data pins D0to D7, with D0 as the least significantdigit and D7 as the most significant digit.

The binary equivalents of numbersobtained by incrementing powers of 2 upto 7 are given below:

It is clear from the table that the re-sulting binary numbers will produce therunning light effect. Delay function de-fines the speed of running. ‘Go to’ state-ment is used to take control uncondition-ally to ‘for’ loop, so as to repeat the run-ning process.

By changing the formula of producingbinary number patterns, one can get dif-ferent actions. The multi-mode lightchaser program is divided into a numberof cases. Each case will produce two ormore actions. These cases are made toswitch automatically using switch state-ment and one ‘for’ loop. Further, by chang-ing the delay time, one can increase ordecrease the speed of running lights.

EFY note. The complete source-levelprogram of multi-mode chaser lights inC language has been published in Soft-ware Section of this issue on page No.86. It will also be included along withthe executable version of the program inthe next month’s EFY-CD.

Decimal number Binary equivalents1 000000012 000000104 000001008 00001000

16 0001000032 0010000064 01000000

128 10000000


the bottom part of the LED gets the sup-ply and therefore only the red part of theLED is lit. The formulae for working outthe values of current-limiting resistors foreach colour LED are shown in Table I.These relationships are applicable to thecircuits of Figs 1 and 2.

DWIVEDI

S.C.

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M.K. CHANDRA MOULEESWARAN

Fuse status indicators are verysimple to construct using a fewcomponents. These go very nicely

with all sorts of power-supplies andother instruments that use power-supply sections. The logic and the

formula, if any, used witheach circuit/figure are shownin the correspondingtruth tables.

Fig. 1 shows theuse of a 3-pin bi-colour LED. Whenthe fuse is intact,

both red andgreen parts ofthe LED are litand the LEDemits a yellowlight. With thefuse in blowncondition, only

Fig. 2 employs an additional flashingLED in series with the red part of the bi-colour LED. So the fuse failure is indi-cated by the flashing of LED as well asthe red part of the bi-colour LED.

Fig. 3 shows the use of a bi-colourLED in the AC mains supply circuit. Theunique feature of this circuit is that justby altering the resistor values, it can beused in low-voltage AC circuits or DC cir-cuits.

The AC is converted into pulsatingDC using rectifier diodes before applica-tion to the LED sections via current-lim-iting resistors. For higher power dissipa-tion in current-limiting resistors, a seriescombination of resistors can be used. Be-cause of the pulsating voltage, the LEDswould produce a flickering effect. The to-tal series resistance with each LED sec-tion may be calculated by dividing 200volts with the desired LED current (say,10 mA).

Fig. 4 shows the use of a 2-pin bi-colour LED. The two LEDs are internallyconnected in reverse, so they glow both

TABLE II (REFER FIG. 2)Indicator Details

Fuse status Bias to LED1 and LED2 Colour ofLED2-anode A1-red anode A2 green anode LED1 and LED2

Intact Forward Forward Forward Continuous green LED1+flash red LED1+flash redLED2=green and yellowalternate+flash red

Blown Forward Forward Nil Flashing red LED1 and LED2

TABLE I (REFER FIG. 1)Indicator Details

Fuse status Bias to LED1 Colour of LED1A1-red anode A2-green anode

Intact Forward Forward Red+green=yellowBlown Forward Nil RedRelationship to evaluate R1 and R2 in Figs 1 and 2:DCVin-VLED % ILED=R1 or R2 in ohmswhere Vin and VLED are in volts, ILED in amperesIn Fig. 2, VLED=VD2+VLED for flasher LED path

TABLE III (REFER FIG. 3)Indicator Details

Bias to LED1 Colour of LED1A1-red anode A2-green anode

Intact Forward Forward Red+green=yellow at 50Hz flickerBlown Forward Nil Red at 50Hz flickerNote. Approximate DCVin at C of D1 or D2 is 200 volts

TABLE IV (REFER FIG. 4)Indicator Details

Supply input Polarity of Polarity to LED1 Colour of LED1the supply at P1 at P2

DC Forward Positive Negative Red-continuousReverse Negative Positive Green-continuous

AC Alternates Alternates Alternates between redat 50Hz/s at 50Hz/s and green at 50 Hz and

appears yellow



ways of the supply polarity connectionsand can be easily used for AC circuits asindicators. The correct polarity is indi-cated by green and the reverse polarityby red. The AC supply is shown by yel-

low, which, in fact, is due to the turning‘on’ of both the colours at the AC mainsfrequency. When the frequency is morethan 20 Hz, the two colours combine toproduce yellow light. Pin identification of

this LED is done usually by using a cur-rent-limiting resistor and DC supply only.

All the circuits can be effectively al-tered to suit an individual’s requirement.

Construction

2001


position 3, 1-kilo-ohm charging resistorR6 is selected by SR1, while SR2 selects

IL KUMAR

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SUN

PRATAP CHANDRA SAHU

H ere is an inexpensive circuit ofa digital capacitance-cum-fre-quency meter that can measure

capacitance in the range of 1 pF to 10,000µF and frequency in the range of 0 to 100kHz. With a slight modification, this cir-cuit can be used as an article counter ora time meter.

The principle. In a frequencycounter, the unknown input is ANDedwith a known time-base period, so thatthe numbers of cycles passed over thetime-base period are counted. The timeperiod can be measured similarly if aknown frequency is gated with the un-known time period. The same instrumentcan also determine the time period of aperiodic waveform or the time elapsed be-tween two events.

In this circuit, the capacitance mea-surement is nothing but the measurementof the time between two events in a charg-ing capacitor. An R-C (resistor-capacitor)circuit works as a time generator and thetime is directly proportional to capacitancevalue under suitable conditions. In thepresent case the condition being satisfiedis that the time period (T) is equal to theproduct RxC, where R is the value of thecharging resistor in ohms and C the ca-pacitance value in farads.

Capacitance measurement. OneRxC time (seconds) is required to chargea capacitor to 63 per cent (approximatelytwo-third) of its final value (applied volt-age).

Consider the following example:If C = 470 pF and R = 1 mega-ohm,

then one RC time period T = 470x10–6

seconds = 470 microseconds.If we select the external frequency for

the counter as 1 MHz (time period = 1microsecond), the counter progresses byone count every microsecond and thecounter reading is 470, as the gate willbe open for 470 microseconds for theabove-mentioned R and C under testing.

We get the capacitance value directly fromthe readout of the counter in picofarads.

Similarly, if we take R = 1 mega-ohmand external frequency = 1 kHz, we canread the value of the capacitor under test(CUT) directly in nanofarads. With R = 1kilo-ohm and frequency = 1 kHz, we canread the value of the CUT directly in mi-crofarads.

Frequency measurement. This in-volves passing the unknown frequency sig-nal for a known time base period throughthe counter. In a 4-digit counter with atime base of one second, the maximumdisplay will be 9999, which means thatwe cannot read a frequency of more than9999 Hz (≈10 kHz). However, if we re-duce the time base to 0.1 second, the fre-quency reading can go up by a factor often to 99.99 kHz (≈100 kHz) as the timebase virtually divides the input frequencyby 10. For low-frequency measurement,we can increase the resolution by a factorof ten by increasing the time base periodto 10 seconds, which is equivalent to themultiplication of the input frequency by afactor of 10.

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The capacitance measurement mode.During the capacitance measurementmode, switches S1 through S5 are keptslided towards position ‘C’. The unknowncapacitor is placed across CUT terminals.Ganged switches SR1 and SR2 are usedfor capacitance measurement. Position 1is used for capacitance range of 1 pF to9999 pF (≈10 nF), position 2 for capaci-tance range of 1 nF to 9999 nF (≈10 µF),and position 3 for capacitance range of 1µF to 9999 µF.

Switch SR1 selects 1 mega-ohm charg-ing resistor in its positions 1 and 2, whileswitch SR2 selects a frequency of 1 MHzin position 1 and a frequency of 1 kHz inposition 2 for the counter operation. In

1 kHz as the frequency for counter opera-tion.

Ganged rotary switches SR3 and SR4are used for frequency measurement modeonly. (EFY note. As decimal indicationis not required during capacitance mea-surement, one might have an additional

PARTS LISTSemiconductors:IC1 - NE555 timerIC2, IC3 - CA3140 high-input

impedance op-ampIC4 (A-D) - 7408 AND gateIC5 - MM74C925 4-digit counter/

7-segment driverIC6 - 74LS121 monostable MVIC7-IC9 - 74LS90 decade counter

(divide-by-10)IC10 - 7476 JK flip-flopIC11 - 7805 regulator +5VD1-D5 - 1N4007 rectifier diodeD6 - 1N4148 switching diodeLED1 - Red LEDT1-T5 - BC547B npn transistorT6 - BS107 FETResistors (all ¼ watt, ±5% carbon, unlessstated otherwise)R1 - 2.2-kilo-ohmR2, R5 - 1-mega-ohmR3, R8, R24 - 4.7-kilo-ohmR4, R20 - 10-kilo-ohmR6, R7, R18R21 - 1-kilo-ohmR9-R16 - 220-ohmR17 - 20-kilo-ohmR19 - 100-kilo-ohmR22, R23 - 560-kilo-ohmVR1 - 1-kilo-ohm presetCapacitors:C1 - 15µF, 25V electrolyticC2 - 0.01µF ceramic diskC3 - 10nF ceramic diskC4 - 10µF, 250V electrolyticC5 - 1000 µF, 25V electrolyticC6 - 100µF, 25V electrolyticC7, C8 - 22 pF ceramicC9 - 0.01µF ceramicMiscellaneous:X1 - 230 AC primary to 9-0-9 volt,

500mA secondary trans-former

XTL - 1MHz quartz crystalS1-S5 - Slide switchS6, S7 - Push-to-on switchSR1-SR2 - Ganged 3-way, 2-pole rotary

switchSR3-SR4 - Ganged 3-way, 2-pole rotary

switchDIS1-DIS4 - LT543 common-cathode,

7-segment display



Fig

. 1:

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diag

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m-f

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‘off’ position for SR3/SR4 ganged rotaryswitch.)

IC1 is a monostable multivibratorbased on timer NE555 and is meant forcapacitance measurement only. In normalcondition, the low output of themonostable turns on the FET (BS107)switch. So the capacitor under test gets

shorted via the FET switch. As and whentriggered by the momentary push-to-onoperation of start switch S6, themonostable provides a pulse of 15-secondduration. As soon as its output goes high,it switches off FET switch. Simulta-neously, it takes pin 5 of AND gate IC4Ahigh.

Now let us examine the conditions atIC2 and IC3 (both CA3140 op-amps). Thevoltage across CUT, after being bufferedby IC2, is fed to the inverting input ofIC3 wired as a comparator. The non-in-verting input of IC3 is biased at 0.63Vcc,which is set accurately by 1-kilo-ohm pre-set VR1. Now the capacitor begins tocharge. As soon as the voltage across thecapacitor crosses 0.63Vcc (i.e. 3.15 voltswith Vcc = 5 volts), the output of IC3goes low. Thus the output of IC3 and alsothat of AND gate IC4A remains high un-til the capacitor charges to 63 per cent ofVcc in one RC time.

Latch-enable (LE) pin 5 of counter IC5(74C925) connected to pin 6 of IC4A re-mains high to pass the clock selected viarotary switch SR2 and coupled to CL(clock) pin 11 of IC5 via AND gate IC4B.It goes low after one CR time to latch itscount as the output of IC3 goes low. Thusthe number of cycles from the frequencysource passed over one CR time is re-corded in the counter and gets displayed.

For precise generation of 1MHz fre-quency, a 1MHz crystal oscillator is wiredaround Schmitt inverter gates N3 and N4.The oscillator output is routed via ANDgate IC4C to slide switch S2 and rotaryswitch SR2 position 1. In capacitance (C)position of switch S2, this signal, afterdivision by three decade counters IC7,IC8, and IC9 (7490), which are commonto both frequency and capacitance metermodes, provides 1kHz signal at pin 12 ofIC9, which, in turn, is extended to posi-tions 2 and 3 of switch SR2. (Note. Theoutputs of IC10 are not used during ca-pacitance measurement. IC10 comes intoplay only during the frequency measure-ment as explained later.)

The NE555 timer used as a monoshotensures the capacitance measurement inan easy and automatic manner. The LEDconnected to AND gate IC4D glows dur-ing the charging of the capacitor. Duringthe measurement of high-value capaci-tances, it may take several seconds tocharge to 0.63Vcc. For low-value capaci-tances, the LED glows for just a momentafter pressing start switch S6. If the LEDgoes off after the start button is pressed,it indicates that the measurement is over.

You can reset NE555 timer usingswitch S7 if you want to make anothermeasurement. If this switch is not pro-vided/operated, you would have to waitfor at least 15 seconds until NE555 timerbecomes normal. Alternatively, you willFig. 3: Actual-size, single-sided PCB layout for digital capacitance-cum-frequency meter

Fig. 2: Internal block diagram and functional description for IC 74C925




of 0.1 second, 1 second, or 10 seconds inpositions 1, 2, and 3, respectively, ofswitch SR3. Q output of IC10 is used toenable counter IC5.

The resetting of counter-cum-displayIC5 is accomplished by the narrow out-put pulse from IC6 (74121), which is gen-erated by the leading (rising) edge of Qoutput of IC10 connected to its B input(pin 5) via switch S5. Thus at the begin-ning of each counting period, IC5 is reset.

IC5 (74C925) is TTL-compatible witha multiplexed 4-digit, 7-segment displaydriver. Its internal block diagram andfunctions are described in Fig. 2. Themaximum frequency display in positions1, 2, and 3 of ganged switches SR3 andSR4 is limited to 99.99 kHz, 9.999 kHz,and 999.9 Hz. The decimal point positionis fixed by switch SR4.

Calibration and testing. Connect amultimeter to the non-inverting terminalof IC3 and set the point at 0.63Vcc = 3.15volts using 1-kilo-ohm preset VR1. To testthe capacitance meter, use a 470pF poly-styrene capacitor with one per cent toler-ance.

Precaution. Try to screen the mainstransformer from the input. Place thetransformer at a place where the chancesof its interference with the input are mini-mal or nil. While measuring the fre-quency, the frequency source under testshould not be touched or loaded to avoidaffecting its frequency due to stray ca-pacitance associated with the test leads.

An actual-size, single-sided PCB forthe circuit of Fig. 1 is shown in Fig. 3,with its component layout shown inFig. 4. ❏

against high voltage.R21 is test selected to get proper 100

Hz rectangular wave form at the outputof gate N2. This 100Hz signal is dividedby decade counters IC7, IC8, and IC9 toobtain 10Hz, 1Hz, and 0.1Hz frequencies.The frequency selected via rotary switchSR3 is then divided by 2 by JK flip-flop7476 (IC10) so as to provide a gate time

have to switch off the complete circuitand then switch it on again.

Frequency counting. In place of1MHz oscillator, a 100Hz full-wave recti-fied (pulsating DC) after being shaped bySchmitt inverter N2, is used as the mas-ter clock to provide the required timebases. The voltage divider network of re-sistors R20 and R21 protects gate N2


RUPANJANA

from ground level (0V) to supply voltage.Thus the reference voltage source shouldbe externally preset, which is feasible withthe help of IC1. This IC can also displaythe input voltage on a linear scale usingten LEDs in the bar graph or the dot

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The fluid-level controller circuit pre-sented here allows you to set thelower and upper fluid levels at

the desired specific positions between twoextreme levels. The total fluid level is di-vided into ten equal parts. Any two ofthese ten positions may be defined as ‘low’and ‘high’ level, respectively. The systemshows the preset levels on the two 7-seg-ment displays and the current fluid levelat any instant on a 10-LED bar graphindicator. The same circuit could also beused for controlling temperature in a simi-lar fashion.

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The main part of the circuit as shown inFig. 1 is dot/bar graph driver LM3914(IC1). This IC is linearly scaled and isintended for use in LED voltmeter appli-cation where the number of illuminatedLEDs indicates the value of input volt-age. It contains a floating 1.2V referencesource between pins 7 and 8 that may beused as the reference input for the IC.The voltage from the sensor is fed to theinput of IC1 at pin 5.

The output of the sensor may vary

Fig. 1: Schematic diagram of fluid-level controller with indicator

BHASKAR BANERJEE

mode. Here we have used the bar graphmode.

The outputs of IC1 are active-‘low’ andhence they sink current to illuminateLEDs. Inverters are used between the out-puts of IC1 and the inputs of IC3 and IC4to invert the active-‘low’ outputs of IC1.There are ten outputs available from IC1,of which only five are used here. One mayuse up to eight outputs of IC1 since IC3and IC4 (4051) are 1-of-8 data selectors.(Note. If 4067 were used in place of 4051,all the ten outputs could be used. It isalso possible to get more than ten out-puts by cascading LM3941 ICs.)

Using this circuit, the maximum fluidlevel can be divided into four equal partsgiving five different level readings from



‘0’ (empty/low level)to ‘4’ (full/high level).Thus thefive levelsare empty,one-fourth,half, three-fourth, andfull. Thisdivision ismeant onlyfor control-ling the

level, while all levelsincluding the inter-mediate levels areconstantly displayedon LED bar graph.

The lower levelcan be set anywherebetween 0 and 3 insteps of 1 and highlevel can be set be-tween 1 and 4. Thefluid level can be

maintained between any two levels by us-ing IC3 and IC4. IC3 selects the high leveland gets inputs of levels 1, 2, 3, and 4,while IC4 selects the low level and getsinputs of levels 0, 1, 2, and 3. All otherunused input pins of IC3 and IC4 are

Fig. 2: Optical sensor

Fig. 3: Sensorusing floatoperated potmeter

Fig. 4: Actual-size, single-sided PCB layout for fluid-level controller with indicatorPARTS LIST

Semiconductors:IC1 - LM3914 bar/dot display

driverIC2 - 4069 hex inverterIC3, IC4, IC5 - 4051 8-channel analogue

multiplexerIC6 - 4520 dual binary counterIC7 - 555 timerIC8 - 4081 quad 2-input AND

gateIC9, IC10 - 4511 BCD-to-7-segment

latch/decoder/driverLED1, 3, 5, 7, 9 - Green LEDLED2, 4, 6, 8,10, 11 - Red LEDResistors (all ¼-watt, ±5% carbon unlessstated otherwise):R1-R10,R16-R31 - 470-ohmR11-R15 - 10-kilo-ohmR32-R33 - 47-kilo-ohmR34 - 1-kilo-ohmVR1 - 10-kilo-ohm presetCapacitors:C1, C2 - 22µF, 25V electrolyticC3, C4 - 10µF, 25V electrolyticC5 - 1µF ceramic diskMiscellaneous:DIS1, DIS2 - Common-cathode

7-segment displayS1, S2 - Push-to-on switch

grounded.The selection takes place according to

the binary word preset at the select inputpins (pin 9, 10, and 11) of IC3 and IC4.The required binary word is generated bya dual divide-by-16 counter IC6 (4520).(IC6 can be replaced by a divide-by-10counter 4518, if desired.) Half of IC6 isused for high level and the other half forlow level. IC6 gets its counting pulse froma 555 timer (IC7) used for generation ofapproximately 1Hz pulse train.

The high level is set by pressingswitch S1, while the low level is set bypressing switch S2. IC6 is reset when thepower is switched on. This power-on-re-set function is realised using capacitorsC1 and C2, and resistors R12 and R13.The part of IC6 connected to high-levelselector also gets reset when the count is5 (101 binary). This reset pulse is gener-ated using AND gates of IC CD4081.

The selected minimum and maximum

levels are displayed by two 7-segment dis-plays DIS1 and DIS2 that are controlledby two BCD-to-7-segment decoders 4511(IC9 and IC10, respectively).

The outputs of IC3 and IC4 are fed tothe select input pins of IC5 (4051). Theoutput of IC5 is fed back to one of itsselect inputs through an inverter. IC5 de-termines the control logic. The pump (orthe heater in temperature controller)should be ‘on’ when the fluid (or tempera-ture) level is below the minimum leveland should remain ‘on’ until the maxi-mum level is reached. It must not start ifthe fluid level falls below the maximumlevel but remains above the minimumlevel. This function is realised by IC5 thatcan operate a pump (or an alarm, or aflow valve, or a heater, as required) ac-cording to this control logic. For this, theinput lines of IC5 are set to appropriatelogic levels, which must not be disturbed.

Sensor. To control the fluid level (say,



water level in a tank), an optical sensoras shown in Fig. 2 may be used. Thisoptical sensor consists of a small filamentlamp (generally used in torch or an IRLED as light source) and an LDR or aphotodiode as the sensor. The filamentlamp may be powered using the samestep-down transformer that is used topower the circuit. Alternatively, a sepa-rate step-down transformer may be usedfor the purpose, but taking into accountthe voltage and current ratings of thelamp.

One may also use the sensor describedin ‘Digital Water Level Meter’ in CircuitIdeas section of the February 2000 issueof EFY. Use that sensor (VR4) as part ofa voltage divider network as shown inFig. 3. If the circuit is used as a tempera-ture controller, a temperature sensor us-ing the popular LM35 IC may be built(refer Circuit Ideas published in March1993 issue of EFY).

Operation. The lower or the mini-mum level is set by pressing switch S2and the upper or the maximum level bypressing switch S1. The two switchesshould be kept pressed until the requiredlevel is displayed. For example, if thelower level is selected 1 and the upperlevel 3, the pump (or heater or a flowvalve) will start when the fluid falls be-low level 1 and will stop when the fluidreaches level 3.

Assembly and testing. The circuitmay be built on a veroboard. However,an actual-size, single-sided PCB and itscomponent layout are shown in Figs 4and 5, respectively. Switches used, shouldbe of good quality. After assembling, thecircuit may be tested using a voltage di-vider (potentiometer) that could be var-

Fig. 5: Component layout of PCB

ied between ground and positive supply.While testing, set preset VR1 to in-

crease or decrease the reference voltagetaking into account the maximum outputavailable from the actual sensor. In case

of power failure, there should be properbattery back-up. Otherwise, the systemwill not behave as desired. Red and greenLEDs are arranged in alternate fashionto make the bar display look attractive.❏

September

2001

Circuit Ideas

2001


using eight XNOR gates as shown in thefigure. Let the output lines from XNORgates be N0 through N7. Consider inputsLp and Mp of the corresponding XNOR

SUNIL KUMAR

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ELECTRONICS FOR YOU� ❚❚❚❚❚ �SEPTEMBER 2001

DR BHASKARA RAO N.

Anormal priority encoder encodesonly the highest-order data line.But in many situations, not only

the highest but the second-highest prior-ity information is also needed. The cir-cuit presented here encodes both the high-est-priority information as well as the sec-ond-highest priority information of an 8-line incoming data. The circuit uses thestandard octal priority encoder 74148 thatis an 8-line-to-3-line (4-2-1) binary encoderwith active-‘low’ data inputs and outputs.

The first encoder (IC1) generates thehighest-priority value, say, F. The active-‘low’ output (A0, A1, A2) of IC1 is invertedby gates N9 through N11 and fed to a 3-line-to-8-line decoder (74138) that requiresactive-‘high’ inputs. The decoded outputsare active-‘low’. The decoder identifies thehighest-priority data line and that datavalue is cancelled using XNOR gates (N1through N8) to retain the second-highestpriority value that is generated by thesecond encoder.

To understand the logic, let the in-coming data lines be denoted as L0 to L7.Lp is the highest-priority line (active-‘low’)and Lq the second-highest priority line(active-‘low’). Thus Lp=0 and Lq=0. Alllines above Lp and also between Lp andLq (denoted as Lj) are at logic 1. All linesbelow Lq logic state are irrelevant, i.e.‘don’t care’. Here p is the highest-priorityvalue and q the second-highest-priorityvalue. (Obviously, q has to be lower thanp, and the minimum possible value for pis taken as ‘1’.)

Priority encoder IC1 generates binaryoutput F2, F1, F0, which represents thevalue of p in active-‘low’ format. Thecomplemented F2, F1, and F0 are appliedto 3-line-to-8-line (one out of eight out-puts is active-‘low’) decoder 74138. Let theoutput lines of 74138 be denoted as M0through M7. Now only one line is active-‘low’ among M0 through M7, and that isMp (where the value of p is explained asabove). Therefore the logic level of lineMp is ‘0’ and that of all other M lines ‘1’.

The highest-priority line is cancelled

gate. Since Mp = 0 and also Lp = 0, theoutput of this XNOR gate is Np = comple-ment of Lp = 1. All other L’s are not changedbecause the corresponding M’s are all 1’s.



ate S2, S1, S0, which represent q. Thusthe second-highest priority value is ex-tracted. Through cascading one can recoverthe third-highest priority, and so on.

For example, let L0 through L7 = X XX 0 1 1 0 1. Here the highest ‘0’ line is L6and the next highest is L3 (X denotes‘don’t care’). Thus p=6 and q=3. Now theactive-‘low’ output of the first priority en-

Thus data lines N0 through N7 are sameas L0 through L7, except that the highest-priority level in L0 through L7 is cancelledin N0 through N7.

The highest-priority level in N0through N7 is the second-highest priorityleftover from L0 through L7, i.e. Nq=0 andNj=1 for q<j≤7. Now these N lines are ap-plied to priority encoder 2 (IC3) to gener-

coder will be F2 F1 F0 = 0 0 1. The inputto 74138 is 1 1 0 and it outputs M0through M7 = 1 1 1 1 1 1 0 1. SinceM6=0, only L6 is complemented by XNORgates. Thus the outputs of XNORs areN0 through N7 = X X X 0 1 1 1 1. NowN3=0 and the highest priority for ‘N’ is 3.This value is recovered by priority en-coder 2 (IC3) as S2 S1 S0 = 1 0 0.


IVEDIThe voltage from the wipers of pre-

sets are multiplexed by CD4067B and the

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S.C. DW

Continuous monitoring of the mainsvoltage is required in many ap-plications such as manual volt-

age stabilisers and motor pumps. An ana-logue voltmeter, though cheap, has manydisadvantages as it has moving parts andis sensitive to vibrations. The solidstatevoltmeter circuit described here indicatesthe mains voltage with a resolution thatis comparable to that of a general-pur-pose analogue voltmeter. The status ofthe mains voltage is available in the formof an LED bar graph.

PRATAP CHANDRA SAHU

Presets VR1 through VR16 are usedto set the DC voltages corresponding tothe 16 voltage levels over the 50-250Vrange as marked on LED1 throughLED16, respectively, in the figure. TheLED bar graph is multiplexed from thebottom to the top with the help of ICsCD4067B (16-channel multiplexer) andCD4029B (counter). The counter clockedby NE555 timer-based astablemultivibrator generates 4-bit binary ad-dress for multiplexer-demultiplexer pairof CD4067B and CD4514B.

output from pin 1 of CD4067B is fed tothe non-inverting input of comparator A2(half of op-amp LM358) after being buff-ered by A1 (the other half of IC2). Theunregulated voltage sensed from rectifieroutput is fed to the inverting input of com-parator A2.

The output of comparator A2 is lowuntil the sensed voltage is greater thanthe reference input applied at the non-inverting pins of comparator A2 via bufferA1. When the sensed voltage goes belowthe reference voltage, the output of com-parator A2 goes high. The high outputfrom comparator A2 inhibits the decoder(CD4514) that is used to decode the out-



put of IC4029 and drive the LEDs. Thisensures that the LEDs of the bar graphare ‘on’ up to the sensed voltage-level pro-portional to the mains voltage.

The initial adjustment of each of thepresets can be done by feeding a knownAC voltage through an auto-transformer

the circuit so that performance of the cir-cuit is not affected even when the mainsvoltage falls as low as 50V or goes ashigh as 280V. During Lab testing regu-lated 12-volt supply for circuit operationwas used.)

and then adjusting the corresponding pre-set to ensure that only those LEDs thatare up to the applied voltage glow.

(EFY note. It is advisable to use ad-ditional transformer, rectifier, filter, andregulator arrangements for obtaining aregulated supply for the functioning of


the truth table shown. Fig. 3 shows theKarnaugh Map simplification of minterms.

When the software program using ‘C’RUPANJANA
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Here is a small circuit of an elec-tronic dice to interface with yourPC. The circuit simulates a digi-

tal dice and uses the parallel-port LPT1provided on the back of the PC. LPT em-ploys a 25-pin ‘D’ type female connector.

‘C’ language provides a built-inoutportb() function to output binary datato the hardware port. To understand this,let us consider the following program:#include <dos.h>main(){int i;printf(“Input a decimal number”);scanf (“%d”,&i);outportb(0x0378,i);}

The above program is used to outputthe binary equivalent of a decimal num-ber entered via the keyboard. ‘Scanf’ func-tion is used to take the input decimalnumber from the keyboard. The‘outportb()’ function directly outputs thebinary equivalent of decimal number toLPT1 (port ID is 0x0378).

For example, after you convert theabove program into an executable file us-ing Turbo C compiler and run it, the pro-gram prompts you to “Input a decimalnumber”. Suppose you enter 15 , then itsbinary equivalent 00001111 is output(written) to data pins D0 through D7 (pins2 through 9) of the 25-pin parallel port.If LEDs are connected to the output pinsof the parallel port, along with resistorsof 220-ohm in series, they can be directlydriven to indicate the binary output num-ber, as the parallel port can directly sup-port the current required for driving theLEDs.

The electronic dice program generatesa random decimal number that is outputthrough data-output lines D0 through D2(pins 2 through 4) of the LPT port in theform of a 3-bit binary number.

Fig. 1 shows the hardware interfacecircuit of a BCD-to-decimal converter em-ploying a 7-segment display driver IC 7447,which directly converts the input BCDnumber into 7-segment display. Fig. 2shows the circuit simulating the electronicdice with dot pattern display that satisfies

language is run after compilation, itprompts you to press letter ‘T’ for simu-lating an action equivalent to throwing ofdice by generating/outputting a random

Fig. 2

VIJAYA KUMAR P.

Fig. 1

TRUTH TABLE

Throw Data pins State of LEDs DisplayLogic stateD2 D1 D0 A B C D E F G

1 0 0 1 OFF OFF OFF OFF OFF OFF ON

2 0 1 0 ON OFF OFF OFF OFF ON OFF

3 0 1 1 ON OFF OFF OFF OFF ON ON

4 1 0 0 ON OFF ON ON OFF ON OFF

5 1 0 1 ON OFF ON ON OFF ON ON

6 1 1 0 ON ON ON ON ON ON OFF



outtextxy(175,20,“**ELECTRONIC DICE**”);setcolor(GREEN);settextstyle(DEFAULT_FONT,HORIZ_DIR,2);outtextxy(x/5,180,“1.Press T to Throw Dice”);outtextxy(x/5,230,“2.Press X to Exit”);/* Actual program */do{ch= getch();ch= toupper(ch);if(ch==‘T’){randomize ();ran=random(6); /* to generate random number between 0&7 */ran=ran+1;outport(PORT,ran); /* outputs BINARY no. to LPT1 */}}while(ch!=‘X’);closegraph();printf(“By Vijaya Kumar.p”);exit(0);}

Fig. 3

number, or press letter ‘X’ to exit the pro-gram. The program is given below:

#include <stdio.h>#include <dos.h>#include <graphics.h>#include <stdlib.h>main(){int ran,PORT = 0x0378;

int gd=DETECT,gm,ch,x,y;initgraph(&gd,&gm ,“” ); /* initializes graphics mode *//* Decorating the screen */x = getmaxx();y = getmaxy();setbkcolor(BLUE);rectangle(10,y-10,x-10,10);setcolor(YELLOW);settextstyle(TRIPLEX_FONT,HORIZ_DIR,3);


SUNIL KUMAR
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H ere is a circuit based on aunijunction transistor (UJT)2N2646 or its equivalent that

can be used as a light-operated organ.Wired as a relaxation oscillator, it canoscillate independently without a tank cir-cuit or complicated RC feedback network.

A light-dependent resistor (LDR) is in-cluded in the emitter circuit of T1 asshown in the diagram. When LDR receiveslight from a light source, such as an elec-

tric bulb, a sharp andpleasing audio toneis heard from thespeaker. The intensityof light falling on LDRcan be varied by wav-ing a hand to and frobetween the lamp andthe LDR. As a result,the frequency of theoutput sound changes.

PRADEEP G.

Construction

2001


pin is low, output pin 3 is high and ca-pacitor C1 starts charging throughpotmeter VR1.

When the voltage across capacitor

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S.C. DWIVEDI

MGMA, pronounced as migma, isa versatile and multi-purposegadget. It can be used for a

range of applications, from a simple toyto domestic and workbench applications.It measures time, compares light output,temperature, resistance and capacitance,etc. You can use this gadget in a numberof ways, depending on your imaginationand creativity.

Basically, MGMA is a resistance-ca-pacitance-controlled oscillator that countsthe pulses for a specific period. If anytransducer, such as light-dependent re-sistor (LDR) or heat-dependent resistor(thermistor), is connected to it, the dis-play shows the value corresponding to itsresistance. Contact or break (normallyopen or closed) type transducers can alsobe used with MGMA.

Fig. 1 shows the block diagram of theMGMA circuit. Block 1 is an oscillator

that is controlled by block 2. Block 2 con-tains another oscillator whose frequencyis much lower than that of the former.The differentiator circuit in block 3 re-sets the decade counters periodically.Blocks 4 and 5 count the pulses, which,in turn, are displayed by blocks 6 and7. Digit 9 in tens counter is decodedby block 8, and its output disables thecounting process and triggers the auralindicator in block 9. Block 10 comprisesthe regulated power supply to run thegadget.

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Oscillator. In Fig. 2, Schmitt trigger in-put NAND gate N1 of IC1 (CD4093), ca-pacitor C1, and potmeter VR1 form theoscillator circuit. Let us presume that ca-pacitor C1 is in discharged state and pin2 of gate N1 is in high state. As the input

C1 reaches above half of the supplyvoltage, input pin 1 of gate N1 goes highand output pin 3 goes low. Now capaci-tor C1 discharges through potmeterVR1. When the voltage across capacitorC1 falls below half of the supply voltage,pin 1 of gate N1 goes low and the outputpin goes high. Now capacitor C1 startscharging again and the cycle repeatsitself.

The pulses from the output of gateN1 reach counter IC2 through resistorR1. Switch S1 is provided to stop thecounting manually by grounding thepulses through R1 when switch S1 ispressed.

Counter and display. The output of

Fig. 1: Block diagram of the MGMA circuit

A. JEYABAL

PARTS LISTSemiconductors:IC1 - CD4093 quad 2-input

Schmitt trigger NAND gateIC2, IC3 - CD4033 decade counter/

7-segment decoderIC4 - 7805 +5V regulatorT1 - BC557 pnp transistorT2 - SL100 npn transistorD1-D7 - 1N4148 switching diodeD8, D9 - 1N4001 rectifier diodeLED1 - Red LEDResistors (all ¼-watt, ±5% carbon, unlessstated otherwise)R1, R6-R9 - 100-kilo-ohmR2 - 220-kilo-ohmR3 - 470-kilo-ohmR4 - 3.3-kilo-ohmR5, R10, R11 - 330-ohmVR1 - 1mega-ohm pot., linearVR2 - 47-kilo-ohm pot., linearCapacitors:C1, C3 - 0.001µF ceramic diskC2 - 4.7µF, 10V tantalumC4 - 1000µF, 25V electrolyticC5, C6 - 0.1µF ceramic diskMiscellaneous:X1 - 230V AC primary to 9-0-9V

AC, 100mA secondarytransformer

S1, S2 - Push-to-on switchS3 - SPST switch, 230V ACDIS1, DIS2 - LT543 7-segment, common-

cathode type LED displaySOC1 - SOC4 - Earphone socketSOC5 - DC IN socketPZ1 - Piezo-buzzer

- IC bases, knobs, mainschord, cabinet

- Banana-type earphone plugs



the oscillator is connected to clock inputpin 1 of IC2 (CD4033, a decade counterfor unit digits). The carry-out pin 5 ofIC2 is connected to the clock input of de-cade counter IC3 that is meant for ten’sdigits. The segment outputs of both IC2and IC3 go to the respective seven seg-ments of DIS1 and DIS2 (LT543) for dis-

playing the number of pulses.Lamp-test (LT) pin 14 of both IC2 and

IC3 is grounded through 100-kilo-ohm re-sistor R8. The test-point (TP) may be usedto check the display. When a high-levelvoltage (5V) is applied to the test-point,all segment outputs go high and the dis-play shows 88.

The display is blanked outwhen the number to be dis-played is 0, provided the rippleblanking input (RBI) pin 3 isheld low. So on reset, onlyDIS1 (unit digit) will show zeroas RBI pin 3 of IC3 isgrounded.

Switch S2 is provided toreset the counter manually.Current-limiting resistors R5and R10 provided with DIS2and DIS1, respectively, areused to reduce the component

count and ensure the proper operation ofdigit-9 decoder circuit.

Display controller and differen-tiator. For accurate reading of thecounter, it must be reset periodicallyand the pulses must be counted for aspecific period. For this an oscillator cir-cuit comprising gate N2, diodes D1 andD2, resistor R2, potmeter VR2, and ca-pacitor C2 is used. This oscillator alsoworks like the previous one, but its charg-ing and discharging paths are separatedby diodes D1 and D2. Its ‘on’ time (high-level output) can be controlled bypotmeter VR2.

When output pin 4 of gate N2 goesfrom low to high state, the differentiatorcircuit comprising capacitor C3 and resis-tor R9 produces a sharp pulse that resetscounters IC2 and IC3. At the same time,gate N1 is enabled as output pin 4 of gateN2 is connected to input pin 2 of gate N1,

TABLECount Decoded output of IC CD4033

a b c d e f g CO0 1 1 1 1 1 1 0 11 0 1 1 0 0 0 0 12 1 1 0 1 1 0 1 13 1 1 1 1 0 0 1 14 0 1 1 0 0 1 1 15 1 0 1 1 0 1 1 06 1 0 1 1 1 1 1 07 1 1 1 0 0 0 0 08 1 1 1 1 1 1 1 09 1 1 1 1 0 1 1 0

Fig. 2: Schematic diagram of MGMA



and it outputs clock pulses. These pulsesare counted by IC2 and IC3 and displayedon DIS1 and DIS2, respectively. So the

oscillator around gate N1is enabled and disabledduring the high and lowstates, respectively, of theoutput of gate N2.

The counters retaintheir last count for read-ing until the output goeshigh once again. Thisreading time is about 2to 3 seconds, which is setby resistor R2. Any in-crease in the value of R2will increase the readingtime and vice versa. Re-sistor R3 connected inparallel across capacitorC3 is used to discharge itquickly and diode D3 isused to block the DC volt-age (when switch S2 ispressed) going to gatesN1 and N3, and otherparts of the circuit.

Digit 9 decoder andaural indicator. It isvery useful to sound analarm for a certain read-ing or otherwise, say, fora particular temperatureor light output or resis-tance value, etc. A perma-nent number 90 is chosenfor simplicity of the de-coding circuit. When thedisplay shows 90, thecounter must be disabledand the buzzer enabled.

From the table of de-coded outputs of IC 4033it is found that for num-ber 9, at least one of thesegment outputs is low (a,b and f are high, while eis low). For number 8,segment e is inverted bytransistor T2. As RBI pin3 of IC3 is grounded, allthe segment outputs golow for 0. The clock-en-able (CE) pin 2 of IC3 ispulled up by resistor R7.

Pin 2 is also con-nected to a, b, f and e seg-ment outputs of IC3through diodes D5, D6,D7, and transistor T2, re-

spectively, that altogether act as ANDgate and bring the CE pin to ground fornumbers 0 through 8. When the number

is 9, the segment outputs a, b, and e arehigh, except the segment output e, whichis inverted by transistor T2. As a result,CE pin of IC2 goes high and the countersare disabled.

Simultaneously, this high-level outputis inverted by gates N3 and N4. The in-verted output from gate N4 forward bi-ases transistor T1 to drive the piezo-buzzer, while the inverted output fromgate N3 grounds the resetting pulses.Diode D4 prevents the high output ofN3 from reaching the reset pins of IC2and IC3.

Power supply. In 5V DC power sup-ply shown at the bottom in Fig. 2, IC7805 (IC4) is employed for better regula-tion. DC input/output socket (SOC5) isprovided to operate the gadget with ex-ternal 9V battery. LED1 acts as a power-on indicator.

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Figs 3 and 4 show suggested actual-size,single-sided PCB layout and componentlayout, respectively, for the circuit in Fig.2. Solder the components in the order ofIC sockets, jumpers, resistors, capacitors,diodes, LED, and transistors. Then con-nect the rest of the components throughwires. Fig. 5 shows the proposed front-panel layout of MGMA.

Before connecting VR1 and VR2 to thePCB, mark the dials using a digital mul-timeter. Both dial 1 and dial 2 (refer Fig.5) are calibrated in terms of resistancefor the variable resistance values of 1mega-ohm in case of VR1 and 47 kilo-ohm in case of VR2, respectively, using adigital multimeter. (Note. There may bedead-ends on both ends of the potmeter,and it may vary in construction frommanufacturer to manufacturer.) Mark thedials for every ten units for easy readingand setting.

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For high-resistance and low-resistancetransducers, use earphone-type socketsSOC1 and SOC3, respectively. For low-capacitance and high-capacitance testing,use earphone-type sockets SOC2 andSOC4, respectively. For SOC1 and SOC2,the reading will decrease for the increas-ing value of resistance and capacitance,and vice versa for SOC3 and SOC4.

Strength-0-meter. This game re-quires two small rods or prods. Connect

Fig. 3: Actual-size, single-sided PCB pattern suggested forthe circuit in Fig. 2




them to an earphone plug using a pair ofwires half a metre long. Then insert theplug into SOC1. Hold the rods in eachhand between forefinger and thumb. Ad-just dials 1 and 2 such that the buzzerbeeps. Then rotate dial 1 slightly in theanti-clockwise direction to read around 70,a point where the buzzer is silent. Nowask your friends one by one to grip therods firmly. The winner is the one whosounds the buzzer or scores higher on themeter. This depends on how hard oneholds the rod, the internal resistance ofthe body, and dampness of the fingers.

Plant tender. You can use MGMA toindicate the time of watering in order toavoid excessive watering of plants. Forthis, insert two metal strips on both sidesof the plant. Connect them to an earphoneplug using wires and insert the plug intosocket SOC3. Since soil-resistance in-creases with loss of water, the alarm canbe set/activated for a specific moisturelevel. Adjust dials 1 and 2 such that thebuzzer sounds when the plant needs tobe watered. The buzzer stops in a shortwhile on sprinkling water over the soilsupporting the plant. The next time thebuzzer will sound automatically when theplant needs to be watered.

Game of quick hands. This game

requires an earphone plug with its twoterminals shorted. Inserting this plug intoSOC4 grounds input pins 5 and 6 ofSchmitt NAND gate N2 via the shortedplug in SOC4. Since output pin 4 is al-ways in high state, its periodic action ofdisabling gate N1 is no longer there.

Connect a 0.1µF capacitor to SOC2using an earphone plug. Since its capaci-tance value is higher than that of capaci-tor C1, the frequency of the oscillator de-

creases. The display shows a readingon momentarily pressing start/resetbutton S2 and then quickly depress-ing stop button S1. Adjust the dial toread 50 in the display. Now tell yourfriends to press button S2 momen-tarily and then S1. One who scoresless is more quicker than the others,and hence the winner.

Water-level monitoring. Five re-sistors R12 through R16 are con-nected in series and the junctions ofthe resistors are extended to the fivelevels of the water tank using wires(refer Fig. 6). A reference rod is alsofitted with its lower end just belowlevel 1.

Plug-in a dummy resistor of 100kinto SOC1 and rotate dial 1 to the zero-resistance position. Adjust dial 2 to read55 in the display. Cover the unit digitwith an opaque tape, so that only theten’s digit is visible. Now remove thedummy resistor. Connect the other endof five-resistor ladder and the referenceprobe to SOC1. The display will showthe water levels from one-fifth to five-fifth of the tank, depending on the actuallevel at that time.

Measuring resistance. The idea issimple. First, VR1 (dial 1) is excluded fromthe circuit by rotating it to zero reading.Then an unknown resistor is connectedto SOC1 and dial 2 is adjusted to read anumber just below 90. Now VR1 (dial 1)is reinstated and rotated to display thesame reading. As dial 1 is marked forresistance values, the position of dial 1indicates the value of unknown resistor.

With MGMA, up to 2-mega-ohm re-sistor can be measured. Connect the un-known resistor to SOC1 using crocodileclips. Rotate dial 1 to the zero-resistanceposition without touching the resistor, oth-erwise your body resistance will get in-cluded in the measurement. Adjust dial 2such that the display reads around 90.The resistor is open if the display shows0, and shorted if you’re unable to set the

reading near 90.Remove the unknown resistor. With-

out disturbing dial 2, slowly rotate dial 1to get the same reading. Now dial 1 showsthe value of unknown resistor.

If the resistor value is less than 40k,use SOC3 and repeat the same procedurewith dial 2 instead of dial 1 for accuratemeasurement. The resistance value canbe read from dial 2.

Checking and measuing capaci-tance. Using MGMA you can measurecapacitances from 0.001 µF to 5 µF. Firstcheck for the usability of the unknowncapacitor. Adjust dials 1 and 2 to read 50in the display. Now check the unknowncapacitor using SOC2 for unipolar orSOC4 for electrolytic/tantalum capacitorswith the inner and the outer terminals ofthe socket for positive and negative ter-minals of the capacitor. If there is nochange in the reading it means the ca-pacitor is shorted and a higher readingimplies it is good.

To find the value of an unknown non-electrolytic (unipolar) capacitor, connectthe same to SOC2. Adjust dials 1 and 2to read a number around 80 in the dis-play. Now, without disturbing the dialsinsert the known capacitors one by onein SOC2. The unknown capacitor value isequal to the value of the known capacitorfor which the display shows the samereading or near the number 80.

The procedure is same for electrolyticand tantalum capacitors, except thatSOC4 is to be used in place of SOC2, en-suring that the inner and the outer ter-minals of the socket are used for positiveand negative terminals of the capacitor,respectively.

Testing a diode. Rotate dial 1 tohigh-resistance position and adjust dial 2such that the display shows a flickering45. Test the diode in SOC3 using an ear-phone plug in the same manner as men-tioned earlier. Interchange the leads andtest again. A shorted diode will not makeany change in the reading, while a goodone gives a reading of around 60 and 90in both the tests. And for the open diode,the display shows 90 in both the tests.

While checking the diodes, a parallelresistance of 100k is required across thediode. Our body resistance may also do.

Other utilities. Heat alarm, firealarm, security alarm, strain gauge, in-truder alarm, rain alarm, number game,timer, and many other circuits can berealised using this MGMA circuit. ❏

Fig. 5: Proposed front-panel layout of MGMA

Fig. 6: Connections for water level monitor


RUPANJANA

light mode (in daytime). Thus it decidesthe mode of operation.

The circuit for four sides of trafficlights (Part II) also controls the time al-lowed for each side of traffic. It is further

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This circuit of an adjustable trafficand street light controller can con-trol the timings of four sides of

traffic lights separately. It can also con-trol the changeover from continuous traf-fic light mode to blinking yellow lightmode (at night), and from blinking yellowlight mode to continuous traffic light mode(during day). In addition, this circuit alsocontrols the automatic switching off/on ofthe streetlights in the mornings and eve-nings with flexible settings—defining themorning and evening time. In order toprevent false triggering of streetlight cir-cuitry due to some shadow or light on thesensor, some time delay is taken into con-sideration before sending the control sig-nal for streetlight operation. Its opera-tion does not require any software andhardware knowledge.

This circuit can also be adopted forsynchronisation with the signals of adja-cent traffic lights by introduction of ap-propriate delay in traffic light signals’ tim-ings.

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The circuit has two parts—the first forgeneration of control signals for streetlightand traffic light modes and the second forgeneration of four sides of traffic light sig-nals.

The circuit for streetlight and trafficlight modes (Part I) controls the switchingtime of streetlights in evenings and morn-ings and the time to changeover from con-tinuous traffic light mode to blinking yel-low light mode (at night), and from blink-ing yellow light mode to continuous traffic

classified into continuous traffic lightmode (for day) and blinking yellow lightmode (for night).

Part I Circuit. The block diagram ofthe circuit for signal generation forstreetlight and traffic light modes isshown above the dotted line in Fig. 1. Anatural light-dependent voltage and a ref-erence voltage, which determines theevening and morning times are connected

PARTS LISTSemiconductors:IC1 - LM358 op-ampIC2 - 7404 Hex invertersIC3, IC6, IC12 - NE555 timerIC4 - 74LS93 4-bit binary

counterIC5 - 74LS164 8-bit serial shift

registerIC7-IC9 - 7476 dual JK master-slave

flip-flopIC10 - 7400 Quad 2-input NAND

gatesIC11 - 7410 Triple 3-input NAND

gatesIC13 - 7408 Quad 2-input AND

gatesIC14-IC17 - 7402 Quad 2-input NOR

gatesT1-T6 - SL100 npn transistorD1-D14 - 1N4007 rectifier diodeLED1, LED3,LED6, LED9,LED12 - 3mm red LEDLED2, LED5,LED8, LED11 - 3mm green LEDLED4, LED7,LED10, LED13 - 3mm yellow LEDResistors (all ¼-watt, 5% carbon, unlessstated otherwise):R1, R2,R18-R21 - 2.2-kilo-ohmR3-R5, R8,R12-R17,R22-R25 - 100-kilo-ohmR6 - 47-kilo-ohmR7, R9, R11 - 10-kilo-ohmR10 - 100-ohmR26 - 47-ohmR27 - 22-kilo-ohmR28 - 6.8-kilo-ohmVR1, VR2,VR4-VR7 - 1-mega-ohm presetVR3 - 100-kilo-ohm presetVR8 - 10-kilo-ohm presetCapacitors:C1 - 220µ, 10V electrolyticC2, C4, C6 - 0.01µ ceramicC3, C5 - 6.8µ, 10V electrolyticMiscellaneous:LDR1S1 - Push-to-on switchFig. 1: Block diagram of traffic and street light controller

RAJESH GUPTA



Fig. 2: Schematic diagram for the traffic and street light controller



individually to the two inputs of a com-parator. Low and high states of the com-parator output decide morning andevening timings, respectively. The outputof comparator is properly delayed for ob-taining the signals for streetlight and traf-fic light modes.

In the detailed circuit diagram shownabove the dotted line in Fig. 2, a naturallight-dependent voltage is obtained at thejunction of light-dependent resistor LDR1and resistor R7. Resistor R6 is used inparallel with LDR1 to limit the variationof the LDR. Light-dependent voltage andvariable reference voltage are connectedto the inverting and non-inverting termi-nals respectively of comparator IC1(a).

In the evening, voltage at the invert-ing terminal of the comparator decreaseswith time due to the increasing resistanceof LDR1. At a particular natural light in-tensity (determined by variable referencevoltage, which can be adjusted with thehelp of preset VR8), it becomes less thanthe voltage at the non-inverting termi-nal. This drives the comparator into posi-tive saturation region. Similarly, in themorning the comparator goes into nega-tive saturation region at the same natu-ral light intensity. In this way, the com-parator gives high voltage (logic 1) forevening and low voltage (logic 0) for morn-ing.

IC1(b), with the non-inverting termi-nal biased at about 1/3rd Vcc, is simplyused as an inverter (though wired as com-parator). The inverted output of compara-tor IC1(a) is coupled to transistor T1through resistor R4, while its direct out-put is coupled to transistor T2 via resis-tor R5.

It is observed that transistor T1 iscut off in the evening and Vcc is appliedto pin 7 of timer IC3 (wired in astablemultivibrator mode) via resistor combi-nation RA1 (=R2+R3+VR1), while in themorning T2 is cut off and Vcc is appliedto pin 7 of IC3 via RA2 (=R1+R8+VR2).In other words, the time period of IC3 isdependent on RA1 from the evening andRA2 from the morning.

The diode pair of D1 and D2 or D4and D5 is used to effectively isolate pin 7of IC3 from being pulled towards groundvia the conducting transistor (T2 in theevening and T1 in the morning). Timeperiod of 555 clock in astable mode canbe determined from the following rela-tionship:

T = RA (C/1.44) + 2 RB (C/1.44)

where RA = RA1 from the evening andRA = RA2 from the morning, while RB =R9 = 10 kilo-ohm and C = C1 = 220 µF.Clock-1 output of IC3 is connected to 4-bit negative-edge-triggered counter74LS93 (IC4).

Period of output QD of IC4 is 16 timesthe clock-1 time period. This QD output(low for first eight clock-1 cycles and highfor the next eight clock-1 cycles, and re-peating thereafter) of IC4 is connected tothe clock input of an 8-bit (positive-edge-triggered) serial shift register 74LS164(IC5).

The output of IC1(a) forms the data(D) input for the shift register. The data(D) at QA output is available after eightclock-1 cycles, while that at QH is avail-able after 120 clock-1 cycles. Thus morn-ing/evening (low/high) data is availableat QA and QH outputs after 8 and 120clock-1 cycles, respectively. Note that theclock-1 period itself differs for morningdata and evening data.

Streetlight indicator (LED1) is con-nected to QA output of shift register IC5.The evening data (high) from comparatorIC1(a) passes to the streetlight after eightclock cycles of clock-1. This delay is takeninto consideration in order to prevent falsesignals to the streetlight due to someshadow or light on the sensor.

The delayed high QH output providesthe control signal for night to the secondpart of circuit and changes continuoustraffic light mode to blinking yellow lightmode. In this way the time at which nightfunctioning of traffic light starts can beadjusted by choosing appropriate time pe-riod for clock-1 by adjusting the value ofRA1. Similarly, the time at which day

functioning of traffic light starts (stopblinking yellow light mode and start con-tinuous traffic light mode) can be adjustedby RA2.

Low (delayed morning signal) andhigh (delayed evening signal) QH outputsgo to the second part of circuit for select-ing the mode of traffic light. Table Isummarises the functioning of the circuitfor signal generation for streetlight andtraffic light modes.

Part II Circuit. The block diagramof the circuit for signal generation for foursides of traffic lights is given below thedotted line in Fig. 1. Here, the 4-bit and2-bit counters are joined together to forma 6-bit counter. Outputs of the 2-bitcounter, representing two MSB digits, areconnected to a decoder that has two con-trol inputs and four outputs. The decoderactivates one of the four outputs depend-ing upon the input (00 or 01 or 10 or 11)of 2-bit counter.

Each output of the decoder can driveclock-2 at a different frequency. These fouroutputs are connected to the four sides oftraffic lights and select each side one af-ter another. The time in which the pre-ceding 4-bit counter counts from 0000 to1111 (16 counts) is the time allowed foreach side of traffic lights.

First, when the 4-bit counter countsfrom 0000 to 0001 (two counts), yellowlight of the selected side will turn ‘on’.From count 0010 to 1101 (12 counts),green light will turn ‘on’. Again from 1110to 1111 count (two counts), yellow lightwill turn ‘on’. Meanwhile, in the otherthree sides of traffic lights that are notselected by the decoder, red light will be‘on’. Similar operation will repeat for each

TABLE IFunctional Summary of Part I Circuit

Time Output Output at Output at Activated RA Street Trafficof IC1(a) QA of IC5 QH of IC5 Resistance Light Light

(LED1) ModeEvening HIGH LOW LOW RA1 OFF AAfter 8 cycles of clock-1 HIGH HIGH LOW RA1 ON A(Delay time for streetlight)After 120 cycles of clock-1 HIGH HIGH HIGH RA1 ON B(Delay time for night)Morning LOW HIGH HIGH RA2 ON BAfter 8 cycles of clock-1 LOW LOW HIGH RA2 OFF B(Delay time for streetlight)After 120 cycles of clock-1 LOW LOW LOW RA2 OFF A(Delay time for day)Evening HIGH LOW LOW RA1 OFF ADelay times and evening/morning times are adjustable.A: Continuous traffic light mode B: Blinking yellow light mode



Fig. 3: Actual-size, single-sided PCB for the circuit in Fig. 2




Thus the 6-bit counter will clear whenQH output is high or the reset button ispressed. The reset key, when pressed, alsocauses counter IC4 and shift register IC5of Part I to be cleared. QH output of IC5is connected to reset pin 4 of clock-3(IC12). The output of this clock is con-nected to inverter gate N4. Low QH (dur-ing day) activates the 6-bit counter anddeactivates clock-3. Due to this, the out-put of inverter gate N4 will be high dur-ing the day. This output is connected toone of the inputs of four AND gates H1through H4. Each of these AND gates isa part of one side of traffic light circuit.

NAND gates B1, B2, and B3 are con-nected to the outputs of flip-flops F2, F3,and F4 of the 6-bit counter. The final out-put of this circuit (the output of gate B2)will be high whenever the first four bitsof the counter are 1110 or 1111 or 0000or 0001 (14 or 15 or 0 or 1), otherwise itwill be low. Accordingly, inverter N5 out-put will be low for the above contents ofthe counter and high for the remainingcontents (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,or 13).

The output of NAND gate B2 and itscomplement (the output of inverter N5)are connected to NOR gates X2 (=E2, J2,K2, and M2) and X3 (=E3, J3, K3, andM3) of the each side of traffic light, re-spectively. Other inputs of X2 and X3NOR gates are common.

The last two flip-flops (F5 and F6) ofthe 6-bit counter are connected to fourNAND gates G1 through G4 in such away that the output of G1, G2, G3, andG4 will be low when last two counter bitsare 00 (0), 01 (1), 10 (2) and 11 (3), re-spectively. For example, when last twobits of counter contents are 01 (1), onlyoutput of NAND gate G2 will be low andothers (G1, G3 and G4) will be high.

The complements of these four NANDgate outputs (obtained from collectors oftransistors T3 through T6) are connectedto the four RA resistors of 555 clock-2.Other terminals of these four resistorsare connected to the anodes of diodes D8,D10, D12, and D14, while their cathodeterminals are all connected to pin 7 of555 clock-2 (IC6). This is analogous tothe fashion in which RA1 and RA2 havebeen connected in Part I in the clock-1circuit.

When last 2-bit counter contents are00, RA3 (=R21+R25+VR7) will become ac-tive and other three resistors RA4, RA5,and RA6 will become inactive. Therefore

of the selected side in its turn.Reset pin of clock-3 and clear pins of

the 6-bit counter are controlled by outputQH from IC5 of Part I. At night, QH will gohigh and the 6-bit counter will clear, whileclock-3 becomes active. As a result, yel-low lights of the four sides of traffic lightwill blink simultaneously.

The detailed circuit diagram is givenbelow the dotted line in Fig. 2. The ac-

tive-‘low’, clear input signal for the 6-bitcounter (formed by dual J-K flip-flopsinside IC7 through IC9) is providedfrom the output of NOR gate E1, whoseone input is connected to QH output ofshift register IC5 of Part I and the otherinput is connected to the output of in-verter gate N3. The input of invertergate N3 is connected to push-to-on resetswitch S1.

Fig. 6: The traffic and street light controller

Fig. 5: Connections for vehicular traffic lights and pedestrians’ signals



the time period of clock-2 of the 6-bitcounter will be dependent upon RA3.

Similarly, when last 2-bit counter con-tents are 01 or 10 or 11, the time periodof clock-2 will be dependent upon RA4(=R20+R24+VR6), RA5 (=R19+R13+VR5),and RA6 (=R18+R12+VR4), respectively.

The output of NAND gate G1 is con-nected to the common input of NOR gatesE2 and E3 of the first side of traffic lightand complements of the outputs of otherthree NAND gates G2, G3, and G4 areconnected to one of the inputs of NORgates J1, K1, and M1, respectively. Theother inputs of these NOR gates are con-nected to QH output of IC5. Red and greenlights are connected to the outputs of NORgates X4 (=E4, J4, K4, and M4) and X2(=E2, J2, K2, and M2), and yellow light isconnected to AND gate of each side of thetraffic light.

During daytime, the outputs of ANDgates (which are connected to yellowlights) will be the same as the outputs ofNOR gates X3(=E3, J3, K3 and M3) ofeach side, because one of the inputs ofAND gates is high in daytime. Low QH

(during daytime) forces NOR gates J1,K1, and M1 to work as the inverter gatefor the other inputs. Therefore the com-mon input of NOR gates X2 and X3 of

sides 1, 2, 3, and 4 will be the same asthe output of NAND gates G1, G2, G3,and G4, respectively.

Let us suppose that initially the con-tents of the 6-bit counter are 000000.When the counter counts up from 000000to 001111, the output of NAND gateG1 will be low and that of other NANDgates G2, G3, and G4 high. Due to this,RA3 will be active and the time period ofclock-2 of the counter will be accordingto RA3.

The high output of NAND gates G2,G3, and G4 forces the output from NORgates J2, K2, M2 and J3, K3, M3 to lowstate. These low outputs are input to NORgates J4, K4, and M4, due to which theoutput of these gates will be high. Itmeans yellow and green lights will be ‘off’and red light will be ‘on’ in the remainingthree sides of the traffic light.

Due to the low output of NAND gateG1 (which is connected to the commoninput of NOR gates E2 and E3 of firstside), the output of NOR gates E2 and E3of first side will depend on the output ofthe three-NAND gate circuit (comprisinggates B1, B2, and B3).

When the 6-bit counter counts from000000 to 000001, the output of the three-NAND gate circuit will be high, which is

connected to NOR gate X2 of each sideand its complement is connected to NORgate X3 of all sides. Due to this, the out-put of NOR gate E3 will be high and thoseof NOR gates E2 and E4 low. In short,during the count period 000000 to 000001yellow light of the first side of traffic lightand red light of the other three sides willbe ‘on’.

When the counter counts up furtherfrom 000010 to 001101, the output of thethree-NAND gate circuit will be low andits complement will be high. Due to thisreason, the output of NOR gate E2 willgo high and that of NOR gates E3 and E4low. Therefore, when counter contents in-crement from 000010 to 001101, greenlight of first side and red light of all theother sides will be ‘on’.

Again from 001110 to 001111, the out-put of three-NAND gate circuit will gohigh, due to which yellow light of firstside and red light of the other sides willturn ‘on’. The time in which the countercounts from 000000 to 001111 can be ad-justed by RA3. The functioning of theother three sides of the traffic light issimilar.

Daytime functional summary of thecircuit for signal generation for four sidesof traffic light is given in Table II. Changein RB resistance (VR3+R11) of clock-2,being common for all sides, will changethe time allowed for each side of trafficlight by an equal amount.

At night, QH output of IC5 will be high,due to which the 6-bit counter will clearand clock-3 will start working. The out-put of NOR gates J1, K1, and M1 andNAND gate G1, and the complement ofthe output of the three-NAND gate cir-cuit will be low. This forces the output ofNOR gate X3 of each side to high state.This high output will turn off all the redlights and give high signal to one of theinputs of AND gates H1 through H4. Theother input of these AND gates is con-nected to the complement of clock-3, dueto which all the four sides of yellow lightwill blink.

The four sides of traffic light signalscan be used for driving vehicular trafficsignals for straight, right, and left turnsand pedestrian’s signals. Fig. 5 showsone of such possible connections of vehicu-lar and pedestrian’s signals. The completecircuit in model form is shown in Fig. 6.Actual-size, single side PCB for the circuitshown in Fig. 2 is given in Fig. 3 with itscomponent layout in Fig. 4.

TABLE IIDaytime Functions of Part II Circuit

Counter Decoder output Activated RA Glowing LEDscontents G1 G2 G3 G4 resistance000000 - 0 1 1 1 RA3 4,6,9,12 (Yellow light of 1st side and000001 red light of other sides)000010 - 0 1 1 1 RA3 2,6,9,12 (Green light of 1st side and001101 red light of other sides)001110 - 0 1 1 1 RA3 4,6,9,12 (Yellow light of 1st side and001111 red light of other sides)010000 - 1 0 1 1 RA4 3,7,9,12 (Yellow light of 2nd side and010001 red light of other sides)010010 - 1 0 1 1 RA4 3,5,9,12 (Green light of 2nd side and011101 red light of other sides)011110 - 1 0 1 1 RA4 3,7,9,12 (Yellow light of 2nd side and011111 red light of other sides)100000 - 1 1 0 1 RA5 3,6,10,12 (Yellow light of 3rd side and100001 red light of other sides)100010 - 1 1 0 1 RA5 3,6,8,12 (Green light of 3rd side and101101 red light of other sides)101110 - 1 1 0 1 RA5 3,6,10,12 (Yellow light of 3rd side and101111 red light of other sides)110000 - 1 1 1 0 RA6 3,6,9,13 (Yellow light of 4th side and110001 red light of other sides)110010 - 1 1 1 0 RA6 3,6,9,11 (Green light of 4th side and111101 red light of other sides)111110 - 1 1 1 0 RA6 3,6,9,13 (Yellow light of 4th side and111111 red light of other sides)Note. The two MSB digits determine the side, while the next four digits determine the time forwhich the mentioned LEDs are ‘on’.



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Set preset VR8 in such a position that theoutput of comparator IC1(a) switches fromone state to the other at a particular in-tensity of natural light. Variable resistorsVR1 and VR2 can be calibrated on a timescale using the following relationships:

VR1 = (1/120) (1.44 TNight/220) 106 –(122.2) 103

VR2 = (1/120) (1.44 TDay/220) 106 –(122.2) 103

where TDay and TNight are delay times inseconds (time interval between switchingof comparator IC1(a) and when the traf-fic light switches its mode) correspondingto day and night, respectively.

Variable resistors VR4 through VR7can be calibrated on a time scale by thefollowing relationship:

VR (4,5,6,7) = (1/16)(1.44 T/6.8) 106 –(122.2) 103 – 2 VR3where T is the time allowed (in seconds)for the side of traffic light in which thecorresponding variable resistance is con-nected.

Possible enhancements. Steppermotor-driven wiper can be used for clean-

ing the dust over the light sensor duringnight time. Control signal for this can beobtained from the shift register.

Also, time-controlling variable resis-tors VR4 through VR7 of Part II can bereplaced by LDRs with a small lightsource whose light intensity varies accord-ing to the strength of traffic on each side.Implementation of this system requirestraffic-sensing sensors. This system will

change the time of each side of trafficlight according to the strength of traffic.

Further, the present circuit being onlya demonstration model uses LEDs forlights. To drive high-wattage lights, onecan easily boost the signals used for driv-ing the LEDs to operate solidstate orelectomechanical relays. ❏

The author is an M.Tech. from IIT, Delhi,and is currently pursuing his Ph.D studies.

October

2001

Circuit Ideas

2001


S.C. DWIVEDI ured as an astable multivibrator to pro-duce rectangular clock pulses for IC5,while NAND gates N1 and N2 generate

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ELECTRONICS FOR YOU� ❚❚❚❚❚ �OCTOBER 2001

The circuit presented here can beused to control the speed of fansusing induction motor. The speed

control is nonlinear, i.e. in steps. Thecurrent step number is displayed on a7-segment display. Speed can be variedover a wide range because the circuit canalter the voltage applied to the fan motorfrom 130V to 230V RMS in a maximumof seven steps.

The triac used in the final stage isfired at different angles to get differentvoltage outputs byapplying short-dura-tion current pulses atits gate. For this pur-pose a UJT relax-ation oscillator isused that outputssawtooth waveform.This waveform iscoupled to the gate ofthe triac through ano p t o c o u p l e r(MOC3011) that hasa triac driver outputstage.

Pedestal voltagecontrol is used forvarying the firingangle of the triac.The power supply forthe relaxation oscilla-tor is derived fromthe rectified mainsvia 10-kilo-ohm, 10Wseries dropping/limit-ing resistor R2.

The pedestalvoltage is derivedfrom the non-filteredDC throughoptocoupler 4N33.The conductivity ofthe Darlington pairtransistors insidethis optocoupler isvaried for getting thepedestal voltage. Forthis, the positive sup-ply to the LED insidethe optocoupler is

the active-low count enable (CE) input us-ing either of push-to-on switches S1 or S2for count up or count down operation, re-spectively, of the BCD counter.

Optocoupler 4N33 electrically isolatesthe high-voltage section and the digitalsection and thus prevents the user fromshock hazard when using switches S1 andS2. BCD-to-7-segment decoder CD4543 isused for driving both common-cathode andcommon-anode 7-segment displays. Ifphase input pin 6 is ‘high’ the decoderworks as a common-anode decoder, and ifphase input pin 6 is ‘low’ it acts as acommon-cathode decoder.

connected via different values of resistorsusing a multiplexer (CD4051).

The value of resistance selected by themultiplexer depends upon the control in-put from BCD up-/down-counter CD4510(IC5), which, in turn, controls forward bi-asing of the transistor inside optocoupler4N33. The same BCD outputs from IC5are also connected to the BCD-to-7-seg-ment decoder to display the step numberon a 7-segment display.

NAND gates N3 and N4 are config-

SUNIL P.B.



Optocoupler 4N33 may still conductslightly even when the display is zero,i.e. pin 13 (X0, at ground level) is switched

to output pin 3. To avoid this problem,adjust preset VR1 as required using aplastic-handled screwdriver to get no out-

put at zero reading in the display.


other audio device as well.When the preamplifier is in ‘off’ state,

switching relay RL1 is off and it allowsconnection of external signals to the soundcard. When the preamplifier is turned ‘on’,the relay is energised by transistor T3
UNIL KUMAR
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S

Here is a stereo tape head pream-plifier circuit for your PC soundcard that can playback your

favourite audio cassette through the PC.Audio signals from this circuit can be di-

rectly connected to the stereo-input (line-input) socket of the PC sound card forfurther processing.

The circuit is built around a popularstereo head preamp IC LA3161. Weakelectrical signals from the playback headsare fed to pins 1 and 8 of IC1 via DCdecoupling capacitors C1 and C6, respec-tively. Components between pins 2 and 3and pins 6 and 7 provide adequateequalisation to the signals for a normaltape playback.

The amplified and equalised signalsavailable at output pins 3 and 6 of IC1are coupled to the inputs of line amplifiercircuit built around transistors T1 (via ca-pacitor C5, potmeter VR1, resistor R8, and

capacitor C12) and T2 (via capacitor C10,potmeter VR2, resistor R19, and capaci-tor C16), respectively. Left and right play-back levels can be adjusted by variableresistors VR1 and VR2. The audio signalsare finally available at the negative endsof capacitors C13 and C17.

The circuit wired around relay drivertransistor T3 serves as a simple sourceselector. This is added deliberately to helpthe user share the common PC sound cardline-input terminal for operating some

after a short delay determined by the val-ues of resistor R21 and capacitor C23. Onenergisation, the relay contactschangeover the signals to internal source,i.e. the head preamplifier.

After constructing the whole circuiton a veroboard, enclose it in a mini me-tallic cabinet with level controls and sock-

ets at suitable points. Use a regulated1A, 12V DC power supply for poweringthe whole circuit including the tape deckmechanism. (A 1A, 18V AC secondarytransformer with 4700µF, 40V electrolyticcapacitor and 78M12 regulator is suffi-cient.)

You can use any kind of tape deckmechanism with this circuit. Use of good-quality playback head and well-screenedwires are recommended.

T.K. HAREENDRAN


S.C. DWIVEDI

XOR gate that can be used both as aninverting and a non-inverting gate by ty-ing any one of the XOR gate inputs highand low, respectively (refer the table).

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This four-channel, two-mode lightchaser circuit produces effects ofrunning holes and running lights.

Each effect, i.e. running lights or running

holes, is repeated five times. Applicationsinclude decorating photographs usingLEDs or driving 230V bulbs via triacs.

Fig. 1 shows the circuit for drivingthe bulbs using triacs, while Fig. 2 is amodification of Fig. 1 for driving LEDswithout using triacs.

In Fig. 1, timer 555 is used as an

VIJAYA KUMAR P.

astable multivibrator for generating clocksignals for decade counter CD4017 (IC2).The speed of running lights can be variedusing preset VR1. CD4030 (IC3) is a quad

For every fourth clock to IC2, its pin7 goes high, which, in turn, clocks IC4.Since the first five outputs of IC4 areconnected together (wired ORed) usingdiodes D3 through D7, the output atthe tied end remains high for every fiveclock pulses at IC4. This output is coupledto one of the inputs of all the four XOR



gates.When the output of IC4 (Q) goes

high, the outputs of IC2 get inverted and

produce the running hole effect. And whenthe output of IC4 (Q) goes low, XOR gatesact as non-inverters and the outputs of

IC2 remain as original and produce therunning light effect.


S.C. DWIVEDI
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PRADEEP G.

Here is a simple and low-cost cir-cuit of heart beat monitor usingreadily available components. It

uses the piezo-electric plate of audiblepiezobuzzers as the sensing device, whichcan be purchased for around Rs 2 onlyfrom component vendors.

The sensor is pressed against humanbody near the heart region. It should makea solid contact with your palm to convertheart beat sound into low-frequency elec-trical variations. These electrical varia-tions are amplified by transistor T1 thatis configured as a common-emitter ampli-fier. Amplified signals are coupled to tran-sistor T2 for driving the audio power am-plifier stage. The speaker reproduces heart

beat notes as audible sound.The two BEL188 silicon transistors

used in the power output stage are freelyavailable. In case you use AC188/128 ger-manium transistors in place of BEL188silicon transistors, replace 220-ohm resis-tors with 47-ohm resistors and 680-ohmresistors with 1-kilo-ohm resistors.


S.C. DWIVEDI

mA (which can be increased to severalamperes with additional pass transistors),output short-circuit protection, and lowerinput voltage.

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D. PRABAKARAN A low power dissipation is achievedby driving external series-pass transistor2N4241 (T1) from pin 2 of CA3085. Nor-mal output pin 8 is returned to groundvia diodes D3 and D4 to ensure error am-plification operation in the linear region.Ripple rejection is approximately 50 dBon no load and 35 dB on full load.

A 2x2x2.5cm aluminium heat sink fas-tened onto a 1.5mm blackened aluminiumsheet of 12.5cm2 area on 2N4241 helpsthe circuit in dissipating heat without ex-ceeding maximum device ratings.

CA3085 can dissipate up to 650mWpower in free air, without any heat sink.AFCO-make C-05-4 heat sink is suitablefor this IC. An improper heat sink maycause device junction temperature to ex-ceed the limit, resulting in progressivedeterioration of the device.

This circuit provides a 12V regu-lated power supply with outputcurrent up to 3 amperes. It is spe-

cially designed for use with 2m handheldrigs with linear power amplifier and CB

portable QRP rigs.The circuit uses monolithic IC CA3085

voltage regulator in 8-lead TO-5 package.Its salient features include good load andline regulation, output current up to 100


S1 as per base current requirement forthe transistor. Two different coloured(green and red) LEDs are used for indi-cation.

Green LED glows if the npn transis-tor under test is good, otherwise not. Like-

S.C. DWIVEDI

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J. BALAJI

This simple-to-construct circuit isuseful for testing both npn andpnp low-power transistors. It com-

prises a few resistors, LEDs, diodes, anda mains step-down transformer.

The 230V mains voltage is steppeddown to about 6 volts before applicationto the circuit. The leads of transistor un-der test are inserted in the test terminals(sockets) marked E, B, and C (for emit-ter, base, and collector, respectively) ap-propriately, i.e. the emitter of thetransistor is to be inserted in terminal E,the base of the transistor in terminal B,and the collector of the transistor in ter-minal C.

The resistor to be connected in serieswith the base terminal is selected withthe help of a 6-position rotary switch

wise, when a pnp transistor is tested, theglowing of red LED indicates that the

transistor is good and no glowing indi-cates that the transistor is bad.

Construction

2001


is automatically selected at successive dif-ferent battery terminal voltages. And whenthe battery gets fully charged, the chargerswitches over to trickle-charge mode.

The circuit consists of the followingsections:

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SUNIL KUMARM.K. CHANDRA MOULEESWARAN

High-power lead-acid battery char-gers usually employ constantvoltage charging method. In such

chargers the charging is monitoredagainst the battery terminal voltage. Con-stant voltage at a constant current re-sults in a very large initial current in a‘flat’ battery and a very low current in apartially charged battery. To overcomethis problem, the charger should be madeto vary the charging current in accordance

with the existing terminal voltageof the battery.

In the circuit presented herethe charging current is adjustedagainst the terminal voltage in sucha way that any battery with anylevel of charge can be connected tothe charger without requiring anymanual adjustment. The chargingvoltage is held constant, while anappropriate charging current range

1. The DC power supply section.

Fig. 1: Schematic diagram of lead-acid battery charger

Fig. 2: Charging current versus battery terminalvoltage



four 15-kilo-ohm resistors R1, R2 and R3,R4 in the path of LED1 and LED2, respec-tively, are rated at 1 watt each.

The output from the secondary oftransformer X1 is rectified by the bridgerectifier comprising 1N5408 diodes D3through D6, rated at 800V, 3A. The recti-fied output is smoothed by three capaci-tors C1, C2, and C3 before being appliedto the rest of the circuit. The 4.7-kilo-ohmresistor R6 acts as a bleeder resistance.LED7 indicates that DC is available atthe output of this section.

The series DC voltage regulationsection. This section is configured aroundpower Darlington transistor TIP142 (T1)that functions in conjunction with tran-sistor T3 (BC549) and preset VR2 to regu-late the output voltage from the DC volt-age regulator section.

Since zener diode ZD1 conducts onlyafter the output voltage reaches 15 volts,the output voltage needs to be adjustedin the vicinity of 15 volts with the help ofpreset VR2. When transistor T3 conductsfully, the base of transistor T1 is pulled

towards ground via resistor R8 andit stops conducting after the outputvoltage exceeds a specific value.

Transistor T2 (also a BC549)helps in current limit adjustments.Low-value, high-wattage resistorsR15 (shunted by R14) through R19connected in series form a current-limiting resistor network at the out-put of transistor T1. This resistornetwork limits the charging currentdepending on the energisation/de-energisation state of relays RL1through RL4 that select the cur-rent range. The resistors are eithershorted or added by respective re-lay contacts RY1 through RY4 de-pending on the charging current re-quirement from the regulator.

The battery status indica-tion-cum-charge current regula-tion section. In this circuit, a quadop-amp LM324 (IC1) is wired as afour-stage comparator to indicatethe battery voltage with the help offour LEDs (LED3 through LED6),while at the same time selectingand driving corresponding relays toset the charging current range.

The 6.8V reference voltage de-veloped across zener diode ZD2 isproportionately applied to the in-verting terminals of comparators A1through A4, while the sampled bat-tery voltage is proportionately ap-plied to the non-inverting terminalsof all the comparators.

Preset VR3 may be adjusted toobtain the reference voltages asshown in Fig. 1. Preset VR4 may beadjusted by applying an externalfixed voltage of 10.5V, 11.5V, 12.5V,or 13.5V across the battery’s screwterminals, ensuring that the corre-sponding LEDs (and relays) lightup (energise) in accordance with thetable.

2. The series DC voltage regulationsection.

3. The battery status indication-cum-charge current regulation section.

The DC power supply section. The230V AC mains supply is connected to astep-down transformer with a secondaryrating of 24V AC, 5A through DPDT toggleswitch S1. When switch S1 is in ‘off’ posi-tion, the availability of mains supply isindicated by green LED1. When switch S1is toggled to ‘on’ position, red LED2 glowsto indicate that the charger is ‘on’. The

Fig. 3: Actual-size, single-sided PCB for battery charger




In the charge characteristic curve ofFig. 2, it can be seen that the terminalvoltage is compared by the comparators

against the preset values and the charg-ing current is selected accordingly. Thusa battery of any charge level can be con-nected and left unattended under the con-trol of this charger circuit.

When the battery is flat with termi-nal voltage below 10.5 volts, the initialcharging current is selected at just oneampere because a higher initial chargingcurrent may cripple both the battery andthe charger. A higher charging current is

PARTS LISTSemiconductors:IC1 - LM324 quad op-ampT1 - TIP142 power Darlington

transistorT2, T3 - BC549 npn transistorT4-T7 - 2N2222A npn transistorD1, D2,D7-D11 - 1N4007 rectifier diodesD3-D6, D12 - 1N5408 rectifier diodesLED1 - Green LEDLED2 - Red LEDLED3 - Bright yellow LEDLED4, LED5 - Bright green LEDLED6, LED7 - Bright red LEDZD1 - 15V, 1W zener diodeZD2 - 6.8V, 1W zener diodeCapacitors:C1, C2 - 2200µF, 40V electrolyticC3 - 1000µF, 40V electrolyticC4 - 470µF, 25V electrolyticC5 - 100nF ceramicResistors (all ¼-watt, ±5% carbon unlessstated otherwise)R1-R4 - 15-kilo-ohm, 1WR5 - 2.2-kilo-ohmR6 - 4.7-kilo-ohm, 0.5WR7, R10, R12 - 1-kilo-ohmR8 - 100-ohmR9 - 470-ohmR11 - 4.7-kilo-ohmR13 - 47-ohmR14-R15 - 0.66-ohm, 3W wirewound or

fusibleR16 - 0.67-ohm, 3W wirewound or



fusibleR19 - 1.0-ohm, 1W wirewoundR20-R23 - 470-ohm, MFR 0.5% or 0.1%R24 - 820-ohm, MFR 0.5% or 0.1%R25 - 10-kilo-ohm, MFR 0.5% or

0.1%

selected only when the battery hasreached a safe level of terminal voltage.

Later, as the battery starts chargingand its terminal voltage starts rising, thecharging current is decreased in propersteps. Upon reaching the full voltage of13.5 volts, the charger switches to thetrickle charge mode with resistor R19coming into the charging path. Option-ally, one can switch off the charger onenergisation of relay RL4 by just remov-ing resistor R19 from the circuit. When-ever the terminal voltage level of the bat-tery goes low, the charger automatically

resumes charging.Figs 3 and 4 show the actual-size,

single-sided PCB and the component lay-out, respectively, of the charger circuit.

Note. To ensure proper functioningof the circuit, use good-quality relays andprecise-value resistors (R14 through R24)with tolerance as mentioned in the PartsList. Connect the metal housing of thecharger circuit to the earth line of the ACmains supply for personal safety. ❏

TABLELED/Relay Operation and Charging Resistance

Battery LED/Relay status Charging Presetvoltage LED3 LED4 LED5 LED resistance current

/RL1 /RL2 /RL3 /RL4<10.5V Off Off Off Off 1 ohm 1A10.5V On Off Off Off 0.33 ohm 3A11.5V On On Off Off 0.53 ohm 2A12.5V On On On Off 1 ohm 1A13.5V On On On On 2 ohms 0.5A** 0.5A is taken as the trickle charging current.

R26-R28 - 1.2-kilo-ohmR29 - 1.5-kilo-ohmVR1-VR2 - 2.2-kilo-ohm presetVR3 - 10-kilo-ohm presetVR4 - 15-kilo-ohm presetMiscellaneous:RL1-RL4 - 24V DC, 500-ohm relay

contacts at 10A DCX1 - 230V AC primary to 0-24V,

5A secondary transformerS1 - DPDT toggle switchF1 - 750mA cartridge glass fuse


PANJANA

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Motorola’s 4MHz 68HC705P6A (IC1) has21 input/output lines, including eight linesof port A (PA0 through PA7), eight linesof port C (PC0 through PC7), three lines

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of port B (PB5 through PB7), and twolines of port D (PD5 and PD7).

Fig. 1 shows the complete clock cir-cuit. The 12V DC power supply is providedto the input of 3-terminal LM7805 (IC2)regulator using external AC/DC adaptor.IC2 converts any unregulated DC voltagebetween +9V and +12V to stable +5V,which is fed to all the ICs on the board.

The +5V Vdd supply to 28-pin DIP

In most applications, a microcontrollerunit (MCU) can satisfy all systemrequirements with no additional

integrated circuits. Due to their lowcost and a high degree of flexibility, newpowerful MCUs are finding way into

many applications that were previouslyaccomplished by mechanical means orby combinational logic. One such applica-tion is digital clock using Motorola’sMC68HC705P6A that has been describedhere.

A.P. PHATAK AND P.W. DANDEKAR

Fig. 1: The microcontroller-based digital clock circuit



on page 47 in April ’97 and caller-IDproject in April ’99 EFY issues.)

Port-D line PD5 is connected to strobe(/clock) input pin 11 of latch 74LS374.Whenever PD5 line makes a low to hightransition, the contents on data input pins3, 4, 7, 8, 13, 14, 17, and 18 are latched tooutput pins 2, 5, 6, 9, 12, 15, 16, and 19 ofoctal latch IC3. The output of the latchcorresponding to PA1 input available atpin 5 of IC3 is fed to open-collector in-verter gate N3 of IC4. The output of N3drives a piezobuzzer to provide an audioindication. Thus the buzzer can beswitched on or off by the software. (Note.Octal latch IC3 was originally intendedfor operating a number of relays. How-ever, since we are presently using IC3 forlatching only a single input (PA1 signalfrom MCU) by taking strobe pin 11 fromlow to high, readers may replace IC3 byany simpler latch circuit, if desired).

Key switches S1 through S3 are con-nected between scan column line PA0 andthree scan return rows PC0 through PC2as follows:Time key (S1) Between PA0 and PC0Store/up key (S2) Between PA0 and PC1Down key (S3) Between PA0 and PC2

Each of the three inputs PC0, PC1,and PC2 has a 33-kilo-ohm pull-up resis-tor connected between these pins and Vcc,which ensures that the input to the portis set to 1 when not in use.

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MC68HC705P6A doesn’t have any stan-dard clock output. Therefore we are gen-erating an interrupt every 125 ms usingthe inbuilt capture/compare capabilitiesof timer inside MC68HC705P6A.

The 16-bit free running counter (FRC)rolls over every 262,144 internal clockcycles. Its resolution with a 4MHz crystalis 2 µs. Whenever the value of FRC matchesthe value written in output compare regis-ter (OCR), an interrupt is generated.

On entry to relevant interrupt serviceroutine (ISR), timer registers are re-initia-lised so that the timer will generate thenext interrupt after current time+125 ms.

To generate a timer interrupt every125 ms, we need to have a count differ-

IC1 is given at pin 28 and pin 14 isgrounded. A 4MHz crystal is connectedto the internal oscillator across pins 26and 27. R4-C1 combination provides thenecessary slowly rising power-on-reset sig-nal. It is double buffered through two in-verter gates of 7406 (IC4) connected incascade to generate an active-low power-on-reset (PONRST) signal that is con-nected to pin 1 of IC1.

PA0 through PA7 lines form an 8-bitbidirectional data bus that is routed tothe following destinations:

• LCD data lines D0 through D7.• Latch 74LS374 (IC3) inputs D0

through D7 (only PA1 from IC1 is pres-ently made use of).

• Scan columns for switch matrix(only PA0 is presently made use of).

Port-B lines PB6 and PB7 are usedas control lines. PB6 goes to register-se-lect (RS) input. PB6 and PB7 control sig-nals decide the data transfer from IC1 toLCD module and whether destination ofD0 through D7 inside the module is dataregister or control register.

Since pin 5 (R/W) is connected toground, LCD module is always in ‘write’mode. Thus whenever E line goes fromlow to high, data present at D0 to D7input lines is stored in the designated reg-ister inside the display module. (EFY Labnote. For more information and instruc-tion set of LCD module, refer the article

Fig. 2: Flow-chart for timer interrupt

continued...

Fig. 3(a): System flow-chart



ence of 62,500 between the OCR and theFRC, so that this count multiplied by 2 µsper count produces a delay of 125,000 µsor 125 ms. This is achieved by capturingthe current value of the FRC and adding62,500 to it. The carry is ignored and thesum is stored in the OCR. The FRC rollsover and hence the sum without carryensures that the difference is maintained.

The ISR maintains four differentcounters as follows:Name Range Frequency of incrementTIME 0-7 Every 125 millisecondsSS 0-59 Every secondMM 0-59 Every minuteHH 0-23 Every hour

In case ‘Time’ counter has become 8,it rolls over to 0 and seconds counter (SS)is incremented. In case, SS becomes 60,it rolls over to 00 and minutes counter(MM) is incremented. When MM reaches60, it rolls over to 00 and hours counter(HH) is incremented. When HH becomes24, it is reset to 00. If the outcome is NOin any of these four comparisons for limitchecking, the control exits from the ISR.

Fig. 2 shows the flow-chart for inter-rupt subroutine called ISR_OCR.

The ISR sets four flags, namely,125ms time over, 1-second time over, 1-minute time over, and 1-hour time over,

in ‘Flagloc’ memory location. These flagsare set when the corresponding time pe-riod is over, as indicated by rolling overof the previous counter in the chain. Thesemay be used in background programs likeMain routine to test and initiate periodictime-triggered functions.

System flow-chart (Fig. 3). Imme-diately after switching on the equipment,the system is initialised and the LCDstarts showing time in HH:MM:SS for-mat. Since no time is set, the displaywill start from 00:00:00. The user can setany time by pressing ‘time’ key.

On pressing ‘time’ key, the displayshows ‘SET MIN HH:MM:SS,’ whereHH:MM:SS will normally be 00:00:00 onpower-on-reset that start incrementing.You can set the value of minutes by us-

ing ‘up’ and ‘down’ keys.Every closure (followed by release) of

‘up’ key causes the minutes’ value to beincremented by one, while the closure of‘down’ key (followed by release) causesthe minutes’ value to be decremented byone. After you are satisfied with the valueof minutes, press ‘time’ key once again.

The unit responds by showing ‘SETHOUR HH:MM:SS’ on the LCD. Just likeminutes, you can now set the value ofhours using ‘up’ and ‘down’ keys. Afteryou’re satisfied, press ‘time’ key once again.

This causes the unit to display ‘TIMESET HH:MM:00,’ where the seconds areautomatically set to 00.

In all key closures, it is the key re-lease operation that acts as the workingedge or trigger. Thus the actions are un-

Fig. 4: Actual-size, single-sided PCB layout for the circuit in Fig. 1


contd...

Fig. 3(b): System flow-chart



dertaken by the unit when a key ispressed and then released, and not im-mediately after the key is pressed.

After one minute, the ‘TIME SET’message is cleared and only the time isdisplayed.

The program shown in the flow-chartis an infinite loop, as the system is de-signed to work continuously.

� ��

The complete software is assembled andtested using WINIDE (Windows-based in-tegrated development environment) thatallows seamless integration of several dif-ferent program modules into one devel-opment environment. Its ‘edit’ utility isused to create the assembly file (.Asm) intext mode.

The .Asm file is created only whenthere are no errors and produces two fileswith extensions, namely, .Lst and .S19. The .Lst is a listing file in text mode thatincludes variable, addresses, code, etc. The.S19 file contains information relating toaddress, code/data, start and termination

Col.(Retd.) A.P. Phatak is professor inelectronics & telecommunications and P.W.

Dandekar is vice pesident at ImpetusComputing, Indore

PARTS LISTSemiconductors:IC1 - 68HC705P6A Motorola

microcontrollerIC2 - LM7805 regulator +5VIC3 - 74LS374 octal latchIC4 - 7406 hex inverter (open-

collector)D1 - 1N4001 rectifier diodeResistors (all ¼-watt, ±5% carbon unlessstated otherwise):R1 - 4.7-mega-ohmR2, R3 - 10-kilo-ohmR4-R7 - 33-kilo-ohmVR1 - 2-kilo-ohm presetCapacitors:C1, C6 - 10µF, 16V electrolyticC2 - 0.22µ ceramic diskC3 - 1µF, 16V tantalumC4, C5 - 33pF ceramic diskC7 - 10µF, 35V electrolytic

Miscellaneous:LCD - LCD module (16 characters

x 1 row)Pz1 - PiezobuzzerS1-S3 - Tactile switchXTL - 4MHz quartz crystal

- 9 -12V, 200mA supplysource

of program which is used by the WINIDEfor programming the OTPROM/EPROMinside the microcontroller.

The WINIDE has an inbuilt simulatorthat can be used to test various sub-rou-tines and logic. After testing the softwareoffline, hardware tests are carried out.

Source code. The complete code alongwith detailed comments is given indigclock.asm file. (EFY note. Thedigclock.asm file, along with .Lst and.S19 extensions, will be included in thenext month’s EFY-CD.)

The software routines to convert bi-nary numbers to binary-coded decimal(BCD) numbers and activate LCD and au-dio indicators are included in the code,but have not been explained as these arebeyond the scope of this article.

The actual-size, single-sided PCB forthe digital clock is shown in Fig. 4 withits component layout in Fig. 5. ❏

November

2001

Circuit Ideas

2001


high, transistor T1 goes off and its out-put at the collector goes low. Since theemitter of transistor T2 is connected tothe collector of transistor T1, and collec-tor and emitter terminals of transistorsT1 through T9 are connected in series,

S.C. DWIVEDI
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ELECTRONICS FOR YOU� ❚❚❚❚❚ �NOVEMBER 2001

T he circuit described here uses low-cost and easily available ICCD4017 to produce a speller type

light display. In such displays, each let-ter of the sign sequentially lights up, oneafter the other, until all letters are glow-ing. After a few seconds, the letters switchoff and the cycle repeats. This circuit pro-vides a maximum of nine channels andtherefore can be used to spell a word orsign having up to nine characters.

Timer IC1 (555) is configured in

astable mode to produce clock signal fortriggering IC2 (CD4017). Speed of switch-ing on the display can be controlled byvarying preset VR1.

CD4017 is a decade counter havingten outputs, of which one output is highfor each clock pulse. However, this pro-duces running lights effect. To change thissequence to get the speller effect, pnptransistors T1 through T9 are wired asshown in the figure. Nine triacs (triac 1through triac 9) are used to drive 230Vbulbs. (In place of 230V bulbs, miniaturelamps connected in series in the form ofcharacters or letters can also be used, pro-vided the voltage drop across the series

combination is 230 volts.)When any of the outputs of IC2 goes

high, the corresponding transistor con-nected to the output goes off. When Q0 is

all transistors next to transistor T1, i.e.transistors T2 through T9, do not get sup-ply and hence all their outputs go low.

Next, when Q1 output goes high, tran-sistor T2 goes off. Thus outputs of tran-sistors T2 through T9 remain low. SinceQ0 output at this instant is low, transis-tor T1 is forward biased and its outputgoes high to light up the first character.

Similarly, when Q2 output goes high,Q0 and Q1 outputs are low and thereforeoutputs of transistors T1 and T2 go highto light up the first and second characters.

This process continues until all tran-sistors turn on, making all the characters

to light up. The cycle repeats endlessly,producing the speller type light effect.

VIJAYA KUMAR P.


UNIL KUMAR A tone signal is generated by transis-tor T2 and R-C coupled phase-shift oscil-

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S

The timer circuit described here pro-vides a pleasant musical tone inyour darkroom at 1-second inter-

vals. The circuit takes up very little spaceand can be easily converted into a metro-nome.

Unijunction transistor (UJT) T1 func-tioning as a relaxation oscillator triggers

the phase-shift audio oscillator circuitbuilt around transistor T2, turning it onand off. As capacitor C1 is chargedthrough preset VR1 and resistor R1, theemitter voltage of UJT rises toward thesupply voltage.

When theemitter voltagebecomes suffi-ciently positive,the emitter be-comes forward bi-ased and dis-charges capacitorC1 through theemitter-base 1(B1) junction andresistor R2. Thevoltage dropacross R2 forwardbiases transistorT2 and turns iton. As capacitorC1 becomes dis-charged, the cur-rent through re-

sistor R2 drops and transistor T2 is cutoff.

lator. Part of the signal taken from thecollector of transistor T2 is coupled to asmall speaker through a transistor-radiotype output transformer.

The 22-kilo-ohm value of resistor R3represents a compromise between tone du-ration and intensity. You can use resis-tors having a value anywhere between 10kilo-ohms and 25 kilo-ohms for differentdurations and intensities of the outputsignals.

Since the unijunction transistor isfunctioning as the oscillator trigger,changing the values of one or more com-ponents in the UJT circuit will changethe rate of the tone burst. The tone fre-quency can be varied by changing thevalue of any or more of capacitors C2through C4 and resistors R5 and R6 inthe phase-shift network.

The primary winding of transformerX1 can be tuned for a slight increase inthe output, using capacitor values be-tween 0.05 and 0.25 µF for C5 by trial-and-error method. Tone pulses should be-gin about ten seconds after the unit isturned on. After a minute or so, adjustpreset VR1 for 1-second beats by compar-ing the timing of the beats with the sec-onds needle on your wristwatch.

D. PRABAKARAN


S.C. DWIVEDI
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Practicing target shooting using areal gun is both expensive andrisky. Also, it is not possible for

everybody to have a gun. The circuit pre-sented here makes you feel the excite-ment of shooting a target situated at a

distance of more than 100 metres with-out any risk or much expenditure.

The circuit simply uses a laser pointer(also referred to as laser torch) as thetransmitter at the gun end. Laser point-ers can reach a maximum of 1 kilometredistance but it is advisable to limit therange within, say, 200 metres.

While constructing the gun no changehas to be made in the readymade pointer.Just tightly fit the pointer inside the toygun, so that the triggering switch can ac-tivate the press-to-on button of the laserpointer, as shown in Fig. 1.

The receiver comprises a counter-cum-7-segment display driver IC (CD4033)with a debouncer formed by 555 timerand an LDR sensor at the input. Thecounter works as a scoreboard and directlyshows the number of successful hits.

The LDR senses the pointer’s laserbeam and activates the monostablemultivibrator wired around 555 timer IC.To increase the sensitively of the receiver,the LDR current is amplified by transis-tors T1 and T2. The timer pulse-width isset at around 100 milliseconds so as towork as a debouncer. The timer output iscoupled to IC CD4033.

CD4033 is a serial decade counter-cum-7-segment decoder/driver. With ev-ery output pulse from monostable IC1,the count in CD4033 gets incremented byone. Thus the output of IC2 reflects thelatest score by a competitor. Pressing re-set switch resets the display too.

You can increase the size of thedisplay board manyfolds using the addi-tional circuit shown in Fig. 3. This mul-

PRATAP CHANDRA SAHU



tiplexed board avoids higher powerconsumption and is necessary if you areusing the module for long-range shoot-ing.

For each segment, you can wire up toten LEDs in parallel. Short the anodes ofLEDs of all segments as it is a common-anode type display. (The output fromULN2003 will be active-low.)

For proper functioning of the receiver,the LDR should be kept covered in sucha way that no external light falls on it.Further, the receiver should be fixedat least two metres from the ground sothat the laser beam is accidentally notdirected towards anybody’s eyes. Thegame can be played both in daylight aswell as at night.

Caution. Never look or stare at thebeam source and do not bounce the beamon a mirror.


ries with positive supply rail, along witha bypass capacitor to the ground, is rec-
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S.C. DWIVEDI

The circuit presented here boostsweak shortwave signals so thatthese can be heard with enhanced

clarity over a shortwave receiver. Further,the receiver doesn’t require any physicalconnection as its placement in the vicin-ity (within 6 to 7 cm) of the circuit willsuffice. The circuit works well over a widerange of supply voltage from 3 volts to 12volts.

Low-noise transistor T1 (BF494 orBF495) is connected as shown in the fig-ure. Resistor R1 gives the DC bias to T1.R1’s value may lie anywhere between l00kilo-ohms and 22 kilo-ohms; it determinesthe quiescent base-emitter current fortransistor T1. Resistor R2 limits the cur-rent flowing through transistor T1 and,in conjunction with capacitor C2, deter-mines the operating point for its stable

ommended for reducing signal loss in thepower supply.

The current consumption is well be-low 10 mA. The transistor works well atmaximum supply and so reduction of re-sistor R1’s value below 22 kilo-ohm is notrecommended, as otherwise the transis-tor may burn off.

This circuit works satisfactorily forboosting signals in 13m-49m band. How-ever, as the frequency increases, its per-formance deteriorates. The same happenswhen the frequency decreases below thatof the shortwave range. For input use along wire as the antenna, while the out-put antenna wire may be limited to about30 cm.

Note. The circuit is prone to self-oscillations if the aerial (input) wire picksup stray radiations from the power sup-ply wires or from the output. So keep thepower supply and output wires well iso-lated from the input.

operation.The number of turns in inductor L1

would have to be reduced as operationarea shifts towards the upper end of thehigh-frequency band. A 180µH RFC in se-

PRAVEEN SHANKER


S.C. DWIVEDI
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Here is a simple power supply cir-cuit that can be used for citi-zen-band and VHF walkie-talk-

ies of power rating up to 10 watts. Thecircuit uses a step-down transformer, fol-lowed by bridge rectifier, filter, regula-tor, and current booster stages.

A pnp power transistor is added tothe circuit to increase its current sourc-ing capabilities. Regulator 7812 can sup-port around 100 mA current. When thecurrent flowing through R1 nears 100mAvalue, the voltage (>0.65V) across theemitter-base junction makes transistor T1to conduct and provide a path for addi-tional current.

The circuit can source around one am-pere of current at 12+1.4 volts=13.4 volts. Both the regulator IC and the power transistor must be mounted on heat sinks.

PRADEEP G.


S.C. DWIVEDI

brief period gives rise to pulsed operationof the sensor module.

Once monostable IC2 gets triggered,

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JUNOMON ABRAHAM

The circuit presented here detectsinterruption in security systems.Its features include no false trig-

gering by external factors (such as sun-light and rain), easy relative positioningof the sensors and alignment of the cir-cuit, high sensitivity, and reliability.

The circuit comprises three sections,namely, transmitter, receiver, and powersupply. The transmitter generates modu-lated IR signals and the receiver detects

the change in IR intensity. Power supplyprovides regulated +5V to the transmit-ter and the receiver.

The power supply and the speaker arekept inside the premises while the trans-mitter and the receiver are placed oppo-site to each other at the entrance wherethe detection is needed. Three connections(Vcc, GND, and SPKR) are needed fromthe power supply/speaker to the receiversection, while only two connections (Vccand GND) are required to the transmit-ter.

The transmitter is basically an astablemultivibrator configured around NE555(IC3). Its frequency should match the fre-quency of the detector/sensor module (36kHz for the module shown in figure) inthe receiver. The transmitter frequency

is adjusted by preset VR2. For makingthe duty cycle less than 50 per cent, di-ode 1N4148 is connected in the chargingpath of capacitor C7.

The output of astable multivibratormodulates the IR signal emitted from IRLEDs that are used in series to obtain arange of 7 metres (maximum). To increasethe range any further, the transmittedpower has to be raised by using morenumber of IR LEDs. In such a case, it is

advisable to use another pair of IR LEDsand 33-ohm series resistor in parallel withthe existing IR LEDs and resistor R5across points X and Y.

The receiver unit consists of amonostable multivibrator built aroundNE555 (IC2), a melody generator, and anIR sensor module. The output of the IRsensor module goes high in the standbymode or when there is continuous pres-ence of modulated IR signal.

When the IR signal path is blocked,the output of the sensor module still re-mains high. However, when the block isremoved, the output of the sensor mod-ule briefly goes low to trigger monostableIC3. This is due to the fact that the sen-sor module is meant for pulsed operation.Thus interruption of the IR path for a

its output goes high and stays in thatstate for the duration of its pulse widththat can be controlled by preset VR1.The high output at pin 3 of the monostablemakes the musical IC to function. Volt-age divider comprising R2 and R3 reducesthe 555 output voltage to a safer value(around 3V) for UM66 operation. The du-ration of the musical notes is set by pre-set VR1 as stated earlier.

For proper operation of the circuit,use 7.5V to 12V power supply. A batteryback-up can be provided so that the cir-cuit works in the case of power failure

also. Potmeter VR3 serves as a volumecontrol.

The transmitter, receiver, and powersupply units should be assembled sepa-rately. The transmitter and the receivershould have proper coverings (booster) forprotection against rain. The length of thewire used for connecting the IR sensormodule and IR LEDs should be minimum.

Note. The heart of the circuit is theIR sensor module (usually used in VCRsand TVs with remote); the circuit workssatisfactorily with various makes of sen-sors. The entire circuit can be fixed inthe same cabinet if the connection wiresto the sensors are smaller than 1.5metres. The reflection property of IR sig-nals can also be used for small-distancecoverage.

Construction

2001


receive input pulses greater than 100 mV(which is the same as the reference volt-age set for comparator IC3, LM319) butless than or equal to 10 volts.

With switch S1 closed, the input pulse

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RUPANJANA

Apulse or a repetitive train ofpulses is one of the most fre-quently encountered electronic

signals, and the conventional way to de-termine its peak amplitude is to have anoscilloscope display of the waveform. Anoscilloscope that has the required band-width to correctly display sub-microsec-ond-wide pulses is an expensive instru-ment, and is often beyond the reach ofmost electronics enthusiasts, hobbyists,and small-scale units. The circuit pre-sented here allows you to measure thepeak amplitude of a single pulse as wellas of a repetitive train of pulses with aconventional multimeter.

The circuit is capable of measuringpeak amplitude of pulses as narrow as100 nanoseconds (ns) up to a maximumof 100V amplitude. There is practicallyno limit on the maximum value of thepulse width. It can also be used to mea-sure the peak amplitude of a repetitivepulsed waveform as long as the time in-terval between two successive pulses isgreater than 100 microseconds (µs).

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The pulse under measurement is fed tothe input of a cascaded arrangement oftwo unity-gain peak detection stages builtaround IC1 and IC2 using high-speed op-amps AD829, as shown in Fig. 1. The op-amp has a guaranteed unity-gain band-width of 120 MHz and a slew rate of 230V/µs, and it is capable of driving highlycapacitive loads. This makes it ideal forreceiving input pulses as narrow as 100ns. D1 and D2 (1N914) are high-speedswitching diodes having a response timeof the order of 2 ns to 3 ns.

The input pulse gets stretched toabout 10 µs at the output of the first peak-detection stage built around IC1 and toabout 100 µs at the output of the secondpeak-detection stage built around IC2.

With switch S1 open, the circuit can

amplitude may be anywhere between 1volt and 100 volts. The closure of theswitch causes division of the input volt-age by a factor of 10 due to the arrange-

ANIL KUMAR MAINI

Fig. 1: Circuit for measuring sub-microsecond pulses



ment of resistors R1 through R3.The peak amplitude of the stretched

pulse at the output of the second peakdetector is the same as the input pulsepeak amplitude. This output amplitude ishalved by resistors R9 and R10 before

feeding thesame to theanalogue in-put of IC5( A D C - t y p eAD0808). Thisensures thatfor the maxi-mum inputpulse ampli-tude of 100volts, the ADCanalogue in-put is limitedto 5 volts,which is themaximum am-plitude it canaccept.

The out-put of the firstpeak detectorstage after adivision by afactor of 2 bythe arrange-ment of resis-tors R11 andR12 feedsc o m p a r a t o rLM319 (IC3).

The leading edge of the pulse output fromthe comparator coincides with the lead-ing edge of the input pulse. The leading-edge comparator output triggers monoshot74121 (IC4) to produce a 1µs pulse (asdetermined by timing components R17-

Fig. 3: Actual-size, single-side PCB layout for the circuit

Fig. 2: Waveforms at various points of the circuit



C10) at its Q-output, with its leading edgecoinciding with the leading edge of theinput pulse.

The monoshot output is passedthrough an appropriate NAND gate logiccircuit built around 7400 (IC9) and it actsas the start-of-conversion pulse for ana-logue-to-digital converter IC5 (ADC0808).The NAND logic is used here to incorpo-rate the reset feature.

The clock generator circuit for IC5 isbuilt around 74HCT04 (IC8) to provide1MHz clock. The clock frequency is de-cided by R24, R25, and C18. The latcheddigital output from IC5 feeds the corre-sponding inputs of DAC0808 (IC6). The

Photograph of author’s prototype


DAC output, which is a latched DC cur-rent, is converted into a proportional volt-age in the current-to-voltage circuit builtaround op-amp LF356 (IC7). This DC volt-age is connected to the multimeter forindication of peak amplitude of the inputpulse to the circuit. Potentiometer VR1 ismeant for calibration.

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Every time there is a pulse at the input,there is a stretched pulse appearing atthe analogue input of the ADC, with itsleading edge coinciding with the leadingedge of the input pulse. Fig. 2 shows wave-

forms available at vari-ous test points marked A,B, C, D, and E in the cir-cuit shown in Fig. 1.Also, there is a start-of-conversion pulse appear-ing at the relevant inputof the ADC. The conver-sion starts at the trail-ing edge (test point E) ofthis pulse 1 µs after theleading edge of the inputpulse.

Since the stretchedpulse is about 100µswide, the peak amplitudeof the pulse 1 µs later isalmost the same as theactual peak amplitude.At the same time, thissmall delay ensures that

the analogue input is already present onthe relevant input at the start of conver-sion.

The latched digital output from theADC feeds the corresponding inputs of theDAC0808 (IC6) as stated earlier. The out-put of the DAC, after conversion into theproportional voltage by LF356 (IC7), isfed to the multimeter (set to appropriateDC voltage scale) for measurement ofpeak pulse amplitude. Potentiometer VR1is used for calibration.

The display holds the peak amplitudeof the last pulse until it is reset usingswitch S2 or it is updated by another pulseat the input. The accompanying photo-graph shows the assembled circuit thatthe author used for performance evalua-tion.

An actual-size, single-side PCB for thecircuit is shown in Fig. 3 and its compo-nent layout in Fig. 4. ❏

PARTS LISTSemiconductors:IC1, IC2 - AD829 op-ampIC3 - LM329 comparatorIC4 - 74121 monostable

multivibratorIC5 - AD0808 analogue-to-digital

converterIC6 - DAC0808 digital-to-

analogue converterIC7 - LF356 op-ampIC8 (N1-N3) - 74HCT04 hex inverterIC9 (N4-N7) - 7400 NAND gateD1, D2 - 1N914 high-speed switch-

ing diodeZD1 - 2.5V zener diodeResistors (all ¼-watt, ±5% carbon, unlessstated otherwise):R1, R2 - 18-kilo-ohmR3, R16 - 1-kilo-ohmR4 - 12-kilo-ohmR5, R6 - 22-kilo-ohmR7, R8 - 15-kilo-ohmR9-R12 - 100-kilo-ohmR13 - 470-ohmR14 - 220-kilo-ohmR15, R18, R19,R24, R25 - 10-kilo-ohmR17 - 2.2-kilo-ohmR20, R21 - 2.7-kilo-ohmR22 - 4.7-kilo-ohmR23 - 33-kilo-ohmVR1 - 50-kilo-ohm presetCapacitors:C1, C2, C4, C5,C7-C9, C11-C17C19 - 0.1µF ceramic diskC3, C10 - 0.001µF ceramic diskC6 - 0.01µF ceramic diskC18 - 56 pF ceramic diskMiscellaneous:S1, S2 - On/off switch (SPST)Meter - Multimeter


tor, the run capacitor value can be calcu-lated using the simple thumb rule (70 µFper HP), while the start capacitor valuemay be determined from Table I.

Manual operation of ESP motor

UNIL KUMAR

S

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Anumber of construction projects aswell as circuit ideas for water-/fluid-level control have appeared

in EFY over the years, but so far no dedi-cated project has appeared for automat-ing the control of submersible waterpumps. Looking into the demand for sucha project from readers, we present here acircuit for automating the operation of anelectrical submersible pump (ESP) basedon the minimum and the maximum lev-els in the overhead tank (OHT). This cir-

cuit can be interfaced to the existingmanual control panel of an ESP and canalso be used as a standalone system afterminor additions.

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Electrical submersible pumps are single-or multiple-stage radial-flow pressure se-ries impeller pumps that are close coupledto the motor for low and medium heads.These find applications in domestic, in-dustrial, irrigation, air-conditioning, andvarious other systems.

The ESPs are classified by the borediameter (which generally varies from 100mm to 200 mm), horse-power (from about0.5 HP to 40 HP), and discharge rate (typi-cally 120 litres per minute for 0.5 HP toabout 2000 litres per minute for 40 HP).These are run at a fixed speed, which is

2850 rpm typically.The ESP body is made of cast iron or

stainless steel. For low and mediumrange, one can use 3-phase or split-phase(also referred to as 2-phase) supply. ESPsof 3 HP or higher rating invariably use 3-phase supply.

Let us consider a typical case of 1.5HPESP with 100mm bore diameter, using asplit-phase motor. The motor draws a run-ning current of 10 to 11 amp, while thestarting current is around 2.5 to three

times the running current value.To obtain a higher initial torque, the

run winding is connected in series with aparallel combination of 120-150µF, 230VAC bipolar paper electrolytic capacitor and72µF, 440V AC run-mode capacitor. Af-ter two or three seconds of running, whenthe motor has picked up sufficient speed,the start capacitor goes out of the circuitbecause of the opening of thecentrifugal switch inside themotor, while the run capaci-tor stays in the circuit per-manently. For ESPs thatdon’t have an integral cen-trifugal switch arrangement,a dual-section start switch(explained later) can be usedto perform the function of thecentrifugal switch.

For the split-phase mo-

(Fig. 1). The control panel comprises anisolator switch, push-to-on single-/dual-sec-tion ‘start’ button, push-to-off ‘stop’ but-ton, a triple-pole moulded case circuitbreaker (MCCB) for motor protection withmagnetic trip and resetting facility (withan adjustable current range of 12 to 25amperes), start and run capacitors, am-pere-meter, voltmeter, neon indicators, etc.

(Note. The MCCBs used for motorcontrol are termed as motor circuit pro-tectors (MCPs). These are classified/cata-logued by number of poles, continuousampere rating, and magnetic trip range(current). For details, you may visit Cut-ler-Hammer’s Website or contact BhartiaCuttler-Hammer dealers.)

Fig. 1 shows a simplified control paneldiagram, along with ESP motor wiring.The ‘start’ pushbutton (green), which isnormally open, and the ‘stop’ pushbutton(red), which is normally closed, are in se-ries with the live or phase line.

The isolator switch is normally in ‘on’position. When ‘start’ button is momen-tarily pressed, the contactor energises viathe closed contacts of ‘off’ button. One ofthe contact pairs of the contactor is usedas the hold contact to shunt ‘on’ buttonand provide a parallel path to the

TRUTH TABLE FOR RELAY OPERATIONWater level Relay operation (2.5 – 3 sec.) Pump motorin tank RL1 (stop) RL2 (Start) operationBelowlow level No Yes StartsAbovelow levelbut belowhigh level No No Remains onReacheshigh level Yes No Stops

Fig. 1: Line diagram of control panel for manual operation of ESP motor Motor rating Start capacitor value (µF)in HP 230V AC (working)

275V AC (surge)1/6 20-251/5 30-401/4 40-601/3 60-801/2 80-1003/4 100-1201 120-1501½ 150-2002 200-250

K.C. BHASIN



section in ‘start’ button (shown in lightshade in Fig. 1) can be used to shuntpoints ‘E’ and ‘F’. Since this switch sec-tion has no hold on contacts, the startcapacitor will go out of circuit as soon as‘start’ button is released. The motor canbe switched off by momentarily depres-sion of ‘off’ button, which interrupts thesupply to the contactor coil.

To interface the control circuit shownin Fig. 2, we use circled points A and B(in parallel with ‘on’ button) and C and D(formed by disconnecting one of the wires

going to ‘off’ button terminal, i.e. in se-ries with ‘off’ button). Points E and F willbe used if the ESP does not have an inte-gral centrifugal switch.

It may be recalled, by referring to Fig.1 of the project ‘Auto Control for 3-phaseMotor’ published in EFY’s June issue, thatwiring of ‘on’ and ‘off’ buttons of 3-phase(4-wire system) and split-phase motors areidentical. Hence the control circuit de-scribed here can equally be used for 3-phase motors of up to about 10 HP. Formotors of higher HP, one must use star-delta type starter configuration.

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As shown in Fig. 2, the 230V AC mains(tapped from the same points from whichit is fed to the control panel of Fig. 1) isstepped down to 12V-0-12V by trans-former X1. The rectified output smoothedby capacitor C1 is used for operation ofheavy-duty 24V, 250-ohm relays RL1 andRL2 having contact rating of 30 amp. Therelay contacts identified by letters ‘A’through ‘F’ in Fig. 2 are to be connectedto identically marked points in Fig. 1.

Note that point C in Fig. 1 is created

contactor coil, which thus latches.The supply to the motor gets completed

via the other N/O contacts of the contactorand the pump motor starts. When the mo-tor gains sufficient speed (around 80 percent of the normal running speed), thecentrifugal switch opens to take the startcapacitor out of the circuit and only therun capacitors (2x36 µF) permanently stayin series with one of the two stator wind-ings of the ESP motor.

In case the ESP is not provided withan integral centrifugal switch, a second

Fig. 2: Circuit diagram for automatic control of ESP motor via control panel (Fig. 1)

Fig. 3: Actual-size, single-sided PCB layout for Fig. 2



by breaking the connection going to pointD on the ‘stop’ switch. We have used re-lay RL1 with single changeover contacts.If you need higher current rating, use re-lays with double changeover contacts byinterconnecting N/C, N/O, and pole of oneset to the corresponding terminals of theother set. The circuit, except for the relaydrivers, is operated with regulated +12Vsupply developed across capacitor C2.

The +12V supply is fed to the com-mon probe in the overhead tank/storagetank via 10-kilo-ohm resistor R1 and di-ode D9. Low-level and high-level probesare connected to the input of CMOS in-verter gates N3 and N1, respectively, via10-kilo-ohm resistors.

The final low-level output at pin 10 ofgate N5 goes high when the water levelin the overhead/storage tank is below thelow-level probe. The final high-level out-put at pin 4 of gate N2 goes high as soonas the water touches the high-level probe.

Both IC1 and IC2 have been config-ured as monostables with a pulse widthof about 2.5 to 3 seconds. This period isfound to work optimally for ‘start’ and‘stop’ switch operation of the manual con-trol panel. The respective monostables forlow level (IC2) and high level (IC1) gettriggered via transistors T2 and T1 whenthe final output at pin 10 of gate N5 orpin 4 of gate N2, respectively, goes high.

The connection of reset pins of IC2and IC1 to the outputs of gates N1 andN2, respectively, ensures that no falsetriggering of monostables takes place dueto the noise generated during changeoverof relay contacts, and also that the tworelays never operate simultaneously.

In the case of mains failure, the pumpstops if it was already running. When themains supply resumes, the pump startsonly when the water goes below the low

level. In such a situation, you can restartthe motor by manual operation of ‘start’button on the control panel.

The connections for the ammeter andthe voltmeter, not shown in Fig. 1, can bemade easily. Connect the voltmeter acrossthe incoming live and neutral lines, andinsert the ammeter in series with the stopswitch by breaking the live line connec-tion after the stop switch.

Transformer, relays, switches, fuse,and neon indicator (with integral resis-tor) are to be mounted on the cabinet.

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The following are the vital points to beborne in mind during wiring, assembly,and installation:

1. One-watt resistor R18 should bemounted leaving some space below it.

2. Use multistrand insulated copperwires of 15-amp rating for taking connec-tions from relay terminals and terminatethem on a tag block, marking each termi-nal properly. Similarly, terminate thepoints to be extended to the OHT/storagetank on a tag block (TB) using 25-28SWGwire, marking them suitably.

3. Mount the relays inside the body ofa suitable metallic enclosure. The enclo-sure should be properly earthed via theearth lead of the mains. Also mount thestep-down transformer inside the sameenclosure/cabinet. Use a TB for incominglive, neutral, and earth connections fromthe mains (to be taken from the manualcontrol panel of ESP motor).

4. After assembly, position the cabi-net as close to the manual control panelof ESP motor as possible and extend con-nections from tag blocks for relay andpower supply to the corresponding points,as explained earlier, using cables of cor-

rect ratings.5. For probes, use stainless steel rods

of about 10cm length and 5 to 8 mm di-ameter with arrangement for screwing thetelephone-type 25/26 SWG wire to be usedfor extending the probes’ connections tothe circuit. Teflon-insulated wires are,however better as they would last longer.The joint may be covered by epoxy.

6. The probes can be hung from thelid of the tank to appropriate levels usingthe same wire. Make sure that the com-mon probe goes up to the bottom of thetank/storage tank.

7. All the wires from tank to the TBsin the cabinet should be routed in such away that they do not interfere with anymains wiring. The length of the wireshardly matters as the CMOS gates usedfor terminating the wires from probeshave very high input impedance.

EFY note. The above circuit is beingused with ESP motor control panel at EFYhead office and is performing satisfacto-rily for over two months now. ❏

PARTS LISTSemiconductors:IC1, IC2 - NE555 timerIC3 - CD4049 hex inverter/bufferT1, T2 - BC548 npn transistorT3, T4 - BD139/SL100 npn transistorD1-D4, D7-D9- 1N4007 rectifier diodeD5, D6 - 1N4001 rectifier diodeZD1 - 12V, 1W zener diodeResistors (all ¼-watt ±5% carbon unlessstated otherwise)R1, R3, R5,R7, R9, R12,R14 - 10-kilo-ohmR2, R6, R11,R15-R17 - 1-kilo-ohmR4, R13 - 220-kilo-ohmR8, R10 - 330-kilo-ohmR18 - 330-ohmCapacitors:C1 - 470µF, 63V electrolytic

capacitorsC2 - 470µF, 25V electrolytic

capacitorsC3, C7 - 47µ, 25V electrolytic

capacitorsC4, C6 - 0.01µF ceramic diskC5, C8 - 10µF, 25V electrolytic

capacitorsMiscellaneous:X1 - 230V AC primary to 12V-0-

12V, 1ampSecondary transformer

L1 - NE2 (neon bulb with inbuiltresistor)

S1 - On/off switchF1 - 3amp fuseRL1 - 24V, 250-ohm, 1 c/o relay,

30A contact rating


December

2001

Circuit Ideas

2001


S.C. DWIVEDI

The high output of gate N1 goes topin 1 of gate N3 of IC4 (7400), while thelow output of gate N2 goes to pin 2 ofgate N3 of IC4. As a result, the output ofgate N3 becomes high and transistor T1

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� ��

ELECTRONICS FOR YOU� ❚❚❚❚❚ �DECEMBER 2001

This high-speed relay tester is in-tended for testing 12V DC 2C/O(changeover) and 4C/O PCB-

mounted relays used in RAX (small-capacity rural automatic exchange) andMAX (main automatic exchange) of C-DOT origin. It is a reliable tool for test-ing relays in bulk. For other than 2C/Oand 4C/O contact relays, slight modifica-tion in the circuit is required.

As soon as the relay is inserted in 28-pin ZIF socket and test pushbutton S2 ispressed, the tester displays ‘pass’ or ‘fail’on 7-segment display. If the relay coil isopen or N/O and N/C contacts are not

functioning as they should during oper-ate and release conditions, the tester im-mediately displays ‘fail’ on 7-segment dis-play. If the relay under test is good, thedisplay shows ‘pass’ on 7-segment display.

When the mains supply is connectedto the circuit by closing switch S1, 5V DCsupply goes to the ICs, transistors (collec-tors), and common points (poles) of therelay under test, and 12V DC supply goes

to one of the terminals of the coil of relayunder test. The outputs from four N/Cand four N/O contacts are alternately ap-plied to N1 and N2 gates, respectively, ofdual 4-input AND gate IC3 (74LS21).

conducts to complete the path for supplyto the coil of the relay under test.

For a good relay, the output of gateN4 is high before its energisation. Afterenergisation of the relay, the output ofgate N3 remain high whereas the outputof gate N4 goes low. This signal is in-verted by gate N5 to display ‘pass’. Theoutput of gate N5 is further inverted bygate N6 to display ‘fail’.

The common segments of ‘pass’ and‘fail’ characters are illuminated by OR gat-ing via diodes D5 and D6, while exclusive‘pass’ and ‘fail’ segments are illuminated

directly through resistors R12 and R13(whichever is high), respectively.

For testing 2C/O relays, keep the knobof push switch S3 (wiring of S3 to relaysocket is shown separately) pressed to by-

KRISHNA SHARMA



pass two C/O contacts out of four C/Ocontacts.

The test procedure is summarised be-low:

1. Switch on the power supply to the

tester.2. Insert the relay to be tested into

ZIF socket and lock it.3. For 4C/O relay leave knob S3 re-

leased, and for 2C/O relay keep the knob

pressed.4. Press test switch S2 and observe

the display for ‘pass’/ ‘fail’.5. Unlock ZIF socket and segregate

the relay as per the result.


DI

(Note. Only eight of the ten outputs ofCD4017s have been used.)

Driving characters at 1 Hz ensures
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S.C. DWIVE

This eye-catching signboard can beused for special occasions such asbirthdays and marriage ceremo-

nies. The characters in the display boardare illuminated one by one, each for onesecond. After the last character is illumi-nated, the entire board gets illuminatedfor 4 to 5 seconds. The above two se-quences are repeated continuously.

Timer 555 (IC1) generates 1Hz pulses,which are applied to decade-counter

PRATAP CHANDRA SAHU

CD4017B (IC5). The output from pin Q9of IC5 triggers 4- to 5-second (pulse width)monostable multivibrator IC2. The out-put of IC2 is ANDed in gate A1 with100Hz stepped down/pulsating DC sup-ply available at the output of the bridgerectifier comprising diodes D1 through D4.The output of AND gate A1 drives seconddecade counter IC4, whose outputs (Q1through Q8) are ORed with the corre-sponding outputs of first counter IC5.

that the characters are illuminated oneby one for one second each. Similarly,100Hz signal driving IC4 ensures that thecharacters are refreshed rapidly for a con-tinuous glow effect due to persistence ofvision. AND gate A2 is used to block 1Hzsignal reaching the first counter (IC5)while the second counter (IC4) is active,i.e. when the output of IC2 is high. WhenIC2 output goes low after 4-5 seconds, itenables gate A2 to pass 1Hz clock to thefirst counter (IC5) and disables the sec-ond counter (IC4) via its reset pin 15.Transistor T1 acts as an inverter.



For illuminating more than one mes-sage, use two rows of characters wiredreverse to each other. This sequence ofcharacters in opposite directions gives aspecial effect.

The characters can be made by wiring

LEDs/torch bulbs (6V, 200mA type) in se-ries/parallel combination or denselypainted glass or transparent plastic illu-minated by torch bulbs. The bulbs shouldbe placed behind each painted character.Each of the eight outputs of ULN2803

can sink a maximum of 500 mA at supplyvoltage of up to 50 volts.

Note. The supply for ULN2803 can bea separate one or the same as used for therest of the circuit. However, ensure theground reference is same in both the cases.


SUNIL KUMARward voltage drop at the base-emitterjunction of transistor T1), it causes for-ward biasing of transistor T1. This re-sults in the collector of transistor T1 tobe pulled down to ground and trigger

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� ��


VIJAY KUMAR P.

In applications like inverters andUPS, the load must not exceed therated output power since it can cause

excess heating of output transformerwindings and active driving devices andthereby damage them.

The circuit presented here canbe used as overload protector forinverters or as an electronic fusein AC mains supply. The mainssupply to the load is routed viathe the N/C (normally closed) con-tacts of relay RL1. In an inverter,the relay contacts could be usedas ‘inverter oscillator’ on/off con-trol. Whenever overload occurs, itinhibits inverter oscillator circuit,which, in turn, stops generationof power.

Resistor R1 is used as theoverload sensing element. Whenthe load exceeds the maximumrated value, it draws current inexcess of its rated value. Thiscauses the potential drop across resistorR1 to increase. An optocoupler is used tosense this voltage drop. The optocoupler,in addition, isolates the AC mains partfrom the rest of the circuit physically.

Resistor R1 is selected as 1 ohm for230V, 500 watts (max.) load capacity.When the load just exceeds 500 watts,the current through R1 is approximately2.1 amperes, producing a potential differ-ence of 2.1 volts across R1. The inbuilt

transistor inside the optocoupler sensesthis voltage and its collector current in-creases proportionally. When the currentreaches the required designed value, volt-age drop across resistor-preset combina-

tion R3-VR1 also increases. (Note. Thepower dissipated in 1-ohm resistor for500W load is just 2.1 watts, which is neg-ligible compared to the maximum powerrating of the load. To use this circuit for1kW load, select R1 as 0.5-ohm, 10W.)

Overload limiting point can be set bypreset VR1. When the potential at wiperof preset VR1 becomes greater thanVZ+VBE (where VZ is the breakdown volt-age of zener diode ZD1 and VBE the for-

IC555, which is connected in bistablemode.

The output of IC1 causes overload in-dicating LED1 to glow and forward bi-ases transistor T2 to energise relay RL1.Once the output of bistable IC1 goes high,it continues to remain high, unless resetpushbutton S1, which is connected be-

tween Vcc and threshold terminal (pin 6)of timer 555, is pressed. On pressing S1,a high pulse is applied to the thresholdpin that resets the flip-flop output to lowstate. The circuit can be reset after re-moving unwanted loads.

Note. Since the circuit is very sensi-tive, fluctuations in AC mains can alsotrigger the circuit undesirably. This ef-fect can be eliminated by using 4.7µF by-pass capacitor C1 as shown in the figure.


S.C. DWIVEDIanode 7-segment LED display (DIS.1,FND507 or LT543).

The audio alarm generator comprisesclock oscillator IC7 (555), whose outputdrives a loudspeaker. The oscillator fre-

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Q uiz-type game shows are increas-ingly becoming popular on tele-vision these days. In such games,

fastest finger first indicators (FFFIs) areused to test the player’s reaction time.The player’s designated number is dis-played with an audio alarm when theplayer presses his entry button.

The circuit presented here determinesas to which of the four contestants firstpressed the button and locks out the re-maining three entries. Simultaneously, anaudio alarm and the correct decimal num-ber display of the corresponding contes-tant are activated.

When a contestant presses his switch,the corresponding output of latch IC2(7475) changes its logic state from 1 to 0.The combinational circuitry comprisingdual 4-input NAND gates of IC3 (7420)locks out subsequent entries by produc-ing the appropriate latch-disable signal.

Priority encoder IC4 (74147) encodes

the active-low input condition into the cor-responding binary coded decimal (BCD)number output. The outputs of IC4 afterinversion by inverter gates inside hex in-verter 74LS04 (IC5) are coupled to BCD-to-7-segment decoder/display driver IC6(7447). The output of IC6 drives common-

quency can be varied with the help ofpreset VR1. Logic 0 state at one of theoutputs of IC2 produces logic 1 input con-dition at pin 4 of IC7, thereby enablingthe audio oscillator.

IC7 needs +12V DC supply for suffi-cient alarm level. The remaining circuitoperates on regulated +5V DC supply,which is obtained using IC1 (7805).

Once the organiser identifies the con-

testant who pressed the switch first, hedisables the audio alarm and at the sametime forces the digital display to ‘0’ bypressing reset pushbutton S5.

With a slight modification, this cir-cuit can accommodate more than four con-testants.

P. RAJESH BHAT


SUNIL KUMARvarying its gain. In order to increase theaudio power, the low-level audio outputfrom the preamplifier stage is coupled viacoupling capacitor C7 to the audio poweramplifier built around BEL1895 IC.

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D. PRABAKARAN

transmitters, and packet radio receivers.Transistors T1 and T2 form the mic

preamplifier. Resistor R1 provides the nec-essary bias for the condenser mic whilepreset VR1 functions as gain control for

The compact, low-cost condensermic audio amplifier described hereprovides good-quality audio of 0.5

watts at 4.5 volts. It can be used as partof intercoms, walkie-talkies, low-power

BEL1895 is a monolithic audio poweramplifier IC designed specifically for sen-sitive AM radio applications that delivers1 watt into 4 ohms at 6V power supplyvoltage. It exhibits low distortion andnoise and operates over 3V-9V supply volt-age, which makes it ideal for battery op-eration. A turn-on pop reduction circuit

prevents thud when the powersupply is switched on.

Coupling capacitor C7 deter-mines low-frequency response ofthe amplifier. Capacitor C9 actsas the ripple-rejection filter. Ca-pacitor C13 couples the outputavailable at pin 1 to the loud-speaker. R15-C13 combinationacts as the damping circuit foroutput oscillations. Capacitor C12provides the boot strapping func-tion.

This circuit is suitable for low-power HAM radio transmitters tosupply the necessary audio powerfor modulation. With simple modi-fications it can also be used inintercom circuits.


SANI THEO
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PRADEEP G.

The smoke alarm circuit presentedhere is based on the readily avail-able photon-coupled interrupter

module and timer IC NE555. The photointerrupter module is used as the smokedetector, while timer 555 is wired in

astable configuration as anAF oscillator for soundingalarm via a loudspeaker.

In the absence of anysmoke, the gap of photo in-terrupter module is clearand the light from LEDfalls on the phototransistorthrough the slot. As a re-sult, the collector ofphototransistor is pulled to-wards ground. This causesreset pin 4 of IC 555 to golow. Accordingly, the timeris reset and hence thealarm does not sound.

However, when smoke is present inthe gap of the photo interrupter module,the light beam from LED to thephototransistor is obstructed. As a result,the phototransistor stops conducting andpin 4 (reset) of IC 555 goes high to acti-vate the alarm.

Note. The unit must be housed insidean enclosure with holes to allow entry ofsmoke.

Construction

2001


analogue electronic device that has asingle control terminal unlike op-amps.
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SUNIL KUMAR ��

The transistor curve tracer is built aroundthe ramp generator and the current-to-voltage converter. The ramp generatorproduces a linear ramp that is applied tothe transistor under test either as thecollector-emitter voltage (VCE) or the base-emitter voltage (VBE). The ramp is alsoused to deflect the electron beam hori-zontally (along x-axis) on the screen ofthe CRO. Similarly, the current-to-volt-age converter converts either the collec-tor current (IC) or the base current (IB)into a proportional voltage that is used todeflect the electron beam vertically (alongy-axis) on the screen.

The signal conditioning and switch-ing circuits, along with the ramp genera-tor and current-to-voltage converter, makea complete curve tracer for the input andoutput characteristics of an npn transis-tor.

Output characteristics (Fig. 1). Theramp and clock generator generates a lin-ear ramp and 1 kHz clock pulses. Theramp is amplified by the ramp buffer am-plifier to 0 to 5 volts. This amplified rampis applied to the collector of the transis-tor under test as the collector-emitter volt-age (VCE) through the current-to-voltageconverter.

The current-to-voltage converter givesan output voltage proportional to collec-tor current IC that is applied to the CROto deflect the beam in y-axis. The 0-5Vramp output is applied to the CRO to de-flect the beam in x-axis. Hence we cantrace the output characteristics of thetransistor with the collector-emitter volt-age (VCE) on x-axis and IC on y-axis.

To trace the output characteristicgraph for various base current (IB) val-ues, the generator’s clock output fed tothe counter is incremented for each clockpulse. The count sequence is 000, 001,010, 011, 100, 101, 110, and 111 (0 to 7decimal). After 111, the counter resets au-tomatically to 000 and the sequence re-peats. The lower three bits of the counterare applied to the base-current control cir-cuit.

The base-current control circuit setsIB in eight discrete 100µA steps, i.e. 0 µA,

A. SARAVANAN

Fig. 2: Block diagram for tracing transistor input characteristics

Fig. 1: Block diagram for tracing transistor output characteristics

Transistor is the basic componentof all electronic equipment. A gooddesign of electronic circuitry re-

quires proper knowledge of the charac-teristics and parameters of transistors.Due to such factors as changes in dopinglevel of impurities and physical dimen-sions, production imperfections, and en-vironmental (ambient temperature, hu-midity, etc) changes, no two transistorscan have the same characteristics.

Transistor is an active device and evena very small change in its parameterscauses a large drift in its operation. Thisaffects the overall efficiency and the reli-ability of an equipment. Hence for an ef-ficient, reliable, and trouble-free design/operation of the electronic equipment, thedesigner must know the characteristicsand parameters of each transistor usedin the equipment.

The manufacturer providesgeneralised family characteristics of tran-sistors bearing specific part numbers.These characteristics are drawn underspecific test conditions such as 25oC tem-perature and 10mA collector current IC.

But as the circuit designed may need tobe operated at different conditions (for ex-ample, at an ambient temperature of 40oCand collector current of 10 mA), themanufacturer’s data is no longer adequate.The manual procedure to draw the char-acteristics of a transistor is tedious andcumbersome. Further, using the manualprocedure, it is not feasible to draw thedynamic characteristics of a transistor.

The transistor curve tracer circuit pre-sented here enables one to draw the in-put and output characteristics of npn tran-sistors in common-emitter configurationon a cathode ray oscilloscope (CRO). Itcan be constructed and calibrated by thedesigner himself. This circuit costs aroundRs 1500 and is designed to satisfy therequirements of most circuit designers.

The circuit can be upgraded to drawthe characteristics of both npn and pnptransistors, field effect transistors (FETs),metal-oxide semiconductor field effecttransistors (MOSFETs), unijunction tran-sistors (UJTs), silicon-controlled rectifiers(SCRs), TRIACs, etc. In general, it can beupgraded for any two- or three-terminal



100 µA, 200 µA, 300 µA, 400 µA, 500 µA,600 µA, and 700 µA. Adjust the step width(100 µA) using a potentiometer such thatthe output characteristics of various npntransistors with various current gains (α)are traced/accommodated.

Input characteristics (Fig. 2). Hereagain, the ramp and clock generator gen-erates a linear ramp and 1kHz clockpulses. The ramp is amplified by the rampbuffer amplifier to 0-5V. This amplifiedramp is attenuated and amplified as re-quired to get 0-1V ramp and applied tothe base of the transistor under test asthe base-emitter voltage (VBE) through thecurrent-to-voltage converter.

The current-to-voltage converter givesan output voltage proportional to base cur-rent IB that is applied to the CRO to de-flect the beam in y-axis. The 0-1V rampoutput is applied to the CRO to deflectthe beam in x-axis. Hence we can tracethe input characteristics of the transistorwith VBE on x-axis and IB on y-axis.

To trace the input characteristicsgraph for various VCE values, the clockoutput of the generator is fed to thecounter and switching circuit. The counter

counts the number of pulses in the bi-nary form. Q0 output of the counter isused as the collector-emitter voltage con-trol that toggles VCE with 0 volt and 10volts for every clock pulse. Thus we cantrace the input characteristics for VCE = 0volt and VCE = 10 volts.

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The transistor curve tracer circuit (Fig.3) comprises power supply, ramp and clockgenerator, ramp buffer and offset null,current-to-voltage converter, counter, basecurrent control, and switching sections.

1. The power supply section. Thecircuit operates on ±12V regulated powersupply. The input AC mains supply isstepped down by transformer X1 to de-liver a secondary supply of 15-0-15V ACat 1 ampere. The output of the trans-former is rectified by a bridge rectifier.The 1000µF, 35V capacitors act as filtersto eliminate ripples and provide unregu-lated DC output voltage.

The unregulated dual DC voltage isconverted by three-terminal ICs AN7812and AN7912 into ±12V regulated power

supply. (Note. Connect 0.1µF decouplingcapacitors between the supply terminalsand ground of every IC in order to sup-press unwanted noise signals in the sup-ply voltage.)

2. The ramp and clock generatorsection. The ramp and clock generatoruses a constant current source (LM334)and a capacitor, in conjunction with timerNE555 (IC3) wired as an astablemultivibrator, to generate a linear ramp.The control terminal of timer 555 (pin 5)is held at a reference voltage of 5 volts bya zener diode so that the upper threshold(VUTP) is at 5 volts and the lower thresh-old (VLTP) at 2.5 volts.

The output current from IC LM334can be controlled with the help of poten-tiometer VR1. This current charges thecapacitor linearly in the form of a linearramp. As soon as the voltage across thecapacitor exceeds the upper threshold volt-age (VUTP), the output of timer 555 changesits state and goes low. This activates thedischarge terminal (pin 7) of timer 555and hence the capacitor quickly dischargesthrough the timer.

As the voltage across the capacitor

Fig. 3: Circuit diagram of transistor curve tracer



Fig. 4: Actual-size, single-side PCB layout for transistor curver tracer




drops below the lower threshold voltage(VLTP), the output of timer 555 changesits state and goes high to disable the dis-charge terminal and further dischargingof capacitor stops. Once again the capaci-tor gets charged linearly through the con-stant current source and the sequence re-peats. Thus the potential across the ca-pacitor is a positive linear ramp between2.5 volts and 5 volts. The ramp frequencycan be controlled by varying the chargingcurrent using potentiometer VR1. (EFY

Lab note. During lab testing, we usedAD590 temperature transducer in placeof LM334H as the constant current source,and the method of using the same isshown in Fig. 3 within dotted lines.)

3. The ramp buffer and offset nullsection. Since the output impedance ofthe ramp source is very high, we cannotload it. Also, a DC offset voltage equal tothe lower threshold voltage (VLPT = 2.5V)is present in the ramp output. In order tonullify the offset voltage of the ramp and

Fig. 6: Waveforms at various points in the circuit

to source the current from the ramp, usea buffer amplifier. An op-amp in non-in-verting amplifier configuration is used toachieve this function.

As the input impedance of the non-inverting amplifier is very high, it willnot load the ramp source. Also, it is pos-sible to nullify the DC offset voltagepresent in the ramp output with the helpof ramp offset adjustment preset VR2.

By adjusting feedback preset VR3, theoutput of ramp buffer can be set to de-liver a linear 0-5V ramp. This output isused as VCE for the transistor under testto source the collector current (IC).

To draw the input characteristics ofthe transistor, the base-emitter voltage(VBE) should be varied linearly. For thiswe require a linear 0-1V ramp with suffi-cient current sourcing capability. In or-der to achieve this, a ramp attenuator(voltage divider) and an amplifier areused.

The 0-5V ramp output of ramp bufferis attenuated by the potential divider net-work (comprising resistors R4 and R5) fol-lowed by an op-amp (IC5) connected innon-inverting configuration. The gain ofthe op-amp can be adjusted using presetVR5 connected in the feedback path.

In order to nullify the offset voltageof the op-amp, balancing preset VR4 isconnected between the offset null termi-nals of the op-amp. The output of the op-amp is 0-1V linear ramp, which is usedas the base-emitter voltage (VBE) for sourc-ing the base current (IB) of the transistorunder test.

4. The current-to-voltage convertersection. The spot on the CRO screen isdeflected in proportion to the potentialapplied to its input. Hence in order todeflect the beam along y-axis, which isthe current axis (collector current IC inthe transistor output characteristics andbase current IB in the transistor inputcharacteristics), the current component isto be converted into a proportional volt-age.

The current to be measured is passedthrough series resistor R7 of 10-ohm, ±1%MFR (metal film resistor). Potential dropVout across the resistor, according to theOhm’s law, is proportional to current Ithrough it and is given by the followingrelationship:

V = IRwhere Vout = 10xI

Hence, there is a potential drop of 10mV per mA of the current through the



circuit. We cannot apply this small float-ing potential directly to the CRO for asignificant deflection. Therefore we use adifferential amplifier to have an outputvoltage with respect to the ground that isproportional to the current though the cir-cuit. The differential amplifier has a gainof 100 that can be fine-tuned with thehelp of gain adjust preset VR7 in the feed-back path.

The current-to-voltage converter con-verts the current of 1 mA into a poten-tial difference of 1 volt that can be ap-plied to the CRO to deflect the beam invertical axis. In order to nullify the off-set voltage of the op-amp, connect a bal-ancing preset to the offset null terminalsof the op-amp.

5. The counter section. The base cur-rent (IB) is to be changed in discrete stepsfor every ramp to enable the transistor’soutput characteristics for various IB val-ues simultaneously on the CRO screen.

In the counter circuit, the output oftimer 555 (IC3) from pin 3 is a squarewave that intimates the end of ramp. Thisoutput is used as clock pulse for thecounter wired around CMOS binary/de-cade, up/down IC MC14029B or CD4029B(IC7).

IC7 is wired as a 3-bit binary up-counter so that the output of the counter(Q2, Q1, and Q0) is incremented by bi-

nary 1 for every clock pulse. The countsequence is 000, 010, 011, 100, 101, 110,and 111, i.e. 0 through 7 decimal. After111, the counter is automatically reset to000, and once again the count sequencerepeats. Hence we get eight discrete logiclevels, and accordingly we can set the basecurrent (IB) using a base current controlcircuit.

Similarly, to draw the input charac-teristics of the transistor under test forvarious collector-emitter voltage (VCE) val-ues, the collector-emitter voltage (VCE) isto be changed for each ramp. The leastsignificant bit (Q0) of the counter is usedto toggle the collector-emitter voltage (VCE)from 0 volt to 10 volts. Thus we can viewthe input characteristics of the transistorfor VCE= 0 volt to VCE= 10 volts simulta-neously on the screen of the CRO.

6. The base current control section.This section receives the input from thecounter circuit and varies the base cur-rent (IB) of the transistor. The output ofcounter IC7 in series with a high-valueresistor acts as the constant currentsource. The high-level outputs of thecounter are fairly constant at 10 volts.

When we connect a resistor of 100kilo-ohms in series with Q0 output of thecounter, it supplies a constant current of100 µA during its logic 1 state. Similarly,when we connect a resistor of 50 kilo-ohms (two 100 kilo-ohm resistors in par-allel) in series with Q1 output of thecounter, it supplies a constant current of200 µA during its logic 1 state. Using 25-kilo-ohm resistor in series with Q2 out-put we can get a constant current sourceof 400 µA.

When more than one current sourceare connected in parallel, the result issimilar to having a current source equalto the sum of individual source currents.

If we use the base current (IB) settingas it is for a transistor with large currentamplification factor (α), its collector cur-rent (IC) gets saturated for much smallervalues of IB and only two or three tracesappear on the screen of the CRO. To getthe maximum number of traces, reducethe base current by increasing the seriesresistor values through IB SET potenti-ometer VR8. With the help of VR8, wecan adjust the base current in incremen-tal steps from 10 µA to 100 µA.

(Note. Connect two 100-kilo-ohm re-sistors in parallel to get 50-kilo-ohm re-sistor. Similarly, connect four 100-kilo-ohm resistors in parallel to have 25-kilo-

ohm resistor. This method has been shownin Fig 3.)

7. The switching section. Certaincircuits are common in tracing both theoutput characteristics and input charac-teristics. The ramp and clock generator,ramp buffer and amplifier, and countercircuits are retained at their places forboth output and input characteristics. Butto trace the output characteristics the cur-rent-to-voltage converter is to be con-nected in the collector of the transistorunder test and to trace the input charac-teristics it is to the connected in the baseof the transistor (refer Figs 1 and 2 foroutput and input characteristics, respec-tively).

To have minimum complexity, the col-lector and the base circuits of the transis-tor are switched suitably using achangeover switch on the front panel. Theswitching details are obvious from the cir-cuit diagram in Fig. 3.

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Wire the circuit on a 2.5mm, IC-type gen-eral-purpose printed circuit board (PCB)as shown in Fig. 3. The use of glass-ep-oxy PCB is recommended. An actual-size,single-side PCB for the circuit is shownin Fig. 4, with its component layout shownin Fig. 5.

Carefully solder all the componentsand use sockets for ICs. All range resis-tors used should be stable, close-tolerancetype (preferably MFRs). Preferably uselinear-type IB SET potentiometer andmount it on the front panel of the instru-ment. Enclose the circuit board, powertransformer, and other circuit componentsin a metal box having approximate di-mensions of 22x17x7.5 cm. Extend inputand output leads to the correspondingpoints in the circuit. Terminate the out-puts for connection to the CRO in BNC(F)connectors.

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After construction, check the circuit thor-oughly for short circuits, breaks, and opencircuits on the PCB. After switching onthe instrument, let it warm up for a fewminutes before commencing with the cali-bration. Calibration procedure of the cir-cuit is as follows:

1. Check and ensure ±12V regulatedvoltage with respect to ground.

2. Connect a CRO to shorted pins 2

Fig. 7: Actual output curves on CRO (shownwithout retrace)

Fig. 8: Actual input curves on CRO (shownwithout retrace)



and 6 of timer 555 (ramp output). A lin-ear ramp with positive slope is observedon the screen of the CRO. By adjustingfrequency control potentiometer VR1, setthe frequency of the ramp at 1 kHz (referwaveform 1 in Fig. 6).

3. Connect the CRO to the output oframp buffer. Adjust preset VR2 to nullifythe DC offset voltage in the output oframp buffer. Adjust preset VR3 to set theamplitude of ramp output to 0 to 5 volts(refer waveform 2 in Fig. 6).

4. Connect CRO at the output of rampattenuator and amplifier. Adjust presetVR4 to nullify the DC offset voltage inthe output of ramp buffer. Adjust presetVR5 to set the amplitude of ramp outputto 0 to 1 volt (refer waveform 3 in Fig. 6).

5. Calibrate the current-to-voltage con-verter by connecting a 1-kilo-ohm. 1%metal film resistor between the collectorand emitter terminals of the transistorunder test. Connect the output of the cur-rent-to-voltage converter to a CRO. Byobserving the ramp waveform on the

screen of the CRO, nullify DC offset volt-age using preset VR6 and adjust the am-plitude of the observed ramp waveformto 0-5 volts with the help of preset VR7.Calibrate the current-to-voltage converterto convert 1 mA of current into 1 volt(refer waveform 4 in Fig. 6). Then checkthe clock output by connecting the CROto pin 3 of timer 555 (refer waveform 5 inFig. 6).

6. Verify the outputs of the counterby using a dual-trace oscilloscope. Con-nect one input channel of the CRO withclock pulses at pin 3 of IC3 and the out-puts at pins 6, 11, and 14 of counter IC7to the other input of the CRO sequen-tially (refer waveforms 5, 6, 7, and 8 inFig. 6).

7. Short-circuit the base-emitter ter-minals of the transistor under test. Se-lect input/output characteristics switch S2to output characteristics position and con-nect the CRO to the output of the cur-rent-to-voltage converter. By adjusting IB

SET potentiometer VR8 on the front panelof the instrument, check proper opera-tion of the base-current section by observ-ing stair-case ramp of varying amplitudeon the screen of the CRO (refer wave-form 9 in Fig. 6).

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After calibration, the instrument is readyfor use to trace the input and output char-acteristics of npn transistors. Follow theoperating procedure given below everytime to get correct traces of input andoutput characteristics of the transistor:

1. Connect the x-axis and y-axis BNCpins of the transistor curve tracer to thecorresponding inputs of the CRO.

2. Plug in the AC cord of both theCRO and the transistor curve tracer andswitch them on.

3. Set the CRO inputs to ground.4. Allow warm-up time of at least 10

minutes for the circuit components to getstabilised.

5. Set the CRO for X-Y mode of op-eration.

6. Adjust intensity and focus controlsto get a sharp spot on the screen of theCRO.

7. Set the volts/div control of x-axis to0.5 volt/div.

8. Set the volts/div scale of y-axis to 2volts/div.

9. Adjust the position controls of theCRO to position the spot on the left bot-

tom of the screen ((0,0) position in thegraph).

10. Set the inputs for DC coupling tothe CRO.

11. Connect the transistor whose char-acteristics are to be traced to the transis-tor curve tracer, ensuring correct pin con-figuration.

12. Set the selector switch for input/output characteristics to the output char-acteristics position.

13. Release the CRO inputs fromground and switch them over to connectinputs.

14. Now view the output characteris-tics of the transistor. Fine-tune the IB setpotentiometer to get eight traces on thescreen of the CRO.

15. To trace input characteristics ofthe transistor, change the input/outputcharacteristics selector switch to the in-put characteristics position.

16. Set the volts/div control of x-axisto 0.1 volt/div and observe the input char-acteristics likewise.

Figs 7 and 8 show a typical transistor’soutput and input characteristics, respec-tively, on the CRO screen (without re-trace).

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To draw the characteristics of pnp tran-sistors, insert an inverter circuit in theramp path of collector-emitter voltage VCE

and base-emitter voltage VBE, and invertthe output of the current-to-voltage con-verter.

By using a potential divider andbuffer amplifier circuit in place of thebase-current control circuit you can drawthe characteristics of FETs andMOSFETs.

To trace the forward characteristicsof diodes, connect the anode of the diodeto the base terminal and the cathode tothe emitter terminal. Set the transistorcurve tracer to draw input characteris-tics, and the CRO screen displays theforward characteristics of the diode.

Similarly, with simple add-on circuitsto the motherboard, you can draw thecharacteristics of UJTs, SCRs, TRIACs,etc.

Thin and faint retrace lines visiblealong with the characteristic traces canbe removed by connecting a retrace blank-ing circuit to the Z-mod input of the CRO.Almost all CROs exceeding 30MHz band-width have the Z-mod input facility. ❏

PARTS LIST

Semiconductors:IC1 - 7812, +12V regulatorIC2 - 7912, – 12V regulatorIC3 - NE555 timerIC4, IC6 - µA741 op-amp (IC OP-07

op-amps can be used inplace of µA741 withadvantage)

IC7 - MC14029B/CD4039 binary/decade up-/down-counter

IC8 - LM334H/AD590 tempera-ture sensor

ZD1 - 1N4007 rectifier diode

Resistors (all ¼-watt, ±1% MFR, unless statedotherwise):R1, R5, R6,R8, R9 - 1-kilo-ohmR2, R4 - 22-kilo-ohmR7 - 10-ohmR3, R10, R11(A,B), R12(A-D) - 100-kilo-ohmVR1 - 1-kilo-ohm potmeterVR2 - 2.2-kilo-ohm presetVR3, VR4,VR5, VR6 - 10-kilo-ohm presetVR7 - 150-kilo-ohmVR8 - 1-mega-ohm potmeter

Capacitors:C1-C4, C9 - 0.1µF ceramic diskC5, C6 - 1000µF, 35V electrolyticC7, C8 - 100µF, 25V electrolyticC10 - 0.01µF ceramic disk

Miscellaneous:X1 - 230V AC primary to

15V-0-15V AC, 500mAsecondary transformer

S1 - On/off switchS2 - DPDT switch


IL KUMARvia individual 10-kilo-ohm resistors R14through R21.

Initially, all the eight Q outputs ofIC1 and IC2 are at logic 0. The auxiliaryrelay contacts of the subunits, which aredepicted here by push-to-on switches S1

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R.G. THIAGRAJ KUMAR AND S. RAMASWAMY

In applications like power stations andcontinuous process control plants, aprotection system is used to trip

faulty systems to prevent damages andensure the overall safety of the personneland machinery. But this often results inmultiple or cascade tripping of a numberof subunits.

Looking at all the tripped units doesn’treveal the cause of failure. It is thereforevery important to determine the sequenceof events that have occurred in order toexactly trace out the cause of failure andrevive the system with minimal loss oftime.

The circuit presented here stores thetripping sequence in a system with up toeight units/blocks. It uses an auxiliary re-lay contact point in each unit that closeswhenever tripping of the correspondingunit occurs. Such contact points can beidentified easily, especially in systems us-ing programmable logic controllers (PLCs).

This circuit records tripping of up toeight units and displays the order inwhich they tripped. A clock circuit, how-ever fast, cannot be employed in this cir-cuit because the clock period itself will bea limiting factor for sensing the incidenceof fault. Besides, it may also mask a num-ber of events that might have occurredduring the period when the clock was low.Hence the events themselves are used asclock signals in this circuit.

Fig. 1 shows the block diagram of thetripping sequence recorder-cum-indicator.

The inputs derived from auxiliary relaycontacts (N/O) of subunits or push-to-onswitches are latched by RS flip-flops whenthe corresponding subunits trip, causingthe following four actions:

1. The latch outputs are ORed to acti-vate audio alarm.

2. The latch outputs are differentiatedindividually and then ORed to provideclock pulses to the counter to incrementthe output of the counter that is initiallypreset at 1 (decimal).

3. Each individual latch output acti-vates the associated latch/decoder/driverand 7-segment display set to display thenumber held at the output of the counter,which, in fact, indicates the total numberof trips that have taken place since thelast presetting.

4. LEDs associated with each of thelatch, decoder, and driver sets remain litto indicate the readiness of the sets toreceive the tripping input. LEDs associ-ated with the tripped unit go off.

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IC1 and IC2 (CD4043) Quad NOR RS flip-flops in Fig. 2 are used to capture andstore the information pertaining to thetripping of individual units. Reset pins ofall the eight flip-flops and sub-parallel en-able (PE) pin 1 of BCD up-/down-counterCD4510 (IC3) are returned to ground via10-kilo-ohm resistor R22, while set pinsof all RS flip-flops are returned to ground

through S8, connect the set terminal ofthe corresponding stage of RS flip-flop to+12V whenever tripping of a specific sub-unit occurs. This makes the output of theassociated flip-flop go high. Thus when-ever a sequence of tripping of subunitsoccurs, the corresponding outputs (1Q to8Q) go high in the order of the tripping ofthe associated subunits.

All the eight Q outputs are connectedto the corresponding latch-enable inputsof BCD latch-cum-decoder-driver ICs(CD4511). These Q outputs are also ORedusing diodes D1 through D8 to activatean audible alarm and also routed to a setof differentiator networks (comprising ca-pacitors C1 through C8 and resistors R2through R9).

A differentiator provides a sharp pulsecorresponding to the tripping of a sub-unit. All such differentiated pulses areORed via diodes D9 through D16 andcoupled to the counter stage formed byIC3 (CD4510, a synchronous up-/down-counter with preset) after amplificationand pulse shaping by transistor amplifierstages built around transistors T2 and T3.These pulses serve as clock to count thenumber of trippings that occurred after areset.

PARTS LISTSemiconductors:IC1, IC2 - CD4043 quad NOR RS latchIC3 - CD4510 BCD up-/down-

counterIC4-IC11 - CD4511 BCD-to-7-segment

latch/decoder/driverT1-T11 - BC547 npn transistorT12-T19 - BC557 pnp transistorD1-D16 - 1N4007 rectifier diodeDIS1-DIS8 - LT543 common-cathode

7-segment displayResistors (all ¼-watt, ±5% carbon, unlessstated otherwise):R1-R11,R13-R38 - 10-kilo-ohmR12, R39-R46 - 1-kilo-ohmR47-R102 - 470-ohmCapacitors:C1-C8 - 0.01µF ceramic diskMiscellaneous:S1-S8 - Push-to-on switch or relay

contacts (N/O)S9 - Push-to-on switchPZ1 - Piezobuzzer

- 12V, 500mA power supplyFig. 1: Block diagram of tripping sequence recorder-cum-indicator



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Let us assume that three units,say, E, H, and A (fifth, eighth,and first), tripped in that orderfollowing a fault.

When the system is reset (be-fore any tripping), the outputs ofall RS flip-flops (1Q through 8Q)are low. This LE* active-lowmakes latches IC4 through IC11transparent and as the counteris preset to 1 (since P1 input ishigh while P2, P3, and P4 arelow) with the help of switch S9,all the latches hold that ‘1’ andtheir decoded ‘b’ and ‘c’ segmentoutputs go high.

However, the common-cath-ode drive is absent in all the 7-segment displays because drivertransistors T4 through T11 arecut off due to the low outputs of

Fig. 2: Schematic diagram of tripping sequence recorder-cum-indicator

Fig. 3: Actual-size, single-side PCB of the main control portion of tripping sequence controller-cum-indicator circuit



indicating that unit E tripped first. Thecorresponding LED5 goes off as transis-tor T16 is cut off. Also, latch IC8 is dis-abled due to logic 1 on its pin 5 and there-fore it does not respond to further changesin its BCD data input. Simultaneously,the buzzer goes on to sound an audiblealarm, indicating the emergency situationat the plant.

The differentiator formed by C5 andR6 responds to the low-to-high transitionof 5Q and generates a short pulse. Thispulse passes through diode D13 and tran-

sistors T2 and T3 and reachesclock pin of counter IC3. Thecounter counts up and its outputbecomes 0010 (decimal 2).

As mentioned earlier, all thedisplay units other than E havethe drive signal on segments a,b, g, e, and c now but are offbecause of the missing common-cathode drive. When the nextsubunit H trips, output 8Q expe-riences a low-to-high transitionand the corresponding display(DIS8) shows digit ‘2’. The abovesequence of operation holds truefor any further subunit tripping—with the displayed digitincrementing by one for each se-quential tripping.

In the prototype, LEDs D17through D24 were fixed below thecorresponding 7-segment displays

pertaining to subunits A through H toprovide a visual indication that these unitsare ready to respond to a tripping.

The circuit works satisfactorily withtwisted-pair wires of length up to 5 metres.In electrically noisy environments, thelength of the cable has to be reduced or ashielded twisted-pair cable can be used.

An actual-size, single-side PCB lay-out for the main control portion of thetripping sequence recorder-cum-indicatorcircuit is shown in Fig. 3 and its compo-nent layout in Fig. 4. The PCB layout forthe indicator set comprising IC4, DIS1,transistors T4 and T12, LED1, etc isshown in Fig. 5 and its component layoutin Fig. 6. The indicator set of Fig. 5 canbe connected to the main PCB of Fig. 3using Bergstrip type SIP (single-inline-pin) connectors as per requirements.

This tripping sequence recorder-cum-indicator circuit can also be used in quizgames to decide the order in which theteams responded to a common question.For this, provide push-to-on switches onthe tables of individual teams and a mas-ter reset to the quiz master. Modify thealarm circuit suitably with a retriggerablemonostable stage so that the audiblealarm stops after a short interval. ❏

all RS flip-flops and hence the displaysare blank. At the same time, the low out-puts of all RS flip-flops (1Q through 8Q)forward bias pnp transistors T12 throughT19 associated with LED1 through LED8of each of the displays. As a result, allthese LEDs glow, indicating no tripping.

Now when unit E trips, output 5Q ofRS flip-flop IC2 goes high to provide thebase drive to common-cathode drive tran-sistor T8. This, in turn, activates DIS5(fifth from left in Fig. 2) to display ‘1’,

Fig. 5: Actual-size, single-side PCB forlatch decoder/driver and display circuit ofone subunit

Fig. 6: Component layout for Fig. 5

Fig. 4: Component layout for Fig. 3

The End

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Electronics for You Projects 2001