Electronics 2 Manuals

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Federal Urdu University of Arts, Science & Technology Islamabad – Pakistan Electrical Engineering

ELECTRONICS - II

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THIRD SEMESTER ELECTRONICS II

BASIC ELECTRICAL & ELECTRONICS LAB

DEPARTMENT OF ELECTRICAL ENGINEERING

Prepared By: Checked By: Approved By:

Engr. M. IDREES Engr. M.Nasim Khan Dr.Noman Jafri

Lecturer (Lab) Electrical, Senior Lab Engineer Electrical, Dean,

FUUAST-Islamabad FUUAST-Islamabad FUUAST-Islamabad




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Name: __________________________________________________

Registration No: __________________________________________

Roll No: _________________________________________________

Semester: _______________________________________________

Batch: __________________________________________________




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CCCOOONNNTTTEEENNNTTTSSS

Exp No List of Experiments

1Verification of the calculated values of a BJT amplifier

2Implementation of or gate using BJT’s

3 Plot the drain characteristics of a JFET

4 JFET fixed bias network

5 JFET self bias network

6 JFET voltage divider bias network

7 JFET as an amplifier

8 Implementation of the buffer amplifier using lm 741

9 Implementation of non inverting amplifier using lm 741

10 Implementation of inverting amplifier using lm 741

11 Implementation of summing inverting amplifier using lm741

12 Determination of input – offset voltage for the lm 741

13 Active low pass filter design using op-amp

14 Active high pass filter

15 Astable operation of the 555-timer

16 Monostable operation of 555-timer




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Experiment No 1

VERIFICATION OF THE CALCULATED VALUES OF A BJT AMPLIFIER:

Hardware:

BJT

DC Power Supply

Multimeter

Capacitor

Resistor Breadboard

Connecting Wires

Circuit Diagram

Procedure:

Construct the circuit as shown in the diagram. Use the multimeter to find out the types of the

transistor and the value of Beta. The conditions for the circuit are set as:IC = 2mA and VCE = VCC/2.Find the value of R C and R B.

The following relationships will be used in the calculations.

R C = VCC-VCE/IC.R B = VCC-VBE/IB.

IB = βIC

Once the values of R B and R C can be calculated, construct the circuit.




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Apply a small AC signal and measure the output signal.

Calculated Values:

Actual Values Used:

Value of RB Value of RC

Result (Input vs. Output)

Input Signal Output Signal

In the graph below, sketch the input and output wave forms.

Teacher’s Signature:

Teacher’s Name: Date:

Values of RB Value of RC




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Experiment No 2IMPLEMENTATION OF OR GATE USING BJT’S

Hardware:

Two Transistors

Power Supplies

ResistorsLED’s

Multimeter Breadboard

Connecting Wires

Circuit Diagram

Prework:

Understand the working of a digital logic OR gate. See how the truth table is constructed and also

understand the outputs of the OR gate.

Procedure:




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Construct the circuit as shown above. Clearly mark the inputs and outputs of the circuit. Apply the

different possible combinations of the inputs to the circuit and construct the truth table. Verify theoperation of the lab circuit.

Truth table for an OR gate:

Input (A) Input (B) Input (Y)

0 0

0 1

1 0

1 1

Results for the Circuit:

Input (A) Input (B) Vout0 0

0 1

1 0

1 1

Draw the circuit diagram of AND gate below.






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Experiment No 3

PLOT THE DRAIN CHARACTERISTICS OF A JFET:

Hardware:

Two MillimetersTwo Resistors

Two Power SuppliesOne JFET

Circuit Diagram

Procedure:

Construct the circuit diagram as shown above. Set VGS = 0V and measure ID = VRD/R D. As VGS =

0V, therefore the resulting drain current is the IDSS withVGS = 0V, Slowly Increase VDD to 5V. Measure VDS and ID. Increase VDD to 10V again measure

VDS and ID. Take couple of more measurements by increasing the value of VDD. Plot the resulting

curve.Repeat the same procedure with VGS = -1V and VGS = -2V.

Value of IDSS for VGS = 0V: (mA)

Table for VGS = 0V




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VDD (V) ID (mA) VDS (V)

05

10

1518

20

Table for VGS = -1V:


05

1015

18

20

Table for VGS = -2 v:


0510

15

18

20

In the graph below, sketch he characteristics curve using the readings taken:




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Teacher’s signature:

Teacher’s name: Date:




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Experiment No 4

JFET FIXED BIAS NETWORK:

Hardware:

JFET transistor 2N4166 (or equivalent), Multimeter, Resistors, Power

Supplies.

Procedure:

For the fixed bias configuration, VGS will be set by an independent dc supply. the vertical lines of

constant VGS will intersect the transfer curve developed from Shockley’s equations.

Construct the network as shown in the figure below and insert the measured value of R D.

Circuit Diagram

Set VGS to zero volts and measure the voltage VRR . Calculate ID from ID = VRD/R D using the valueof R D. Since VGS = 0 V the resulting drain current is the saturation value IDSS. record this value:

(From Measured)IDSS =

Make VGS more and more negative until VRD = 1mA (and ID = VRD/R D = 1µA). Since ID is very

small(ID = 0A),the resulting value of VGS is the pinch-off voltage VP. Record that value:

(Measured)VP =




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Using the values above for IDSS and VP, sketch the transfer curve using Shockley’s equation.If VGS = -1V, determine IDQ from the curve. Show all work, label the straight line defined by VGS as

the fixed bias line.

(Calculated) IDQ =

Set VGS = -1V in your circuit and measure VRD. Calculate IDQ using the measured value of R D

measure the current ID.

(Measured) VRD =

(From Measured) IDQ =

Compare the measured and calculated values of IDQ.


Teacher’s Name: Date




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Experiment No 5JFET FIXED BIAS NETWORK

Hardware:

JFET Transistor 2N4166 (or Equivalent)

Multimeter Resistors

Power supplies.

Procedure :-

For the fixed bias configuration, Vgs will be set by an independent DC supply. The vertical lines of constant Vgs will intersect the transfer curve developed from Shockley’s equations.

Construct the network as shown in the figure below. Insert the measured value of Rd.

Set Vgs to zero volts and measure the voltage Vrr. Calculate Id from Id=Vrd/Rd using the value of

Rd. Since Vgs=0V the resulting drain current is the saturation value Idss.Record this value:

(From measured)Idss=

Make Vgs more and more negative until Vrd=1mV (and Id=Vrd/Rd=1µA). Since Id is very small

(Id=0A), the resulting value of Vgs is the pinch-off voltage Vp. Record that value.

(Measured)Vp=

Using the values above for Idss and Vp, sketch the transfer curve using Shockley’s equation.If Vgs=-1V, determine IDQ from the curve. Show all work. Label the straight line defined by Vgs

as the fixed bias line.

(Calculated)IDQ=




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Set Vgs=-1V in your circuit and measure Vrd. Calculate Idq using the measured value of Rd.Measure the current Id.

(measured) Vrd=

(From measured) Idq=

Compare the measured and calculated values of Idq.






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Experiment No 6

JFET SELF BIAS NETWORK

Hardware:

JFET transistor 2N4166(or Equivalent),Multimeter

ResistorsPower Supplies.

Procedure:-In the self-bias configuration, the magnitude of Vgs is defined by the product of the drain current Id

and the source resistor Rs. The network bias line will start at the origin and intersect the transfer curve at the quiescent(DC) point of operation. The resulting drain current and gate-to-source

voltage can then be determined from the graph by drawing a horizontal and vertical line from the

quiescent point to the axis respectively. Note: The larger the source resistance, the more horizontalthe bias line and the less resulting drain current.

Construct the network as shown in the figure below. Insert the measured value of Rd and Rs.

Draw the self-bias line defined by Vgs=-IdRs on a sheet of graph paper and find the network Q

point. Record the quiescent values of Idq and Vgs below. Label the straight line as the self-bias line.

(Calculated)Idq=

(Calculated)Vgs=

Calculate the values of Vgs,. Vd, Vds, and Vg and record below.

(Calculated)Vgs=




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(Calculated)Vd=

(Calculated)Vs=(Calculated)Vds=

(Calculated)Vg=

Measure the voltage Vgs, Vd, Vds, and Vg and compare with the calculated result.

Wave-Shape:






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Experiment No 7

JFET VOTAGE DIVIDER BIAS NETWORK

Hardware:-JFET transistor 2N4166(or Equivalent)

Multimeter,

ResistorsPower supplies

Procedure:-In the voltage divider configuration the voltage divider voltage and the drop determine Vgs across

the surface source resistance. That is:

Vg=R2Vdd/R1+R2And

Vgs=Vg-IdRs

Construct the network as shown in the figure below. Insert the measured resistor values.

Using the Idss and Vp determine in Experiment No.4, draw the voltage divider bias line on a sheetof graph paper and find the network Q point. Label the resulting straight line as the voltage divider line.

To draw the bias line determines two points as follows and then connect the two points with astraigtht line.

For Vgs=Vg-IdRsIf Id=0mA then Vgs=Vg-(0)Rs=Vg




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And if Vgs=0V then Id=Vg/Rs

Draw a straight line through the above two points and extend it until it intersect the transfer curve.

The coordinates of the intersection determine the quiescent values of Id and Vgs. Record the values

Below:

(calculated)Idq=

(calculated)Vgsq=Calculate the theoretical values of Vd, Vs and Vds and record below:

(calculated)Vd=

(calculated)Vs=(calculated)Vds=

Measure the voltages Vgsq, Vd, Vs and Vds and record below:

(Measured)Vgsq=(Measured)Vd=

(Measured)Vs=(Measured)Vds=

Calculate Idq from the measured voltages and compare with the calculated values. Idq can be foundusing

Idq=Vdd-Vd/Rd






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Experiment No 8

JFET AS AN AMPLIFIER

Hardware: JFET transistor2N4166(or Equivalent),Multimeter

Resistor

Power supplies.

Purpose of the ExperimentThe pupose of this experiment is to investigate the operation of a common-source JFET transistor amplifier.

Some Circuit Notes:

The JFET is a general pupose, n-channel, JFET(k246gr or Equivalent).We will assume Idss=10mA,Vgs=-4V and gm=2.5mS in the prelab analysis.

PrelabFor the circuit shown, predict the following DC parameters: Id, Vd, Vg and Vds, using the bias line

technique. Recall that the operating point of the JFET can be found graphically from the

intersection of the JFET Tran conductance or transfer equation( wwhich relates Id to Vgs) with thecircuit bias line equation (Vgs=-Ids*Rs). (A very rough approximation for this circuit is that Vgs~-

2V).

Draw an AC equivalent circuit, and predict the voltage gain(Av), input impedence Zi, and outputimpedence Zo, assuming all capacitors act as AC short. Also draw the composite waveform

expected at test pointsA,B,C andVo in the circuit, assuming the input signal Vin is a100mV peak,

1kHz sine wave.

Also draw a basic black box model (or Equivalent) for a voltage amplifier, consisting of an input

impedence Zi, a dependant voltage source, and an output impedence Zo. (Recall that Zi appears

across the input of the amplifier, and Zo appears in series with the output of the amplifier’sdependant voltage source). Refer to this simple equivalent circuit for the procedures that follow.

You can measure Zi by inserting a test resistor e.g 1MΩ in series with the signal input to the

amplifier, and measuring how much of the AC generator signal actually appears at the input of the

amplifier.

You can determine Zo as follow: temporarily remove the load resistor, and measure the unloaded

AC output voltage. Then replace the load and re-measure the Ac output voltage. Use thesemeasurements to determine Zo.




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Lab MeasurementsIn lab circuit measurements:-

Build the circuit shown and verify all of the predictions above. First check the DC quiescent

voltages with no AC input signal. If these are reasonably close to your predictions, connect theca

input signal to the input of the amplifier. Use DC coupling and dual-trace on the oscilloscope asappropriate to observe the wave forms seen at various points. Is the output signal close to expected?

How do the waveforms seen at the FET’s drain and the output compare? What kind of waveform if any is seen at test point B? Then temporarily remove Cs and re-measure the output voltages did it

decrease as expected? Note that if you increase the input signal Vo will increase along with the non-

linear distortion created by the variation in FET trans-conductance gm. You can reduce this non-linear distortion by adding a small swamping resistor of say 100 ohms at the source. What price is

paid for this benefit?

Comments and Conclusions

Compare your results with your prefab calculations. Explain any significant discrepancies. Alsoexplain clearly the purpose or function of the various components in the circuit e.g what is the

purpose of the source bypass capacitor? Why does a swamping resistor reduce the non-linear

distortion and at what cost? How does this circuit generally compare to a common-emitter

amplifier?




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Figure 1 – Common JFET Amplifier Source

Results

Draw input and output waveform:



Input signal voltage Output signal voltage Gain




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Experiment No 9

IMPLEMENTATION OF THE BUFFER AMPLIFIER USING LM741

HardwareLM 741 & Oscilloscope

Procedure:Construct the buffer amplifier circuit as shown below. Connect a 1kHz, 3

V p-p sine wave to the input and use the oscilloscope to observe the input and output signals.Compute the voltage gain.




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Explain briefly the operation of the buffer amplifier ?

What was the voltage gain of amplifier?




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Voltage Gain

Draw input and output waveform:






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Experiment No 10

IMPLEMENTATION OF THE INVERTING AMPLIFIER USING LM 741

Hardware:

LM 741 & oscilloscope

Procedure:

Construct the inverting amplifier as shown below. Calculate the resistors needed to produce a voltage gain of 15. Connect a 1kHz, 0.5 V p-p sine wave to the input and use the

oscilloscope to observe the input and output signals. Compute the voltage gain.




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V out = Vi (-R2/R1) R stability = (R1 * R2 )/ (R1+R2)

Explain briefly the operation of inverting amplifier?

What was the gain of the amplifier?

Gain :




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Sketch the observed input and output waveform below :






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Experiment No 11

IMPLEMENTATION OF THE SUMMING INVERTING AMPLIFIER BY USING LM741

Hardware :LM 741 & oscilloscope

Procedure:Construct the Summing Inverting amplifier as shown below. Calculate the resistors such

that the input V1 has gain of 5 and the input V2 has a gain of 10. V1=1.0 VDC and V2=0.1 Vp-p

sine wave. Use the oscilloscope to observe the input and output signals. Compute the voltage gain.




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V out = -( V1 [R3/R1] + V2 [R3/R2] )

R stability = The smaller of ( R1*R3 ) / ( R1 + R3 ) or ( R2* R3 ) / ( R2 + R3 )






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Experiment No 12

DETERMINATION OF INPUT OFFSET VOLTAGE USING OP-AMP

Hardware741 OP-AMP

Resistors (10k, 100k, 220k (2), 100(2), 560)

Procedure

a) Connect the circuit in Figure 1. Again make sure that you have powered the chip with the dual

power suplly (15v). This is called an inverting amplifier circuit. It will be analyzer in more detail inthe next lab. For this test the input to the amp is grounded. Measure the output voltage. This is the

output offset voltage.

Figure 12: Offset Voltage Measurement Circuit




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b) The input offset voltage of the amplifier can be calculated by dividing the output offset voltage

by the gain (1000).

c) Replace the 100k resistor with a 220k resistor and repeat step a) and b). Note that the gain this

time is 2200.

d) Repeat a & b with 1k resistor.e) Report your results.

f) To eliminate this offset voltage connects the stationary ends of a 5k pot to pins 1 and 5. Nowconnect the wiper of the pot to the-15v supply. Use the pot to zero the output of the amp this is how

offset voltage is eliminated. (See Figure 2)

In your experiments due to pot sensitivity, you may not get a full zero on the output. A 10 mVvoltage at the output will be sufficient.

Figure 2: Elimination of offset voltage




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Results and observations

Connect Vcc, Vee, and ground then connect the 5v supply between the inverting and Non-inverting

input of741

Reverse the polarity of 5V supply

Question:

What is Vout now?

Question:

Are the results what you expect from the open loop gain?

Measure Vout when the input is grounded.

Compute the input offset voltages.






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Experiment No 13

Hardware

OP-Amp

Resistors

Capacitor

Active Low Pass FilterThe most common and easily understood active filter is the Active Low Pass Filter. Its principle of operation and frequency response is exactly the same as that for the previously seen RC low pass

filter, the only difference being it uses an op-amp for amplification and gain control. The simplest

form of a low pass active filter is to connect an inverting or non-inverting amplifier, the same as

those discussed in the Op-amp tutorial, to the basic RC low pass filter as shown.First-order Low Pass Butterworth Filter

This 1st-Order low pass Butterworth type filter, consists simply of a passive RC filter connected to

the input of a non-inverting operational amplifier. The frequency response of the circuit will be the

same as that of the passive RC filter, except that the amplitude of the output signal is increased bythe pass band voltage gain of the amplifier and for a non-inverting amplifier this given as: 1 +

R2/R1.

For a non-inverting amplifier circuit, the magnitude of the voltage gain for the filter is given as afunction of the feedback resistor (R2) divided by its corresponding input resistor (R1) value and is

given as:

Voltage Gain for a First-order Low Pass Filter

Where:




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AF = the Passband Gain of the filter, (1 + R2/R1)

ƒ = the Frequency of the Input Signal in Hertz, (Hz)ƒc = the Cut-off Frequency in Hertz, (Hz)

When dealing with filter circuits the magnitude of the pass band gain of the circuit is generally

expressed in Decibels or dB as a function of the voltage gain, and this is given as:

Magnitude of Voltage Gain in (dB)

Frequency Gain(Vo/Vin)






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Experiment No 14

HARDWARE:

Capacitor

Resistor OP-AMP

Active High Pass Filter

A 1st-Order (single-pole) Active High Pass Filter as its name implies, attenuates low frequenciesand passes high frequency signals. It consists simply of a passive filter section followed by a non-

inverting operational amplifier. The frequency response of the circuit is the same as that of the

passive filter, except that the amplitude of the signal is increased by the gain of the amplifier and for a non-inverting amplifier the value of the pass band voltage gain is given as 1 + R2/R1.

First-order High Pass Butterworth Filter

This 1st-Order high pass Butterworth type filter consists simply of a passive filter followed by a

non-inverting amplifier. The frequency response of the circuit is the same as that of the passivefilter, except that the amplitude of the signal is increased by the gain of the amplifier.

For a non-inverting amplifier circuit, the magnitude of the voltage gain for the filter is given as a

function of the feedback resistor (R2) divided by its corresponding input resistor (R1) value and is

given as:Voltage Gain for a First-order High Pass Filter




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Where:

AF = the Pass band Gain of the filter, (1 + R2/R1)ƒ = the Frequency of the Input Signal in Hertz, (Hz)

ƒc = the Cut-off Frequency in Hertz, (Hz)

When dealing with filter circuits the magnitude of the pass band gain of the circuit is generally

expressed in Decibels or dB as a function of the voltage gain, and this is given as:Magnitude of Voltage Gain in (dB)

For a 1st-Order filter the frequency response curve of the filter increases by 20dB/Decade or

6dB/Octave up to the determined cut-off frequency point which is always at -3dB below the

maximum gain value. As with the previous filter circuits, the cut-off or corner frequency (ƒc) can befound by using the same formula:

The corresponding phase angle or phase shift of the output signal is the same as that given for the

passive RC filter and leads that of the input signal. It is equal to +45o at the cut-off frequency ƒcvalue and is given as:

A simple 1st-Order active high pass filter can also be made using an inverting operational amplifier

configuration as well, and an example of this circuit design is given along with its corresponding

frequency response curve. A gain of 40dB has been assumed for the circuit.

Frequency Gain(Vo/Vin)






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EXPERIMENT 15

A STABLE OPRATION OF 555 TIMER

555/556 Astable

An Astable circuit produces a 'square wave', this is adigital waveform with sharp transitions between low

(0V) and high (+Vs). Note that the durations of the

low and high states may be different. The circuit iscalled an Astable because it is not stable in any state:

the output is continually changing between 'low' and

'high'.The time period (T) of the square wave is the time for

one complete cycle, but it is usually better to consider

frequency (f) which is the number of cycles per second.

T = time period in seconds (s)

f = frequency in hertz (Hz)R1 = resistance in ohms ( )

R2 = resistance in ohms ( )

C1 = capacitance in farads (F)

The time period can be split into two parts: T = Tm +Ts

Mark time (output high): Tm = 0.7 × (R1 + R2) × C1Space time (output low): Ts = 0.7 × R2 × C1

Many circuits require Tm and Ts to be almost equal; this is achieved if R2 is much larger than R1.For a standard astable circuit Tm cannot be less than Ts, but this is not too restricting because the

output can both sink and source current. For example an LED can be made to flash briefly with long

gaps by connecting it (with its resistor) between +Vs and the output.This way the LED is on during Ts, so brief flashes are achieved with R1 larger than R2, making Ts

short and Tm long. If Tm must be less than Ts a diode can be added to the circuit as explained

under duty cycle below.

555 astable output, a square wave

(Tm and Ts may be different)

555 astable circuit

1.4T = 0.7 × (R1 + 2R2) × C1 and f =

(R1 + 2R2) × C1




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Choosing R1, R2 and C1:

R1 and R2 should be in the range 1k to 1M . It is best to choose C1 first because capacitors areavailable in just a few values.

Choose C1 to suit the frequency range you require

(use the table as a guide).Choose R2 to give the frequency (f) you require.

Assume that R1 is much smaller than R2 (so that

Tm and Ts are almost equal), then you can use:

0.7R2 =

f × C1

Choose R1 to be about a tenth of R2 (1k min.)unless you want the mark time Tm to be

significantly longer than the space time Ts.

If you wish to use a variable resistor it is best tomake it R2.

If R1 is variable it must have a fixed resistor of at least 1k in series

(this is not required for R2 if it is variable).

Astable operation

With the output high (+Vs) the capacitor C1 is charged by current flowing through R1 and R2. The

threshold and trigger inputs monitor the capacitor voltage and when it reaches 2/3Vs (threshold

voltage) the output becomes low and the discharge pin is connected to 0V.The capacitor now discharges with current flowing through R2 into the discharge pin. When the

voltage falls to 1/3Vs (trigger voltage) the output becomes high again and the discharge pin isdisconnected, allowing the capacitor to start charging again.

This cycle repeats continuously unless the reset input is connected to 0V which forces the output

low while reset is 0V.An Astable can be used to provide the clock signal for circuits such as counters .

555 Astable frequencies

C1R2 = 10k

R1 = 1k

R2 = 100k

R1 = 10k

R2 = 1M

R1 = 100k

0.001µF 68kHz 6.8kHz 680Hz

0.01µF 6.8kHz 680Hz 68Hz

0.1µF 680Hz 68Hz 6.8Hz

1µF 68Hz 6.8Hz 0.68Hz

10µF 6.8Hz0.68Hz(41 per min.)

0.068Hz(4 per min.)




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A low frequency Astable (< 10Hz) can be used to flash an LED on and off, higher frequency flashes

are too fast to be seen clearly. Driving a loudspeaker or piezo transducer with a low frequency of less than 20Hz will produce a series of 'clicks' (one for each low/high transition) and this can be

used to make a simple metronome.

An audio frequency Astable (20Hz to 20kHz) can be used to produce a sound from a loudspeaker or

piezo transducer. The sound is suitable for buzzes and beeps. The natural (resonant) frequency of most piezo transducers is about 3 kHz and this will make them produce a particularly loud sound.








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Beware that electrolytic capacitors leak charge which substantially increases the time period

if you are using a high value resistor - use the formula as only a very rough guide!

For example the Timer Project should have a maximum time period of 266s (about 4½

minutes), but many electrolytic capacitors extend this to about 10 minutes!

Monostable operation

The timing period is triggered (started)

when the trigger input (555 pin 2) is

less than 1/3 Vs, this makes the output

high (+Vs) and the capacitor C1 starts

to charge through resistor R1. Once the

time period has started further trigger

pulses are ignored.

The threshold input (555 pin 6)

monitors the voltage across C1 and

when this reaches 2/3 Vs the timeperiod is over and the output becomes

low. At the same time discharge (555

pin 7) is connected to 0V, discharging the capacitor ready for the next trigger.

The reset input (555 pin 4) overrides all other inputs and the timing may be cancelled at any

time by connecting reset to 0V, this instantly makes the output low and discharges the

capacitor. If the reset function is not required the reset pin should be connected to +Vs.

Power-on reset or trigger

It may be useful to ensure that a monostable circuit is reset or triggered

automatically when the power supply is connected or switched on. This is

achieved by using a capacitor instead of (or in addition to) a push switch

as shown in the diagram.

The capacitor takes a short time to charge, briefly holding the input close

to 0V when the circuit is switched on. A switch may be connected in

parallel with the capacitor if manual operation is also required.

This arrangement is used for the trigger in the Timer Project. Power-on reset or

trigger circuit




Edge-triggering:

If the trigger input is still less than 1/3 Vs at the end of the time

period the output will remain high until the trigger is greater than

1/3 Vs. This situation can occur if the input signal is from an on-off switch or sensor.

The Monostable can be made edge triggered, responding only to

changes of an input signal, by connecting the trigger signal through

a capacitor to the trigger input. The capacitor passes sudden

changes (AC) but blocks a constant (DC) signal. For further

information please see the page on capacitance. The circuit is

'negative edge triggered' because it responds to a sudden fall in the

input signal.

The resistor between the trigger (555 pin 2) and +Vs ensures that the trigger is normally high

(+Vs).



edge-triggering circuit

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