Electronic Devices and Circuits

ES154 Lecture Notes

Harvard > DEAS > EECS

> ES154 HOME

ES154 Home

Handouts

Lectures

Homework Assignments

Laboratory Assignments

Sample Exams

Course-Related Links

Useful Information

Lecture Notes:

No. Lecture No. Lecture

1Course Info and Overview 11

Integrated Circuit Design (Current Mirrors)

2Review of Circuit Analysis 12

Differential Amplifiers

3Amplifier Models and Freq Response 13

High-Gain Differential Amplifiers

4Operational Amplifiers and Op Amp Circuits 14

High-Frequency Analysis (OCT)

5Introduction to Semiconductors 15 Feedback and Stability

6PN Junctions and Diode Circuits 16

Overview and Examples of Op Amp Design

7MOSFET Devices and Circuits

8Single-Stage MOSFET amps and High-Freq Model

9Bipolar Junction Transistor

10Single-Stage BJT amps and High-Freq Model

2003 Edited by: Gu-Yeon Wei (December 06, 2004 )

http://www.deas.harvard.edu/courses/es154/lectures.html11/12/2004 17:25:52

ES154 Lecture 1

Fall 2004 1

Wei 1

ES 154Electronic Devices and Circuits

Fall 2004

Gu-Yeon WeiDivision of Engineering and Applied Sciences

Harvard [email protected]

ES 154 - Lecture 1Wei 2

Course Objectives

The objective of this course is to provide you with a comprehensive understanding of electronic circuits and devices. The course presents a basic introduction to physical models of the operation of semiconductor devices and examines the design and operation of important circuits that utilize these devices. We will look at how to design circuits using discrete components and as integrated circuits.

Due to the varying background of students in the class, we will start with a review of some basics (of circuit theory), review the operation and characteristics of semiconductor devices (namely, BJTs and MOSFETs), and build up to more advanced topics in analog circuit design.

Due to time constraints, we will concentrate on analog circuits,amplifiers in particular. Digital CMOS circuits and VLSI design issues are covered more extensively in CS148.

ES154 Lecture 1

Fall 2004 2


Course Material

The lecture notes and the textbook, Electronic Circuit Design by Comer & Comer (C&C) will be the principle reference materials used in the class. The notes will cover specific material in thetextbook that I find important and interesting. The notes will also include material (for more detail) not covered in the textbook. You are responsible for all of the material in the notes and sections in C&C that are assigned as reading. Assigned reading will be indicated at the beginning of each set of lecture notes.

Supplementary reading may also be assigned. They will usually be in the form of supplementary web pages found on the course web site or sections in reference books that can be found in theGordon McKay Library.


Additional Reading

To provide additional information and/or an alternative explanation of the material in the notes and C&C, supplemental reading from other textbooks will be included in the notes. While these readings are not required, they are often helpful in understanding the material.

References (found in G. McKay Library) Electric Circuits, Nilsson and Riedel, Prentice, 6th Ed., 2001.

Electric Circuit Analysis, Johnson et al, Prentice Hall, 1997.

The Art of Electronics, Horowitz and Hill, Cambridge, 1989.

Analysis and Design of Analog Integrated Circuits, Gray et al, Wiley, 2001.

The Design of CMOS Radio-Frequency Integrated Circuits, Lee, Cambridge, 1998.

Device Electronics for Integrated Circuits, Muller and Kamins, Wiley, 1986.

Design with Operational Amplifiers and Analog Integrated Circuits, Franco, McGraw Hill, 2002.

Design of Analog CMOS Integrated Circuits, Razavi, McGraw Hill, 2001.

ES154 Lecture 1

Fall 2004 3


Course Information

Lectures Tues and Thurs 10 11:30AM in MD 221 Lecture notes will be handed out in class and will be available on the course web page

(www.deas.harvard.edu/courses/es154) Homework

Assigned on Tuesdays and due the following Tuesday in class You allotted a total of three late days that you can use throughout the semester.

Lab Maxwell Dworkin B129 and B123 (in the basement) There will be several experimental laboratory assignments throughout the semester.

You may be required to complete pre-lab assignments prior to going into lab. Lab write-ups due with homework assignments on Tuesdays

Final Project There will be final project due at the end of reading period You have the option to work on anything that pertains to the material taught in this

class, i.e., analog circuits Exams

Take-home midterm Final exam


Homework Grading

One additional requirement that I have is for each of you to participate in at least one homework grading session.

Several reasons why they are useful Forces you to revisit the homework assignment at least once Provides insight into alternate ways of thinking about a

problem Shows you how difficult (and easy) it can be grade ones

homework write-up Pizza and drinks!

Organization We will provide the solutions and point distribution TF will schedule them

ES154 Lecture 1

Fall 2004 4


Class Participation and Office Hours

ASK QUESTIONS!!! I will make an effort to periodically stop and see if everyone

understands the lecture material. However, you should stop me at any time if you have any questions.

If you are confused about something, chances are so is someone else.

OFFICE HOURS You are also encouraged to stop by our office hours. Or, if

you are around on the 3rd floor of MD and you see my door open, stop by and say hello. My office is MD333.

Take advantage of office hours. Its a resource that too many students seem to neglect.

Wei 8

Lecture 1:

A Brief Overview of Electronic Devices and Circuits



ES154 Lecture 1

Fall 2004 5


Overview

Reading C&C: Chapter 1

Supplemental Reading Lee: Chapter 1 A nonlinear history of radio Nilsson: Chapters 1-4 (basic circuit analysis)

BackgroundThis lecture is intended to give you a brief overview of what you can expect to learn from this course. There are additional interesting tidbits of historical trivia sprinkled into the lecture for fun. At the end, we review basic circuit theory that you shouldve all seen before in a physics course or ES50. If not, do the Nilsson reading above. It should be pretty straight forward if you have seen the material before.


Why Electronics?

Why use electronics Electrons are easy to move / control

Easier to move/control electrons than real (physical) stuff Discovered by J.J. Thomson in 1898

Move information, not things phone, fax, WWW, etc. Takes much less energy and $

Development of modern electronics has been driven by Communication Computation

ES154 Lecture 1

Fall 2004 6


Communication Alternatives


Origins of Radio

Marconi generally regarded as the inventor of the radio in 1896 Used a spark gap transmitter (used by Heinrich Hertz to verify

Maxwells prediction that electromagnetic waves exist and propagate with a finite velocity) and Eduardo Branlys coherer as the receiver.

Demonstrated transatlantic wireless communication in 1901

ES154 Lecture 1

Fall 2004 7


Computing Alternatives

Babbage Difference Engine

Abacus

Mechanical Cash Register


BIG Electronic Computers

ENIAC (Electrical Numerical Integrator And Calculator developed by Mauchly

and Eckert in 1946 17,468 vacuum tubes,

70,000 resistors, 10,000 capacitors, 1500 relays, 6000 manual switches, and 5 million solder joints; covered 1800 sq. feet of floor space; weighed 30 tons; consumed 160kW

Built to calculate ballistic trajectories (ballistic firing tables)

ES154 Lecture 1

Fall 2004 8


Early Electronic Devices

Building electronics: Started with tubes, then miniature

tubes Transistors, then miniature

transistors Bardeen, Brattain, and Shockley

invent the first germanium point-contact transistor at Bell Labs in 1947 (they received a Nobel prize for this discovery).Built an amplifier

Components were getting cheaper, more reliable but: There is a minimum cost of a

component (storage, handling ) Total system cost was proportional

to complexity


Beginning of Modern Devices

Then along came the Integrated Circuit (IC) Invented by Jack Kilby of Texas Instruments in 1958 (received a

Nobel Prize in Physics 2000)

Independently, Robert Noyce of Fairchild Semiconductor had an idea for unitary circuits

ES154 Lecture 1

Fall 2004 9


3mm

4mm

Modern ICs

The IC industry has been able to continue to reduce the size of transistors and increase the number of devices that can be integrated onto a single device

intel 4004 (71, 2.3K transistors, 10-um technology, 108-kHz)

Itanium 2

20021-GHz130-W0.18-um

221M transistors

421-mm2(~20 x 21 mm)


Where Do We Start?

Ostensibly from the beginning. Volts and Amps (basic circuit analysis)

Independent voltage sources and current sources

Dependent sources Passive elements resistors, capacitors,

inductors Operational Amplifier (op amp)

A general purpose, closed-loop amplifier used to implement linear functions. Its performance and function are defined by the external components (feedback network or loop) surrounding it.

First introduced in early 1940s Originally comprised of vacuum tubes Used for computation (i.e., addition, subtraction,

multiplication, etc.)

ES154 Lecture 1

Fall 2004 10


Whats inside these op amps?

Brief introduction to semiconductors Conductors vs. Insulators vs.

Semiconductors P-type, N-type

PN Junctions Diodes and diode circuits

Bipolar Junction Transistors (BJT) How they work Different types of BJT circuits

Metal Oxide Semiconductor Field Effect Transistors (MOSFET) How they work Different types of MOSFET circuits


Modeling the Operation of Circuits

Frequency Response Analysis Circuits operate over a limited frequency range of the incoming and

output signal We will construct models for the circuits and look at gain and

bandwidth relationships w.r.t frequency

ES154 Lecture 1

Fall 2004 11


Feedback

Once weve looked at the frequency response of circuit operation, it becomes important to spend some time on basic feedback theory. At this point, we shouldve seen feedback at work in op amp circuits, but we didnt worry about frequency response and stability b/c we assumed an ideal amplifier.

We will spend some time on open-loop and closed-loop response characteristics of circuits with feedback.

Then, we will investigate stability and compensation techniques for extending the bandwidth of amplifiers


CAD Tools

We will rely on two sets of tools to help us design and verify circuits in various homework and lab assignments.

Circuit Simulations HSPICE an analog circuit simulator SUE Schematic User Environment is a graphical tool for

drawing circuits and then creating a netlist from HSPICE MATLAB

Mathematical tool for frequency response analysis and create pretty graphs

ES154 Lecture 1

Fall 2004 12


SUE looks like.


Review of Circuit Basics

Some basic circuit elements (and their symbols) that we will be using extensively in the class

Examples from Nilsson, Electric Circuits, 3rd ed., 1991

Ideal Independent Sources

i = constantv =

v = constant i =

Resistor

v = i R

R C

Ideal Dependent Sources

i = C dv/dt

L

v = L di/dt

Capacitor Inductor

v

i

v

i

v

i

ES154 Lecture 1

Fall 2004 13


Kirchhoffs Laws

Kirchhoffs Current Law (KCL): The algebraic sum of all of the currents at a node in a circuit equals zero.

Kirchhoffs Voltage Law (KVL): The algebraic sum of all of the voltages around any closed path in a circuit equals zero.

R1

R2v1

vs v2

is i2

i1

KVL: vs - v1 - v2 = 0

KCL: is - i1 = 0i1 + i2 = 0


Example with a Dependent Source

Heres a quick example of a circuit that we will see later when we model the operation of transistors. For now, lets assume ideal independent and dependent sources

RC

RE

VCC

iCC

iE

iC

V0iB

i2

i1 R1

R2

iB

We can write the following equations:i1 + iC - iCC = 0

iB + i2 - i1 = 0

iE - iB - iC = 0

iC = iBV0 + iERE - i2R2 = 0

-i1R1 + VCC - i2R2 = 0

ES154 Lecture 1

Fall 2004 14


Resistive Circuits

Series vs. Parallel Resistors

R1 R2 R3

R4

R5R6R7

isv Req_seriesv

is

v Req_parallelis

R1 R2 R3is


Divider Circuits

Current and voltage divider circuits using resistors

R1

R2

vs

i

vo

is R1 R2v

i1 i2

ES154 Lecture 1

Fall 2004 15


How can we measure current and voltage?

dArsonval meter movement consists of a movable coil placed in the field of a permanent magnet. Current in the coil creates a torque in the coil, which rotates until torque is balanced by restoring spring. Designed so deflection of the pointer is directly proportional to current in the movable coil.

(from Nilsson, 3rd edition)


Ammeter, Voltmeter, and Ohmmeter

DC Ammeter: The shunting resistor RA and dArsonval movement form a current divider

DC Voltmeter: Series resistor RV and dArsonval movement form a voltage divider

Ohmmeter: Measures the current to find the resistance

d'Arsonval movementRAAmmeter terminals

d'Arsonval movement

RV

Voltmeter terminals

d'Arsonval movement

RbRunknown

ES154 Lecture 1

Fall 2004 16


Wheatstone Bridge

Used for precise measurements One example is to measure resistance of Runknown

Adjust R3 until imeter = 0, then Runkown = R2R3/R1

V

R1 R2

R3 Runkown

imeter


Source Transformations

Source transformations can be a useful way to simplify circuits Thevenin and Norton Equivalents

Can represent any sources made up of sources (both independent and dependent) and resistors

Converting to a Thevenin equivalent

Rs

vs i = vs / Rsi

Rs

vsv v = vs

ES154 Lecture 1

Fall 2004 17


Thevenin and Norton

Thevenin and Norton are equivalent from the terminals

But, if I gave you two black boxes and said one is a Thevenin and one is Norton, could you tell them apart? What would you do?

Rs

vs is Rp


Maximum Power Transfer

It is often important to design circuits that transfer power from a source to a load. This will be an important concept when we are designing amplifiers. There are two basic types of power transfer: Efficient power transfer (e.g., power utility) Maximum power transfer (e.g., communication circuits)

Transfer an electrical signal (data, information, etc.) from the source to a destination with the most power reaching the destination. There is limited power at the source and power is small so efficiency is not as much of a concern.

Assume there is a source that can be represented as a Thevenin equivalent circuit. Determine RL so that the maximum power is transferred.

source RT

vT RLiL

ES154 Lecture 1

Fall 2004 18


Superposition

A distinguishing characteristic of linear systems is the principle of superposition:

Whenever a linear system is excited, or driven, by more than oneindependent source of energy, we can find the total response by finding the response to each independent source separately and then summing the individual responses.

Mathematically, A system specified by T[] is linear if for all a1, a2, x1(n), and x2(n),

we have:

Technique: short circuit voltage sources and open circuit current sources calculate for one source at a time and then sum


Example of Superposition

vs = 3 V is = 2 A

R1 = 8

R2 = 4 i2 = ?

vs = 3 V

R1 = 8

R2 = 4 i2'

is = 2 A

R1 = 8

R2 = 4 i2''

Find i2 using superposition

ES154 Lecture 1

Fall 2004 19


Next Lecture

We will continue to review basic concepts in electric circuits. In particular, we will review circuits containing inductors, capacitors, and resistors, and some analytical tools to deal with them in the frequency domain.

ES154 Lecture 2

Fall 2004 1

ES154 Lecture 2Wei 6

Step Response of an RC Circuit

Lets find the step response of an RC circuit using the following example circuit.

Summing the current around node A gives

t = 0

vCi

R Cis

A

ES154 Lecture 3

1

Wei 1

Lecture 3

Amplifier Models and Frequency Response



ES154 - Lecture 3Wei 2

Overview

Reading Chapter 3

BackgroundIn this course, we will be spending a lot of time on looking at how to use and build amplifiers. So, it is important to understand what an amplifier basically is and what its characteristics are. This lecture will review some basic amplifier models and then see how we can characterize their operation across different frequencies by creating Bode plots.

ES154 Lecture 3

2


Basic Amplifier Model

Characteristics Amplify signals that vary about zero volts Powered by one or more DC voltages (power supply voltages) Requires proper DC biasing to operate Amplifies small incremental input signal and produces a magnified

signal at the output with some gain


Practical Example

DC bias voltage Vbias sets DC operating point and results in DC output bias VQ (quiescent voltage)

Small input signal vin is amplified

ES154 Lecture 3

3


DC Blocking

The DC operating point of the input signal may not be the same as the desired DC input voltage for the amplifier. May also be true for the output. We would like to set the DC operating point for the amplifier independently.

Use coupling capacitors (or DC blocking caps), Cc1 and Cc2, to block out the DC component of input and output signals DC input and output operating points set by the amplifier We later see how this affects the amplifier gain vs. frequency


Example

Example of a single-stage amplifier (using a transistor) C blocks DC component of

signals from vin DC operating point of amplifier

input is set by R1 and R2(resistor divider)

Equivalent circuit for the amplifier for small signals (small-signal model) for midband frequencies C is a short Model MOSFET as a voltage-

controlled current source

ES154 Lecture 3

4


Gain Elements

There are different types of gain elements Voltage, current, transconductance, transimpedance Lets focus on voltage gain elements for now

Characteristics Ideal voltage amplifier has infinite input impedance and zero

output impedance Real amplifiers have finite input and output impedance

Coupling caps used to isolate DC voltages of amplifiers input and output, but cause low-frequency gain rolloff

Parasitic capacitances (inside amplifier circuitry) cause high-frequency gain rolloff


Ideal Voltage Amplifier

Model amplifier with a voltage-controlled voltage source (VCVS) VCVS has infinite input impedance and zero output impedance Gain is set by A

ES154 Lecture 3

5


Non-Ideal Voltage Amplifier w/ Coupling Caps

Still use VCVS to model amplifier, but add resistors and capacitors to model non-idealities Finite input impedance (Cin and Rin) Finite output impedance (Rout and Cout)

Coupling caps (Cc1 and Cc2) are large (F range) while parasitic caps (Cin and Cout) are small (pF range) This allows us to create different (simpler) models depending on

frequency of signals


Midband Model

For midband frequecies, model Coupling capacitors (Cc1 and Cc2) as short circuits Parasitic capacitors (Cin and Cout) as open circuits

How do the parasitic resistors affect gain?

Usually, Rin >> Rs and Rout

ES154 Lecture 3

6


Low-Frequency Model

At low frequencies Cannot ignore coupling caps Ignore parasitic caps

How do the coupling caps affect gain?


High-Frequency Model

a

b

vabA*vab

Rs

RLvin

c

d

voutRin

Rout

Cin Cout

At high frequencies Coupling caps are shorts Cannot ignore parasitic caps

What happens to the gain?

ES154 Lecture 3

7


Poles and Zeros of H(s)

Rewriting a rational function as the ratio of two factored polynomials enables us to identify the poles and zeros of H(s). Later, we will see what poles and zeros mean for circuits. For now, here is the general form

The roots of the denominator are poles () and the roots of the numerator are zeros ().

The poles and zeros can have both real and imaginary components and we can visualize them as points on a complex s-plane.

X-axis = real Y-axis = imaginary


Bode Plots

Plotting the frequency response of H(s) can be a very useful tool for analyzing circuit behavior. A Bode plot is a graphical technique that gives a feel for the frequency response of a circuit.

Later, we will use MATLAB to create accurate Bode plots from transfer function equations

But, we should know the basics behind how Bode plots are created Lets start with a simple example assume real, first-order Poles and Zeros

Substituting j for s gives

To understand the response of H(s) or H(j), we need to look at its magnitude |H(j)| and phase (j) with respect to frequency .

ES154 Lecture 3

8


Bode Plots Primer

First, rearrange the equation into a standard form.

Then, solve for |H(j)| and ()

90o comes from the pole at =0.


Amplitude Plots

Amplitude plot involves the multiplication and division of factors. To simplify, we present the amplitude in terms of a logarithmic value decibels (dB).

Amplitude of H(j) in dB is

So, going back to our example, the amplitude in dB is

The best way to plot the effects of these poles and zeros is to plot them individually and then put it together.

We will estimate the plots with straight line approximations each pole causes the plot to slope downward at 20dB/dec or (-6dB/oct) each zero causes the plot to slope upward at +20dB/dec or (+6dB/oct)

* Note: the book uses octaves

ES154 Lecture 3

9


Amplitude Plots (2)

1. 20log10K is a straight line since it is independent of 2. For the zero, at z1, the plot increases at 20dB/dec


Amplitude Plots (3)

3. The plot of 20log10() is a straight line that decreases at 20dB/dec and intersects 0dB at =1

4. For the pole, the plot is a flat line until p1 and then decreases at 20dB/dec

ES154 Lecture 3

10


Amplitude Plots (4)

Now, put them all together (multiplication = addition in dB).

(1)

(2)

(3)

(4)


More Accurate AdB Plot

We can make the straight-line approximation plots more accurate for first order poles and zeros by correcting the amplitudes at the corner frequency of the poles and zeros.

At the corner,

ES154 Lecture 3

11


Phase Plots

We can again use the straight-line approximation for phase plots.

Some rules phase associated with constant = 0 phase associated with poles or

zeros at origin (w=0) is +/- 90 degrees

phase associated with first order poles or zeros not at origin is: < corner /10 phase = 0 > 10 * corner phase = +/- 90

degrees = corner phase = +/- 45

degreesNOTE: + for zeros and - for poles


Phase Plots (2)

Putting them together

ES154 Lecture 3

12


Bode Plots of Complex Poles and Zeros

Complex Poles and Zeros make the Bode plots a little more challenging to draw, but we can still make some approximations.

Complex poles and zeros always come in conjugate pairs

If < 1, then roots are complex. If 1, can factor into ( s+p1 )( s+p2 ) and plot as we did before.

The complex poles and zeros come in pairs and so: Causes +/- 40dB/dec changes in slope in magnitude plots Causes +/- 180 degree phase shifts also.


Complex Poles (Amplitude)

Changes the actual amplitude plots depending on the damping coefficient .

ES154 Lecture 3

13


Complex Poles (Phase)

It also changes the phase plot


Summary of Bode Plot Characteristics

Given a transfer function that is a ratio of a product of factors, where the factor is in the form ( s+a ) factors in the numerator correspond to zeros

causes amplitude plot to slope upward at 20dB/dec starting at the zero corner frequency

causes +90 degree phase shift after the zero corner frequency factors in the denominator correspond to poles

causes amplitude plot to slope downward at -20dB/dec starting at the pole corner frequency

causes -90 degree phase shift after the pole corner frequency a can be a complex number but must come in conjugate pairs

Bode plots work best for poles and zeros spaced apart by a 10 in frequency b/c then there is little interaction between them.

ES154 Lecture 3

14


Example: Low-Frequency Response

Lets look at how the coupling capacitor (Cc1) at the input affects the low-frequency response of the amplifier

p sets the lower cutoff frequency


Example: High-Frequency Response I

Consider the effect of Cin (assume Cout = 0)

This circuit has a single-pole response and the upper 3dB bandwidth (upper cutoff frequency) is at p

ES154 Lecture 3

15


Example: High-Frequency Response II

If we now also consider Cout, the gain has the following form

If p1

ES154 Lecture 3

16


Miller Equivalent Circuit

The bridging impedance can be simplified with an equivalent circuit

Av

Zy

AvZy

1-AvZy

1-1/Av


Capacitive Miller Effect

The Miller equivalent circuit is easier to solve Weve already solved this circuit

Equivalent circuit

ES154 Lecture 3

17


Multistage Amplifier

Often a single amplifier stage does not provide enough amplification Can achieve higher gain by cascading amplifier stages Must consider the effects of input and output impedances If coupling caps are used between stages, how do you calculate the

lower cutoff frequency? With parasitic capacitances, how do you calculate the upper cutoff

frequency? Later, we will see how cascading multiple amplifier stages can lead to

wider overall bandwidth (higher upper cutoff frequency)

ES154 Lecture 4

1

Wei 1

Lecture 4

Operational Amplifiers and Op Amp Circuits




Overview

Reading Chapter 4

Supplemental Reading Sedra&Smith: Ch. 2

BackgroundArmed with our circuit analysis tools and basic understanding ofamplifiers, lets now look at operational amplifiers (op amps). Op amps were initially constructed out of vacuum tubes, then discrete transistor components. With the advent of the integrated circuit, op amp ICs came out in the 60s (e.g., from Analog Devices Inc.). They are extremely useful because they are versatile and one cando almost anything with op amps. We will begin by looking at an ideal version of the op amp and see how they are useful. Then, we will investigate various non-idealities of real amplifier designs and how they affect op amp circuits.

ES154 Lecture 4

2


Op Amp Terminals

At a minimum, op amps have 3 terminals: 2 input and 1 output. An op amp also requires dc power to operate. Often, the op amp requires both

positive and negative voltage supplies (V+ and V-).

1

2

3

op amp symbol (we will use most often)

1

2

3

V-

V+

op amp symbol with power supply connections


Ideal Op Amp

The op amp is designed to sense the difference between the voltage signals applied to the two input terminals and then multiply it by some gain factor A such that the voltage at the output terminal is A(v2-v1).

One of the input terminals (1) is called an inverting input terminal denoted by - The other input terminal (2) is called a non-inverting input terminal denoted by + The gain A is often referred to as the differential gain or open-loop gain We can model an ideal amplifier as a voltage-controlled voltage source (VCVS)

1

2

A(v2-v1)

v2

v1 i1=0

i2=0

3

ES154 Lecture 4

3


Ideal Op Amps Characteristics

Ideal op amp characteristics: Does not draw input current so that the input impedance is infinite

(i.e., i1=0 and i2=0) The output terminal can supply an arbitrary amount of current (ideal

VCVS) and the output impedance is zero The op amp only responds to the voltage difference between the

signals at the two input terminals and ignores any voltages common to both inputs. In other words, an ideal op amp has infinite common-mode rejection.

The frequency response of an ideal op amp is flat for all frequency. In other words, it amplifies signals of any and all frequencies by the same amount A.

Lastly, A is or can be treated as being infinite. Useful b/c we can easily specify a closed-loop gain (using feedback) as will see later.

We will see later that real op amps do not have the characteristics above, but we strive to make them behave as close to an ideal op amp as possible.


Op Amps in the Inverting Configuration

Lets look at an op amp in an inverting closed-loop configuration.

There are two resistors R1 and R2 R2 is called the (negative) feedback

resistor and also closes the loop. (A resistor between terminals 2 and 3 would be a positive feedback resistor.)

Closed-Loop Gain G Defined,

Assume A is infinite and the amp is trying to produce a finite voltage on terminal 3. Then, the voltage difference between terminals 1 and 2 should be very small, v2-v10 and Ainf. By definition

So, we say there is a virtual short between the two terminals (1 and 2) and that terminal 1 is a virtual ground since terminal 2 is grounded.

R1

R2

vI vO

1

2

i1

i2

i = 03

ES154 Lecture 4

4


Inverting op amp contd

Use KCL to solve for the close-loop gain.

We can adjust the closed-loop gain by changing the ratio of R2 and R1 If the input is a sine wave, then the output is a sign wave phase-shifted by 180 degrees The closed-loop gain is (ideally) independent of op amp open-loop gain A (if A is large

enough) and we can make it arbitrarily large or small and of desired accuracy depending on the accuracy of the resistors.

This is a classic example of what negative feedback does. It takes an amplifier with very large gain and through negative feedback, obtain a gain that is smaller, stable, and predictable. In effect, we have traded gain for accuracy. This kind of trade off is common in electronic circuit design as we will see more of later.

R1

R2

vI vO

1

2

i1

i2

i = 03


R1

R2

vI vO

1

2

i1

i2=i1

i = 0-vOA

Finite Open-Loop Gain

Since infinite A is not physically possible, what happens when A is finite?

Instead of a virtual ground, assume input terminal 1 has potential vO/A

As A infinity, G -R2/R1 and the voltage at terminal 1 goes to 0 the virtual ground assumption we made earlier

To minimize the effects of open-loop gain on G, we want

ES154 Lecture 4

5


Input Resistance

Assuming an ideal op amp (open-loop gain A = ), in the closed-loop inverting configuration, the input resistance is R1.

To make Rin high, need to make R1 high which is not practical What happens when A = finite? From the last slide

Solve for Rin = vI/i1


Output Resistance

Now, lets look at the output resistance To solve for output resistance, zero out the input and figure out the resistance

looking into the output terminal

Roa is usually small and so Rout is negligible when A is large

R1

R2

Roa Rout

i1

i2

v2

v1 vt

A(v2-v1) = -Av1

ES154 Lecture 4

6


Model of Closed-Loop Inverting Amplifier

We can model the closed-loop inverting amplifier (with A = ) with the following equivalent circuit using a voltage-controlled voltage source

Rin= R1vI

RO= 0

-(R2/R1)vI


Inverting Configuration with General Impedances

Lets replace R1 and R2 in the inverting configuration with impedances Z1(s) and Z2(s). We can write the closed-loop transfer function as

By placing different circuit elements into Z1 and Z2, we can get interesting operations. Some examples

Integrator Differentiator Summer UnityGain Buffer

Vi Vo

1

2

Z2

Z1

ES154 Lecture 4

7


Inverting Integrator

We replace Z2 (the negative feedback impedance) with a capacitor and Z1 is a resistor.

How about in the time domain?

Vi Vo

1

2

R

C

(log scale)

|Vo/Vi| (dB)

1/RC

-20db/decvi

vC


Integrator contd

While the DC gain in the previous integrator circuit is infinite, the amplifier itself will saturate. To limit the low-frequency gain to a known and reliable value, add a parallel resistor to the capacitor.

What does the magnitude response look like?

Vi Vo

1

2

R1

C

R2

ES154 Lecture 4

8


Differentiator

Vi Vo

1

2

C

R

20dB/dec

1/RC

AdB

(log scale)

How would you set a nominal low-frequency gain?


Weighted Summer

You can also building a summer.

vo

1

2

R1 Rfv1

R2v2

Rnvn

ES154 Lecture 4

9


Non-Inverting Configuration

To avoid the inversion, shown is a non-inverting configuration

Whats the input impedance?

Now what happens as R1 infinity and Rf 0

Unity-Gain Amplifier Useful for buffering between stages

vo

1

2

R1

Rf

vI

vo

1

2vI


Difference Amplifier

Now, we can combine the non-inverting amplifier and inverting amplifier configurations to beable to take a difference between two inputs. You can use superposition or brute force it

vo

R1

Rf

v1

v2R2

R3

v+

v-

ES154 Lecture 4

10


So far, we have assumed infinite gain and infinite bandwidth (BW) for the amplifier, but that is not reality. Amplifiers have finite gain and BW. Heres an example of the open-loop gain vs. frequency plot of an amplifier.

Notice that the gain can be very high at low frequency, but starts to roll off at a low frequency also. They are also frequency compensated to roll off at -20dB/dec (or a single pole) to guarantee that op amp circuits will be stable (more on this later in the semester when we talk about the guts of building amplifiers and feedback stability).

Finite Open-Loop Gain and BW


Finite Open-Loop Gain and BW contd

We can represent frequency response characteristics of this amplifier as we did for a single-time constant low-pass filter.

For frequencies much greater than b ( >> b) we can approximate the gain as

t is called the unity-gain BW. So the gain can be represented as

assuming b is very small (low)

So given this equation, we can find the gain at any frequency (assuming a single-pole magnitude response)

ES154 Lecture 4

11


Frequency Response of Closed-Loop Amplifiers

Lets look at the closed-loop gain equation we derived earlier for for an amplifier with finite op-amp open-loop gain A.

if A0 >> 1+R2/R1, then we can approximate the equation as

Therefore, the closed-loop gain has a response that rolls off at 20dB/dec at a frequency, -3dB, that is a function of the gain set by the input and feedback resistors.

Plot the magnitude response vs. different R2/R1


Gain-Bandwidth Tradeoff

RF

R1

vinvout

With real amplifiers, there is a tradeoff between gain and BW For multi-stage amplifiers, the maximum BW can be achieved for a

desired gain when the BW of each stage is equal. For identical stages, the BW for each stage is equal when gain per stage is equal.

Gain dB

0 dB

Open Loop

RF/R1 large

RF/R1 small

RF/R1 = 1

b t = A0 b

A0

ES154 Lecture 4

12


Gain BW Product (GBW)

The product of gain and BW is a very useful value when designing amplifiers and amplifier circuits

Provides a measure of how good you amplifier is (want higher GBW) GBW is constant anywhere along the plot above for a particular design


BW for Multi-Stage Amps

We define the bandwidth of an amplifier to be

Now, consider multiple amplifier stages (iterative stage amp)

Assume we use identical stages and we can write the expression for gain of each stage as:

ES154 Lecture 4

13


BW for Multi-Stage Amps (2)

Then, the overall gain is the product of the gain for each stage

The upper cutoff frequency is when the overall gain magnitude drops by 3bB or

and

so

Notice the overall -3dB BW shrinks with more stages (BW shrinkage)


Optimizing BW

So, do we want to cascade a large number of low-gain amplifiers (w/ high BW) or a small number of high-gain amps (w/ low BW)?

To optimize BW for a specified gain, we need to balance two trends Smaller number of stages = less BW shrinkage Higher gain per stage = lower BW per stage

For n 3, we can approximate BW shrinkage as

If we use identical stages, then we know that each stages has

ES154 Lecture 4

14


Optimizing BW (2)

Now, we can find the optimum number of stages (n) by differentiating the expression for the overall BW with respect to n and solving for when the derivative = 0. To simplify the math, let Ao = ek (k = ln Ao)

So, you first need to figure out the optimal n for a desired Aoand then calculate the gain for each stage and the resulting BW you get due to BW shrinkage.


Output Saturation

So far, we have been looking at the amplification that can be achieved for relatively small (amplitude) signals. For a fixed gain, as we increase the input signal amplitude, there is a limit to how large the output signal can be. The output saturates as it approaches the positive and negative power supply voltages. In other words, there is limited range across which the gain is linear.

From Sedra&Smith

ES154 Lecture 4

15


Slew Rate (BW limited)

Another source of nonlinear distortion comes from the limited slew rate of the amplifier. Remember, we modeled the amplifier as a single time constant circuit. Thus, an input signal sees attenuation beyond the BW of the op amp.

Lets look at the time domain response of the circuit by taking the inverse Laplace transform of the amplifiers transfer function multiplied by a step with magnitude Vin.

The output does not change instantaneously. Rather, we see an exponential response that slews the output up. The maximum output slew rate is defined as the derivative of the output voltage at t=0.


Voltage Offsets

The circuit implementation of amplifiers is subject to a variety of imperfections during its fabrication. This imperfection can be due to physical imbalances that occurs even at DC (or zero frequency).

To understand this problem, assume the two inputs to the amplifier are connected together. Instead of a zero output, in real circuits, we get a non-zero positive or negative voltage at the output.

One can model the imbalance by adding a DC voltage offset on one of the terminals. This is an input offset voltage (VOS) in the amplifier which can be compensated for with a voltage of equal magnitude and opposite polarity to make the output voltage go to zero.

Vout = 0

Vout = 0VOS

ES154 Lecture 4

16


Input Bias Currents

In real amplifiers, the two input terminals sometimes have to be supplied with dc currents called input bias currents. They can be represented by two current sources IB1 and IB2. Furthermore, there can be mismatch between these currents IOS.

We can reduce the output voltage effects from the input bias current by adding a resistor into the positive terminal. However, mismatches between IB1 and IB2(IOS = IB1 - IB2) results in an offset voltage VOS=IOSRf.

IB2

IB1

IB2

IB10V

IB1

0

VO=IB1Rf

Rf

R1

ES154 Lecture 5

1

Wei 1

Lecture 5

Semiconductor Basics


Harvard University

Wei 2

Semiconductors

Reading: Chapter 5 Supplemental Reading:

Streetman, Solid State Electronic Devices, Ch. 3, App. IV Sedra&Smith Ch. 3

Background The electronics industry today is based on semiconductors, due to

our well-developed ability to affect the electronic properties of the solid.

Understanding semiconductors allows us to understand the functioning of circuit elements, as well as grasp future possibilities and limitations.

These notes were originally created by Kathy Aidala (TF in 2002)

ES154 Lecture 5

2

Wei 3

Band Theory

Analogy to atoms From chemistry, we are familiar with the idea of electron

clouds orbiting the nucleus. The energy of the different clouds, or levels, is discrete.

Adding energy can cause an electron to jump into a higher level. In the same way, an electron can lose energy and emit a specific wavelength of light when falling to a lower energy level. (Atomic spectra)

Pauli Exclusion Principle: no two electrons can occupy the same exact state at the same time. This is why electrons fill the energy levels in the way they do.

Valence electrons are the electrons bound farthest from the nucleus

Wei 4

Band Theory

What is a crystalline solid? A volume of atoms covalently bonded in a periodic structure with

well defined symmetries. Example: Silicon

Face-Centered Cubic (FCC) structure Group-IV elements (4 valence electrons)

Where are the electrons? Covalent bonds share electrons. The e- are delocalized, they can

move around the crystal, orbit any atom, as long as there is an open state (cannot violate Pauli Exclusion)

This forms discrete energy bands. Solving SchroedingersEquation in the specific periodic structure reveals these bands.

ES154 Lecture 5

3

Wei 5

Specifics of Crystals

In an atom, electrons orbit in their shell, at a given energy. In a crystal, many electrons occupy a small energy band. There is a

width to the energy band, which is why Pauli Exclusion is not violated. Within the band, electrons can move easily if there are available states,

because the difference in energy is tiny. Between bands, electrons must get energy from another source,

because the band gap can be significant.

Atom SemiconductorEvalence

Econduction

EFermiEgap

Wei 6

Fermi Energy

The highest energy an electron reached if you were to fill the solid with the intrinsic number of electrons at absolute zero. (No added thermal energy)

Meaningful! There is a sea of electrons sitting beneath this energy. If you bring two solids together with different Fermi energies,

the electrons will move around to reach an equilibrium. (Foreshadowing: PN junction)

If you try to put a lower energy electron into a solid (at absolute zero) with a higher Fermi energy, it wont fit. It cannot be done due to Pauli Exclusion.

If the highest energy electron exactly fills a band, the Fermi Energy is near the center of the bands.

ES154 Lecture 5

4

Wei 7

Beyond 0 K: Fermi-Dirac Statistics

Fermi Energy: The energy state whose probability of being occupied is exactly 1/2 .

Electrons obey Fermi-Diracstatistics, which describe the probability of an electron being present in an allowed energy state.

Note that if there are no states at a given energy (i.e., in the band gap) there will be no electrons, even if there is finite probability.

Wei 8

Different Types of Solids

Fermi level falls inside the energy band. Easy for electrons to move around

Fermi level falls between bands, with a large band gap.

SiO2: 9 eV.

Fermi level falls between bands, with a small band gap.Si: 1.11 eV, Ge:0.67 eV,

GaAs: 1.43

ES154 Lecture 5

5

Wei 9

Transport in Semiconductors

Electrons that get excited into the conduction band carry current. The space left behind in the valence band is called a hole.

Holes also conduct current. In reality, its the movement of all the other electrons. The hole allows this motion. (Bubbles)

Holes can easily travel up in energy. Holes have positive charge. Current flows in the same direction as the holes move. Holes have different mass (effective mass) and mobility compared

to electrons.

Econduction

EFermiEgap

Evalence

Wei 10

Intrinsic Semiconductor Summary

Fermi Level: All solids are characterized by an energy that describes the highest energy electron at 0K, the level which has1/2 probability of being occupied at finite temperature.

Semiconductors: A solid with its Fermi level exactly betweenbands, with a band gap small enough to be overcome at room temperature.

Both electrons and holes carry current.

Econduction

EFermiEgap

Evalence

ES154 Lecture 5

6

Wei 11

Controlling the properties of aSemiconductor

Doping Replace some Si atoms with atoms that

do not have four valence electrons.

These atoms will have an extra electron (group IV), or an extra hole (group III).

Doping increases the number of carriers and changes the Fermi level.

Silicon: 4 valence electrons.Each Si atom bonds to four others.

e-

e-

Wei 12

Phosphorus Doping (N-type)

Phosphorus has 5 valence electrons. P atoms will sit in the location of a Si atom in the lattice, to avoid

breaking symmetry, but each will have an extra electron that does not bond in the same way.

These electrons form their own band. Exactly where depends on the amounts of the two materials.

This new band is located closer to the conduction band, because these extra electrons are easier to excite (and can move around more easily)

EFermiEconduction

Evalence

ES154 Lecture 5

7

Wei 13

Boron Doping (P-type)

Boron has 3 valence electrons. B will sit at a lattice site, but the adjacent Si atoms lack an electron to

fill its shell. This creates a hole. These holes form their own energy band. This band is located closer to the valence band, because these extra

holes are easy to excite down into the valence band.

EFermi

Econduction

Evalence

Wei 14

Doping

N-type materials: Doping Si with a Group V element, providing extra electrons (n for negative) and moving the Fermi level up.

P-type materials: Doping Si with a Group III element, providing extra holes (p for positive) and moving the Fermi level down.

EFermiEvalence

EFermi

Econduction

Evalence

Econduction

N-type P-type

ES154 Lecture 5

8

Wei 15

Equilibrium Concentrations: electrons

N(E) f(E)Carrier concentration

Wei 16

Equilibrium Concentrations: holes

N(E) f(E)

Carrier concentration

ES154 Lecture 5

9

Wei 17

Intrinsic Semiconductors

In intrinsic semiconductors (no doping) the electron and hole concentrations are equal because carriers are created in pairs

This allows us to write

As the Fermi level moves closer to the conduction [valence] band, the n0 [p0] increases exponentially

Wei 18

Temperature Dependence of Carrier Concentrations

The intrinsic concentration depends exponentially on temperature. The T3dependence is negligible.

Ionization: only a few donors [acceptors] are ionized.

Extrinsic: All donors [acceptors] are ionized

Intrinisic: As the temperaureincreases past the point where it is high enough to excite carriers across the full band gap, intrinsic carriers eventually contribute more.

At room temp (300K), the intrinsic carrier concentration of silicon is:

ES154 Lecture 5

10

Wei 19

Moving Carriers (i.e., current)

There are two mechanisms by which mobile carriers move in semiconductors resulting in current flow Drift

Carrier movement is induced by a force of some type Diffusion

Carriers move (diffuse) from a place of higher concentration to a place of lower concentration

Wei 20

Drude Model of Conductivity

Electrons are assumed to move in a direct path, free of interactions with the lattice or other electrons, until it collides.

This collision abruptly alters its velocity and momentum. The probabilty of a collision occuring in time dt is simply dt/, where is

the mean free time. is the average amount of time it takes for an electron to collide.

The current is the charge*number of electrons*area*velocity in a unit of time. For j = current density, divide by the area. The drift velocity (vd) is a function of charge mobility (n) and electric field (E).

At equilibrium, there is no net motion of charge, vavg = 0. With an applied electric field, there is a net drift of electrons [holes]

against [with] the electric field resulting in an average velocity. This model allows us to apply Newtons equations, but with an effective

mass. The effective mass takes the interactions with the rest of the solid into account.

ES154 Lecture 5

11

Wei 21

Drude Model

Consider an electron just after a collision. The velocity it acquires before the next collision will be acceleration*time

We want the average velocity of all the electrons, which can be obtained by simply averaging the time, which we already know is .

We can also write this in terms of mobility:

Taking both holes and electrons into account, we end up with thefollowing formula for current density due to drift.

Wei 22

- Hall Effect

Moving electrons experience a force due to a perpendicular B field

An electric field develops in response to this force.

The sign of this field perpendicular to the flow of current determines the carrier type.

Density and mobility can also be calculated.

ES154 Lecture 5

12

ES154 Lecture 5 Intro to SemiconductorsWei 23

Diffusion

Diffusion results in a net flux of particles from the region of higher concentration to the region of lower concentration This flux leads to current (movement of charged particles) Magnitude of current depends on the gradient of concentration

Dn is the diffusivity coefficient

Diffusivity is related to mobility by Einsteins relationship

Typical values for Si at room temp Dn = 34 cm2/s and Dp = 13 cm2/s

Wei 1

Lecture 6PN Junctions and Diode Circuits


Harvard University

ES154 - Lecture 6: PN Junctions and Diode CircuitsWei 2

Overview

Reading: Chapter 5 Supplementation Reading:

Streetman, Solid State Electronic Devices, Ch. 5 Sedra&Smith Ch. 3.1~5

Background Now that we have learned the semiconductor basics, we will look at

one of the simplest semiconductor devices that can be built by abutting two pieces of semiconductors (silicon) each doped with different dopants. Given that the two pieces are n-type and p-type semiconductors, the device is called a PN junction. The interaction between the two material types at the boundary (or junction) results in some very interesting and useful properties.

A PN junction is one way to build diodes. We will take a brief look at what can be built with diodes.


Ideal Diode

Lets begin with an ideal diode and look at its characteristics

From Sedra&Smith


Characteristics of PN Junction Diodes

Given a semiconductor PN junction we get a diode with the following current-voltage (IV) characteristics.

Turn on voltage based on the built-in potential of the PN junction

Reverse bias breakdown voltage due to avalanche breakdown (on the order of several volts)

From Sedra&Smith


The forward bias current is closely approximated by

where VT is the thermal voltage (~25mV at room temp)k = Boltzmans constant = 1.38 x 10-23 joules/kelvinT = absolute temperatureq = electron charge = 1.602 x 10-19 coulombsn = constant dependent on material, between 1 and 2 (we will assume n = 1)IS = scaled current for saturation current that is set by dimensions

Notice there is a strong dependence on temperature We can approximate the diode equation for i >> IS

In reverse bias (when v


Mobile Carriers

Now lets look at physical mechanisms from which the current equations come. Weve seen that holes and electrons move through a

semiconductor by two mechanisms drift and diffusion

In equilibrium, diffusion current (ID) is balanced by drift current (IS). So, there is no net current flow. Drift current comes from (thermal) generation of hole-electron pairs (EHP).


Band Diagrams

When the P-type material is contacted with the N-type material, the Fermi levels must be at equilibrium.

Band bending: The conduction and valence bands bend to align the Fermi levels.

Electrons diffuse from the N-side to the P-side and recombine with holes at the boundary. Holes diffuse from the P-side to the N-side and recombine with electrons at the boundary. There is a region at the boundary of charged atoms called the space-charge region (also called the depletion region b/c no mobile carriers in this region)

An electric field is created which results in a voltage drop across the region called the barrier voltage or built-in potential

P-type N-type

Ei

Efn

Ec

Ev

Ei

Ec

Ev

Efp

n

p

Ei

Ef

Ec

Ev

E-field

qV0


What happens when P-type meets N-type?

Holes diffuse from the p-type into the n-type, electrons diffuse from the n-type into the p-type, creating a diffusion current. The diffusion equation is given by

Once the holes [electrons] cross into the n-type [p-type] region, they recombinewith the electrons [holes].

This recombination strips the n-type [p-type] of its electrons near the boundary, creating an electric field due to the positive and negative bound charges.

The region stripped of carriers is called the space-charge region, or depletion region.

V0 is the contact potential that exists due to the electric field.

Some carriers are generated (thermally) and make their way into the depletion region where they are whisked away by the electric field, creating a drift current.


Equilibrium motion of carriers

In equilibrium, diffusion current is balanced by drift current. Moreover, the built-in potential (electric field) stops the diffusion by imposing a larger barrier to holes and electrons.

The diffusion current is determined by the # of carriers able to overcome the potential barrier. The drift current is determined by the generation of minority carriers (in the depletion region) which then move due to the E-field. This generation is determined by the temperature.

At equilibrium, the two components are equal


E-field and Built-in Potential

Diffusion is balanced by drift due to bound charges at the junction that induce an E-field.

Integrating the bound charge density gives us the E-field

Integrating the E-field gives the potential gradient


Junction Built-In Voltage

With no external biasing, the voltage across the depletion region is:

Typically, at room temp, V0 is 0.6~0.8V How does V0 change as temperature increases?

Interesting to note that when you try to measure the potential across the pn junction terminals, the voltage measured will be 0. In other words, V0 across the depletion region does not appear across the diode terminals. This is b/c the metal-semiconductor junction at the terminals counteract and balance V0 . Otherwise, we would be able to draw energy from an isolated pn junction, which violates conservation of energy.


P-type N-type

0-xp xn

Wdepl

-xp xn

E(x)

E0

x

Width of Depletion Region

The depletion region exists on both sides of the junction. The widths in each side is a function of the respective doping levels. Charge-equality gives:

The width of the depletion region can be found as a function of doping and the built-in voltage

s is the electrical permittivity of silicon = 11.70 (units in F/cm)


pn Junction in Reverse Bias (1)

Lets see how the pn junction looks with an external current, I (less than IS), applied

electrons leave the n side and holes leave the p side depletion region grows V0 grows IDdecreases

in equilibrium, there is a VR across the terminals (greater than V0)

If I > IS, the diode breaks down

As the depletion region grows, the capacitance across the diode changes.

Treating the depletion region as a parallel plate capacitor


V- +

p n

Reverse bias: apply a negative voltage to the p-type, positive to n-type.

Increase the built-in potential, increase the barrier height.

Decrease the number of carriers able to diffuse across the barrier.

Diffusion current decreases. Drift current remains the same (due to

generation of EHP). Almost no current flows. Reverse leakage

current, IS, is the drift current, flowing from n to p.

Reverse Bias (2)


Reverse Breakdown

Zener Breakdown: The bands bend so much that carriers tunnel through the depletion region. This will occur in heavilydoped junctions when the n-side conduction band appears opposite the p-side valence band.

Avalanche Breakdown: carriers have enough energy to ionize an electron-hole-pair (EHP), creating more highly energetic carriers, which collide to form more EHPs, which creates


pn Junction in Forward Bias (1)

Now lets look at the condition where we push current through the pn junction in the opposite direction.

Add more majority carriers to both sides shrink the depletion region lower V0diffusion current increases

Look at the minority carrier concentration lower barrier allows more carriers to be

injected to the other side

Note that np0 = ni2/NA and pn0 = ni2/ND This comes from two equations


Excess minority carrier concentration is governed by the law of the junction(proof can be found in device physics text). Lets look at holes.

The distribution of excess minority hole concentration in the n-type Si is an exponentially decaying function of distance from xn

where Lp is the diffusion length (steepness of exponential decay) and is set by the excess-minority-carrier lifetime, p. The average time it takes for a hole injected into the n region to recombine with a majority carrier electron

The diffusion of holes leads to the following current density vs. x


In equilibrium, as holes diffuse away, they must be met by a constant supply of electrons with which they recombine. Thus, the current must be supplied at a rate that equals the concentration of holes at the edge of the depletion region (xn). Thus, the current due to hole injection is:

Current due to electrons injected into the p region is

Combined


Minority Carrier Concentration and Current Densities in Forward Bias

Current is due to the diffusion of holes and electrons. Current is dominated by holes or electrons depending on the relative doping of NAvs. ND

Is NA > ND or NA


Forward Bias (2)

V+ -

p n

Forward bias: apply a positive voltage to the p-type, negative to n-type.

Decrease the built-in potential, lower the barrier height.

Increase the number of carriers able to diffuse across the barrier

Diffusion current increases Drift current remains the same Current flows from p to n


Review of Biasing

Applying a bias adds or subtracts to the built-in potential.

This changes the diffusion current, making it harder or easier for the carriers to diffuse across.

The drift current is essentially constant, as it is dependent on temperature.


Photodiodes

Diodes have an optical generation rate. Carriers are created by shining light with photon energy greater than the bandgap.

One wants large depletion widths and long diffusion lengths, as it is only in these areas that excited carriers will make it across the junction.

Photodetector: operate in third quadrant. Compromise between speed and junction width leads to a p-intrisic-n junction, where carriers will be rapidly swept across, and can quickly diffuse in the p and nregions.

Solar Cell: operating in the fourth quadrant generates current, though small.


Light Emitting Diodes

When electrons and holes combine, they release energy.

This energy is often released as heat into the lattice, but in some materials, known as direct bandgap materials, they release light.

Engineering LEDs can be difficult, but has been done over a wide range of wavelengths.

This illustration describes the importance of the plastic bubble in directing the light so that it is more effectively seen.


Diode Circuits

Look at the simple diode circuit below. We can write two equations:


Diode Small-Signal Model

Some circuit applications bias the diode at a DC point (VD) and superimpose a small signal (vd(t))on top of it. Together, the signal is vD(t), consisting of both DC and AC components

Graphically, can show that there is a translation of voltage to current (id(t))

Can model the diode at this bias point as a resistor with resistance as the inverse of the tangent of the i-vcurve at that point

And if vd(t) is sufficiently small then we can expand the exponential and get an approximate expression called the small-signal approximation (valid for vd < 10mV)

So, the diode small-signal resistance is


Perform the small signal analysis of the diode circuit biased with VDD by eliminating the DC sources and replacing the diode with a small signal resistance

The resulting voltage divider gives:

Separating out the DC or bias analysis and the small-signal analysis is a technique we will use extensively


Rectifier Circuits

One of the most important applications of diodes is in the design of rectifier circuits. Used to convert an AC signal into a DC voltage used by most electronics.


Simple Half-Wave Rectifier

Only lets through positive voltages and rejects negative voltages

This example assumes an ideal diode

What would the waveform look like if not an ideal diode?


Full-Wave Rectifier

To utilize both halves of the input sinusoid use a center-tapped transformer


Bridge Rectifier

Looks like a Wheatstone bridge. Does not require a center-tapped transformer.

Requires 2 additional diodes and voltage drop is double.


Peak Rectifier

To smooth out the peaks and obtain a DC voltage, add a cap across the output

Wei 1

Lecture 7

MOSFET Devices and Circuits



ES154 - Lecture 7 - MOSFETsWei 2

Overview

Reading Chapter 6

Supplemental Reading Sedra&Smith: Chapter 5.1~5.4

Background Now that we have a basic understanding of semiconductors and PN

junctions, we will build on that knowledge to look at a transistor device called a MOSFET. This is the first of two transistors types that we will be studying in this course. Most modern ICs are built using these transistors. While they are commonly used to implement digital circuits, we will look at their analog characteristics and talk about how to build amplifiers with them.We begin with the physical structure and a qualitative understanding of how MOSFETs operate. We will derive some current-voltage equations for the transistor. We will also use band diagrams to provide some theoretical rigor to our initial qualitative understanding. Then, we will look at some non-ideal characteristics of the transistor. Lastly, we will analyze the DC operation of MOSFETs.


Enhancement-Type MOSFET

Most widely used field effect transistor (enhancement type) Lets look at its structure and physical operation

3 terminal device (gate, source, drain) Additional body (or bulk) terminal (generally at DC and not used for signals) Two types:

nMOS and pMOS


nMOS Transistor

Four terminal device: gate, source, drain (and body) No connection between the gate and drain/source (separated by oxide) Voltage on gate controls current flow between source and drain

Gate-oxide-body stack looks like a capacitor Gate and body are conductors SiO2 (oxide) is a good insulator Called Metal-Oxide-Semiconductor (MOS) capacitor

Gate no longer made out of metal, but poly


Basic nMOS Operation

Body is commonly tied to ground (0V) When the gate is at a low voltage (VG = 0):

P-type body is at low voltage Source-body and drain-body diodes are OFF (reverse bias)

Depletion region between n+ and p bulk No current can flow, transistor is OFF


Basic nMOS Operation Contd

When the gate is at a high voltage Positive charge on gate of MOS capacitor Negative charge attracted to oxide in the body (under the gate) Inverts channel under the gate to n-type Now current can flow through this n-type channel between source and drain Transistor is ON


pMOS Transistor

Similar to nMOS, but doping and voltages reversed Body tied to high voltage (Vdd) Gate low: transistor is ON

inverted channel of positively charged holes Gate high: transistor is OFF Bubble indicates inverted behavior of the pMOS


MOSFET in More Detail

An ON transistor passes a finite amount of current Depends on terminal voltages and mode of operation We will derive current-voltage (I-V) relationships

To enhance our understanding of MOS devices, lets take quick aside to look the characteristics of a MOS capacitor and at banddiagrams


Aside MOS Capacitor

Gate and body form a MOS cap Operating modes

Accumulation

Depletion Repels positive charge

Inversion Inversion layer forms under

the gate


Aside MOSFET Band Diagrams

A more rigorous look at MOSFETs requires us to again use band diagrams energy diagram drawn relative to the vacuum level at equilibrium (no voltage applied) metal work function, M, energy required to completely free an electron from the metal electron affinity, , is the energy between the conduction band and vacuum level

Vacuum Level

M

EfEi

metal

oxide

semiconductor

N-type semiconductor


Aside Block Charge diagram

Provides information about the charge distribution inside a MOS structure no charges at equilibrium when bias is applied, charge appears within the metal and semiconductor at

the interfaces to the oxide voltage drop across the oxide and there is an electric field due to the +Q and Q

charge separated by the oxide

We will use band diagrams and block charge diagrams to better understand how MOS devices work

position

charge

M O S

+Q

-Q


Aside Applying Bias

Look at a pMOS (n-type bulk) device and see how applying a bias on the gate affects the band and block charge diagrams

Accumulation(VG > 0)

M O S

+Q

-Q

Depletion(small VG < 0)

M O S

+Q

-Q

Onset ofInversion(VG = Vt)

M O S

+Q

-Q

Inversion(VG < Vt)

M O S

+Q

-Q

holes


Terminal Voltages

The modes of operation depend on terminal voltages Vg, Vd, and Vs

Vgs = Vg - Vs Vgd = Vg - Vd Vds = Vd - Vs = Vgs - Vgd

Source and drain are symmetric diffusion terminals (transistors are symmetric devices)

By convention, source is the terminal at the lower (higher) voltage for the nMOS(pMOS) transistor

Hence, Vds > 0 nMOS body is grounded. First assume that

source is grounded as well Three regions of operation

Cutoff Linear Saturation


nMOS Cutoff Mode

Vgs < Vt and so there is no channel Source tied to body at 0V Need a channel for current to flow Ids = 0


nMOS Linear Mode

Vgs > Vt and so a channel forms underneath the gate Vt is the threshold voltage that sets when a channel forms

Current flows from d to s Electrons flow from s to d

Ids increases with Vds Similar to a linear resistor


nMOS Saturation Mode

Vds > Vgs Vt and channel pinches off at the drain side b/c Vgd < Vt at the drain side (no channel at drain side)

We say current saturates and Ids is independent of Vds Transistor operates similar to a current source


I-V Characteristics

In the Linear region of moderation, Ids depends on How much charge is in the channel How fast the charge is moving


Channel Charge

MOS structure looks like a parallel plate capacitor while operating in inversion Gate-oxide-channel


Carrier Velocity

Charge is carried by e-

Carrier velocity v is proportional to the lateral E-field between source and drain

Time for carriers to cross the channel is


nMOS Linear I-V

Combine the channel charge and velocity to find the current flow Current = amount of charge in the channel / time it takes the

carriers to get across the channel


nMOS Saturation I-V

If Vgd < Vt, channel pinches off near the drain When Vds > Vdsat = Vgs Vt

Now, drain voltage no longer increases current and current saturates (Idsat)


Device Operation Review

No gate voltage (vGS = 0) Two back to back diodes both in reverse bias no current flow between source and drain when voltage

between source and drain is applied (vDS >0) There is a depletion region between the p (substrate)

and n+ source and drain regions Apply a voltage on vGS > 0

Positive potential on gate node pushes free holes away from the region underneath the gate and leave behind a negatively charged carrier depletion region

transistor in depletion mode As vGS increases, electrons start to gather at the surface

underneath the gate (onset of inversion) When vGS is high enough, a n-type channel is induced

underneath the gate oxide where there are more electrons than holes (strong inversion)

This induced region is called an inversion layer (or channel) and forms when vGS > some threshold voltage Vt and current can flow between S & D

Transistor is in inversion mode

When vDS = 0, no current flows between source and drain


Linear Operation

With vGS large enough to induce a channel, apply a small potential vDS Causes current to flow between source and drain (electrons flow from source to drain) Magnitude of iD depends on density of electrons in channel which depends on vGS

(larger vGS = higher density of electrons) Conductance of channel is proportional to vGS-Vt (called excess gate voltage or

effective voltage or gate overdrive) Current is proportional to vGS-Vt and vDS that causes current to flow i-v curve shows the transistor operates like a voltage-controlled linear resistor

Notice iD = iS and iG = 0 due to the gate oxide

iD

vDS (small)

vGS


Triode to Saturation Region

Assume vGS is at a constant value > Vt and increase vDS vDS appears as a voltage drop across the channel and at different points along the

channel, the voltage is different Voltages between the gate and points along the channel are also different ranging from

vGS at the source to vGS-vDS at the drain Induced channel is a function of voltage across the oxide at the different points and so channel

depth varies across the length of the transistor i-v curve bends over as vDS increases due to the smaller channel depth At vDS = vGS-Vt channel depth is almost zero at the drain side

Current stays flat for higher voltages vDS > vGS-Vt The transistor is said to now operate in the saturation region (not to be confused with the

saturation region in BJTs)


Saturation Region

As vDS increases, the channel gets smaller and smaller on the drain side until vDS = vGS Vtat which point the channel is said to be pinched off

Increasing vDS beyond this point as little (ideally no) effect on the channel shape Current remains constant and said to saturate Transistor enters saturation at vDSsat = vGS Vt

vDSchannelsource drain

vDS = 0

vDS >= vGS - Vt


Deriving the iD-vDS Relationship

First consider the linear (triode) region of operation vDS < vGS - Vt (vGS > Vt is assumed) Consider a point along the channel of infinitesimal width dx at x and voltage v(x) The electron charge at this point is:

where Cox is the parallel-plate cap formed by the gate electrode and the channel

vDS produces as electric field along the channel (in the negative x direction)


The electric field causes electron charge dq(x) to drift with a velocity dx/dt

Where n is the electron mobility in the channel Current is the movement of charge and so

Rearrange the equation and integrate along the length of the channel

Gives the current in the linear (triode) region:

When vDS=vGS-Vt, we get the saturation current equation


nMOS I-V Summary

Shockley 1st order model of transistors

Cutoff

Linear

Saturation


+ Ideal Quadratic nMOS i-V

Vds

ids

Vg = 1.0V

Vg = 1.5V

Vg = 2.0V

Vg = 2.5V

saturation starts

linear saturation


nMOS and pMOS

Weve just seen how current flows in nMOS devices. A complementary version of the nMOS device is a pMOS shown above

pMOS operation and current equations are the same except current is due to drift of holes

The mobility of holes (p) is lower than the mobility of electrons (n) Current is lower in pMOS devices given the same dimension and voltages.


Circuit Symbols

We represent MOSFETs with the following symbols The book specifies nMOS vs. pMOS with arrows (direction of current flow) I will use bubbles b/c they are easier to distinguish quickly

a digital circuit designers way of drawing symbols These are symmetric devices and so drain and source can be used

interchangeably

nMOS or nFET pMOS or pFET


i-v Characteristics

For small values of vDS, vDS2 is small and so near the origin, we can approximate the transistor as a linear resistor


We can get a relationship between iD and vGSwhen the transistor is in saturation

Let vGS-Vt = VDS

MOS vs. BJT Current is quadratic with voltage in MOS vs.

exponential relationship in BJT


Some Non-Ideal Characteristics

Channel-length modulation Body effect Velocity saturation


Channel-Length Modulation

Like the Early effect in BJTs, there is an effect in MOSFETs that causes drain current to vary with vDS in saturation (finite output resistance)

As vDS increases beyond vDSsat, the pinch off point moves away from the drain by L and has the effect of changing the effective channel length in the transistor

Account for this effect with a (1+vDS) term in the saturation current equation


Channel-length modulation makes the output resistance in saturation finite


Body Effect

So far, we have been ignoring the substrate (or bulk or body) of the transistor and assumed that is it tied to the source. However, we cannot always make that assumption.

In integrated circuits, the body is common to many MOS transistors and is connected to the most negative (positive) supply for nMOS (pMOS) transistors.

The resulting reverse-bias voltage between the source and substrate affects device operation.

Reverse bias will widen the depletion region and reduces channel depth which can be modeled as changing the threshold voltage

where Vth0 is the threshold voltage when VSB=0, f is a physical parameter, is a fabrication-process parameter

is typically 0.5-V1/2 As VSB increases, Vt increases which affects the transistors i-v characteristics


Temperature Effects

Vt and mobility n,p are sensitive to temperature Vt decreases by 2-mV for every 1C rise in temperature mobility n,p decreases with temperature

Overall, increase in temperature results in lower drain currents


Velocity Saturation

So far, the saturation current equation is quadratic with overdrive voltage (vGS-Vth) and said to obey the square law which is valid for long channel length (>1-m) devices

As transistor dimensions decrease, gate oxide gets thinner and there is a higher vertical and horizontal electrical field that the electrons moving through the channel experience

Causes electrons to bounce up to the oxide (more scattering) and saturates the velocity at which current flows across the channel

Can approximate the effect of velocity saturation with the following power-law equation for saturation current

ranges from 1 to 2 depending on process technology (transistor length) This approximation is not rigorous, but convenient to use. More accurate

models of the velocity saturation equation can be found in more advanced courses that cover MOS devices and circuits


Real nMOS i-V Curve

i-v curves of nMOS transistor in 0.5-m CMOS technology

W = 2.5-m, L = 0.6-m


Depletion-type MOSFETs

Depletion-type MOSFETs have a channel with zero vGS (symbol is drawn with channel)

must apply negative vGS to turn off device Can be used as resistor loads (will see later)


MOSFET at DC Example

Current Mirror What is vGS? How is ID related to ISRC? What is ID vs. VD?

VD

IDISRC

vGS


MOSFET Amplifier

The MOSFET can be configured to operate as an amplifier. One of the simplest amplifier configurations one can build with a MOSFET is a common-source amplifier.

Requirements for proper operation MOSFET must operate in saturation

Depends on RD and voltage biasing VGS


Load Line

Use a load line to see the operating point of the transistor w.r.t. RD and VGS


DC Biasing

There are many ways to bias the CS nMOS Amp. Here are two ways

What is VIN (or VGS) for the circuit on the right? What is the cap for?


DC Bias

First bias MOSFET in saturation region (equivalent to active region in BJTs) to operate as an amplifier

set vgs = 0 and find ID (for now, assume =0)

To be in saturation,

Apply a small signal, vgs, to the gate


Three components of iD

First term = DC current Second term = current proportional to vgs Third term = undesired nonlinear distortion

Make vgs small to reduce effect of third term

This is the small-signal condition and lets us use the following approximation

and we can relate id to vgs with a transconductance


Small-Signal Voltage Gain (vd/vgs)

This gain e

Documents

Electronic Devices and Circuits