Electronic Beam-Steering IC for Multimode and Multiband RFID

1310 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 57, NO. 5, MAY 2009

Electronic Beam-Steering IC forMultimode and Multiband RFID

Michael Yan-Wah Chia, Member, IEEE, Piew Yoong Chee, Member, IEEE, Wing Fai Loke, Jee Khoi Yin,Chiew Kok Ang, Siew-Weng Leong, Member, IEEE, Kim Loon Chee, and Agnes Ah Lan Peh

Abstract—The performance of an RF identification (RFID)system can be limited by the static radiation pattern of a reader orinterrogator. In this paper, a novel and low-power CMOS chip hasbeen designed to enable beam steering for the RFID interrogator.This is suitable for the RFID system, operating from 900-MHzto 2.4-GHz bands, which uses passive and active RF tags. Oursolution does not change the basic transceiver design in order tominimize the cost of the system. The chip has been implementedin 130-nm CMOS. It can provide up to eight time shifted signalsto feed the multiple RF synthesizers in a phased array. This issuitable for the RFID reader, which requires multibands andmultimodes, covering ISO-18000-6, Electronic Product Code, andIEEE 802.11b/g standards. The size of this die is 1.2 mm� andit consumes only 10 mA. It can provide multiple delayed signalswith 5-ps resolution. This will translate to a 2 scanned angle at2.4-GHz band. Measured results for the integrated circuit andphased arrays will be provided.

Index Terms—Beam steering, phased array, RF identification(RFID).

I. INTRODUCTION

T HE NUMBER of RF identification (RFID) applica-tions has increased rapidly in recent years. These are

primarily driven by the demands from the major customerssuch as Walmart [1], the Department of Defence, etc., and theemerging international standards from the International Stan-dards Organization (ISO), Electronic Product Code (EPC), andIEEE. These applications can be highly diversified. Typically,users who require short range (0.5–10 m) tracking exploitpassive RF tags. These are interrogated by a reader operatingat 800/900-MHz bands, which comply with EPC and ISOstandards. Here, the key concern is to power up the passivetags. The dc power supply of the tags comes from the externalRF power radiated by the RFID reader. The performance inthis system is primarily limited by the national spectrum regu-lations and the static antenna beam pattern. Users who requiretracking items over longer distances (up to a few hundredsof meters), prefer RFID readers or access points operating at

Manuscript received May 27, 2008; revised November 28, 2008 and January28, 2009. First published March 31, 2009; current version published May 06,2009.

M. Y.-W. Chia, P. Y. Chee, J. K. Yin, C. K. Ang, S.-W. Leong, K. L. Chee,and A. A. L. Peh are with the Institute for Infocomm Research, I R, A*STAR,Singapore 138632 (e-mail: [email protected]).

W. F. Loke was with the Institute for Infocomm Research, I R, A*STAR,Singapore 138632. He is now with the School of Electrical and Computer En-gineering, Purdue University, West Lafayette, IN 47907 USA.

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TMTT.2009.2017299

2.4 GHz. Typically these are using WIFI-IEEE 802.11b/g orZigBee-IEEE 802.15.4 standards to locate battery-poweredtags. RFID reader that use beam steering [2]–[5] can improvethe system performance.

Emerging RFID applications are driving the need for multiplemodes and frequency bands. Hence, a beam-steering technique,which can enable multiband and multimode transceivers to op-erate at 900 MHz and 2.4 GHz, is highly desirable.

In this paper, we will present the design of a novelbeam-steering integrated circuit (IC) to control the phasesof the frequency synthesizers (FSs) [4], [5] in a phased array.This method is suitable for a multiband and multimode RFIDinterrogator or reader operating from 900 MHz to 2.4 GHz.Our beam-steering method has exploited the concept of analogdelay-locked loop (DLL) [6]. We have implemented thison 130-nm CMOS to give variable time shifted signals upto 5-ps resolution. The radiation patterns of our phased ar-rays at 900 MHz and 2.4 GHz will be measured to validatethe performance. Finally, the chip was also tested with aphased-array reader to boost the reading rates of the passiveRFID tags in a cluttered indoor environment. This electronicbeam-steering IC was able to achieve picosecond precision toenable fine beam scanning from 900-MHz to 2.4-GHz bands.The system design of the beam-steering array will be discussedin Section II. We will reveal the IC architecture design for thebeam-steering device in Section III and present the measuredresults in Section IV. Finally, our conclusions are summarizedin Section V.

II. SYSTEM DESIGN OF PHASED ARRAY

A. Phased-Array Architecture

The array factor (AF) of a linear phased array can be repre-sented by

(1)

where is the radiated angle as shown in Fig. 1. The antennaelement [7] are each spaced a distance apart by with amplitude

, phase excitation , and wavenumber .Note the phase for scanned angle or direction as follows:

(2)

Equation (2) can also be expressed as the time delay betweentwo antennas by

(3)

0018-9480/$25.00 © 2009 IEEE

CHIA et al.: ELECTRONIC BEAM-STEERING IC FOR MULTIMODE AND MULTIBAND RFID 1311

Fig. 1. RFID transceiver for 800–900 MHz and 2.4 GHz with electronic beam-steering.

Beam forming can be designed using analog and digitaltechniques [2], [3], [8], and [9], but there is a tradeoff in per-formance [5]. It is important to achieve low power and low costin a commercial RFID system. Our earlier works have used adual port direct digital synthesizer (DDS) to provide referencesignals with small time delay to drive the phased-locked loops(PLLs) in the transmitters for a phased array [4], [5] operatingat 800–900 MHz. However, the architecture of a typical DDSis meant for generating signals with variable frequency andphase. It requires complex and high-speed digital processingand high-performance digital-to-analog converter to produceanalog waveforms. Generally, DDS requires high power sinceit consumes hundreds of milliwatts. Hence, we have proposed anew time-delay chip for the steering RF beam. It only consumes10 mA, much lower power than DDS and the CMOS die size isonly 1.2 mm . This will lead to a low-cost solutions for RFIDapplications [6]. Our designs provide the reference clocks orsignals for each PLL within the RF transmitter and receiver, asshown in Fig. 1 so it does not require any modification to thesetransceivers [3]. It can achieve a fine degree of scanning byexploiting time shifts in picoseconds. The chip will drive theRF synthesizers for the transmitters and receivers so as to steerthe radiated beam adaptively. 5-ps delay will translate to about4.65 scanned at 2.4 GHz. This performance can easily matchthe high resolution obtained from a digital beam-forming array.

A typical PLL used in an RFID transceiver includes a phasefrequency detector (PFD) and charge pump (CP), loop filter(LF), voltage-controlled oscillator (VCO), integer, or fractionaldivider , as shown in Fig. 2. The transfer function can be rep-resented in the -domain using a Laplace transform as follows:

(4)

The source signal triggers a change in phase (e.g.,a step phase or ramp phase) at the input of a PLL in the trans-ceiver. The output signal of the PLL will change with the phaseaccordingly and settle at in the steady state [10], [11].In our case, the source signal for the PLL is derived from ourbeam-steering device. It provides multiple signals with variabletime shift or delay. This delay will translate to phase change

Fig. 2. Typical FS includes CP-PFD LPF, VCO, and integer-� divider or frac-tional-� for PLL.

for each transceiver in the array in order to steer the RF beam.The data source may create in-phase (I) and/or quadrature (Q)signal, which is used to modulate the carrier, as shown in Fig. 1.Alternatively, data can be modulated on the carrier by switchingthe power amplifier (PA) [5]. The output of each PA is finallyconnected to the antenna. The outputs between two antennasin the array produce a phase difference of , which is ulti-mately summed together in the air, but in the receiving mode,each chain will down-convert the RF signal to IF. This is thenadded or summed using an analog combiner at the IF. In thispaper, only beam steering for the transmitter chains operating at900-MHz and 2.4-GHz bands using this time-delay IC modulewill be evaluated.

III. BEAM-STEERING IC DESIGNS

A true time-delay circuit can be realized as a passive trans-mission lines or resistive (R) and capacitive (C) componentsat the expense of a large silicon die area [12], [13] and highlosses in power. In addition, the timing accuracy may sufferdue to process variations. Alternatively, active circuits can beused to produce time-delayed signals [12]–[14], which occupy asmaller die area, but it is not easy to achieve a small time delay,in the order of picoseconds, typically found in a DDS. More-over, the DDS consumes higher power and requires a large sil-icon area, which leads to higher cost [15]. A commercial DDStypically consumes a few hundred milliamperes. Several DDSsor a DDS with multiple outputs are required for a phased array.This leads to even higher power consumption and cost. Our elec-tronic beam-steering device, which exploits true time-delay out-puts using active CMOS circuits [6], aims to provide a better andalternative solution to this problem.

The principle of our time-delay circuits is based on analogDLL. DLLs are widely used to generate on-chip clocks in mi-croprocessors, memory interfaces, and communication ICs. Thedesign offers good performance in the timing jitter as comparedto the conventional PLL [16]. The jitter does not accumulate, asthere is no close-loop in the delay cells. A basic DLL, as shownin Fig. 3, consists of a series of voltage-controlled delay cellsthat forms the voltage control delay line (VCDL), a phase de-tector (PD), a CP and an LF. A PD instead of a PFD is often re-quired in a DLL as the output clock needs only one cycle delayof the input reference signal . A PD ensures that the outputsignal will not lock to the harmonics (multiple cycles)of the input clock.


Fig. 3. Block diagram of a typical analog DLL.

Fig. 4. Three operation conditions of the PD.

The PD detects the phase difference between the referencesignal and the output signal and generates errorsignals and to drive the CP. The three operating con-ditions of the PD are depicted in Fig. 4. The difference in thepulsewidths give the phase error between and . If the

pulse is larger than the pulse, will be trailingbehind the phase of . If the pulse is smaller than the

pulse, the phase is leading the . These errorsignals are integrated by the CP and LF to produce a dc con-trol voltage to adjust the delay of the VCDL outputs. Thedelay of one clock cycle is achieved when the PD produces equalpulsewidth and signals. In the steady-state condi-tion, the outputs of the delay cells give a set of clockedsignals, which, in the ideal case, are spaced apart by ;where is the clock period of . The delay of each delaycell is . One of the main causes that degrades the perfor-mance of the DLL is the nonlinearity of the delay line. It causesthe delay to deviate from the ideal value of due to themismatch in the devices. Selecting a highly linear delay cell isan important criterion for the DLL to achieve accurate timingdelay.

A. Beam-Steering Architecture Using Partial DLL (P-DLL)

Table I shows the specifications of the true time-delay systemor module for electronic beam steering. It provides multiple de-layed reference clocks or signals for the array of PLLs or FSs.Fig. 5 shows the architecture of our IC design. It consists of amodified or P-DLL connected to a first set of multiplexer, dig-ital phase interpolator (DPI) and a second set of multiplexers.Circuits for coarse and fine delay calibrations are crucial forcompensating errors at the output. Finally, the delay outputs arebuffered with slew-rate control.

TABLE ISPECIFICATIONS OF THE TIME-DELAY MODULE FOR BEAM STEERING

Our P-DLL incorporates two additional circuit blocks: a com-parator at the input and a programmable reference delay beforethe PD block. The reference signal can be derived froma crystal oscillator, up to a frequency of 100 MHz. The dc levelfor the comparator is set at 0.75 V. The comparator will con-vert the input signal to digital pulses , which is operating atfull swing if the signal amplitude is above 0.75 V. is theinput signal for the programmable reference delay, as well asthe VCDL in this modified DLL.

The reference delay circuit can be programmed digitallyusing the “phase tuning control signal,” but this will initiallyintroduces some delay error to this DLL. The idea here is toexploit the phase-locking mechanism of the DLL to lock or fixthe relative time difference or delay (Section III-B) to giveus a stable estimate of the delay first. This delay can be set fromabout 80, 85, to 500 ps and the typical measured error due tothe reference delay circuit is about 20%. After determining thedelay error (e.g., 20%) by measuring the output of the chip, weare able to correct this using our calibration circuits to give anaccurate signal at the final output, as described in Section III-E.In general, additional delay errors due to mismatches in de-vices, etc., in the other part of the circuit will further contributeto the inaccuracy. Hence, calibration is required to give awell-controlled delay.

The 80–500-ps delay from this P-DLL can be further phaseinterpolated, as described in Sections III-B and D to give5–75 ps. The multiplexers give various combinations of thesignal to deliver from 0-, 5-, to 500-ps delay for beam steering.The measured results of our chip in Section IV have validatedour design methodology.

B. Reference Delay Circuit

Our reference delay circuit consists of a chain of inverterbuffers, as shown in Fig. 6. Each large delay buffer introducesabout 500-ps delay, whereas the propagation delay of the smalldelay buffer is about 30 ps. The final delay is obtained by set-ting the binary code B0 to Bn through the “phase tuning con-trol signal.” The PD compares the output of the VCDL with thedelayed version of the reference signal . The P-DLL usesthe inherent closed-loop mechanism to tune the VCDL and lockthe time delay of the programmable reference delay circuit. Inthe locked condition, the delay of one unit of each voltage con-trolled delay cell is

(5)


Fig. 5. Beam-steering IC architecture with true delay in picoseconds using modified DLL or P-DLL.

Fig. 6. Reference delay circuit schematic.

where

total number of delay cells in the VCDL;

time delay of relative to .

For example, tapping one large buffer (500 ps) and ten smallbuffers (30 ps) in the reference delay circuit generates about800-ps delay. Using a ten VCDL cell in the P-DLLwill lock the delay to 80 ps. If an additional 30-ps buffer is used,the delay is increased from about 80 to 83 ps. Hence, the theoret-ical delay resolution is about 3 ps, but in the actual design, we are

able to achieve 5 ps with calibration. Hence, the actual calibratedoutput becomes 85 ps instead of 83 ps. Variations in process,supply voltage, and temperature produce a typical error of 20%delay in the reference delay circuit, but this can be measured andcorrected later using calibrated circuits. Hence, the output of theP-DLL is 80, 85, and 90 ps up to 500 ps (using at least ten largebuffers). We have to note that the various mismatches in the sub-sequent circuit blocks (multiplexers, etc.) will contribute furthererrors, which can be larger than the delay caused by the buffersof the reference delay circuit. Hence, our calibration circuits arecrucial for correcting the errors generated from the P-DLL andthe other part of the circuits to give the desired accurate delay.

C. Delay Cell

The delay unit in the VCDL is a self-biased Maneatis loadsdifferential delay cell, as used in [4] and shown in Fig. 7. Thisdelay cell has a high linearity range and power supply rejectionratio (PSRR) to ensure small timing jitter at the output. Theeffective delay of each cell is defined as

(6)


Fig. 7. Maneatis loads delay cell.

where

variable resistance of the symmetric load;

effective delay cell output capacitance.

The delay of the variable delay cell unit dictates the truetime delay generated through the P-DLL. The smallest delay isthe minimum propagation delay of the delay cell when isreaching its minimum level. The minimum delay time dependson the process technology. In this case, the chip has been im-plemented in lower cost 130-nm CMOS process, which givesa minimum delay of 80 ps after accounting for the variationsin voltage, temperature, and process. The delay generated fromthis P-DLL is between 80–500 ps.

D. Phase Interpolation

A secondary circuit has been implemented to achieve the timedelay from 5 to 75 ps. The programmable time-delay operationis divided into two circuits, as shown in Fig. 5. The delay from80 to 500 ps (ch1c–ch8c) at a 5-ps incremental step is gener-ated through the P-DLL with the help of the small buffer in theprogrammable reference delay circuit. The DPI is introduced asa secondary circuit to cover the time delay from 5 to of 75 ps(ch1f–ch8f). The DPI is used to interpolate the rising edges ofits two input signal. These inputs are connected to the outputs oftwo adjacent delay cells (ch1c and ch2c in Fig. 5) in the P-DLLthrough a multiplexer (Mux). The Mux will select from eitherthe signals from the P-DLL or as the input for the DPI.When the beam-steering system requires 0 ps or no delay, theMux will select as the input to the DPI.

The schematic of a short-circuit current suppression (SCCS)interpolator [17], [18] consisting of a pre-charge PMOS tran-sistor and a pair of NMOS discharge transistors and logic cir-cuits for the DPI is shown in Fig. 8. The SCCS interpolator iscapable of producing a precise interpolation ratio. The interpo-lation error is minimized by suppressing the short-circuit cur-rent between and GND during a period when both PMOSand NMOS transistors are switched on simultaneously. The in-terpolation circuit is a combination of two homo-interpolators

Fig. 8. DPI. (a) DPI circuit design. (b) Multiple DPI or D configuration andits characteristics.

and a hetero-interpolator, as shown in Fig. 8(b). The homo-in-terpolator derives its inputs from the same signal source. Theoutput from the homo-interpolator is the delayed input signal.The inherent delay matches the propagation delay of ahetero-interpolator with inputs from two different signal sourcesfor interpolation. The delay time for the interpolation circuit canbe expressed as follows:

(7)

(8)

where

propagation delay of DPI;

time difference of two different inputs;

threshold voltage for inverting next gate;

current of one discharging transistor.

The SCCS interpolator can achieve a precise interpolationratio, as proven in (8). Each interpolator is able to halve thetime difference between the rising edges of two input signals.There are four stages of interpolators connected in series insidethe DPI block. The output time delay of the DPI block is ;where is the time delay of ch1c and ch2c. When of ch1cand ch2c is 80 ps, the relative delay at the DPI outputs is 5 ps.The DPI helps to reduce the delay (5–75 ps) beyond the limita-tion of the P-DLL.

E. Output Calibrations

The programmable reference circuit, P-DLL, and mismatchesdue to transistors, layout, and bonding wires will contribute tothe delay errors. This issue is even more critical when the delayis below sub-10 ps. Calibration circuits are required to compen-sate the errors due to the relative delay between the adjacentchannels. Our calibration scheme consists of two sets of circuitsto calibrate for each output or channel. The coarse calibrations


for correcting the timing errors up to 100 ps at a resolu-tion of 10 ps and the fine calibrations for the timing errors up to

10 ps at a resolution of 0.5 ps.The calibration circuit consists of a series of binary weighted

unit capacitor connected to each of the delayed output orchannel. The value of the capacitive load connected to eachdelayed output is digitally programmed. Fig. 9(a) shows one ofthe output channel connected to the capacitors for calibration,which we will refer to as “calibration capacitors.” Both coarseand fine calibration circuits are similar, except that the coarsecalibration capacitors have a larger capacitance. When the

signal is “1,” the switch is connected to capacitor.

The calibration procedures are described as follows.1) When the chip is first powered up, in the default state, all

the channels will have their most significant bit (MSB)calibration bit (CTRLn) equal to “1” and the remainingbits equal to “0.” All the chan-nels are loaded with half of the total “calibration capac-itors.”

2) Once the desired delay is programmed using the “phasetuning control signal,” the relative delay between thesignals from the adjacent output channels is monitoredusing an oscilloscope.

3) If the error is larger than 10 ps, the delay is cali-brated using a series of coarse “calibration capacitors.”The number of bits to be switched either on(“1”) or off (“0”) will depend on the value of the errorsand whether the error is positive (relative delay is toolarge) or negative (relative delay is too small).

4) When the measured error is less than 10 ps, the fine“calibration capacitors” are used to minimize the error towithin 0.5 ps. A similar procedure of programmingthe bits is also carried out for the process of finecalibration.

5) If the error is 10 ps at the start of calibration, thecalibration program will only need to activate the finecalibration process.

With the coarse and fine calibration circuits connected in se-ries, we can achieve calibration to at least 100 ps with a res-olution of 0.5 ps. Each delayed output or channel has its own setof calibration circuit that can be calibrated independently. Thefine and coarse calibrations are implemented using the conceptof “relative delay” [6] with the schematics shown in Fig. 9(a).As shown in Fig. 9(b), there are two branches of capacitors foreach control bit . The switches and the inter-connec-tions contribute to the capacitance of of both branches. The

capacitors are NMOS transistors of size . Ifchanges from “0” to “1,” the capacitor will switch to ca-pacitor in one of the channels. This will also changethe relative delay between two channels because the time differ-ence is proportional to . The unit capacitance of con-sists of both NMOS and PMOS capacitors. Thishas the following advantages. Firstly, using the relative capaci-tances can eliminate the effect of parasitic capacitances from theswitches and metal inter-connections to achieve the fine or smalldelay. Secondly, this design is easy to implement since it onlyneeds a switch to select either of the two capacitances. Thirdly,

Fig. 9. (a) Fine calibration circuit for one output channel. (b) Single bit relativecapacitance. (c) Simulated relative delay between channel 1 and channel 2 whenthe �� is switched on for channel 2.

the area of the layout will be smaller if was generated usingmetal layers. Fig. 9(c) shows the simulated results of the delaybetween channels 1 and 2 using our fine calibrations. Channel 2least significant bit (LSB) calibration bit (i.e., '` forchannel 2 and '` for channel 1) is switched on. Therelative delay between these channels is about 250 fs at a typicalcorner simulation. The worst case corner simulation shows thatthe delay is about 0.5 ps. The subsequent calibration bits con-sist of of MOS capacitors in binary multiplication ofand .

The delayed outputs from the P-DLL (ch1c–ch8c) and DPI(ch1f–ch8f) are connected to a multiplexer. Depending on therequirement of beam steering, either P-DLL or DPI will be se-lected as the outputs. The eight true time-delayed outputs fromthe multiplexer are connected to a set of slew-rate controlledbuffers. The circuit is designed to drive high impedance and50- loads (but not simultaneously).

IV. RESULTS

A. Beam-Steering Device Measurements

Our IC has been implemented using a 130-nm CMOS processoperating at 1.5 V. The microphotograph of the chip is shownin Fig. 10. Fig. 11 shows the measurement setup with the chipmounted on the printed circuit board (PCB) for testing purposes.


Fig. 10. IC die photograph.

Fig. 11. Setup for measuring true time-delay IC module.

Figs. 12 and 13 show the measured results of the chips oper-ating at the delay of 5 and 500 ps, respectively. The oscilloscopecan only measure up to four channels at one time, but similar re-sults are also observed in the remaining four ports of the chip.Fig. 12 indicates that the time difference between channels 1and 2 is 5.03 ps, channels 1 and 3 is 10. 39 ps, and channels1 and 4 is 15.57 ps. Hence, the relative time delay is betweenports and is close to 5 ps. The measured results have validatedthe calibration accuracy and is well within 0.5 ps.

The measured jitter for 5-ps time delay are 2 ps [root meansquare (rms)] and 18 ps (peak to peak), respectively. The mea-sured results are summarized in Table II. The active die sizeexcluding bond pads is 1.2 mm . Power consumption is about10 mA, much lower than DDS, which consumes several hun-dreds milliamperes.

B. Radiation Patterns and RFID Reader Protocol Testing

Our beam-steering module was tested with different sets oftransmitter arrays at 900-MHz and 2.4-GHz bands. We have de-signed an RFID interrogator with one receiver, but two sets of

Fig. 12. Measured time-delay outputs of the chip at 5 ps.

Fig. 13. Measured time-delay outputs of the chip at 500 ps.

TABLE IISUMMARY OF THE MEASURED RESULTS OF THE IC CHIP

transmitters and FS, which can operate from 902 to 928 MHzaccording to ISO 18000-6B protocol [5]. The beam-steeringmodule feeds two synthesizers, each with 10-MHz referencesignals. These can be time shifted or delayed according to con-trol settings for the IC. The FSs can hop at 500-kHz channelswith a Manchester coded amplitude shift-keying signal across902–928 MHz, but the radiation pattern measurements wereperformed using a continuous wave fixed at 924 MHz. For thisexperiment, an array of two dipole antennas spaced at about ahalf-wavelength (16.23 cm) was connected to outputs of twotransmitters only. Using a time delay at 0, 22, and 44 ps wouldtranslate to a phase difference of 0 , 7.318 , and 14.64 ac-cording to (3). The corresponding scanned angle of the phased


TABLE IIISCANNED ANGLE VERSUS TIME DELAY (PHASE DIFFERENCE)

FOR THE PHASED ARRAYS AT TWO FREQUENCIES

Fig. 14. Measured radiation patterns at 924 MHz using array of 2 antennas.

Fig. 15. Measured radiation patterns at 2.412 GHz using an array of fourantennas.

array would change from 0 , 2.32 and 4.65 respectively, asshown in Table III, using (2). Generally, the main lobe scannedor steered as the time delay increased, as shown in Fig. 14. Therewere good agreements at bore-sight (0 ) with 0-ps delay andscanned angle of 2 using 22-ps delay, but there was some dis-crepancy between the theoretical and measured scanned angleat 44-ps delay. The ripples observed in the pattern have cre-ated some distortions in the measured results. This problem hasoccurred because of the difficulty in synchronizing the trans-mitters of the phased array with the remote receiver setup at924 MHz. However, there was no problem synchronizing at2.412 GHz, as shown by the radiation patterns in Fig. 15. In thiscase, our beam-steering chip was tested using four sets of com-mercial RF transceivers obtained from MAXIM, for IEEE 802.11g/802.11b. In this experiment, the adjacent antenna spacingwas spaced 3.7 cm apart to give an antenna aperture lengthof 11.1 cm for four linearly polarized discone antennas. Thephased array was also scanned at similar angles as 924 MHz,but the time delay required for 2.412 GHz is 5 and 10 ps, re-spectively, much smaller than 22 and 44 ps for 924 MHz. Thisis to be expected since the higher carrier frequency translates toa shorter cycle. A smaller time-delay step is required to achieve

the same scanned accuracy. Very good agreements between the-oretical and measured results were also observed in Fig. 15 andTable III at 2.412 GHz.

Finally, the chip was further validated in an RFID interrogatoroperating at ISO 18000-6b protocols at 900-MHz band usingthe same setup as [5]. In this experiment, the performance of asingle antenna, beam-switching, and electronic beam-scanningusing two transmitters and one receiver was compared. Note thatin a modulated backscattering RFID system, the backscatteringtag does not used an RF reference oscillator so there is no need tosynchronize with the transceiver of the RFID reader, unlike theremote receiver setup used for pattern measurements (Fig. 14).Here, the experimental setup was meant to emulate a typicalindoor environment for item level tagging. An array of two cir-cular polarized antenna connected to a reader were located at1.2 m above the floor. There were 48 commercial RFID tags(each the size of a credit card) mounted on a fabric. The tags arepacked less than 2 mm apart and arranged side-by-side into twovertical columns and 24 horizontal rows [5]. Our beam-steeringmodule was able to scan the phased array up to 22-ps time-delayresolution to give the 2 scanned angle. The carrier frequen-cies was hopping from 900 to 928 MHz according to the ISO-180006b communication protocols. The poorest performancewas obtained using a single antenna where only 21% of the tagswere read by the reader. However, better results were obtainedusing our beam-scanning method with a 78% success rate. Beamswitching achieved only a 35% success rate. Such performanceswere also observed at further distance from the tags. Similarmeasured results were also reported using the commercial DDSfrom Analog Devices [5]. The beam-steering array using ourchip has helped to power up more passive tags to improve theRFID system performance, which uses the ISO-180006b pro-tocol. Better read rates may be improved by redesigning the tagsor changing the position of the tags, but this is not always pos-sible in practice.

Practical testing of a wireless communication link using ourtransmit beam-steering array at 2.4 GHz will require measuringthe performance of bit error rate (BER) and packet error rate(PER) of several remote active receivers or tags under variouspropagation channel conditions, i.e., receivers located at dif-ferent positions in the room, corridor, etc., over a wide area.This will require launching a dedicated test and measurementcampaign using communication protocols analyzers, testers,etc. Several earlier works, such as [3], [19], and [20], haveproven that transmit beam steering can improve the perfor-mance of WLANs with their measured and simulated results.Thus, our study will complement these results by providing alow-cost IC chip solution.

V. CONCLUSION

A low-power CMOS IC based on a new P-DLL architec-ture can provides up to 5-ps delay resolution for beam scan-ning has been developed for multiband and multimode RFIDapplications. The chip can enable the RF FSs in the transmitterchains of a phased array to reconfigure the beams adaptively.The measured radiation patterns for phased arrays at 900 MHzand 2.4 GHz have been validated. The chip has also improved


the system performance of an RFID interrogator and passivetags operating in the ISO 18000-6b standard.

ACKNOWLEDGMENT

The authors would like to acknowledge the support ofA*STAR, Singapore, and N. Cahoon, IBM, Boston, MA, in thebusiness partner program.

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Michael Yan-Wah Chia (M’94) was born in Singa-pore. He has received the B.Sc. (first-class honors)and Ph.D. degrees from Loughborough University,Loughborough, U.K.

In 1994, he has joined the Center for WirelessCommunications (CWC), Singapore, as a Memberof Technical Staff (MTS). He is currently a PrincipalScientist and Program Director of Power AwareWireless Sensor Networks with the Institute forInfocomm Research �I R�, A*STAR, Singapore.He also holds an adjunct position with the National

University of Singapore. He has authored or coauthored over 144 publicationsin international journals and conferences. He holds approximately 12 patents.He has led several major wireless research programs in Singapore, particularlyin the areas of RFID and ultra-wideband (UWB). Recently, he began leading alarge research program on terahertz of the Science and Engineering ResearchCouncil (SERC), Singapore. He has secured many large projects funded byindustry such as EADS, IBM, etc. Since April 2004, his team has also beeninvited into the IBM Business Partner Program for silicon design. His main re-search interests are UWB, terahertz, beam-steering, wireless broadband, RFID,antennas, transceivers, RF integrated circuits (RFICs), amplifier linearization,and communication and radar system architecture.

Dr. Chia has held appointments on several Technical/Advisory Commit-tees in industry and national government bodies such as Infocomm Develop-ment Authority (IDA) and SPRING. He has been an active member of orga-nizing committees in various international conferences and was the programco-chair of the IEEE International Workshop of Antenna Technology (IWAT)2005. He was an invited keynote speaker at the IEEE International Conferenceof UWB 2005. He was the general chair of the International Conference onUltra-Wideband (ICUWB) 2007. He has also been a member of the ExecutiveCommittee of ICUWB since 2007. He is a member of the Editorial Board for theTRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES. He was a recipientof the Overseas Research Student (ORS) Award presented by U.K. universitiesand a Research Studentship Award presented by British Aerospace, UK.

Piew Yoong Chee (S’90–M’00) received the B.E. de-gree in electrical engineering from the University ofMalaya. Malaya, Malaysia, in 1988, and the M. Eng.degree from Nanyang Technological University, Sin-gapore, in 1992.

In 1999, he joined the Center of Wireless Commu-nications. He is currently a Research Manager withthe RF and Optical Department, Institute for Info-comm Research, I R, Singapore. His research inter-ests and activities include analog and RF integratedcircuit (RFIC) designs for wireless communications

applications.

Wing Fai Loke received the B. Elec. Eng. degreefrom the National University of Singapore, Singa-pore, in 2004, and is currently working toward thePh.D. degree at Purdue University, West Lafayette,IN.

From 2005 to 2008, he was with the Institute forInfocomm Research, I R, Sinapore. His research in-terests are RF and analog circuits.

Jee-Khoi Yin was born in Johor Bahru, Malaysia,in 1976. He received the B.Eng degree in electricalengineering from the University of Malaya, KualaLumpur, Malaysia, in 2000.

From 2000 to 2001, he was with the Altera Corpo-ration, Penang, Malaysia, as an IC Design Engineer.Since 2001, he has been with the Institute for Info-comm Research, I R, Sinapore. His research inter-ests are RF and analog circuits.


Chiew Kok Ang received the Master and Bachelordegrees in electrical engineering from the NationalUniversity of Singapore, Singapore, in 1998 and1996, respectively.

He is currently a Research Manager with the Insti-tute for Infocomm Research, I R, Sinapore, where heis involved with RFID and terahertz systems. Prior tothat, he was an RF System and RFIC Design Engi-neer with Motorola Electronics, BaseComm, and theCentre for Wireless Communications.

Siew-Weng Leong (M’96) received the Diplomadegree in electronic and communication engineeringfrom Singapore Polytechnic, Singapore, in 1987,the B.Eng degree in electrical engineering fromNanyang Technological University, Nanyang, Sina-pore, in 1994, and the M.Sc degree in electricalengineering from the National University of Singa-pore, Singapore, in 2001.

He is currently a Research Manager with the In-stitute for Infocomm Research, I R, A*STAR, Sin-gapore. His research interests include RF transceiver

architecture and circuits for RFID, wireless local area networks (WLANs), andUWB.

Kim Loon Chee received the Bachelor of En-gineering degree in electrical engineering fromNanyang Technological University, Singapore, in2000, and the Master of Science degree in electricalengineering from the National University of Singa-pore, Singapore, in 2004.

He is currently a Senior Research Officer withthe Institute for Infocomm Research, I R, A*STAR,Singapore. Since 2000, he has been involved withwireless communications research and developmentsprojects. He had been involved with RFID projects,

contact tracing systems, and wireless sensor networks.

Agnes Ah Lan Peh received the B.Sc degree in tech-nology with electronics engineering from the Singa-pore Institute of Management University (UniSIM),Singapore, in 2005.

Since 1999, she has been with the Institute for In-focomm Research, I R, A*STAR, Singapore. Her re-search interests are DLL design for high-speed com-munications

Documents

Electronic Beam-Steering IC for Multimode and Multiband RFID