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INTERNATIONAL

WINTER 1980

IntroductionThis special publication from ETI magazine is the secondin a series of three; the first was published in late autumn1979.

The series comprises the best 250-300 pagesselected from well in excess of 1500 published in ETI onaspects of circuit design during its history.

The articles included in this series are intended to givethe reader an insight into how circuits work, how they

ContentsOP -AMPSBasic theory and useful circuits

TRANSISTOR OPERATING POINTSimple equations that eliminate guesswork

40 CMOS CLOCKSMultivibrator designs using gates

PRACTICAL GUIDE TO REED SWITCHESThe perfect device for low -current switching

Edited by: Halvor Moorshead, Peter GreenProduction: Diego Rincon, Dee CamilleriThanks to: ETI-Canada (for cover design)

No. 2

are designed and to provide some fairly conventional'building blocks'.

Keeping track of current design techniques is noteasy due to the rapid introduction of new devices andnew technologies: we hope this publication helps tocover the problem.

Halvor MoorsheadEditorial Director - ETI

4 V-FETS FOR EVERYONE!New technology explained

41

19 CHOOSING AND USING TRANSFORMERSA complete guide

51

, 21 DIGITAL ELECTRONICS BY EXPERIMENT .Principles of TTL circuit design

55

. 29 GAIN CONTROL 83An examination of electronic control of gain

Electronic Circuit Design No 2 is an Electronics Today International SpecialPublished by: Modmags Ltd, 145 Charing Cross Road, London WC2H OEEDistribution by: Argus Distribution LtdPrinted by: QB Limited, Colchester

Copyright. All.material in this publication is subject to world-wide copyright protection. Permission to reproduce in whole or part must be soughtfrom the Editors. All reasonable care has been taken in the preparation of this publication to ensure accuracy but the publishers cannot be heldJegally responsible for any mistakes etc that may occur

ELECTRONICS CIRCUIT DESIGN - WINTER 1980 3

OP AMPSOpen up any data sheet on a particular op -amp and you will be confronted with as many as forty different electricalparameters and performance graphs which should reveal all that you need to know about the device. Most of these,

parameters will be qualified by the conditions under which they were measured and the test arrangementsused to make the measurements. This apparent 'overkill' of data is likely to be very confusing to the newcomer,

however it need not be so. Tim Orr explains.

Let's discuss some basic principles. An op -amp (oroperational amplifier) is just a high gain amplifier,

you stick a voltage into it and a much larger voltagecomes out of it. Op -amps have two inputs, inverting andnon -inverting, which are denoted by -- and + respec-tively. The op -amp amplifies the difference in thevoltages applied to these two inputs, the output goingpositive if the + input is positive with respect to the -input, and vice versa, however this is virtually useless,because the voltage gain is uncontrollably large and thedistortion high. The way in which both of theseparameters are controlled is by the use of negativefeedback. An op -amp with negative feedback is shownin Fig. 1. It employs two resistors to set the closed loopvoltage gain, and as long as this is small compared to theopen loop gain, it will be determined by the resistor ratioRF/ RI. The open loop gain, the voltage gain when RF isremoved, is typically of the order of 100 000. Thismassive gain is clearly much too large to be used withoutfeedback. Closed loop voltage gains of 100 are about asmuch as it is practical to use.

Biased ExampleThe arrangement in Fig. 1 is known as a 'virtual earth'amplifier. The non -inverting input is connected to earth,and the inverting input is maintained by -the feedbackapplied via RF at a voltage which is virtually earthpotential.

The input impedance of the amplifier in Fig. 1 issimply RI. The output impedance is a little more com-plicated, it is approximately

output impedence of the op amp x closed loop gainOpen loop gain

RFCLOSED LOOP VOLTAGE GAIN = - V OU TV IN

(AV) RF

V IN RI

INVERTING INPUT

NON -INVERTINGINPUT

10M

OUT

Figs. 1 and 2 (farleft) show (upper)the basic invertingop -amp stage. Gainis given by the ratioof resistors RF /RI,input impedance issimply RI while theoutput impedanceis more compli-cated (see text).Fig. 2 (lower)shows a stage witha gain of 10 and aninput impedance of1M.

Suppose we want an amplifier with again of 10, and aninput impedance of 1M. This means that RI is 1M.Therefore RF must be 10M (see Fig. 2). With a 1 Vsinewave as the input signal we get a 10V sinewave asthe output. However, when the input signal is held at OV(ground potential), the output voltage is not 0 V. it itpositive! This is an error voltage, which may be undesir-able. The cause of the problem is the 'INPUT BIASCURRENT' of the op -amp. -The input of many op-arripss,looks like the circuit shown in Fig. 3. If these transistorsare to operate correctly they need a standing emittercurrent which implies that they need an input, basecurrent. It is this base current which is the op -amp's'INPUT BIAS CURRENT.' For a 741 this current can beas large as .05 uA. In the arrangement of Fig. 2 thiscurrent can only come through RF, which means that theoutput voltage could be as large as 0.5 uA X 10M,which is + 5 V! One way to remedy, this error is to use acircuit shown in Fig. 4. A resistor has been inseited,between the non -inverting input and ground. Thisresistor has the value of RF in parallel with RI. It alypisboth the inputs to sink slightly and thus maintein thevoltage balance at the inputs. The output voltage is4innearly 0 V. However, the two input transistors may notbe that well matched, so the input bias currents may bedifferent into each input. This is known as the 'INPUT.OFFSET CURRENT' and its effect can be nulled bymaking the 910 k resistor in Fig. 4 a variable resistor. Ifthe bias currents (for a 741 say) were zero, then theoutput voltage would still not be 0 V.

Get Set, They're OffThe output voltage could range between ± 6OrnV. Thisis due to the 'INPUT OFFSET VOLTAGE' which fora 741can be as much as ± 6mV, which is then multiplied by

NPN DIFFERENTIAL PAIR

NON -INVERTINGINPUT

1M910k

10M (AFTROX)

INVERTING show (upper) Si' Figs. 3 and 4 (left),

INPUT typical op -amp in-put stage. This is adifferentialamplifier made upof a pair of NPN -transistorstransistors drivenby a constant cur-rent source. Fig. 4(lower left) showsa 910k resistor in

V OUT op -amp. Thisthe + input of the

reduces the effectsof the INPUT

910k AV = -10 OFFSET CUR -Z IN = 1M- RENT.

OUT = COW '

ELECTRONICS CIRCUIT DESIGN WINTER 1980

the closet: loop voltage gain of the stage (in this case 10)giving uS 60mV. This can be compensated by usingthe circuit Shown in Fig. 5. Terminals 1 and 5 on a 741can be used to compensate for the input offset voltage.The input offset voltage is the V, imbalance between thetwo input transistors.

Now that we know how to eliminate the spurious DCoffsets, we can try designing some dynamic circuits andfind out why they don't work as expected! For example,try putting a 1 V sinewave at 200 kHz into a circuit ofFig. 5. What you would expect is a 10 V, 200 kHzsinewave at the output - but you don't get one. Whatappears is a rather bent 200 kHz triangle waveform. Thisis because the 'slew rate' of the op -amp has beenexceeded. The slew rate is the speed at which the outputvoltage can move, and for a 741 is typically 0.5V /p.secwhen it crosses zero, so the op amp faced with thisdemand just gives up and SLEW limits, drawing outstraight lines as it does so.

Listen To The Band(width)Another problem is 'BANDWIDTH.' A 741 has a GAINBANDWIDTH product of approximately 1 MHz. Thismeans that the product of the voltage gain times theoperating frequency cannot exceed 1 MHz.

For example, if you want the amplifier to have a gainof 100, then the maximum frequency at which this gaincan be obtained is 10 kHz. Fig. 6 illustrates this phe-nomenon. Curve A is the open loop response, note thatthe voltage gain is 1 at 1 MHz, hence the gain band-width product of 1 MHz. The slope of the curve is -20dB/decade, which is caused by a single 30p capacitorinside the IC. Now, if the resistor ratio is set to give avoltage gain of 100, then the op -amp gives a frequencyresponse shown by curve C, which is flat .up until 10kHz. A gain of 10 rolls off at 100kHz (D) and a gain of1000 rolls off at 1 kHz (B).'Thus it is very easy to see justwhat the closed loop frequency response will be. How-ever, don't forget the slew rate problem. You may beable to construct an amplifier with a voltage gain of 10,which works up to 100 kHz, but the output voltage will' be limited to less than 3 V pp! Another problem isdistortion in the op -amp. Negative feedback is used toiron out any distortion generated by the op -amp, butnegative feedback relies on there being some sparevoltage gain available. For instance, say the op -ampgenerates 10% distortion and there is a surplus voltage

V IN

VOLTAGE GAIN AV = V OUT

1M

910k IOFFSET VOLTAGEADJUSTMENT

V IN

V OUT

-VCC

Fig. 5 A variable resistor con-nected between pins 1 and 5 ofa 741 can be used to reduce theeffects of the INPUT OFFSETVOLTAGE.

A1000,000

100,000

10,000

1,000

100

10

gain of 1 000.. ,open- loop gaini.e.( closed loop gain''

then the distortion will be reduced to approximately,open loop distortion 10% _0.01%surplus voltage gain 1To156

So, negative feedback is used to eliminate distortionproducts. However, if there is no surplus voltage gain, asin the case of a 741 amplifier working at 10 kHz, with aclosed loop gain of 100, then the distortion will risedramatically at this point.

Current ThinkingMost op -amps have a voltage output, although somehave a current output. If you short-circuit a voltageoutput then large currents could flow and thermaldestruction might follow. To overcome this problem,most op -amps have a current limited output so that theycan suffer an indefinite short to ground. A 741 is limitedto about 25 mA. Another current of note is the supply'BIAS CURRENT. This is the current consumed whenthe op amp is not driving any load. For a 741 this currentis typically 2mA, which makes it rather unsuitable forsmall battery applications.

There are some op -amps which can be programmedby inserting a current into them so that their supplycurrent can be controlled. This means that they canconsume only micropower when in their 'standby'mode, and they can be quickly turned on to perform aparticular task.

Voltages DifferentlyIn the few examples shown so far, the op -amp has beenused to amplify voltages which have been generatedwith respect to ground. However, sometimes, it isrequired to measure the difference between two vol-tages. In this case you would use a 'Differential'amplifier, Fig. 7. By using two matched pairs of resis-tors, the formula for the voltage gain is made verysimple. It is thus possible to superimpose a 1 V sinewave on both the inputs, and yet have the output of theamplifier ignore this common mode signal and onlyamplify any differential signals. The amount by whichthe common mode signal is rejected is called the CM RR(the Common Mode Rejection Ratio) and is typically 90dB for a 741. Thus a common mode 1V signal would bereduced to 33 uV.

Fig. S Graph of open loop res-ponse of a 741 (A) togetherwith curves indicating res-ponse at various values ofclosed loop gain (B, C and D).

A

B

C

D

10 100 1k 10k 100k 1M

FREQUENCY Hz

V1 R1

V2

R2

V OUT

Fig. 7. Typical dif-R4 ferential op -amp

stage. By usingmatched pairs ofresistors the formulafor voltage gain ismade simple.

V OUT r(R1 + R21 R4 l -_(R3R3 + R41 R1 V2

BUT IF WE MAKE R1 = R3AND R2 = R4

THEN V OUT = R2- V1)

R2R1 Vi


Another rejection parameter to be noted is the supplyvoltage rejection ratio. For a 741 the typical rejection is90 dB, that is, if the power supply changes by 1 V thechange in voltage at the op -amp output will be 33 uV.

When designing with op -amps it is very important toknow what voltage range the inputs will work over, andthe maximum voltage excursion you can expect at theoutput. For instance, the 741 can operate with its inputsa few volts from either power supply rail, and its inputscan withstand a differential voltage of 30V (with a powersupply of 36 V).

This is not true of all op-arnps, some have a verylimited differential input voltage range, for instance theCA3080 will zener when this voltage exceeds '5 V andthe amplifier performance will then be dratticallychanged.

The output excursion of the op -amp is also important.The 741 can only typically swing within about 2j V'ofeither supply rail, whereas the CMOS op-amp can Swingto within 10mV of either rail so long as the load into'which they are driving is a very high impedance.

NON -INVERTING AMPLIFIERAn op -amp is used to provide voltage gain, but in thiscase the output is in phase with theinput. The minimumgain is unity and,occurs when RB is an open circuit. Theop -amp has maximum bandwidth at unity gain, and any

-increase in the gain will cause a reciprocal decrease inbandwidth.

V IN

R IN

RA

Fig. 8. Non -inverting amplifier.

V OUT

AV= + RARB+RB

ZIN = RIN

ZOUT = LOW

HIGH SLEW RATE AMPLIFIERThe slew rate of the op -amp has been increased by

the addition of a pair of transistors. These transistorsincrease the output voltage range by allowing thevoltage to swing to within OV5 of either supply rails. Theoutput of the op -amp hardly moves at all. Without aninput signal, the output voltage is 0 V and the op -ampdrains approximately 2 mA from the supply rails.

This current passes through the 180R resistors andsets up a voltage which is not quite sufficient to turn oneither transistor. When a positive voltage is applied tothe input, the op -amp tries to swing negative but it:has a47R (R4) resistor connected from its output to ground.

+15 V 0

R2

R1

4k7 15p

2V IN

Fig. 9 High slewrate amplifier.

SIMPLE INTEGRATORAn op -amp and a capacitor can be used to implement Ida high degree of accuracy, the mathematical process ofintegration. In this case, current is summed over a periodof time and the resultant voltage generated is theintegral of that current as a function of time. Whafthitmeans that if a constant voltage is imputed to the cifeurt,a ramp with a constant slope is generated at the output.When the input is positive, the output of the op -ampramps negative.

In doing so it pulls the inverting terminal negative so,as to maintain a 'virtual earth' condition. In fact the inputcurrent (Vin / R1) is being equalled by the currentflowing through the capacitor, thus equilibiium cismaintained. The equation governing the beheviour of acapacitor is C x dV /dt = i, where dV /dt is the rate ofchange of voltage across the capacitor.

Therefore Thus

dV I dV VinDT = -C dt 131C

So, when a square wave is applied to the circuitinFig. 10, triangle waveforms are generated. FI-Z wasadded to provide DC stability. Its inclusion does slightlycorrupt the mathematical processes, but not enor-mously. A good point about this integrator design is thatit has a very low ouput impedance. You can put a lead onthe output and the op -amp will still generate the samewaveform - that's what is so nice about negativefeedback.

Fig. 10. Simple integrator.

Thus, as it tries to swing negative, it draws lots of currentfrom the negative rail. This current flows through R5,and in dOing so turns on Q2. This transistor then pullsR2 down and thus provides negative feedback. Thesame sequence of events occurs when the input isnegative except that R3 and Q1 are then involved. Thusthe high current capabilities of discrete transistors arecombined with a high voltage gain of an op -amp toproduce a moderately powerful amplifier. The voltagegain is set by R2 /R1.

Transistors Q1 and 02 introduce a phase shift, whichmay give -rise to a high frequency instability and osailla-tion. This can be cured by some frequency compensa-tion applied to the amplifier or by increasing the overallvoltage gain.

6 ELECTRONICS CIRCUIT DESIGN - WINTER 1980

No Noise Is Good NoiseThe last`op-amp characteristic to be discussed is Noise.The noise figures given in the specifications are veryconfusing. This is due to the fact that noise is,specified inso many different ways that it is often difficult tocompare devices. One may be specified in terms ofEquivalent Input Noise and another device in terms ofnV VHz (nano volts per root Hertz)! As a generalisation itis true to say that most op -amps are relatively noisy.Some op -amps are labelled low noise, and these are

quieter than the average op -amp but more noisy than awell designed discrete component amplifier. For audiowork you can use ordinary op -amps for processing highlevel signals (100mV to 3V), but for amplifying low levelsignals (1 mV to 100mV) you would be advised to use alow noise device. The larger the voltage gain you obtainfrom an op -amp stage, the worse will be the noise,therefore keep the closed loop gain to a bare minimum.

That is the end of the theory, now for some practicalexamples of op -amps in use.

SIMPLE DIFFERENTIATORMathematically, differentation is the reverse process tointegration. Thus, in the differentiator circuit the C and.the R are reversed with respect to the integrator circuit.

The input waveform is a triangle with a constant riseand fall slope. This constant slope, when presented to acapacitor will generate a constant current. When theslope direction reverses, then so will the current flow.This current when passed through a resistor (R1), willthen generate a square wave.

2.5V IAA1 kHz

R1 270R loon

Fig. 11. simple

12 V REGULATED POWER SUPPLYThe large open loop voltage gain of an op -amp is veryuseful in providing a regulated low output impedancepower supply. A 5V1 voltage reference is generated by azener diode ZD1 (this voltage reference could be mademore stable by running it at constant current). A PNPtransistor is used as a series regulator. However, thistransistor inverts the signal from the op -amp output, andso, in order to get negative feedback, the feedback istaken to the non -inverting input! The operation is asfollows. The inverting input is held at 5V1. If the 'PSUOUTPUT' tries to fall, the voltage at the non -invertinginput falls. Therefore the op -amp's output will also fall,thus turning on the PNP transistor which then pulls upthe 'PSU OUTPUT.' Thus the output voltage is stabil-ised. Also, the output impedance is very low, due to thisnegative feedback. The output impedance at highfrequencies (where the op -amp gain is low) is furtherreduced by the 10u capacitor. To squeeze the last dropof voltage out of the system, before a collapsing unre-gulated supply rail causes the regulated supply to dropout, a 5V1 zener diode (ZD2) has been included. This

+VE UNREGULATED SUPPLY 30V -4.12.2V

PNP

PSU OUTPUT

+12V

Fig. 12. 12 V regulated power supp y.

allows the op -amp output to work at about 7 volts belowthe unregulated supply rail. Thus, a regulated output ismaintained until the PNP transistor saturates. Thismeans that the unregulated rail can fall to within about200 mV of the regulated rail!

LEVEL CLAMPINGIt is sometimes required to limit the excursion of theoutput voltage of a linear amplifier. This can be achievedby using non-linear feedback, in this case with zenerdiodes. Once the voltage at the op -amp's output exceedsthe zener breakdown voltage plus a forward diode drop(0V7 from the forward biased Zener), the effectiveimpedance of the feedback becomes very low. Thus thevoltage gain, above this zener voltage, also becomesvery low. The output voltage appears to be clamped at afixed potential. By changing the zener value, thispotential can be varied at will. Also, by making the twozeners have different values, correspondingly differentnegative and positive levels can be obtained. This circuitis, however, far from ideal. The zener diodes don't havevery sharp 'Knees' in their transfer characteristics andthe clamping can sometimes be very sloppy, particularlywhen low voltage zeners are used. Also, the zener diodes

ELECTRONICS CIRCUIT DESIGN - WINTER 1980

Fig. 13. Level clamping 5V1 5V1

10k

V IN

W I 2VV OUT

+5.7

- OV-5.7

tend to have a large amount of charge storage, whichimpairs the high frequency performance.

Sometimes, however, sloppy clamping is considereduseful. For instance, if the zeners are replaced by twoordinary diodes in pirallel and pointing in differentdirections. Then any signal applied to the input willreceive some non-linear distortion. This distortion is richin odd harmonics, and is the basis of many FUZZ boxdesigns for musical effects units.

7

Single Op Amp Oscillator

This circuit has a Schmitt trigger and a 'sort of integra-tor' all built around one op -amp. The positive feedback isvia the 10k resistors. The 'integration', or rather, thetiming, is controlled by the RC network. The voltage atthe inverting input follows that of the RC chargingexponential, except that it is confined to be within theupper and lower hysterysis levels. Thus the hysterysislevels and the Rt time constant determine the frequencyof the operation. It is possible to make the output squarewave have a large mark to space ratio. By closing theswitch SW1, the discharge time of the capacitor be-comes eleven times faster than the rise time. Thus asquare wave with an 1 1 :1 mark space ratio is generated.

10k 10k

V IN

V IN

V OUT -1VYV

100k

100k

V IN

nV OUT

50k

02

100k100k

OV 00T

Precision Half Wave Rectifier

Rectifying small signals with any accuracy can be verydifficult with just diodes due to their forward voltagedrop of about 0.6 V. However, an op -amp can be used toreduce this voltage drop to apparently nothing. Considerthe circuit shown. There is negative feedback so that'virtual earth' circumstances exist. When Vin is positive,D1 conducts to maintain the virtual earth, D2 is reversebiased and so the output is just a 100k resistor con-nected to 0 V. When Vin goes negative, the output risespositively, D2 is turned on and D1 turned off. As thevirtual earth is being maintained, the output voltage isthe exact inverse of the input voltage. This is true for allnegative inputs. Therefore, the output is composed ofpositive going half sinewaves. A precision half waverectification has occurred. In fact the diode error is verysmall, being equal to

600 mV

(surplus voltage gain)

Therefore as the input frequency increases, and thesurplus voltage gain decreases, the amount of precisionalso falls.

By adding the original and the half wave rectifiedsignals together in the right ratio, it is possible to fill inthe half cycle gaps and thus to generate a precise fullwave rectification. The addition of one summing op -ampand three resistors is all that is needed as shownopposite.


Precision Peak Voltage Detector with a LongMemory Time

The circuit shown has negative feedback only forpositive signals. That is, the inverting input can only getsome feedback when diode D1 is forward biased andthis can only occur when the input is positive. When apositive input signal is applied the output of the op -amprises until the inverting input reaches the same potential.In so doing, the capacitor C is also charged to thispotential. When the input goes negative, the diode D1becomes reverse biased and so the voltage 'on thecapacitor remains there, being slowly discharged by theop -amp input bias current and the resistor R (10M). Theop -amp used has a MOS FET input, having an exceptio-nally low input bias current of 10 pico amps. Thus thedischarge of the capacitor is dominantly controlled bythe resistor R, giving a time constant of ten seconds.Thus the circuit detects the most positive peak voltageand remembers it.

Led Bar PPM Display for Audio

The peak voltage detector can be used to control anilluminated audio level monitor displaying the samecharacteristics as a PPM (Peak Programme Meter). A barcolumn of LEDs is arranged so that as the audio signallevel increases, more LEDs in the column light up. TheLEDs are arranged vertically in 6 dB steps. A fastresponse time and a one second decay time has beenchosen so as to give an accurate response to transientsand a low 'flicker' decay characteristic. The op -amps thatdrive the LEDs are being used as comparators. On each'of their inverting inputs they have a DC referencevoltage, which increases in 6 dB steps up the, chain. Allof their non -inverting inputs are tied together andconnected to the positive peak envelope of the audiosignal. Thus as this envelope exceeds a particular

.voltage reference, that op -amp output goes high and theLED lights up. Also, all the LEDs below this are il-luminated.

AUDIO INPUT +Ve PEAKENVELOPE

Ve REFERENCE

1k

ALLTIL209LEDS '""

Basic Summing Circuit (Mixer)

A virtual earth amplifier can be used to mix severalsignals together. The output voltage is a mixture of allthe inputs. The amount of an input that appears at theoutput is inversely proportional to the input resistor. Ifthe input voltages are fed into potentiometers beforebeing fed to the mixer, then their individual levels can bemanually adjusted. This is the basis of most audiomixers, although only the cheaper units use op amps.Most op -amp mixers will degrade the signal to noiseratio of the signals by more than a good discretecomponent amplifier.

V1

V2

INPUTV3

Va

R1

V OUT = -R5 V1 4. V2 + V3 + V4R1 R2 R3 R4


Window Comparator

V OUT4.

V IN

Vref vVrefLOWER - UPPER

A window comparator gives an output which in this caseis 0 V, when an input voltage lies in between twospecified voltages. When it is outside this 'window', theoutput is positive. The two op -amps are used as voltagecomparators. When Vin is more positive than Vref(upper) the output of 1C1 is positive and D1 is forwardbiased. Otherwise the output is negative, D1 reversebiased and hence Vout is 0 V. Similarly, when Vin ismore negative than Vref (lower), the output of IC2 ispositive; D2 is forward biased and thus Vout is positive.Otherwise Vout is 0 V. Thus only when Vin lies within thewindow set by the reference voltages is Vout 0 V.

High Performance Sample and Hold

It is often necessary to have a circuit that will sample ananalogue voltage and then remember it for a long timewithout any significant corruption of that voltage. This isknown as a sample and hold circuit and one use of it is tostore the voltage from the keyboard connected to anelectronic music synthesiser. The voltage is then used tocontrol the pitch of a voltage controlled oscillator and soit is very important to have a high performance sampleand hold. A drift of less than one semitone (80 mV) in tenminutes is required. A sample and hold is simply anelectronic switch, a storage capacitor and a high input,impedance voltage follower. In the circuit shown, when!switch SW1 is positive the FET is turned on, and has aresistance of about 400R. Thus the input voltagecharges up the capacitor through the FET. When SW1 isnegative, the FET is turned off (pinched off), and canhave a resistance of thousands of Megohms. To get along storage time the op -amp must have a very low inputbias current. For the CA3140, this current is about 10pico amps, i.e., 10-11 amps. Therefore the rate at whichthe capacitor will be discharged by this current can beworked out from the equation, C(dv / dt)= I .

where dv / dt is the rate of change of voltage on thecapacitor.Therefore:dv= i = 10-11 =22µV/sdt C 0,47 x 10-6

This is a very low drift rate, much better than we need.However, the actual drift rate will probably be in excessof this, due to surface leakage on the printed circuitboard, leakage through the FET, and internal leakage inthe capacitor. It is advisable to use a high voltage,non -polarised capacitor in this circuit to keep the leakagecurrents to a minimum. Also, to stop surface leakage asimple PCB trick can be used, that of making a guardring around the sensitive components.

Normally any potential stored on the capacitor mayleak to ground across the surface of the PCB, but if wemake the surrounding surface a conducting track held atthe same potential as that of the capacitor then thepotential difference is virtually always zero, and hencethe surface leakage is greatly reduced.

OV IN

+Ve

? swi-Ve

2N3819

D1

GUARD RING

C 470n

/7777 400V400V

DI = 1N914

CA3140

PRINTED CIRCUIT BOARD LAYOUTGUARDRING

2N3819 V OUT

CA3140

V OUT


Linear Voltage Controlled Oscillator

This oscillator is very similar to the triangle square waveoscillator shown in Part 1, except that this one is voltagecontrolled. The integrator and Schmitt trigger action arethe same as before, but the feedback has been altered.The input voltage Vin is applied differentially to theintegrator via the resistor network. The larger the valueof Vin, the faster the integrator ramps up and clown.Thus the frequency of the operation is determined by anexternal positive control voltage. The frequency islinearly proportional to this control voltage.

When the output of the Schmitt is low, Q1 is off andso all the input voltage is applied to the inverting input.Half of the input voltage is always applied to thenon -inverting input. Therefore the integrator's outputramps downward until the Schmitt flips into its positivestate. Now, Q1 is switched on and the voltage at theinverting input is negative with respect to the non -inverting input. Hence the integrator now rampsupwards.

Silent Audio Switching

Sometimes electronic switches for audio signals arerequired. FETs can be used to perform the switching, butthey can cause distortion, the resultant output imped-ance is not very low and clicks generated by the switch-ing signal can break through. The circuit shown virtuallyeliminates all of these problems. By using an op -amp avery low output impedance is obtained as well as thepossibility of selecting or mixing one or more of manyinput channels. Because of the virtual earth mixing, thevoltage across any FET that is switched on is very small.If the input voltage is 1V and the FETs ON resistance is470R, then the voltage across the FET is about 10 mV.When large voltages are applied to a turned on FET, thedistortion is large, but if the voltage is small (10 mV,say), the distortion could be less than 0.1 %. Thus thevirtual earth mixing enables low distortion operation.Lastly, to stop the generation of switching clicks, a timeconstant of 47 msec has been enforced at the gate of theFETs.

47k

ON = OVOFF = - 15V TV n

ON = OVOFF = -15V

V OUT

SWITCH TIME CONSTANT 47mS

T47n

Simple Musical Chime GeneratorThe circuit shown is that of a multiple feedback band-pass filter. The preset is used to add some positivefeedback and so further increase the Q factor. Theprinciple of operation is as follows. A short click (pulse) isapplied to the filter and this makes it ring with afrequency which is its natural resonance frequency. Theoscillations die away exponentially with respect to timeand in doing so closely resemble many naturally occur-ring percussive or plucked sounds. The higher the Q thelonger the decay time constant. High frequencyresonances resemble chimes, whereas lower frequen-cies sound like claves or bongos. By arranging several ofthese circuits, all with different tuning, to be driven bypulses from a rhythm generator an interesting pattern ofsounds can be produced. There may be some stabilityproblems when high Q or high frequency operation isinvolved. To achieve better performance, an op -amp

with a greater bandwidth than the 741 should be used.Alternatively, a different structure, such as a statevariable filter could be used. Qs of up to 500 can beobtained with this latter circuit.

PULSE FROM ARHYTHM GENERATOR

100k- 185 X 1000 X C Hz


MARK SPACE POT.

100u10k Lon

20

Variable Alarkspace Squarewave Generatorwith Automatic Level Adjustment

By putting a triangle wave into one input of a comparatorand a manually controlled DC level into the other, it ispossible to generate a variable ratio mark /space squarewave. However, if the amplitude of the triangle variesthen so will the markspace ratio. Alternatively, if youwant the manual control to produce a very thinwaveform at one end of its travel, then you will probablyneed a preset and a very stable triangle amplitude.However, this circuit solves these problems. The DCvoltage is generated by a peak voltage follower, IC1,driven by the triangle itself. Thus the circuit tracks thepeak voltage level. Secondly, only 97% of this voltage isever fed to the comparator, IC2, and so at the end of themarkspace pot, a 60:1 ratio square wave is generated.At the other end of the pot the ratio is 1:1. A 748 is usedas the comparator because it has more bandwidth thanthe 741. As the frequency of the triangle increases, itmay be necessary to use an even faster op -amp for IC2 oreven a comparator.

+Ve ref (+MI 1M

1k

V0OUT

1V/OCTAVE

Exponential Voltage to Current/Voltage Con-verter

The circuit shown converts a linear input voltage into anexponential current or voltage. This type of circuit isused in music synthesisers to change linear controlvoltages into musical intervals. That is, if the circuit wereused to control an oscillator, input increments of 1 Vwould change the pitch by one octave. The exponentialcharacteristics of a transistor are exployed to generatethe correct transfer function. Q1 and Q2 are a matchedpair of transistors, preferably a transistor dual. IC1maintains Q1 at a constant current. Thus, the op -ampserves only to bias the emitter of the second transistorQ2 into a suitable operating region. The purpose of Q1 isto generate this bias voltage. The base emitter junctionof a transistor has a high temperature coefficient (-1.9mV/°C) and so the reason for using a matched pairls touse the first transistor, Q1, to provide temperaturecompensation for the second.

Logarithmic Voltage to Voltage Converter

The output voltage is logarithmically proportional to theinput voltage. The difference between this circuit andthe previous is that the exponentiator is in the feedbackloop of the op -amp and hencd the mathematical functionhas been inverted. The circuit is useful for performingtrue logarithmic compression or for converting linearinputs into dBs.

12 ELECTRONICS CIRCUIT DESIGN WINTER 1980

Simple Triangle to Sinewave Converter

A simple way of converting a triangle to a sinewave isshown. The logarithmic characteristic of the diodes isused to approximate to that of a sine curve. The distor-tion to be expected is of the order of 5%. However, thedistortion may be tolerable if the sinewave is only used togenerate audio tones.

-1.75V

DI. D2 = 1N914

+MY

01NPN

100k SET LEVEL100n

RANDOMNOISE

Noise Generator

The zener breakdown of a transistor junction is used inmany circuits as a noise generator. The breakdownmechanism is random and so generates a small noisevoltage. Also this voltage has a high source impedance.By using the op -amp as a high input impedance, high ACgain amplifier, a low impedance, large signal noisesource is obtained. The preset is, used to set the noiselevel by varying the gain from 40 to 20 dB.

DIGITAL ON//OFF CONTROL

R2100k

R1100k

ADJUST"OFF"

R4100k

01PNP

R647k

Transistor Used To Turn An Op Amp On Or Off

When transistor Q1 is switched off, the circuit behavesas a voltage follower. By applying a positive voltage tothe emitter of Q1 via a 10K resistor, the transistor ismade to turn on and go into saturation. Thus the lowerend of R4 is shorted to ground. The circuit has nowchanged into that of a differential amplifier (see fig 7,Part 1), but where the voltage difference is always Ov.Now as long as the resistor ratios in the two branchesaround the op -amp are in the same ratio then thereshould be zero output. A 4K7 preset is used to null outany ratio errors so that the 'OFF' attenuation is morethan 60dB. The high common mode rejection ratio of a741 enables this large attenuation to be obtained.

Fast Symmetrical Zener Clamping

The problem with using two zeners, back to back inseries to get symmetrical clamping are One: the knee ofthe zener characteristic is rather sloppy. Two: chargestorage in the zeners causes speed problems and Three:the zeners will have slightly different knee voltages andso the symmetry will not be all that good. The circuitovercomes these problems. By putting the zener inside adiode bridge then the same zener voltage is alwaysexperienced. The voltage errors due to the diodes aremuch smaller than those due to the zener. Also thecharge storage of the bridge is much less. Lastly bybiasing the zener on all the time, the knee appears to bemuch sharper.

1N914

VIN

.1*iiN,914

1N914

3k3

+15V

-15V

V OUTVz + 1.2V

(MAXIMUM OUTPUT)


Musical Envelope Generator and ModulatorA gate voltage is applied to initiate the proceedings.When the gate voltage is in on the ON state, Q1 is turnedon, and so the capacitor C is charged up via the attackpot in series with the 1K resistor. By varying this pot, theattack time constant can be manipulated. A fast attackgives a percussive sound, a slow attack the effect of'backward' sounds. When the gate voltage returns to itsoff state, Q2 is turned on and the capacitor is thendischarged via the decay pot and the other 1K resistor,to ground. Thus the decay time consant of the envelopeis also variable.

This envelope is buffered by ICI, a high impedancevoltage follower and applied to Q3 which is being usedas a transistor chopper. A musical tone in the form of asquarewave is connected to the base of Q3. This turnsthe transistor on or off and thus the envelope is choppedup at regular intervals, the intervals being determined bythe pitch of the squarewave.

The resultant waveform has the amplitude of theenvelope and the harmonic structure of the squarewave.IC2 is used as a virtual earth amplifier to buffer the signaland D1 ensures that the envelope dies away at the end ofa note.

.10V

OFF ON. OFF

OV

GATE

OUTPUT ENVELOPE

1M ATTACK

1M DECA

TONE0k INPUT

Drawing circles on a scope

The circuit is that of a quadrature sine andoscillator. Two integrators are employed and there isoverall positive feedback. Thus the system oscillatesproducing sinusoids. Amplitude stabilisation is obtainedwith a diode bridge and a zener diode. The process ofintegration produces a 900 phase shift. Therefore ifthere is a sine wave being put into an integrator, a cosinewill appear at its output. Quadrature oscillators can beused to generate circular displays on oscilloscopes byconnecting the two outputs to the X and Y inputs. Otheruses include quadrature panning in voltage controlledaudio systems and they are also used in audio frequencyshifters.

1N914

270k

COSINE

(\f\I

1N914

5V1 ZENER

SINE(J.00kSET AMPLITUDE

XY SCOPEDISPLAY

V OUT

'N

91.POT ROTATION

Turning a Linear Pot into a Log Pot

By using the virtual earth characteristic of an op amp, alinear pot can be made to have the characteristics of a logpot. It seems to be fair to say that low cost linear pots arefar more linear than log pots are logarithmic. Thus thelinear pot can be turned into a better log pot than theactual log pot itself. By varying the resistor ratio 5k6 to50k, other laws can be produced, such as something inbetween log and linear or maybe a law that is even moreextreme than a log law.


All Pass Notch Filter

Sometimes when processing analogue signals there is aconstant tone which is causing a nuisance and so anactive filter is called upon to notch it out. The filter can betuned so that its notch is at exactly the same frequencyas this signal so that it can be selectively attenuated. Thismethod is sometimes used to remove unwanted mainshum from poor quality recordings. The circuit works asfollows: IC1 and 2 are a pair of all pass filters. These'filters have a flat frequency response, but their phasechanges with frequency. Their overall maximum phaseshift is 360°, a phase shift of 180° occurring at afrequency of 1 / 2CR Hz. At this frequency the signals areinverted. Thus, by mixing the phase delayed signal withthe original, cancellation can be produced which forms anotch in the frequency response. The preset is used toget the deepest notch available. The operatingfrequency can be changed by varying the two resistorsR. For instance for 50 Hz operation, R should be:

10.66k x100050 -213.2k Nearest E12 fit is 220k.

V IN

V OUTV IN

fc - 2-771-CR

fc FREQUENCY

Wk

ADJUSTNOTCH DEPTH

fc = 1kHzC= 15n

R 10k66

V OUT

INPUT 0CLOCK 14

+10V

OV

CK

A

X

CK INH RESET

V OUT

3

CD4017

OUTPUTS

MA"10k

9TIME

TYPICAL COMPLEX WAVEFORM

R9

VDD

Vss

13 08

+10V

04/7

Analogue Linear Segment Drawer

If you want to draw, repeatedly, a complex analoguewaveform with up to 9 discrete sections then the circuitshown will enable you to do it. The CD401 7 is a decadecounter /decoder. A clock is applied to its input and asequence of decoded outputs is generated. That is,output 0 goes high, then output 1, then output 2, etc.Only one output is high at any point in time. This is thesequence generator. There is also an inverter (IC,) whichdrives an integrator (IC2) which can be reset to zero by aswitch. Thus, if we connect output 1 to A, the inte-

v our grator's output will ramp upwards, if we connect it to B itwill ramp downwards and if we connect it to C the switchwill clamp the output to OV. Also, by varying the valuesof R1 to 9, the integrator's ramp rate can be controlled.Thus by selectively routing the outputs to either A, B, orC and by selecting the resistor values, a complex 9

segment waveform can be drawn out.


Simple Musical Envelope Generator

A simple generator can be constructed using theCA3080, made by RCA. This circuit will also enable theuse of any audio waveform the harmonic structure ofwhich will not be significantly affected as it ismodulated. The CA3080 is an op amp with a difference.It has a current output and an extra input into which acurrent, IA is fed. The output is the product of the inputvoltage X IA. Thus the IA can be used to control theamplifier's gain.

Also the input voltage range for low distortion opera-tion is very low, of the order of ± 25mV.

In this circuit, the CA3080 is being used as a twoquadrant multiplier. A small voltage, (± 25 mV), isapplied to its non -inverting input. When the switch S1 isclosed, the capacitor C is charged up and a current ofabout 150$1 A flows into the lA input terminal. When Siis opened, C discharges through the 150k resistor intothe IA input. This current dies away exponentially. As theoutput is the product of the input voltage x IA, then anexponential envelope is generated. Breakthrough afterthe decay is very good, better than -80 dB.

39kV IN 0---AAN1/4---

(M2V P -P

PRESS TOSTARTENVELOPE

///7SW1

+15V

"1\1-1 - Ri+1 MUSTNOT BE GREATERTHAN ±5V

2 OUT = 4k7415V + HYSTERESIS LEVELS

= 4k7 X IA

-15V

Simple Schmitt Trigger withProgrammable Hysteresis

Again the multiplier qualities of a 3080 can be used toproduce a versatile schmitt trigger. DC positive feedbackis used and so a schmitt trigger action is produced,although the size of the hysteresis levels is determinedby IA. All of the IA current flows out of the amplifier'soutput and through R2, thus setting up the hysteresislevel. Therefore increasing IA will increase this level andvice versa. The positive and negative hysteresis levelsare symmetrical about OV.

Simple Speech Filter

The telephone system has been designed for speechcommunication. The bandwidth of the system is 300 Hzto 3400 Hz, which has been arrived at after many yearsof experimentation. Thus, it is true to say that much ofthe information in speech is contained between thesefrequency limits. The circuit shows a filter structure that'will simulate the telephone bandwidth. It could havemany uses, for instance as a 'speech 'filter' for noisyradio reception or land line communications, or as avoice detector for a light show.

boon0-11oon

-11VIN

5k6

V OUTV IN

HP+12dB/

OCTLP-12dB/OCT.

285Hz 3287Hz FREQUENCY

16ELECTRONICS CIRCUIT DESIGN -WINTER 1980

0

+VE

OV

IN IC2

CA314

DATA FROM A DAC

+5V

-5V 'DELAYED GATE PULSE.DATA MUST CHANGE ATREGULAR INTERVALS

II I I I

THE 4016 IS A CMOSANALOGUE TRANSMISSIONGATE

0V OU1

Cleaning Up Digitally Generated SignalsWith 2 Sample and Holds and an integra-tor

The output from a digital to analogue converter (DAC) iscomposed of a series of steps which' have been selectedby a series of binary numbers. The output of the DACmay represent the result of some computation done by amicroprocessor or the contents of a digital memory. Ifthe number of bits that control the DAC is low (less than8), then the output will look like a series of discrete steps,plus lots of digital 'glitches'. Therefore, if this signal is tobe displayed on an oscilloscope, the overall picturequality will be very poor. One way to clean up thingswould be to join up all the steps with straight lines and ifdone successfully a great improvement can be obtained.The only problem is that the distance between steps iscontinuously varying and so the slope of the straightlines will need to be variable as well. This process isknown as linear point interpolation and can be achievedwith two sample and holds and an integrator.

A delayed gate pulse is generated, so that once theDAC's output has settled the sample and hold switchesmomentarily open, sample the information and thenclose. The output of the first sample and hold (IC1)drives an integrator (IC2), the output of which drives thesecond sample and hold (IC3). The second unit providesnegative feedback around the integrator, but it isdelayed by one time interval. Thus a momentary positivegoing signal will pass through the first sample and holdand cause the integrator to ramp in a negative direction.When the next time interval arrives, the first sample andhold returns to OV, and the second obtains a negativevoltage. This then makes the integrator ramp positively.The size of the integrator's capacitor C should be chosento suit the clock speed of the DAC. An inverter, IC4 hasbeen included to correct the inversion caused by theintegrator.

Digitally Controlled Invert/ Non -Invert

The FET is digitally controlled to be either ON (a fewhundred ohms shorting the non -inverting input of the ICto ground), or OFF (an open circuit). When the FET isOFF, the circuit is that of a voltage follower. When theFET is ON, the non inverting input is, to all intents andpurposes, grounded, and so the circuit is that of a virtualearth amplifier with a voltage gain of -1, that is, aninverter.

Controllable Slew Limiter

The current output of a CA3080 can be used to producea controllable slew limiter. The 3080 is used as a voltagefollower, but with a capacitive load. Thus it is possiblefor this stage to correctly follow small signal variations,but to slew limit when the input signal is larger. Thespeed of the slew limiting is determined by the current

A high input impedance voltage follower (CA3140) isused to buffer the signal. This circuit is sometimes usedas a non-linear filter to limit fast signals; also, it can beused as a portamento circuit for a music synthesiser.

INVERTOV

NON INVERT

--15V

CONTROL 15kCURRENT

V OUT

ELECTRONICS CIRCUIT DESIGN - WINTER 1980 1 7

ETIPRINTS are a fast new aid for pro-ducing high quality printed circuitboards. Each ETIPRINTS sheet con-tains a set of etch resistant rub downtransfers of the printed circuit boarddesigns for several of our projects.

ETIPRINTS are made from our originalartwork ensuring a neat and accurateboard. We thought ETIPRINTS weresuch a good idea that we havepatented the system (patent numbers1445171 and 1445172).

PARTS LISTShown below is the listing for Earlier sheets are available,the last year's ETIPRINTS. ring Tim Salmon for details.

026 Motor Speed Controller 033 LED Audio Display (2 boards) Aug 79 036D Power Switch Nov 79(2 Boards For Controller) (topside pattern) SelectorBattery Indicator July 79 Bench Amp (double sided)

NICD Charger037A Encoder Dec 79

(double sided)027 CCD Phaser Project 034 Cable Tester Nov 79Rev. Monitor Book Reaction Tester 037B Decoder (top side) Dec 79

Seven Speech CompressorPreamp Power Supply 037C Decoder Dec 79

028 Race Track, Spirit Level Project Rectifier & De -Thump (bottom side)Egg Timer, Bongos Book BoardBench Supply, Oscillator Seven Power Amp (2) 038A Long Period Dec 79

(price £1.60) TimerRain Alarm029 Bass Enhancer Project 035 Oven Leakage Detector Nov 79 Touch SwitchDigital Freq. Meter (4 boards) Book Pinball Wizard Flash Trigger

Seven Pseudo Random036A 3 x Display Board Nov 79 Noise Gen

030 ETIWET, Continuity Tester Project Relay ActivatorMetal Locater, Light Dimmer Book Points Controller 038B Hum FilterUltrasonic Switch (2 boards) Seven Dice

036B Data Distributor Nov 79 Logic Probe Dec 79031 Tone Control Project (double sided)

House Alarm (2 boards)Torch Finder

BookSeven

036C Train SpeedController

Nov 79038C Function

Generator Dec 79

Track Cleaner & 039 Buffer032 LED Audio Display (2 boards) Aug 79 Electronic Pot Moving Coil Preamp(underside pattern) (double sided) Process Controller Jan 80

HOW IT WORKSLay down the ET/PR/NT andrub over with a soft penciluntil the pattern istransferred to the board. Peeloff the backing sheetcarefully making sure thatthe resist has transferred. Ifyou've been a bit carelessthere's even a 'repair kit' onthe sheet to correct anybreaks!

BUY LINESORDER TODAY

Send a chOque or P 0 (Payable to ETI fYlaaazine) to

ETI PRINT, ETI MAGAZINE145 Charing Cross Road, London WC2H OEE

8018

INC P & PELECTRONICS CIRCUIT DESIGN -- WINTER 1980

TRANSISTOROPERATING POINTDesigning a transistor amplifier? Take the guessing out of finding the correctDC or static operating point of a transistor with this simple approach byW. R. Masefield.

In the design of transistor amplifiers, one of the firstconsiderations is to establish the correct DC or staticoperating point for the transistor. Probably the most

common method used by the amateur is that of having aguess, followed by trial and error juggling with com-ponents on the breadboard.

There is no need for that; there is a way of predictingthe operating point and finding some of the circuitcomponent values to be optimised before leaving thedrawing -board. Nor is any advanced mathematics used,but it is as well to have a calculator with logs to basee facility.

Common LawWhatever circuit configuration is used, common emitter,common base, common collector (emitter follower), thefact does not alter that there is a certain relationshipbetween the base -emitter voltage V and the emittercurrent IE. This relationship is exponential, and, becauseof this, a plot of In I, against VBE is a straight line as in fig.1.

Vbe

0.8

0.4

0.2

10 8 -6 -4 -2 0 Inge)

Fig. 1. As the 1E, vb. relationship is exponential, a graph of In IEagainst VBE is a straight line.

It is a simple matter to verify this, using the circuit offig. 2. The voltmeter must have a high impedance,otherwise the value of 1, will be incorrect.

As the graph is a straight line, it can be described bythe linear equation:

VBE = m(InIE)+Vo (1)

Fig. 2. The circuit used to verify the relationship between IE andVBE.

This equation is extremely useful, and it is worthwhiledetermining the slope, m, and the intercept, Vo for anytransistor to be used in the circuit under development.

As the graph is a straight line, only two points areneeded to determine it. One point is given by the intercepton the V axis. This is V° and is the base -emitter voltagewhen the loge of the emitter current is zero, i.e. when 1, =1 mA.

If the emitter current is now changed to 1E, and thecorresponding base -emitter voltage is VBE, then the slope,m, is given by

Vo-VBE(2)m-

Inl

This turns out to be of the order of 30 X 10-3 when VBEis in volts and IE is in mA.

The only other parameter required is hFE. Note that thisis not hie which is the dynamic forward current transfer.hFE is the static forward current transfer, and can bedetermined by measuring lc and I,. Then:

hFE = 117 (3)

Armed with these three parameters, m, V° and hFE, theoperating conditions in any circuit can be found. Theseare summarised below. The resistor suffixes have been sochosen to make things easier when writing a calculatorprogram for speeding up the calculations.


Fig. 3 Common Emitter Mode with base potential bias

The given conditions will be supply rail voltage, V, thedesired collector voltage Vc, generally half rail voltage, thecollector load, R3, to give a suitably low output resistanceand economical lc, and the potential divider R,, R2 to takea current that is likely to swamp the base current and sogive a fixed reference voltage, usually about 2V at thebase. Then.

V. R2VB- (4)

(5)V-V,

.` R3

1

IE = lc( 1 +-)hFE

(6)

VBE = m(In 1E) + Vo (7)

VE = VB-VBE (8)

R4 =VE

(9)(9)

This sequence therefore enables the critical resistor R4to be determined accurately.

Fig. 4 Common Emitter with Bcse-Collector Resistor Bias

Given the supply rail voltage, V, the collector voltageVc about half V, and the emitter voltage, VE generally 1volt, the load R3 is again chosen as a compromise betweenlow output resistance and low collector current, then:

Vcc c (10)RV

R VE (1 1 )E

IE

IB (12)1 +h FE

VBE =m(InIE)+V. (13)

VEtt = Vc -VBE-VE (14)

VR.= RI(15)

le

This sequence enables both R, and R4 to be deter-mined accurately.

Fig. 5 Common Collector (Emitter Follower)

Given the supply rail voltage, V, the emitter voltage, VE,usually half the rail voltage, and the emitter load, R4is chosen to give a compromise between low outputresistance and economical emitter current, then:

VE- (16)

VBE=m(InlE)+Vo (17)

VB = VE VBE (18)

I (19)1B- 1+ hu

Vc, -VBR1 - (20)

18

This sequence allows R, to be found accurately.Although on paper the above sequences look

laborious, if a programmable calculator is available, it ispossible to put all of them into program memory, and alldata in the data registers, then try different values ofresistors until optimum values are found. At this, stage thebreadboard may be prepared, in the knowledge that thevalues obtained will be close to those actually needed.


40 CMOS CLOCKSThere are many ways of using the CD4001 and CD4011 CMOS ICs to makebistable, astable and monostable multivibrator circuits. Ray Marston presentsthe definitive work on the subject, with 40 practical circuits.

The amateur and professional circuit designer oftenfinds himself in the situation where he needs to usea minimum -cost CD4001 or CD401 1 CMOS pulse

or clock generator circuit, or where he needs to use a fewspare CMOS NAND or NOR gates from an existing circuitto make up a multivibrator that will meet his specificdesign needs. In either case, the designer will find aconcise guide to practical NAND- or NOR -gate CMOSmultivibrator circuits of inestimable value.

This is just such a guide. It presents some fortydifferent ways of using the low-cost CD4001 andCD401 1 quad 2 -input gate CMOS integrated circuits inbistable, astable and monostable multivibrator applica-tions. All of the circuits shown can be operated over thefull five volts to fifteen volts supply range when usedwith 'B' series CMOS.

0-- -O.

OUT

41.1.11411441

Fig. 1. Outline and pin connec-tions of the CD4001.

THE CD4001 and CD4011 ICsFigures 1 and 2 show the outlines and pin connectionsof the CD4001 and CD401 1 integrated circuits. Thesetwo ICs are quad 2 -input gates. The CD4001 providesNOR gate functions and the CD401 1 provides NANDgate functions. Fig. 1 shows the truth table of each of thefour NOR gates of the CD4001 Note that the output ishigh if both inputs are low, but goes low if either or bothinputs go high. Fig. 2 shows the truth table of each of thefour NAND gates of the CD401 1 . The output is normallyhigh and goes low only if both inputs are high.

0-

OUT

Fig. 2. Outline and pin connec-tions of the CD4011.

OV

The CD4001 and CD401 1 are very inexpensive ICs.They typically retail at about 16 pence each in one-offquantities (allowing for some variation between sup-pliers), which works out at about 4 pence per gate. Theycan be used in a wide variety of very useful two -gatemultivibrator applications and are thus highly cost-effective devices.

Bistable Multivibrator CircuitsThe CD4001 and CD401 1 can both be used in two -gateR -S (Reset -Set) bistable multivibrator circuits, but havequite different input triggering requirements. Fig. 3shows the practical circuit and waveforms of a pulse -triggered NOR version of the bistable. The circuit hastwo outputs, a normal output from ICla and an invertedoutput from IC1 b. When a positive -going trigger pulsewhich switches between roughly zero and full supply isapplied to the IC1 b input, the normal output sets highand locks in this state irrespective of any further signalsat the input of '1C1 b. The output can only be reset lowagain by applying a positive -going pulse to the input ofICla, at which point the output goes low and is thenimmune to any subsequent trigger pulses at the input ofIC1 a.

+Ve

WeOV

RESET

SETR1

10k to10M

OUT

OUT

ICI IS 4001

SET RESET

+Ve

ov

ov

+Ve

Fig. 3. Practical circuit of a pulse -triggered NOR bistable.

Note that the input terminals of IC1a and IC1 b aretied to ground (the zero -volts line) via R1 and R2: theseresistors can have any convenient values in the range10k to 10M. If inputs to IC 1a and IC1 b are direct -coupled from preceding logic networks, however, R 1and R2 can be omitted from the circuit.

Manual NOR GateFig. 4 shows a manually -triggered version of the Fig.3 NOR gate circuit. This type of circuit is often referred toas a 'noiseless' switch, since its output is unaffected bythe contact bounce, etc., of its two control switches.


SET RESET

+Ve

_J L 0v

'SIiET

ICI IS 4001

Fig. 4. Manually triggered NOR bistable.

+Ve

OV

NAND BistableFig. 5 shows the CD401 1 NAND gate version of thebistable circuit. This circuit is almost identical with thatof Fig. 3, except for the positioning of R1 and R2. Note,however, that the NOR gate circuit needs positive -goingtrigger pulses, while the NAND circuit needs negative -going pulses, and that the set pulse is applied to ICI b inthe NOR circuit, but to IC1a in the NAND circuit.

RI10k TO10M

+Ve

OV SET

RESET+Ve

OV

Vdd

R210kTO 10M

OUT

OUT

SET

J

ICI IS 4011

Fig. 5. A CD4011 NAND bistable, pulse triggered.

Manual NAND BistableVdd

SET

RESET

+Ve

OV

+Ve

OV

RESET

OV

+Ve

I OV

Fig. 6. Manually triggered NAND bistable.

Fig. 6 shows the manually -triggered version of theNAND -type bistable. Note here that although R1 and R2are shown as having values of 10k, they can in fact haveany resistance values from a few thousand ohms up toabout 10M, depending on the precise details of thespecific application. This versatility leads to the deve-lopment of the touch -triggered NAND bistable circuit ofFig. 7, in which R1 and R2 have values of 10M, and thecircuit can be triggered by placing any resistance that issignificantly less than 10M (such as finger resistance)across the touch contacts. R3 and R4 are used in thiscircuit to protect the inputs of the two gates.

+Ve

ov

Vdd Vdd

SET RESET

I +Ve

L ov

IC1 IS 4011

Fig. 7. Touch -triggered NAND bistable.

+Ve

OV

The bistable circuits that we have looked at so far alluse same -polarity (either both positive or both negative)trigger signals. In some applications, however, it isnecessary or convenient to use opposite -polarity signalsto trigger the bistable, and this type of action can beobtained by placing an inverter stage in series with oneor other of the normal bistable input terminals. Figs. 8and 9 show two alternative circuits of this type.

+Ve

O IV

+Ve

R110k TO10M

SET

RESET

ov

Vdd

R210k TO10M

SET RESET

+v.

0v

+Ve

ov

OUT

OUT

IC1 IS 4011

Using opposite -polarity signals to trigger a 4011 bistable, Fig. 8(above), and a 4001 bistable, Fig. 9 (below).

Vdd

R210k TO10M

RESET

OV

SET

OUT

IC1 IS 4001

OUTR110k TO10M


Fig. 10 shows alternative ways of connecting a2 -input NAND or NOR gate so that it acts as a simplepulse inverter stage. These circuits are useful in amultitude of applications.

VDD

IN 4011

OR 0--EIN

4001

IC1aOUT

4011

ORIN

vss

4001

Fig. 10. Using a 2 -input NAND or NOR gate as an inverter.

OUT

OR

Basic 2 -Gate Astable CircuitsThe CD4001 and CD401 1 can both be used in a varietyof basic 2 -gate astable multivibrator circuits. In thesecircuits the gates are connected as simple inverters, sothe two types of IC give identical performances.

CMOS AstableNOTE:IC1-4001 OR 4011

0v

Fig. 11. Circuit of the basic 2 -gate CMOS astable.

The most basic and useful 2 -gate CMOS astablecircuit is shown in Fig. 11. This circuit generates adecent square wave output, has excellent thermalstability and operates at about'l kHz with the componentvalues shown. The frequency is inversely proportional tothe C -R time constant, so the frequency can be raised bylowering the values of either Cl or R 1. In practice, Clmust be a non -polarized capacitor, and can have anyvalue from a few tens of picofarads to a few micro -farads. R1 can have any value from about 4k7 to 10M.For variable frequency operation, wire a fixed and avariable resistor in series in the R1 position.

The output of the Fig. 11 astable circuit switches(when lightly loaded) almost fully between the zero andpositive supply voltage levels, but the junction of R1 andCl is prevented from swinging below zero or above thepositive rail levels by the built-in clamping diodes at theinput of IC1a. This characteristic causes the operatingfrequency of the circuit to be somewhat dependent onsupply rail voltages. As a rough rule of thumb, thefrequency falls by about 0.08% for each 1% rise insupply voltage. Typically, if the frequency of this astableis normalised with a 10 volt supply, the frequency willfall by 4% at 15 volts, or rise by 8% at 5 volts.

Also, the operating frequency of the Fig. 11 circuitdepends somewhat on the transfer voltage value of theindividual gate that is used and can be expected to varyby as much as 10% between individual ICs. The outputsymmetry of the waveform is also dependent on thetransfer voltage value of the IC and, in most cases, thecircuit will give a non -symmetrical output. In the vastmajority of 'hobby' and other non -precision applica-tions, these deficiencies of the basic astable circuit are oflittle practical consequence.

Some can be minimised by using the 'compensated'astable circuit of Fig.12, in which resistor R2 is wired inseries with the input of IC 1 a. This resistor can have anyvalue between two and ten times that of R1, and its mainpurpose is to allow the R 1 -C1 junction to swing freelybelow the zero and above the positive supply railvoltages during the switching action and thus reduce thedependance of the 'circuit operating frequency on thesupply voltage. Typically, when R2 is given a value tentimes greater than R1, the frequency varies by onlyabout 0.5% when the supply voltage is varied between5 and 15 volts.

NOTE:IC1=4001 OR 4011

OUT

Fig. 12. A compensated astable circuit.

OV

The basic and compensated astable circuits of figs.11 and 12 can be built with a good number of detailvariations. Some of these are shown in Figs.13 to 18. Inthe basic astable circuit, for example, C1 alternatelycharges and discharges via R1. Figs. 13 to 15 show howthe basic circuit can be modified to give alternate C1charge and discharge paths.

NOTE:IC1=4001 OR 4011D1=IN4148

Ov

Fig. 13. Modifying the circuit to give C1 alternate charge anddischarge paths and produce a non -symmetrical outputwaveform.

Fig. 13 shows one way of modifying the astable so thatit gives a non -symmetrical output waveform. Here, C1charges in one direction via R1 and R2 in parallel, to givea high output, but discharges in the reverse direction viaR2 only, to give a low output.

NOTE:IC1-4001 OR 4011D1,D2=1N4148

Fig. 14. Controlling the astable's on and off time.

Ov

On/Off ControlFig. 14 shows how the circuit can be further modifiedby also wiring a diode in series with R2, so that the ONtime of the output is controlled only by Al, and the OFFtime is controlled only by R2. These two circuits can bemade to give variable outputs by replacing either or bothof their timing resistors with a fixed and a variableresistor in series.


Variable SymmetryFig. 15 shows how the astable can be modified togive a variable symmetry or M /S -ratio output, whilemaintaining a near -constant frequency. Cl in this circuitcharges in one direction via D1 -R2 and one half of RV1and in the other direction via D2 -R 1 and the other half ofRV1. The M /S -ratio can be varied over the range 1:10to 10:1 via RV1.

NOTE:IC1=-4001 OR 4011D1,D2=1N4148

OVOUT

Fig. 15. Controlling the mark/ space ratio.

Fig. 16 shows the circuit of a multi -tone push-buttonactivated astable. Normally, when all push-buttonswitches are open, R5 holds the input of IC1a (and thusthe output of IC1b) low. Resistors R1 to R4 all havevalues that are low relative to R5, so the circuit acts as anormal astable when any one of the push-buttonswitches is closed. This circuit can be used in multi -tonemusical instruments and gadgets, etc. and has the majoradvantage that it draws negligible current when in thestandby mode. There is no limit to the number ofpush-button switches that can be used with the circuit.

R510M

PBI PB2 IPB3

R1 R2 R3

NOTE:IC1 = 4001 OR 4011R1-R4=10k TO IMO

Fig. 16. Circuit of a multi -tonepush button activated astable.

NOTE:IC1 = 4001 OR 4011

FM ORVOLTAGE -CONTROLINPUT R2

100k

Fig. 17. Frequency modulation of an astable.

PRESSPB

OV

OUT

OV

OUT

Frequency ModulationFig. 17 shows how the astable can be subjected tofrequency modulation or voltage control of frequency bysimply feeding the FM or voltage -control signal to theinput of IC1a via a resistance that is much larger than R1and Fig. 18 shows how the circuit can be furthermodified to act as a special -effect voltage -controlledoscillator that shuts off when the input voltage fallsbelow a pre-set value.

ICI IS 4001 OR 4011

yin

RV1100kSETCUT-OFFVOLTAGE RISING VOLTAGE

it It

CUT-OFF

+Ve

OV

Fig. 18. Using an astable as a voltage -controlled oscillator withan output cut-off.

Gated 2 -Gate Astable Circuits

GATEJ

IC1 IS 4011

+Ve

OV

+Ve

OV

Fig. 19. A NAND astable with a normally -low output, gated by ahigh input signal.

All of the astable circuits of Figs. 11 to 15 can bemodified for gated operation, so that they can be turnedon and off via an external signal, by simply using a2 -input NAND or NOR gate in place of the inverter in theIC1a position and applying the input control signal toone of the gate input terminals. The CD4001 andCD401 1 ICs can both be used in this type of application,but give quite different types of gate control and outputoperation. Figs. 19 and 20 show the two basicversions of the gated astable circuit.

,ve

ov

+Ve

OV

GATE ICI IS 4001

Fig. 20. A NOR astable with a normally -high output, gated by alow input signal.

Note that the Fig. 19 NAND astable circuit has anormally -low output and is gated by a high input signal,while the fig. 20 NOR astable has a normally -highoutput and is gated by a low input signal. Also note that,although R2 is shown in the diagram as having a value of10k, R2 can in fact have any value in the range 10k to10M and can be omitted altogether if the gate signal isapplied from a preceeding logic state.


Note in the Fig. 19 and 20 circuits that the outputsignal terminates immediately the input gate signal isremoved. Consequently, any noise present at the gateterminals of these circuits also appears at their outputs.

GATEINPUT

GATEINPUT

D2

GATE]

OUT

IC1 IS 4011D1&2 ARE 1N4148

+Ve

OV

+Ve

OV

Fig. 21 (above) and Fig. 22 (below) overcome the problem ofnoise appearing at the gate terminals.

IC1 IS 4001D1&2 ARE 1N4148

- +V

Ov

Figs. 21 and 22 show how the circuits can be modifiedto overcome this defect. Here, the gate signal of IC1a isderived from and from the outputof IC1b via diode OR gate D1 -D2 -R2. As soon as thecircuit is gated from the outside world via D2 the outputof IC1b reinforces the gating via D1 for the duration ofone half astable cycle, thus eliminating any effects of anoisy outside world signal. The outputs of the circuits arecomplete numbers of half cycles. Note that R2 is anessential part of these circuits.

OUT

Pal(CLOSED)

' OV

PalCLOSED

--I I --

-1_111-1.11- +V'OV

Fig. 23 (top) and Fig. 24 (above) show manually -triggeredastables with noise -elimination networks.

Figs. 23 and 24 show manually -triggered versions ofthe Fig. 21 and 22 circuits. These circuits are of partic-ular value when they are used as low speed clockgenerators, operating at about 5 Hz: when PB 1 is brieflystabbed, the generate a single clean clock pulse: whenPB 1 is held down, they generate five clean clock pulsesper second.

Clock Generator Circuits

IC1=4001 OR 4011

RV147kSET

ile;H 11*. 111*.

ov

OUT

Fig. 25. Speeding up the rise and fall times of the astable outputto produce clean clock signals.

.The 2 -gate astable circuit is generally not suitable fordirect use as a clock generator with fast -acting countingand dividing circuits. Such circuits require the use ofclean clock signals, with fast rise and /or fall times. Theproblem is that 2 -gate astables designed around 'A'series or non -buffered CMOS produce clock outputswith rather slow rise and fall times, whereas 2 -gateastables designed around buffered -output 'B' seriesCMOS produce outputs with good rise and fall times, buttend to produce "dirty' clocking if there is the slightesttrace of noice on their power supply lines.

Fortunately, these problems can easily be overcomeby wiring a couple of inverter -connected gate stages inseries with the output of the astable circuit, as shown inthe example of Fig. 25. These inverter stages speed upthe rise and fall times of the astable output waveformand also produce effective level shifting between theoutput of the astable and the clock input terminal of anyexternal device, thereby reducing or eliminating theeffects of noise on the clock circuit.

The Ring -of -Three Astable Circuit

IC1-4001 OR 4011 OV

Fig. 26. The 'ring of three' astable circuit produces a very clean

output waveform.

An alternative way of making a clock generator is to usethe 'ring -of -three' astable circuit of Fig. 26. This circuit issimilar to the basic circuit of Fig. 11, except that thepositions of R1 and Cl are transposed, and the invertinginput stage (1C1a) of the Fig. 11 circuit is effectivelyreplaced by an ultra -high -gain non -inverting stage(comprising IC1a and IC1b in series) in the Fig. 26


circuit. Because of the very high gain of its compositeinput stage, the Fig. 26 "ring -of -three" circuit produces avery clean output waveform, with excellent rise and falltimes, and is directly suitable for use as a clock genera-tor.

The "ring -of -three' astable circuit can be subjected toall of the basic design variations shown for the 2 -gateastable. For example, Cl alternatively charges anddischarges via R1 in the same way as in the Fig. 11circuit, so the circuit can be subjected to all of thevariations shown in Figs. 13 to 15. It can be designed ineither basic or 'compensated" versions, etc.

VDD

GAT F+,ov

0

Fig. 27. A gated NOR 'ring of three' circuit with a normally lowoutput, gated by a low input.

the "ring -of -three" circuit offers interestingpossibilities when it is used in the gated mode, becauseit can be gated on and off via either its IC1b or IC1cstages. Figures 27 to 30 show four variations on thistheme.

VDD

GAT

IC1=4001

0v

OV

Fig. 28. A gated NOR 'ring of three' circuit with a normally highoutput, gated by a low input.

Figs. 27 and 28 show alternative versions of thegated NOR -type 'ring -of -three' circuit. Both circuitsneed a 'low' signal to gate the astable on. Note that theoutput of the circuit is normally -low if the gate signal isapplied to IC1c, or is normally -high if the gate signal isapplied to ICI b.

GAT

R168k

10n

IC1b IC1c

100k

IC1,4011

GAT!]

OUT

Fig. 29. A gated NAND 'ring of three' circuit with a normally lowoutput, gated by a high input.

OV

GATEI L

Fig. 30. A gated NAND 'ring of three' circuit with a normally highoutput, gated by a high input.

Similar variations are found in the NAND version ofthe gated 'ring -of -three' circuit, as shown in Figs. 29 and30. These circuit need a "high" signal to gatethem on, and have a normally -low output if the gatesignal is fed to ICI b, or a normally -high output if the gatesignal is fed to IC1c.

Monostable Multivibrator Circuits

4-Ve

OV -

IN

Fig. 31. A 2 -gate NOR monost-able multivibrator.

Vdd

IN ' ovA -1--7 VeIOV

OUT --I 1.----------+Ve

OV4'1 ls/uF F.

OV

The CD4001 and CD401 1 can both be used to makean exceptionally useful type of 2 -gate monostablemultivibrator or pulse generator circuit. The two basicversions of this circuit are shown in Figs. 31 and 32.In these circuits the duration of the output pulse isdetermined by the values of R1 and C 1 , andapproximates one second per microfarad of Cl valuewhen R1 has a value of 1M 5. In practice, Cl can haveany value from roughly 100 p to a few thousand u, andR1 can have any value from about 4k7 to 1 OM.

One outstanding feature of these circuits is that theinput trigger pulse or signal can be direct coupled andhas no appreciable effect on the length of the circuit's

ov output pulse: the trigger pulse can be shorter or longerthan the output pulse. The NOR version of the circuit hasa normally -low output, and is triggered by a positive -going input pulse, while the NAND version of the circuithas a normally -high output and is triggered by anegative -going input pulse.

A signal feature of these circuits is that the pulsesignal appearing at point "A"' has a length that is equalto that of either the output pulse or the input triggerpulse, depending on which is the greater of the two. Thisfeature is of value when making pulse -length compara-tors and over -speed alarms, etc.


The Fig. 31 and 32 circuits have,only two significantdefects. One of these is that the pulse length dependssomewhat on the transfer voltage value of the individualIC that is used in the circuit. The other is that the pulselength also depends somewhat on the supply voltagevalue that is used with the circuit, just as the operatingfrequency of the basic 2 -gate CMOS astable variesslightly with the supply voltage value. These defects areof little consequence in most practical applications,however.

+Ve -IN

OV -

Vdd

R210k C1

1u0

R1

1M5 IC1 IS 4011

OUT

j+Ve

OV

Fig. 32. A 2 -gate NAND +Ve

Amonostable multivibrator. OV-4OUT +Ve

OV

If a number of the Fig. 31 and 32 circuits are to beinterconnected to give cascaded delays (as in a

delayed -pulse generator, for example), an inverter stagemust be interposed between the outputs and inputs ofsuccessive monostables, to give correct -polarity triggersignals. Figure 33 shows the basic system.

OUT 1 OUT 2

0

M0.119 MONOT MONO0-TRIGGER

3

INPUT

Fig. 33. Using monostables withinverters to produce cascadeddelays.

OUT 30

IN

OUT1 -n--OUT2

OUT3

Alarm Call Sound Generator CircuitsA single CD4001 or CD4011 IC and one or moretransistors can readily be used to make a variety of typesof very useful alarm call sound generator circuits.Figs. 34 to 41 show some practical circuits of thistype. In all cases, the circuits can be powered from anysupply in the rartge 5V to 1 5V and can be used with anyspeaker in the range 3R to 100R. Output powers rangefrom tens to hundreds of milliwatts, depending onspeaker impedances and supply rail voltages used, butcan readily be boosted to tens of watts by using additio-nal transistor power -boosting stages.

Vdd

P81 ITRESET

SET

R110k

IC1a

1CM

100RTOTAL

Fig. 34. Circuit of a NOR latching monotone alarm call generator.

Figs. 34 and 35 show two versions of a latchingmonotone alarm call generator. IC1 a and ICI b are wiredas a bistable multivibrator and when a trigger pulse isapplied to the circuit the IC1a-IC1b bistable self -latchesand switches on the IC1c-IC1d-1 kHz astable tonegenerator. The circuit can be reset to the OFF state bymomentarily closing PB1.

Idle

R368k

Cl10n

SET

IC1 IS 4011Q1 IS 2N3904

RESET

SET

Vdd

R110k

Vdd

R210k

0P131

RESET

/7)77

IC1a

IC1b

100RTOTAL

Fig. 35. Circuit of a NAND latching monotone alarm callgenerator.


10n

ICI = 400102 2N3906

Vdd

_n__ 0TRIGGERINPUT Al

10k

IC1a

Fig. 36. A NOR alarm call generator with auto turn-off.

Figs. 36 and 37 show versions of an auto -turn-offmonotone alarm call generator. IC 1 a and IC1b are wired.as a monostable multivibrator, which turns on theIC1c-IC1d astable for about 10 seconds each time that itis triggered.

-ITRIGGERINPUTINPUT

0

RI10k

Vdd

IC1a

R2IM5

10u

Fig. 37. A NAND alarm call generator with auto turn-off.

The Fig. 38 and 39 circuits generate a pulsed -tonesignal, in which a 1 kHz astable (IC 1 c and IC 1 d) is gatedon and off by a 6 Hz astable (IC1a and IC1b) when asuitable control signal is applied to the input terminal ofIC1a.

Finally, Fig. 40 shows a warble -tone generator, whichswitches through a 2 -tone cycle once per second when asuitable control signal is applied to the inputs of IC1aand IC1c, and which generates a sound similar to aBritish police car siren. The depth of frequency varia-tion of the circuit is determined by R3, which can haveany value in the approximate range 1 20k to 1 MO.

100RTOTAL

ICI = 4001Q1 = 2N3906

II10n

R410k

ON OFFCONTROLINPUT

RI10k

0

Vdd

Fig. 38. Generating a pulsed -tone signal with 6Hz and 1kHzNOR astables.

ON OFF

CONTROLINPUT

10n

= 401101 = 2N3904

RI10k

Vdd

10ORTOTAL

Fig. 39. Generating a pulsed -tone signal with 6Hz and 1kHzNAND astables.

ON OFF

Syr

O

CONTROLINPUT

Vdd

R110k

10n

C1 = 4001Q1 = 2N3906

100n

R3120k TOIMO

Vdd

Fig. 40. A warble -tone generator - sounds like a police car siren.

100RTOTAL


PRACTICAL GUIDETO REED SWITCHES

he dry reed is an almost per-fect low -current switch.

It is fast - operating timesof less than one millisecond aretypical. It is reliable - as many asone billion operations can beachieved. And it is cheap - quantityprice is well under 25p.

The dry reed switch is not by anymeans a new device for it was in-vented back in 1945 by Dr W. B.Ellwood of the USA's Western Elec-tric Corporation.

But it was ahead of its time. Itremained practically unnoticed bythe engineering world until a decadeago when it was 'rediscovered' bythe telephone industry.

And since then reed switches arereceiving interest and acceptance atan ever increasing rate.

In its basic form, a reed switch is amagneto -mechanical relay. In otherwords it relies upon a magnetic forceto initiate a mechanical switchingaction.

ONTACTS

ENVELOPEnFILLED WITHI INERT GAS

REEDS

GLASS ENVELOPE

CONNECTIONS

Fig. 1. The basic reed switch.

THE BASIC SWITCHA typical reed switch is shown in

Fig. 1. It consists of two flattenedferromagnetic reeds sealed in a glasstube. The reeds are fixed, one ateach end of the tube, so that theirfree ends overlap in the centre butwith a 0.01" gap between them.

During the sealing operation theair inside the tube is pumped out andreplaced by dry nitrogen so that thecontacts operate in an inertatmosphere.

When the reed switch is broughtwithin the influence of a magnetic

The reed switch is functional andversatile. It is almost the simplestelemental form of switch and hasinnumerable applications - fromstraightforward functions in whichswitch actuation is initiated by theproximity of a permanent magnet -to complex logic and computingfunctions, using hundreds ofelectromagnetically driven reeds.The practical three-part series, byCollyn Rivers, explains how andwhy they are used.

MAGNET POSITIONFOR PULL -IN

3"

MAGNET POSITIONFOR DROP -OUT

Fg. 2. The reeds close when the magnet isbrought within one inch, and will remainclosed until the magnet has been moved atleast three inches away.

field (either from a coil or a magnet)the reeds - being ferromagnetic -become a flux -carrying portion of themagnetic circuit. The extreme endsof the reeds will assume oppositemagnetic polarity, and if sufficientflux is present, the attraction forcesovercome the stiffness of the reedsand they flex towards each other andtouch.

When the magnetic field isremoved the reeds spring back totheir original positions. There ishowever a difference between thevalue of field required to close thereeds, and the reduced value thatwill allow them to open again. -

A typical example of this is shownin Fig. 2. In this example the reedsclose when the magnet is broughtwithin one inch, but they will remainclosed until the magnet has beenmoved about three inches away.

This phenomena - which iscaused by magnetic hysteresis in thereeds - can be considerably

MAGNET(FIXED)

MAGNET(MOVING)

Fig. 3. A fixed magnet of opposite polarity tothe moving magnet may be used to reducepull -in, pull-out differential.

reduced by introducing a secondmagnet, of opposite polarity, on thefurther side of the switch. This isillustrated in Fig. 3. The fixed mag-net must not be mounted within thenormal pull -in position for singlemagnet operation, otherwise thereed switch will be held in a closedposition by the second magnet andwill open when the moving magnetis brought close to the switch. Byselecting the correct types andstrengths of magnets the differentialcan be set to practically any requiredvalue.

1N

1-1MAGNET

(FIXED)

11

S

N

MAGNET(MOVING)

Fig. 4. 'Normally closed' operation can beobtained by biasing a 'normally open' reedswitch with a fixed magnet. The movingmagnet cancels out the fixed magnet andthus allows the switch to open.

Fig. 5. This type of reed switch may be usedfor either change -over, or normally closedoperation.

ELECTRONICS CIRCUIT DESIGN -- WINTER 1980 29

(A)

Magnetic

shield cam

(C)

Tachometer applications, requiring thesimplest addition to the moving part andoffering ability to work in unfavourableconditions, plus high speed operation.

a

I

a

b

- -C

Fig. 6. Linear planes of operation; movementof the magnet in any of the planes indicatedmay be used to actuate the switch.

Magnets

(D)

(8)

Fined magnet

Magneticshield cam

Fig. 7. Rotary motion may also be used toactuate a reed switch. In A and B theswitches are stationary and the magnetsrotate. In examples C and D both theswitches and the magnets are stationary andthe switch operates whenever the cutoutportion of the magnetic shield is betweenmagnet and switch.

30

OPERATING MODES

As can clearly be seen in Fig. 1,the reed switch is 'normally open'.The reeds close when a magnet isbrought close to the switch enclos-ure.

However there are many applica-tions where the switch is required tobe 'normally closed' and to openwhen the magnet is introduced. Thiscan be done either by biasing theswitch with a second magnet (asshown in Fig. 4), or by using a reedswitch with change -over contacts(Fig. 5).

In most applications where a reedswitch is opened or closed by apermanent magnet, the magnet isfitted to a moving part, and the reedis fitted to a stationary part.

There are, however, a number ofapplications in which both the mag-net and the reed must be located ona stationary component. Operationmay then be effected throughdistortion of the magnetic field by anexternal moving ferrous mass. If themagnet and the reed are sufficientlyclose, the reeds switch will be nor-mally closed, but will be opened bythe magnetic shunting effect of theexternal ferrous object. Altern-atively, the magnet may be locatedso that the reeds are normally openand the external ferrous object usedto 'reinforce' the field and thus closethe reeds.

There are many different ways inwhich a moving magnet may becaused to operate a reed switch.

Linear planes of operation areshown in Fig. 6; movement of themagnet in any of the planes a -a, b -b,and c -c will operate the switch.Magnet selection is fairly ciritical ifthe switch is operated in mode b -b,spurious operation may be causedby negative peaks on the magnet'sfield pattern curve. If these are large,the reeds will pull -in three times asthe magnet is moved from one endof the switch to the other.

Rotary motion may also be used.Various ways of achieving this areshown in Fig. 7. (A most versatileand simple impulse generator can be

put together in a few minutes byplacing one or more magnets on agramophone turntable and fasteninga reed switch to the motor baseboard (Fig. 8). Switching rates fromapprox one every two seconds towell over 2,000 a minute can beselected merely by changing theturntable speed and /or using moremagnets!)

Since the reed switch is truly a

Flow control and indication, minimisingrestraint on the moving part and avoidingperforation of the container wall.

Position control and indication, obviatingmechanical contact with its implications ofwear, and simplifying mounting.

Door switches, obviating mounting andadjustment problems, and offering totalconcealment for security devices.

J4 OPERATIONSPER REVOLUTION

TURNTABLE

Fig. 8. Simple yet versatile impulse timer canbe improvised by placing one or moremagnets on a gramophone turntable.

sealed device, it can be used inapplications where conventionalswitches are not permitted, or wherethey have very limited life. Reedswitches are frequently used insimple on/off push buttons, andoutdoors, in dusty areas such ascement plants, especially in areaswhere explosive gases may be pre-sent.

OPERATING LIFE

The operating life and load car-rying characteristics of reed switchesare interrelated. A switch mayoperate for 100 million or even1,000 million closures providing it isswitching very low currents. But the

Switching in explosive atmosphere, obviatingignition risk; in dust filled atmospheres whereconventional contacts would be unreliable;and in extremely cold conditions wereordinary switches would freeze up. Inradioactive environments, magneticoperation can maintain integrity of shielding.

0

(A) Load

(B)

(C)

(D)

nn H --D

04

Diode

Fig. 9. Contact protection techniques: A -Resistor shunting load. 6' - Capacitorshunting contact. C - Resistor -capacitorseries network for ac loads. D - Diodeshunting.

same type of switch may fail afterhalf a dozen switching cycles if theload greatly exceeds the designedrating. The majority of reed switchesare manufactured with contactratings between 0.1 A and 3.0A.

The current handling capacity ofreed switches varies from type totype. In general the rating will bedetermined by the size and surfaceplating of the reeds, for the reed is anelectrical conductor, and current.rating will be a function of contactarea.

The maximum rated contactloading is only applicable for purelyresistive loads. If the load iscapacitive or inductive the switchmust either be drastically derated, orthe switch contacts protected in asuitable fashion.

Four suitable methods of contactprotection are shown in Fig. 9.

In dc circuits all that may be req-uired is a resistor shunted across theload (Fig. 9A). Where the load is arelay coil or operating solenoid aresistor of approximately eight times

SPECIFICATIONS STANDARD MINIATUREMaximum voltage

Maximum currentMaximum powerMax. initial resistanceMax. end -of -life resistancePeak breakdown voltageClosure rateInsulation resistanceTemperature rangeContact capacitanceVibrationShock

150 Vdc250 Vac2.0A25W50 m.ohms2 ohms500V400 Hz5000 M.ohms-55°C to +150°C1.5 pF10G at 10-55Hz15G minimum

50 Vdc150 Vac0.5A6W100 m.ohms2 ohms300 V2000 Hz1000 M.ohms-55°C to +150°C0.5 pF10G at 10-55Hz15G minimum

Life at rated load 5 x 106 operations 5)(106 operationsLife at zero load 500 x 106 operations 500 x 10' operationsTable 1. Typical specifications for standard and miniature reed switches.

the coil resistance is adequate toabsorb a major portion of the in-duced energy when the circuit isinterrupted. The addition of the res-istor will of course increase thesteady-state current flow but thisextra load is negligible.

Another cheap and simple way toprotect the reed switch is to wire acapacitor across the contacts. Therequired value depends upon loadcurrent, but something between 0.1uf and 1.0 uf will be sufficient. (Fig.9B).

The most generally used methodof protection is the resistor -capacitorseries network shown in Fig. 9C.This circuit must be used if theswitched load current is ac. Theresistor should be approximately160 ohms and the capacitorsomewhere between 0.1 uf and 1.0uf. That this is an extremely effectivemethod was proven by a recent trialduring which a motor starter wasswitched 50 million times withoutfailure.

The component values may eitherbe determined empirically (as de-scribed below) or mathematically. Inthe latter case, the componentvalues can be obtained from -

12C= - , R -10 10X1(1+50/E)

Fig. 10. Reed switch / Triac combination maybe used to switch single phase loads as highas 125 Amps. Components shown in dottedlines must be included if the load is reactive.

Safety interlock switching, giving extremereliability and simplicity of application tocomplex mechanical layouts. Reed insertcompletes circuit to illuminate warning lampor permit further stage of operation.

0.10f

100(1


in pocket calculators. Non-volatilememories are the types using pre-setregisters (such as read-onlymemories or ROMs) or which usemagnetic tapes or cores or othertypes of storage which are noterased when power is switched off.A simple type of volatile memory is aSISO shift register with its outputconnected bad( to its input so thatthe information is read back in afterone complete set of clock pulses;this type of memory can only deliverits contents in the order in whichthey are stored. If the register has

parallel outputs with gates, how-ever, it becomes possible to findwhich digit (0 to 1) is stored in eachflip-flop, so that, in the language ofcomputing, random access is pos-sible. This is a simple random accessmemory (RAM).

At this point it is worth pointingout that most memories in generaluse permit random access. The typeof memories which we refer to asRAM are random access memorieswhich can be written as well as readwhen suitable inputs are applied.

CO

Al

They should properly be called ran-dom access read /write memories.Read only memories are usually alsorandom access, but the informationwhich is stored has been put thereeither by the manufacturer (in thedesign stage) or by the user (as withPROM) when the memory is firstused. In the older types of PROM,using fusible links, the memory can-not be altered once programmed,except by fusing a few more links.The more modern UV erasablePROM's permit complete erasureand re -programming.

(b)Al B2-

C1HA81

COHA

ASi

Fig. 3. Above: Adders (a) Half -adder circuit, using NAND -gatesand inverters. (b) Full adder, using half adders and OR -gate.

Fig. 4. Right: (a) Schematic of 7482 two-bit full adder. Noteagain the advantages of medium scale integration. (b) Truthtable.

Fig. 5. Below: SISO shift register connected as a memory - theinformation must be read out in serial form.

A

QCLOCK

B C

O

O

1

OUT

(a)

)

)

))

)

(b)

)

TRUTH TABLE

Si

52

C2

INPUTS OUTPUTSco=o CO = 1

Al B1 A2 B2 S1 S2 C2 S1 S2 C2

0 0 0 0 0 0 0 1 0 0

1 0 0 0 1 0 0 0 1 0

0 1 0 0 1 0 0 0 1 0

1 1 0 0 0 1 0 1 1 0

0 0 1 0 0 1 0 1 1 0

1 0 1 0 0 1 0 1 1 0

0 1 1 0 1 1 0 0 0 1

1 1 1 0 0 0 1 1 0 1

0 0 0 1 0 1 0 1 1 0

1 0 0 1 1 1 0 0 0 1

0 1 0 1 1 1 0 0 0 1

1 1 0 1 0 0 1 1 0 1

0 0 1 1 0 0 1 1 0 1

1 0 1 1 1 0 1 0 1 1

0 1 1 1 1 0 1 0 1 1

1 1 1 1 0 1 1 1 1 1


PRACTICAL GUIDETO REED SWITCHES Part 2

Reed switches are actuated by amagnetic field.

This field can be generatedby a permanent magnet, or by anelectrically energised coil. Whencoils are used, the reed switch issimply inserted within the coilformer and it is then closed (oropened) when current is passedthrough the coil.

It operates, in fact, as a relay, andin this form reed switches are usedby the million, in telephone systemsaround the world.

When a reed switch is to be elec-trically actuated, an indication of themagnetic field strength that is re-quired is generally quoted by themanufacturer in terms of so manyampere -turns. This figure may rangefrom 50 AT to 250 AT (but as ex -

In the second partof this series,Collyn Riversexplains howreed switchesmay beelectricallyactuated.

Turns 7,520 9,600 15,900 15,000 19,500 25,000 36,000 43,100 53,000 66,500 86,800

Ohms 219 355 550 855 1,390 2,380 4,320 6,380 9,900 16,000 25,000

:-....

%

-5

3vs

50AT 1.5 6:5 1.8 5 2.3 4.2 2.8 3.3 3.5 2.5 4.8 2 6.1 1.4 7.3 1.2 9.4 0.8 12 0.75 15.7 0.6

100AT 3.0 13 3.6 10 4.6 8.4 5.7 6.7 7.1 5.1 9.5 4 13 2.8 14.7 2.3 19 1.9 24 1.5 31 1.2

150AT 4.5 20 5.3 15 6.9 12.6 8.5 10 11 7.6 14 6 18 4.2 22 3.5 28 2.7 36 2.3 47 1.8

200AT 6.0 26 7.0 20 9.2 17 11 13 14 10.2 19 8 24 5.6 29 4.6 38 3.8 48 3.0 94 2.4

250AT 7.5 33 8.8 25 11.5 21 15 16 18 12.7 24 10 30 7.0 37 5.8 47 4.6 60 3.8 110 3.0

a me v ma y ma v ma y ma v ma V ma V ma v ma V ma V ma

Table 2. Data for standard size reed switchoperating coils - bobbins to be 2" long X0.220" inside diameter, winding build up willbe approx. 0.2".


Fig. 11. Bobbin for standard sized reedswitch.

plained later, this may be substan-tially reduced by the judiciouspositioning of a bias magnet).

Various combinations of turns,wire sizes and dimensions may beused to close any specific type ofswitch, and these parameters will inturn be determined not only by therequired number of ampere -turns,but also by the circuit voltage andcurrent that is available. For examplea switch that requires 100 ampere -turns may be actuated by a 220 ohmwinding drawing 13 mA at 3.0 V., orby a 25,000 ohm winding drawing1.2 mA at 31 V.

Table 2 provides all the data re-quired to design operating coils for awide variety of standard sized reedswitches (ie, 2.75 overall, 2.0long, 0.217 diameter).

The operating coil may either bewound on a bobbin manufacturedspecifically for the purpose (Fig. 11).or made up from a length of paper,aluminium or plastic tubing that is aneat fit over the outside diameter ofthe glass reed.

Another method of makingoperating coils is to wind them,using a cement coated wire, onto anarbour that is shaped to create the

0

Linevoltage

Coil

voltage

Fig. 12. Magnet assists reed switch to close,and thus reduces coil energy requirement.

Fig. 13. In this circuit, reed switch is latchedby aiding permanent magnet, and reset bymagnetic opposition from reset coil field.

Polarity

MagnetV'

Line

voltage

....mommomil=111111,

LoadPolarity

Coil

voltage

Fig. 14. Normally closed operation usingmagnetic bias.

Fig. 15. This type of reed switch may be usedfor either change -over or normally closedoperation.

desired final form. After removalfrom the arbour, the winding shouldbe protected by a layer of insulatingtape.

EXTERNAL MAGNETIC FIELDSA reed switch is influenced by a

magnetic field regardless of whetherthat field is produced by theoperating coil or by some othermagneto -motive force. The mag-netic force generated by the fieldwinding can be modified or evencompletely cancelled by the fieldfrom a nearby permanent magnet, orby the alternating flux from a nearbychoke, transformer or other induc-tive device. Even the proximity of asheet steel chassis may affect theenergy at which a reed switch willjust actuate.

But the effect of external mag-netic influences may be usefullyexploited to modify the characteris-tics of the basic reed switch assem-bly.

For example the ampere -turnsrequired to close any given switch,can be halved by placing a magnet ashort distance away from the coil -the magnet's polarity must be thesame as that of the operating coil.The positioning of the magnet isfairly critical and is best determinedby trial and error (Fig. 1 2).

A similar method can be used to

obtain a latching action. In this casethe method exploits the magneti&hysterisis of the reed switch. Themagnet is placed far enough awayfrom the coil so that it does not closethe reeds magnetically, but suf-ficiently close so as to hold the reedsclosed once they have been actuatedby an electrical signal through thecoil.

In this example the reed relay canbe unlatched only by physicallyremoving the magnet, or byapplying opposite polarity drivethrough the operating coil.

A further modification of themagnetic latching principle is shownin Fig. 13. Here, whilst magneticlatching is still used, the operatingcoil has two windings, one of whichis used to actuate the relay, and theother, which is connected inopposite polarity, is used to unlatchthe relay.

A magnet may also be used toconvert a normally open reed relayto normally closed operation. This isdone by locating the magnet suf-ficiently close to the reed so that thecontacts are held closed. (Fig. 14).The coil is wound so as to produce amagnetic flux of opposite polarity tothe magnet. When the operating coilis energised, the resultant magneticflux will cancel out that from thepermanent magnet, and the reedwill open.

Change -over action may beobtained either by using a reedswitch specially made for the pur-pose (Fig. 1 5) or by using a magnetand two normally open reedswitches actuated by a commonoperating coil (Fig 1 6).

It is possible to actuate a numberof separate reed switches locatedinside one large operating coil, butdue to variations in the sensitivitybetween one reed and another, andthe positioning of individual reedswitches within the operating coil, itis not possible to predict the contactaction sequence. All other thingsbeing equal the most sensitive reedwill operate first. This will then act asa magnetic shunt, retarding the

/k A

mmssiraft.-Bias magnet

Fig. 16. Change -over action may also beobtained by combining a magnet and twonormally open switches actuated by a com-mon operating coil.

Form A

Form B


3

2

E

0100

bouncetimetime

.......

Operate

Operatetime

Bounce timei _,

200 300

Current as percent of just -close value

operation of the remaining reedswitches. This is a major differencefrom conventional electro-mechanical relays where a singlearmature or card drives all of themovable contacts and any pair ofcontacts can be adjusted to ensuresynchronous operation or a specificcontacting sequence.

Nevertheless if a current at least150% of the just -operate ampere -turns of the highest rated switch ofthe group is applied suddenly, thiseffect is less noticeable, and in mostapplications may be virtuallyneglected.

SWITCHING CHARACTERIS-TICS

The moving blades inside a reedswitch have very low mass and moveonly a few thousandths of an inch.The operating coil is not iron coredand so has little self-inductance thusallowing a magnetic field to build-upvery rapidly. These factors combineto ensure that a reed relay is aninherently quick -acting device, infact, operating times of less than onemillisecond are quite typical.

The speed at which any specificreed relay closes is primarily a func-tion of the number of ampere -turnsin the operating coil. But when thecontacts close they normally bouncetwo or three times and the harder therelay is driven (ie, the greater thenumber of ampere -turns) the greater

Fig. 17. Variation of operate and bounce timewith energising current.

Fig. 18. Reed switch logic module.

the number of times that the con-tacts bounce. In general reed relaycoils are designed so that nominalrated coils are designed so thatnominal rated voltage producesapproximately 50% more ampere -turns than the just -operate value.This gives optimum total operatetime including the contact bouncetime (Fig. 1 7).

After the contacts have closedand have stopped bouncing, thereeds continue to vibrate for a shorttime. This vibration produces mag-netostriction contact noise - adamped oscillatory voltage that de-cays to zero - and this may causeproblems in low signal level circuits.

With no suppression devicesacross the operating coil, reedrelease time is very fast - it may beas short as 25 micro -seconds. Ad-ding a suppression diode has little, ifany effect on the operate or bouncetimes, but it does significantlylengthen the release time. Forexample, the release time of astandard type of reed without a sup-pression diode may be 50 micro-seconds, but with a diode the releasetime may be extended to a milli-second or so.

Due to the geometry of the reedswitch construction, the capacitancebetween contacts is low, and withstandard sized reed relays this willbe about one pico-farad. Thecapacitance between the reeds andthe operating coil will be about 2.5pico-farads but this can be reducedto approximately 0.5 pico-farads byinterposing a grounded electrostaticshield between the coil and the reed.

Some thermal EMF will begenerated at the junction of dissimi-lar metals in reed switches due to theheating produced by energising thecoil. This thermally -generated EMFmay be undesirable if the reeds are

Inputcoilwindings

Switchcapsule

Biascoil

used to switch low level analoguesignals - as for example in data -logging or thermocouple measure-ments.

For applications where the ther-mal EMF must be held to the mini-mum a bi-stable latching reed relayshould be used. A short pulse to theset coil operates the relay, no heatgenerating holding current is thenrequired. Another short pulse to thereset coil releases the relay. Usingthis type of operation, the latchingrelay thermal EMF remains belowfive micro -volts, compared to asmuch as 100 micro -volts for con-tinuously energised relays.

REED SWITCHES AS LOGICELEMENTS

The reed relay is almost an idealbuffer between solid state devices

INPUT

INPUT2

Fig. 19. The reed relay as an AND gate. Eachcoil can produce V2 a 'flux unit', and an outputis obtained only when voltages are applied toboth inputs.


INPUT

INPUT2

Fig. 20. Reed relay OR gate. Either coil canclose reed switch.

and higher power output elements.The winding impedance and currentlevels is well suited for the collectoror emitter circuits of standard tran-sistors, and it can also be driven bymany IC elements.

With the recent introduction ofthe 'pico-reed' switch, a single polerelay is now available in a dual -in -

line package, making it bothphysically and electrically compat-ible with integrated circuit com-ponents. And as reed relays becomesmaller their operating speeds in-crease, so that a pico-reed relay canbe made to follow 1 kHz pulses.

Reed switches are finding in-creasing use as logic elements foruse in adverse environments. Theyare capable of performing a largevariety of logic functions includingAND, OR, EXCLUSIVE OR, and NOToperations. The relays can be used

A 0

B0

Co

00

O

O

0 0 0 4224

0440

O

4.4S 0:044

49,2j244

Fig. 21. Cross -bar matrix switching, theappropriate relay will close whenever bothcoils of any given relay are coincidentallyenergised.

to construct flip-flop circuits, andthese can be used in binary, binarycoded decimal and decimalcounters, ring counters, up -downcounters and shift registers.

Whilst operating speed is veryconsiderably slower than with solidstate logic elements, there is not thesame necessity for precise voltageand frequency regulation, nor thesusceptibility to voltage transients.And for these reasons reed relaylogic circuits are becoming in-creasingly used in industrial equip-ment.

A wide range of reed relay logicelements are commercially available- generally in a configuration simi-lar to that shown in Fig. 18. Theindividual reed switches are sur-rounded by bias coils, and these inturn share a common input windingcoil. By adjusting the ampere turnslevel to both input winding and theindividual bias windings, a multi-plicity of functions can be obtained.A permanent magnet can also beused in this type of logic element toprovide memory or latching func-tions.

When designing reed relays aslogic elements, the amount of mag-netic flux that is required to close therelay is regarded as one flux unit.Thus a two input AND gate consistsof one reed switch surrounded bytwo windings each of which cangenerate one half a 'flux unit' (Fig.19).

It is possible to expand the con -

0

O

09041004O

C0004Q90

C

0

Fig. 22. How a 'memory' may be incorporatedin a matrix element.

cept to produce three, four or fiveinput AND gates by providing aseparate winding for each input,such that each winding provides1 /nth of the total required flux.

An OR gate is produced by pro-viding two windings either of whichcan be energised to the level of oneflux unit (Fig. 20). Thus a voltage ineither winding can cause the relay toclose. Again as with the AND gate, anumber of windings may be usedprovided each one can provide onefull flux unit.

The basic OR gate can be used asan exclusive OR gate simply byreversing the direction of onewinding. In this application if eitherone or the other winding is ener-gised then the relay will close, but ifboth are energised then the resultantmagnetic fields will cancel out andthe relay will remain open.

Inverted operation is provided byusing relays that are magneticallybiased into normally closed opera-tion.

Cross -bar matrix switching isreadily achieved by using a doublewound relay, in which each windingprovides half a flux unit, at eachselection point, ie, A1, A2, A3, etc(Fig. 21). The appropriate relay willclose whenever both coils of anygiven relay are coincidentally ener-gised.

The cross bar switching systemmay be used with a magnetic orelectrical memory if required. Fig.22 shows how two reed switchescan be used, together with a latchingwinding, to provide an electricalmemory in a reed relay cross barswitching system. In this form thematrix will remember the inputsafter they have been removed, untilthe latching power supply is inter-rupted.


PRACTICAL GUIDETO REED SWITCHES Part 3

Reed switches can be com-bined with solid-state elec-tronic components to provide

extremely reliable and maintenancefree circuitry.

The low operating current of theactuating coil is well within the col-lector current rating of practicallyany transistor (and most linear inte-grated circuits). Many simple practi-cal circuits can be constructed usinga single transistor and a reed switch.

The circuit shown in Fig 23 iscommonly used to open or close arelay when an external circuit ismade or broken. It iscommonly usedin simple burglar alarm installations.

In operation, the transistor is cutoff by a short circuit across points 'A'and 'B' (shown as dotted lines).

Because the transistor is cut off, thereed relay operating coil in the tran-sistor's collector circuit is not ener-gized, and the relay contacts areopen.

If the short circuit is removedfrom points 'A' and 'B', the transis-tor is biased on via the 1 5k resistor,the relay coil is energized and thereed switch is closed. Current con-sumption of this circuit - whilst therelay is de -energized - is less thanone milliamp.

The circuit shown in Fig. 24 has asimilar function to that of Fig. 23,except that the relay will close whena short is placed across points 'A'and 'B'.

FIG. 24ov

Final part of thisseries describesreed switchapplications.

It is often necessary to arrange forthe relay to remain closed eventhough the actuating signal is onlymomentary. This can be done byusing an actuating coil, containingtwo reed switches, and using one ofthe reed switches to short out thetransistor the moment the coil isactuated - Fig 25 refers.

A very sensitive circuit that can beused as a moisture sensing switch isshown in Fig. 26. This circuit has again of well over 2500.

The relay will close whenever theresistance between points 'A' and'B' fall below a few hundred thou-sand ohms. The 100k potentiometeris not an essential part of the circuit,but may be included as a 'sensitivity'

ELECTRONICS CIRCUIT DESIGN -- WINTER 1980 3 7

ovFIG. 26

control. The current consumption ofthis circuit, when the relay is de-

energized, is less than one micro -amp.

Any of these circuits (Figs. 23,24, 25, 26) may be combined withthe Triac actuating circuit shown inFig. 27 and used to switch very highcurrent loads.

For example the moisture sensingcircuit shown in Fig. 26 can becombined with the Triac switchingcircuit to energize a large motordriven pump. If necessary, threereed switches may be combined inone energizing coil to switch threeTriacs in a three phase circuit. Usingthis principle loads of severalhundred Amps may be switchedwithout using a single contact.

An unusual application for a pairof reed switches is shown in Fig. 28.

This circuit can be used to switcha common antenna to either a trans-mitter or receiver. As the capacitybetween the contacts on the open

FIG. 27

RECEIVER

RECEIVER

reed is less than 0.2 pF, the systemmay be used at very high frequency.

Time delays of up to 10 secondscan be obtained using the simplecircuit shown in Fig. 29. The delay isadjusted by the 50k potentiometer.It is not practicable to obtain longerdelays than 10 seconds by in-creasing the size of the capacitor.RESONANT REEDS

Resonant reed switches arebasically similar in construction tonormal reed switches, except thatone reed is designed to resonatemechanically when its operating coilis energized at a specific frequency.At the other frequencies the reed willnot move to any extent.

As the reed only makes contactfor a portion of each cycle, it isusually necessary to arrange forlatching action, or for some form ofstorage or pulse lengthening circuit.

Resonant reed switches are usedfor a variety of applications whereresponse is required only to onespecific frequency - these includecommunications, selective signal-ling, data transmission, telemetry,frequency monitoring etc.

Reed switches may also be usedin very sophisticated logic circuits,usually in applications where theirimmunity to noise causes them to bechosen in preference to the generallycheaper solid-state components.

Fig. 30 shows a four -stage shiftregister which uses reeds as mag-netically latched devices in simplemagnetic circuits. The information ineach stage is stored as closed oropen switches, and the condition ofeach stage is transferred to the nextas the shift control is operated. Onlya single contact set is used for con-trol purposes in each stage, as thestate of a stage is stored as a capaci-tor charge during the shifting inter-val. However each stage hasauxiliary switching contracts for out-put purposes.

The basic principle of operationcan be considered as a series oflatching relays. Momentarily closingthe 'set' contact energizes coil Si

COMMON TRANSMITTER

BOBBIN

. VsANTENNA TRANSMITTER

Fig. 28. Here reed relays are used to switch a common antenna to either receiver ortransmitter. As the capacitance between the reeds is less than a 2pF, the arrangementmay be used at very high frequency.

FIG. 29

and closes reed switches STG 1. Theassociated bias magnet latchesthese switches closed, thus allowingthe 'set' contact to be re -opened.The logic state of the first stage maynow be shifted to the second stageby operating the shift contacts in thissequence:

a. Closing contact A, thus chargingcapacitor C2.

b. Closing B for a few millisecondsand thus unlatching STG 1switches.

c. Opening contacts A and B.d. Immediately and momentarily

closing contact C. Capacitor C2now discharges through coil C2via contact C. Switches STG2now close and are latched by theassociated bias magnet. Theswitches associated with thesecond stage are now closed andthose of the first stage are open.

Sequential operation of the shiftcircuits in this manner moves theclosed or open logic state of the reedswitches from each stage to the nextstage in sequence.

Two additional sets of contactsare provided in each stage, one setmay be used to provide visual indi-cation of the logic state of the stage,the second set may be used to trig-ger particular operations wheneverrequired.

Reed switches may also be usedin many types of coding and de-coding systems. A simple decimal tobinary encoder is shown in Fig. 31.In this circuit, the input is from adecimal keyboard energizing reedrelay coils, while the output is infour -bit binary. Single, double, andtriple switch relays are required forthis application.

MERCURY WETTED CON-TACT RELAYS

The mercury wetted contact relayovercomes the problem of contactbounce that is inherent in the dryreed switch.

The construction of the mercurywetted switch is shown in Fig. 32. Itconsists of a glass encapsulated reed


0. SIG 1

OUTPUTCONTACTS

0, -

JUMPERLIJ

NZC1 mQ

<1.7

SI 4=4R I

STG 1

1 SET-J-.SHIFT CONTACT FUNCTION

A -- CAPACITOR CHARGING CONTACT B RESET CONTACTC - SET CONTACT

cr. SIC 2 STG 3 J. STG

V. V.

24v d c

I SHIFT

4I CONTACTS

- V.13

A\

Fig. 30. This four -stage shift register uses reed relays.

Fig. 31. Reed switch decimal binary encoder.

which has one end immersed in apool of mercury. The other end ofthe reed is capable of moving bet-ween two sets of stationary contacts.The mercury flows up the reed bycapillary action and wets the surfaceof the fixed and moving contacts.Thus a mercury to mercury contact ismaintained whilst the contacts areclosed.

The resistance of mercury is verylow and contact to contact resist-ances of mercury wetted switchesrarely exceed 50 milliohms. This issomewhat less than if the contactswere permanently solderedtogether!

The mercury wetted switch maybe opened and closed in a similarfashion to its dry reed counterpart.Operating times are typically 10milliseconds at normal coil current,falling to three milliseconds at twicethe normal ampere -turn rating. Therelease time is typically fourmilliseconds under any conditions.

Apart from their high current car-rying capacity, mercury wettedreeds have extremely long life sincecontact erosion is eliminated.

The disadvantages of mercurywetted reeds are poor resistance toshock and vibration, and the need tomount the reed vertically.

FUTURE DEVELOPMENTSA lot of development work is cur-

rently being undertaken - particu-larly toward the use of cladded reedmaterial.

O 1 0 1 0 1 0

O 0 1 0 0 1

O 0 0 0 1 1 1

O 0 0 0 0 0 0

Nickel -iron reeds combine opti-mum magnetic characteristics withthe high internal damping that isrequired to minimize contactbounce; but the material is by nomeans an ideal conductor, and be-cause of this, high resistivity losseswithin the switch are appreciable athigh current loadings.

Cladding with gold or coppersubstantially reduces many of theundesirable characteristics of thenickel -iron reeds. This claddingreduces the effect of skin resistance.- which can be appreciable at highfrequencies - and if the cladding iscontinued right to the ends of theexternal lead -outs - it virtuallyeliminates the thermal emfsgenerated when a copper wire issoldered to a nickel -iron reed in aconventional reed switch.

Another problem currently beinginvestigated is that of reed switchcontacts failing to separate, es-pecially after they have been heldclosed for long periods at high tem-peratures. This is caused bymolecular migration and the result-ant metallic bond cannot be brokenby the low separating force avail-able. This problem has not yet beencompletely overcome but currentdevelopment is toward heat treat-ment to produce a diffusion of goldinto the nickel -iron base, and multi -layer diffusion techniques.

Prices of reed switches are stilldecreasing, and as they becomecheaper, new markets are openingup.

The motor industry in particular isusing reed switches in fuel injectionand ignition systems. The securityindustry appreciate the reliablemaintenance -free service that can beobtained. Machinery manufacturersare beginning to use reed switchesin applications in which adverse en-vironments preclude open switchcontacts.

For what other type of switch canremain static for twenty years andthen work perfectly the first time thatit is actuated?

SUPPORTINGLE ADWIRE

NORMALLYCLOSEDCONTACTS

NORMALLY OPENCONTACTS

AR MATURE

MERCURY POOL

Fig 32. Construction of amercury wetted reed switch


HobbyprintsAn easy, patented method of making PCBs for HE projects.

How to use HOBBYPRINTS.1. Clean the PCB as you would for any work giving it a rub downwith fine sandpaper (we even supply this in the kit). A quick wipeover with lighter fuel will help to remove any grease marks.2. Lay down the HOBBYPRINT and rub over with a soft penciluntil the pattern is transferred to the board. Peel off the backingsheet carefully making sure that the resist has transferred. Ifyou've been a bit careless there's even a 'repair kit' on the sheetto correct any breaks!

3. Cut the board to size and put it in the Ferric Chloride.4. When etching is completed, wash the board and use thesandpaper or a scouring powder to remove the resist. The resistpattern is pretty hardy but is easily removed at the final stage5. All you've got to do now is drill the board. Time? Only aboutten minutes from beginning to end plus etching time (15minutes usually with a good acid).

.4-441

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VFETSFOR

EVERYONE!This article, by Wally Parsons, first app-eared in our Canadian edition. We thinkthat V-FETs represent a large step for-ward in power amplifier technology andso we have reprinted it.

The first part of `V-FETs for Everyone'covers the theory behind V-FETs andwhat their specifications mean. Part twowill describe how V-FETs are used atpresent and how to design V-FET circuitry.

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S ince the semi -conductor is precisely that, abattery across the ends of a p -type or an n -typebar will cause current to flow through the

material, just as it does through a vacuum tube. If ap -type material is joined to the surface of an n -type bar,located between the battery terminals, a pn junction isformed, and if this junction is reverse biased, a spacecharge or field is produced of opposite polarity whichwill inhibit current flow, just as the control gridinhibits current flow in a vacuum tube. Changing thisreverse voltage causes a large current change, andtherefore amplification results.

A simple FET (J-FET) is shown in Fig. 1. With agiven drain - source voltage, maximum currentflows under zero gate voltage conditions and at somereverse levels, no current will flow. Also, as in thevacuum tube, load characteristics are not reflected tothe input circuit, because current is not controlled bycarrier injection as in bipolars, but by voltage levels.

AN

Fig 1: N -channel JFET construction and symbol

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Fig 2: N -channel depletion horizontal MOSFET construction andsymbol

A variation is the Metal Oxide Semi -conductorField Effect Transistor. (MOSFET) (Fig. 2) a far moreversatile device whose technology is virtually thecornerstone of modern computer technology,


although it has had less use to date in linear applica-tions such as audio amplification.

MOSFETS come in two basic types. In both typesthe gate consists of a metal electrode separated fromthe channel by a thin oxide layer. In the depletiontype current flow is controlled by the electrostaticfield of the gate when biased. Voltage relationshipsare the same as for the J-FET, except that when theJ-FET is forward biased current will flow through thejunction (after all, it is a pn junction). This does notcontribute to amplification, and may even destroy thedevice. When a depletion MOSFET is so biased it mayresult in increased current flow and, provided cur-rent, dissipation, and breakdown ratings are suitable,the device may be driven on both sides of the zerovolts point as with vacuum tubes. Unlike vacuumtubes under these conditions, the gate draws nocirrent and therefore does not require the driver todeliver power.

The enhancement type MOSFET shown in Fig. 3, ismore widely used. The source and drain are separatedby a substrate of opposite material, and under zerogate volts no current flows. However, when sufficientforward bias is applied to the gate the region underthe gate changes to its opposite type (e.g. p -typebecomes n -type) and provides a conductive channelbetween drain and source. Carrier level and conduc-tion are controlled by the magnitude of gate voltage.Although J-FETS, and especially MOSFETS, havecertainly delivered on their original promise, in onearea they are particularly conspicuous by their ab-sence, and that is in the area of power. Unfortunately,the channel depth available for conduction is limitedby the practical limits on gate voltage. The lowercurrent density has been the primary limitation dueto the horizontal current flow.

VMOSRecent years have seen the introduction and com-mercial use of Vertical Channel J-FETS, notably bySony and Yamaha (Fig. 4). The vertical channelpermits a very high width -length ratio, permitting adecreased inherent channel resistance and high cur-rent density. Unfortunately it exhibits the samedisadvantages as the small signal J-FET, plus, inavailable devices, a very high input capacitance,ranging from 700pf to around 3000pf, limiting highfrequency response. In addition, since they must bebiased into the off condition, bias must be applied'before supply voltage and removed after the supply ifit is to be operated anywhere near its maximumratings. This problem doesn't exist with vacuumtubes because of heater warm-up time, althoughsome "instant -on" circuits impose heavy turn -onsurges.

This necessitates a complex power supply, andindeed Yamaha, for example, uses more devices in thesupply than it does in its amplifier circuits. However,the construction does make possible the design ofcomplementary types and Nippon Electric and Sonyboth have high power devices available. Unfortun-ately, neither company seems anxious to make de-tailed information available, so there is little todisclose here beyond the fact that they are said tohave characteristics similar to those of triode tubes.

SOURCE TERMINAL DRAIN TERMINAL

DRAIN

Fig 3: N -channel enhancement horizontal MOSFET constructionand symbol

Fig 4: Vertical junction FET construction

Fig 5: Vertical MOSFET construction (Siliconix)

However, the Vertical MOSFETS by Siliconix arereadily available, at reasonable prices, and themanufacturer most generous in providing data. Thefollowing information is extracted from their appli-cation note AN76-3, Design Aid DA 76-1, plus devicedata sheets.

The DeviceNotice in Fig. 5 that the substrate and body areopposite type materials separated by an epi layer(similar to high speed bi-polars). The purpose of thisstructure is to absorb the depletion region from thedrain -body junction thus increasing the drain -sourcebreakdown voltage. An alternative would have in-volved an unacceptable trade-off between increasingthe substrate -body depth to increase breakdownvoltage but increasing current path resistance andlengthening the channel. In addition, feedbackcapacitance is reduced by having the gate overlapn-epi material instead of n + .


20

1 8

16

00

O

MAXIMUM SAFEOPERATION REGION

CONTINUOUS

n5

4

10 20 30

VU, DRAIN SOURCE VOI TAGE v

Fig 6: Output characteristics VMP1

02 04

v.

0

0 4 H.

TRANSCONDUCTANCE

CAPACITANCE

TRANSFER CHARACTERISTICVBB 24V

6 8

VGS GATE SOURCE VOLTAGE .V1

Fig 7: Other VMP1 characteristics

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10 08015

21 ohm,

10

In manufacture, the substrate -drain and epi layerare grown, then the p -body and n + source diffusedinto the epi layer, in a similar manner as the base andemitter of a diffusion type transistor. A V groove isetched through the device and into the epi layer, anoxide layer grown, then etched away to provide forthe source contact and an aluminium gate deposited.It is apparent that this type of device allows currentflow in one direction only; this is not always so with asimilar type of horizontal FET, where source anddrain may be identical in structure and of the samematerial. Therefore, no reverse current flows (wehope!) when used in switching applications, as wasalso the case with vacuum tubes.

In -circuit operation is refreshingly simple: Supplyvoltage is applied between source and drain, with thedrain positive with respect to the source, under whichconditions no current flows, and the device is off. Thisis an enhancement type device and is turned on bytaking the gate positive with respect to the sourceand body. The electric field induces an n channel onboth surfaces of the body facing the gate, and allowselectrons to flow from the negative source throughthe induced channel and epi and through the sub-strate drain. The magnitude of current flow is con-trolled almost entirely by the gate voltage, as seen inthe family of curves (Fig. 6 and 7) with no change,resulting from supply voltage changes above 10V.

Advantages

The vertical structure results in several advantagesover horizontal MOSFETS.

1) Since diffusion depths are controllable to closetolerances, channel length, which is determined bydiffusion depth, is precisely controlled. Thus, width/length ratio of the channel, which determines currentdensity, can be made quite large. For example, theVMP1 channel length is about 1.5 us, as against aminimum of 5 us in horizontal MOSFETS, due to thelower degree of control of the shadow masking andetching techniques used in such devices.

2) In effect, two parallel devices are formed, with achannel on either side of the V groove, thus doublingcurrent density.

3) Drain metal runs are not required when thesubstrate forms the drain contact, resulting inreduced chip area, and thus reduced saturation res-istance.

4) High current density results in low chip capacit-ance. Also, unlike horizontal MOSFETS, there is noneed to provide extra drain gate overlap to allow forshadow mask inaccuracies, so feedback capacitanceis minimized.

In comparison with bi-polars, especially powerdevices, the advantages are even more impressive.

1) Input impedance is very high, comparable tovacuum tubes, since it is a voltage controlled device,with no base circuit drawing current from the driverstage. A 7 V swing at the gate, at virtually 0 A,represents almost 0 W of power, but can produce aswing of 1.8 A in output current. This representsconsiderable power gain and will interface directlywith high impedance voltage drivers.

2) No minority carrier storage time, no injection,extraction, recombination of carriers, resulting invery fast switching and no switching transient in

ELECTRONICS CIRCUIT DESIGN - WINTER 1980 4T

Characteristics VMP 11 VMP 1 VMP 12 Unit Test ConditionsMm Typ Max Min Typ Max Men Typ Max

1

S

A

TI

C

BVDSS Dram -Source Breakdown 35 60 90V

VGS -0.1D - 100µA

2 VGS1thl Gate Threshold Voltage 0.8 2.0 0.8 2.0 0.8 20 VGS VDS; ID - I '''A3' IGSS Gale -Body Leakage 0.5 0 5 0.5

µAVGS - 15 V. VDS . 0

4 ID(c.nfi) Dram Cutoff Current 0.5 0.5 0.5 VGS - 0. VDS - 24 V

5 Imo,0 Dram ON Current 1 2.0 1 20 1 2.0A

VDS - 24 V, VGS 10 V

6 ID(0n) Oldie ON Cui rent 0.5 0.5 0.3 VDS - 24 V. VGS = 5 V

7 sW

CT

H

'DSIon) Dram -Source ONResistance'

2.0 2.5 3.0 3.5 3.7 4.5 VGS - 5 V. ID - 0.1 A

8 2.4 3.0 3.3 4.0 4.6 5.5 VGS = 5 V. ID - 0.3 A9 1 2 1.5 1.9 2.5 76 3.2 VGS - 10 V. ID 0.5 A

10 1.4 1.8 2.2 3.0 3.4 4 0 VGS 10 V. ID - I A

11

D

Y

Aha

I

C

9m Forward Trans conductance' 200 270 200 270 170 mu Vas - 24 V. ID - 0.5 A

12 C, Input Capacitance 48 48 48

pF VGS = 0; Vas = 24 Vt . 1 MHz

13,..,

Crss Reverse Transfer Capacitance 7 7 7

14 CCommon Source Output.. ,Capacdance

33 33 33

15 ION Turn ON Time' 4 10 4 10 4 10 See SwItchtng TimeTest Circuit16 'OFF Turn OFF TIrne ' 4 10 4 10 4 10

Pulse Test Sample Test VMC.Pulse Test Pulse Width -- 80 µsec. Duty Cycle = 1%

Figs 8, 9 & 10: Electrical characteristics of the VMP devices from Siliconix, a freely available VF ET.

class B and AB amplifiers. Switching time for a VMP1is 4 ns for 1 A, easily 10-200 times faster than bi-polars, and even rivalling many vacuum tubes.

3) No secondary breakdown, and no thermalrunaway. VMOS devices exhibit a negative tempera-ture coefficient with respect to current, since there isno carrier recombination activity to be speeded upwith temperature. Thus, as current increases so doestemperature, but the temperature rise reduces cur-rent flow. It is still possible to destroy the device byexceeding its maximum ratings, but a brief near -overload does not result in an uncontrollablerunaway condition. Usually, simple fusing and/orthermistor protection is sufficient for maximumsafety, and even this may be unnecessary with con-servative design. Absence of secondary breakdownmeans that full dissipation can be realized even athigher supply voltages. In this respect they resemblevacuum tubes.

Available DevicesSeven devices representing three families are avail-able. Types VMP-1, VMP-11, and VMP-12 are 2 A,25 W dissipation devices intended for switching andamplifier use and differ only in voltage rating (60 V,35 V, 90 V, respectively). Types VMP-2, VMP-21,VMP-22, are 1.5 A, 4 W devices rated at 60 V, 35 V,90 V respectively, and are intended mainly for highspeed switching, but would also be useful for lowpower amplifiers and as linear drivers for bi-polars,where the latter offer advantages. And finally, typeVMP-4, 1.6 A, 35 W, specifically intended for VHFamplifier use. All except VMP-4 devices feature gateprotection to withstand static discharges and over -voltages, and all are currently available except theVMP-4. All are n -channel. One hesitates to pass

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1.2

0.8

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80µs. 1% DUTY CYCLE PULSE TEST

VGS = lOy

9V

8V

7V

6V

5V

4V

3V2VIV

0 10 20 30 40 50Vps - DRAIN TO SOURCE VOLTAGE (VOLTS)

10

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premature judgement, but if the millenium hasn'tarrived yet, at least it might just be on the way.

ConditionsV-MOS Power FETs like signal MOSFETS, may be'used in a variety of circuit arrangements to performmany different functions. However, no matter whatthe circuit, certain conditions, common to all appli-cations, must be provided. These are supply power,loading, drive signal, and establishment of appro-priate operating points. These are conditionsnecessary for amplification and since all active de-vices function as amplifiers, no matter what the totalcircuit function, the in -circuit performance of anydevice depends on the establishment of these condi-tions.

The electrical characteristics of the VMP1, VMP11,and VMP12, are shown in Fig. 8, and Fig. 9 and 10shows them in graphic form.Since these are uni-directional devices, the source and drain are notinterchangeable, and as they are n -channel devicesconduction can occur only if the drain is positive withrespect to the source, and high enough to ensureoperation in the linear region, as with a vacuum tube,bi-polar transistor, or signal FET.

Like the vacuum tube, the absence of secondarybreakdown allows realization of the full dissipation atany voltage supply up to maximum voltage andcurrent ratings. Thus, where two different designsrequire the same dissipation but different voltage/load current, no derating is required. This is shown inthe "safe operating area" curves. The only bi-polartransistor possessing this characteristic is the single -diffused type, which is also the least suitable for anyapplication requiring wide bandwidth and/or highspeed.


VFETS FOREVERYONE Part 2In general these devices may use any of the types ofoutput circuits in general use with valves andbi-polars, including transformer coupled (Fig. 12)

where the benefits of the absence of charge carrierstorage become apparent in the absence of severeringing at the cross over point, conventional seriesoutput such as in Fig. 1 which is a straightforwardtransformation from a bi-polar circuit (1), and single -ended output with current source, also transposedfrom an excellent bi-polar circuit (2) (Fig. 2).

Bias and DriveThese series of devices are n -channel, enhancementtype MOSFETS, and may be biased and driven usingmethods appropriate to signal types and bi-polars.The drain is made positive with respect to the sourceand the gate enables conduction by being forwardbiased with respect to the source, that is to say it isbiased in a positive direction. Unlike bi-polars, how-ever, they are voltage, rather than current contrdlled,,and circuit values are selected to provide the requiredvoltage. Any current drawn is by the bias networkitself.

Three bias methods are shown; Fig. 3 shows biassupplied from a fixed bias supply. It is the simplestpossible method, allows extremely high input imped-ances, since Rg may be almost any very high valuedesired, and its stability is limited only by the stabilityof the bias supply.

The design shown in Fig. 4 has the advantage ofrequiring no extra supply voltage since it is takenfrom Vdd. Disadvantages are those of impedance andstability. Input impedance consists of the parallelcombination of RI and R2 (disregarding input

11,VYX"SNI"Computerwise - I'd say It's artificial intelligenceand

simulation of behaviour!"

We have received a note from Siliconix giving the!following changes in type number - P-1 1 becomes2N6656; VMP-1:2N6657; VMP-12:2N6658; VUP-21 2N6659; VMP-2 2N6660; VMP-22:2N6661.

Fig. 1. Series output arrangement and Fig. 2 single -ended outputwith current source.

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Fig. 3. High -impedance separate bias supply, Fig. 4 moderateimpedance supply and Fig. 5 high -impedance common supply.

capacitance of the MOSFET and the very low inputleakage). There are practical limits as to how high thiscombinationcan become; if for example, we have a 60volt supply and require 6 volts bias, we might havesome difficulty obtaining higher values than 9megohms and one megohms for R I and R2.

Higher values become more difficult to obtain,stability becomes less reliable, internal inductanceand distributed capacitance become problems, andovercoming these difficulties usually costs money. Inaddition, if Vdd is subject to variation, then biasvaries. In a class AB amplifier this could be quiteserious, since Vdd varies considerably with outputlevel; at high levels, Vdd can be expected to drop,causing a reduction in bias.

While this may reduce the danger of over -drivingthe device, it will be forced to operate in its non-linearregion which may result in unacceptable perform-ance characteristics unless taken into considerationin the overall circuit design (e.g. choice of feedbackvalues). It does provide some degree of overloadprotection, and with correct choice of values can


provide for class AB operation at low levels, shiftingto class B at high levels. With these considerations inmind, and/or where moderate impedances are req-uired, it offers a low cost, simple, and reasonablyreliable method of establishing the operating point.

The method used in Fig. 5 is similar except thatwith the addition of R3 higher input impedances arepossible. Its configuration is similar to a noiselessbiasing system frequently used in low-level bi-polaramplifiers and integrated circuits (e.g. NationalLM381A) but its function is somewhat different.Resistors RI and R2 form a voltage divider as in Fig.4 but their junction now forms a fixed bias source asin Fig. 3. Resistor R3 can be quite high since nocurrent flows. Meanwhile, since the parallel com-bination of RI and R2 are effectively in series with R3they can be reduced to more manageable values.Alternatively R2 can be replaced by a zener diode forstability comparable to Fig. 3.

Input Protection

Unlike most signal MOSFETS, the gate of each ofthese devices, with the exception of the VMP 4, isprotected with an internal 15 volt, 10mA zener diode.Most signal MOSFETS, as well as the VMP 4 areunprotected, or where extremely high impedancesare not required, are protected by back to backzeners. I have no information as to why this differenttechnique is used, but it is obvious that a negativesignal swing on the gate will result in forward currentthrough the zener. If the device is to be drivenbeyond cutoff, the driver must be capable of de-livering current during its negative swing. Altern-atively a constant current source can be used, a serieslimiting resistor or a driver biased to the same class ofoperation as the V-MOSFET.

A constant current source (we'll examine anexample of its use a little later) will limit current driveto the value of the constant current diode used; aseries resistance will drop the drive voltage as thediode draws current. In both cases, diode currentmust be limited to 10mA maximum. Higher currentswill damage the protective zener diode.

However, if a class B output is used, conductiononly occurs during positive half -cycles. Therefore,drive signal is not required during negative half -cycles. If a source or emitter follower driver stage isbiased so as to pass no negative drive, the problemdoes not occur. However, great care must be exer-cised in the design of such a stage to ensure that drivedoes not disappear before the output device is cut off.

This is not too difficult with a class B or near class Bstage; if the output device is operated at zero bias,then a small amount of bias on the driver will ensureconduction during slightly more than 180 degrees.Class AB operation is a little more tricky. If conduc-tion is to occur for 270 degrees, for example, the drivershould conduct for slightly more than this period.

Two types of drive circuits familiar to designers ofbi-polar circuits are the Darlington and Super beta,commonly used together to provide a quasi -complementary circuit. Both circuits are currentamplifiers designed to provide a compound devicewith very high hf and provide base current to theoutput device. However, similar circuits can be used

2.0

1.6

1.2

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Fig. 6. Drain to source resistance against temperature(Siliconix).

TO PREVENT SPURIOUS OSCILLATIONS, A 500:!1K :1 RESISTOR OR FERRITE BEAD (FOR HIGHERSPEED) SHOULD BE CONNECTED IN SERIFS WITHEACH GATE

Fig. 7. Basic circuit for parallel operation.

12V

12 V BULB

HIGH ONLOW OFF

Fig. 8. Circuit of a high -efficiency light dimmer.

with these devices to provide phase inversion in aseries output stage.

Thermal ConsiderationsAs described earlier these devices exhibit anegative temperature coefficient with respect tocurrent, so that as temperature rises, current isreduced, thus providing a self -inhibiting action whichprovides some protection against overload. However,this is not an unconditional effect. Fig. 6 shows the


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39 pF

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Fig. 9. Diagram for series operation.

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Fig. 10. A DC to DC converter (Siliconix).

28 V

P. 4 W

100 Hz -15 kHz

Fig. 11. Simple single -ended transformer -coupled audio poweramplifier (Siliconix).

relationship between RDS (on) and temperature (3),based on a worst case temperature coefficient of 0.7per cent per degree C.

Suppose that the device when on passes a currentof 1 amp which causes it to heat up. The on resist-ance increases (which is why current drops), in-creasing the voltage drop across the device and thedevice dissipation. Now, if adequate heat sinking isused there is no real problem but if it isn't, the onresistance and junction temperature will rise to the

point where extra charge carriers are generated, thusstabilizing RDS(on). That's great, except for the factthat this doesn't occur until the maximum safejunction temperature of 150 degrees has been ex-ceeded.

You'll remember that we said earlier that the devicewas free of thermal runaway problems because of itsnegative temperature coefficient, but it isn't free ofthermal destruction problems, and in any case, ex-cessive temperatures will reduce output conduct-ance. Heat -sinking requirements are, therefore, simi-lar to those of bi-polars. The calculations of thermaloperating conditions are beyond the scope of thisarticle, but interested readers are referred to theSiliconix literature listed in the references, (4).

Extending The RatingsThe current handling capacity and therefore totaldissipation capability may be easily increased bysimply connecting several devices in parallel (Fig. 7).No ballast resistors are needed to ensure propercurrent sharing since if one device draws morecurrent than another it simply gets a little warmerwhich causes it to draw less (assuming adequateheat sinking, of course). The only major precautionneeded is to keep lead inductance in the gate andsource connections to a minimum to prevent parasiticoscillations, unless the devices are driven from a lowimpedance source.

It may be advisable to insert "stoppers" - smallresistors (500 to 1000 ohms) in series with each gate,wired directly to the socket, or ferrite beads mountedon the leads close to the socket terminals. An ad-ditional plus when paralleling several devices is thatthe gm is multiplied by the number of devices used.Mutual conductance gm is specified as the ratio of alarge change in current to a small change in controlvoltage. If, for example, a change of 0.4 volts on thegate produces a change of 0.1 amp through onedevice, connecting two devices in parallel will give usan output swing of 0.2 amps, but it will still requireonly the original 0.4 volts gate swing. Since voltagegain A =gm x RL, if gm is increased, A is increased.

In real use, of course, the internal resistance of twodevices in parallel is less than of one, the optimumload is less, so in amplifier applications, the netamplification A is the same. But notice that the driverequirements have not changed. With bi-polars cur-rent would have to be supplied to each base, thusincreasing the output requirements of the drivers.Indeed, with many high -power amplifiers usingmultiple output devices the drivers are also powerdevices.

We can also extend the voltage ratings by seriesoperation of two or more devices; Fig. 9 shows thetechnique. Resistors RI and R2 bias Q2 on while Cland C2 ensure fast switching. Input control signal isinserted between gate and source of Ql. Ordinarilythe bottom of the divider chain is at ground potentialfor signal frequencies, so that circuit is really acascode.

Maximum current and gin are the same as for onedevice.


Some Practical

Applications

An efficient light dimmer circuit as proposed bySiliconix is shown in Fig. 8. The 4011 acts as a pulsewidth modulated oscillator whose duty cycle is de-termined by the ratio of RI to R2, with R2 adjusted tocontrol the brightness of the bulb. Of special interesthere is the fact that with its fast switching time, theVMP1 is especially suited to pulse width modulationat power levels and suggests it as being suitable foruse in switching, or class D linear amplifiers.

A DC to DC converter is outlined in Fig. 10. TheVMP 1 s form an oscillator with positive feedbackprovided by the additional coil in the gate circuits. Inoperation the upper V-MOSFET is biased on, and thelower V-MOSFET is off. When power is applied theupper device conducts causing current to flow fromVdd through the upper half of the transformerprimary and the upper V-MOSFET to ground. Theinduced current flow through the feedback coildevelops a voltage such as to shift the bias in theupper device off (if the winding is connected withthe correct polarity) and the lower device on. Thiscauses current flow from Vdd through the lower halfof the transformer primary and the lower V-MOSFETto ground.

The secondary circuit consists of a single rectifierand filter. The resistor in the upper gate preventsshorting out of gate bias, and the one in the lowergate keeps both sides balanced. In addition, eachresistor limits current through the protective diodes.These are expensive devices for such an application,but the high reliability, the reduced RF radiation (dueto reduced switching transients) and the circuitsimplicity easily make up for the cost. The very highcircuit impedance allows for running frequency to beset by the self resonance of the transformer.

A single ended and push-pull transformer coupledamplifier for audio applications are shown in Figs. 11and 12. Both designs utilise the biasing system des-cribed in Fig. 4. A load -line drawn on the output cha-racteristic will show the optimum load to be 24 ohms.In Fig. 11 gate drive is supplied by a singlejunction FET, and voltage feedback is taken from theoutput transformer secondary and series fed to thesource of the input device. Distortion is under 2 percent at full output (try to get that with a single endedvalve or bi-polar) and could probably be reduced evenfurther by adopting a source follower output stage.

A push-pull version of Fig. 11 is shown in Fig. 12using a differential input to provide phase splitting,drive, and a feedback point. Although the trans-former winding ratio implies the use of a low imped-ance loudspeaker, a step-up ratio could be used fordirect coupling to an electrostatic speaker, a balancedtransmission line (both with some modification of thefeedback circuit) an unbalanced transmission line, ora 70 volt speaker distribution line.

Notice in both circuits, and in the biasing circuitsshown that no source resistors have been used, eitherfor local feedback or for bias setting. In valve andbi-polar circuits it's a useful technique, and withbi-polars can be used to stabilize bias and controlthermal runaway by using the increased current flowto increase the voltage drop, thus reducing base -emitter voltage. However, if used with these devices,it will actually impair the self-limiting action of itsnegative temperature co -efficient. If temperature

CI

INPUT

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R2

R4

RS

02

U

03

C3

Fig. 12. Transformer -coupled output.

R3

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Fig. 13. Tape recording amplifier.

ANODE

RS

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Fig. 14. A FET as a constant -current source.

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BIAS

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rises due to nigh current, current flow is reduced. Thiswould reduce the voltage drop across a source resis-tor, lowering the source voltage and increasing thegate -to -source voltage, causing an increase in currentflow. The circuit would work great while it lasted -which wouldn't be for long.


RE

FILTER

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1

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Fig. 15. A high -quality40 W amplifier (Siliconix).

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Power AmpIn Fig. 15 we have a high quality power amplifierdesigned by Lee Shaeffer of Siliconix Inc. (5) anddescribed in their application notes. Output currentcapability is increased by using three VMP12s inparallel; providing for 6 amp current, 75 Watt dis-sipation and optimizing the load at 8 ohms. Q11-13operate as a source follower, while Q8-10 form a quasisource follower. This is accomplished by applyinglocal feedback from drain to gate via R14, R15, anddriving the gate by a modified current source. Thisconsists of a cascode circuit with a constant currentdiode as the load.

For the benefit of those not familiar with thesedevices, a constant current diode is really a FETconnected internally as shown in Fig. 14. Sincecurrent in a FET is controlled essentially by thegate -to -source voltage, changes in load or in applieddrain to source voltage have negligible effect sincegate -to -source voltage is held constant. This is acurrent analogue to the zener diode and is describedin detail in Siliconix literature (6).

The design is push-pull from input to output,thanks to differential circuitry throughout, prior tothe drivers. Open loop distortion is low, bandwidthwide, allowing satisfactory performance with only22dB of feedback.

Complete construction plans including PCBlayout are available from Siliconix (7). A word ofcaution. however. Readers accustomed to construc-tion articles in which the writer does everything buthold your soldering iron will find these plans rathersketchy. They consist of a spec sheet, schematic.hoard and parts layout. two paragraphs of construc-tion suggestions. initial adjustments. and a parts list.Parts. generally. are specified as to value and rating.and that's it. These plans are excellent, but they

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0 36V

assume some knowledge and experience on the partof the constructor. Regular 'eti constructors'should have little difficulty.

Finally, how about something elegant for its sim-plicity, such as the Tapered Current Voltage Limitedbattery charger shown in Fig. 16. This is especiallyuseful with Ni-Cad batteries which are intended forstand-by use and are permanently on charge, such as

OUP I

BA I TE RNINOERCHARGE

RI

2115

Fig. 16. Tapered -current voltage -limited battery charger.

electronic clocks. Overnight shut -downs of a fewhours are occasionally but irregularly experienced.Vou know what this can do to clocks. Especiallyalarm clocks which are supposed to make noises, turnon radios, start the coffee at a pre-set time in themorning so you can go to work. Battery operation isnot too satisfactory if the readout is on continuously.,ifid Ni-Cads should not be on permanent floatingcharge.


With this little device current is supplied to thebattery via the VMP-1. Gate voltage is set at a valueequal to the desired end of charge voltage. As thebattery charges its voltage increases, reducing gate -

to -source voltage, thus reducing charging current.When the battery reaches full charge its voltage andthat of the source equals gate voltage, and charge isterminated. If a load is placed across the battery it willdraw current, and as the battery voltage dropsslightly below gate voltage, charging at a trickle rateoccurs - automatic.

ExperimentationThe various applications shown are intended assuggestions for further experimentation on the partof the reader. They are mainly designed to illustratevarious characteristics of the device under consider-ation, and are not necessarily representative of com-mercial practice or of finished designs. In some casesthis may be just as well. But we would be delighted tohear of any readers' experience with any of these orother circuits.

The author's own feeling is that V-MOS constitutesa genuine breakthrough in semi -conductor techno-logy, as important as the silicon transistor and theFET itself. We'll be seeing more of these devices, withhigher ratings (a 10A 200V unit is already underdevelopment) and specialized characteristics. Theyare said already to be in use commercially as mag-netic core drivers.

Digital enthusiasts may be somewhat impatientwith the strong emphasis on audio applications in thispiece but other literature has placed great emphasison digital applications, with little attention paid tolinear techniques beyond the 40 watt amplifier de-scribed here. The serious reader in all areas is referredto the references at the end.

Further literature may be obtained from themanufacturer, Siliconix Inc., 2201 Laurelwood Rd.,Santa Clara, CA 95054, California. They have beenmost helpful in providing information for the prepa-ration of this article.

Have fun.

REFERENCES1. W. Marshall Leach: "Construct a Wide Bandwidth Preamplifier"

Audio. Feb 1977, p. 39.2. Nelson Pas: "Build a Class A Amplifier" Audio, Feb. 1977. P. 29.3.4. Lee Shaeffer: "VMOS-A Breakthrough in Power MOSFET

Technology" Application Note AN76-3, May 1976, Siliconix Inc.5, 7 Lee Shaeffer: "The MOSPOWER FET Audio Amplifier"

Design Aid DA76-1, May 1976, Siliconix Inc.6. "The FET Constant Current Source" Design Idea D171-1.

January 1976. Siliconix Inc. Also Siliconix Field Effect Transis-tors Data Book.

7. Ref. 5.8. Bascom H. King: "Power FETs" Audio, Feb. 1975, p. 42.9. Ed Oxner: "A New Technology: Application of MOSPOWER

FETs For High -Frequency Communications" Tecnhical ArticleTr.76-2, Nov. 1976. Siliconix Inc.

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CHOOSING AND USING

TRANSFORMERSA mains transformer is often the single most expensive item in a project -

H. E. Clayton of Reading Windings takes a close look at this often neglected item.

Transformers are used to increaseor decrease either an AC voltageor an AC current level.

All transformers change both ACcurrent and voltage levels simultan-eously, but no transformer sig-nificantly changes power levels, asthe input power equals the outputpower plus losses which are ingeneral, negligible. Transformers canalso be used to transform impedancefrom one level (in the primary circuit)to another level in the secondarycircuit, the impedance transfer ratiobeing the square of the transformerturns ratio.

It is often possible to usetransformers in the opposite mode tothat for which they were designede.g. by feeding into the secondary of,a step down transformer and using itto step up in voltage. This will,however, usually give an outputvoltage below the rated valuebecause the turns ratio is normallymade less than the rated transforma-tion ratio to compensate for voltagedrops in the windings.

Power transformers can usually beoperated at frequencies higher thanthat for which they were designed,e.g. a 50Hz transformer can be usedat 60Hz, but not vice versa.

What we want is . . .

Before deciding on a transformerfor a particular application, it ishelpful to list one's requirements andto have some idea of what optionsthere are. It is hoped that thefollowing outline will help.

RMS input voltages and supplyfrequency: In addition to the nominalinput voltage the maximum value towhich this can rise should also beconsidered. Most transformers willoperate satisfactorily at about 6%overvoltage for short periods of timebut if it expected to exceed this figureit is advisable to increase the ratedinput voltage. Primary windings canbe tapped to cater for several voltagesbut this adds considerably to the costof the transformer and may detractfrom performance. Twin series -parallel windings on the other hand,although adding a little to the cost, donot substantially interfere withefficiency as all of the winding is inuse for both series and parallelconnections. They are howeverlimited to dual input voltage applica-tions where one voltage is twice theother e.g. 240/120V.Output Currents and Voltages:Unless otherwise agreed, the nominalor rated output voltage is that at fullload output current based on resistiveload. Again, several voltages can beprovided by tapping and, unlike theprimary taps, several secondarytappings can be used simultaneouslyto supply a number of loads. If,however, there is a significantdifference between the load currentsat different tappings, it may bepreferable to have separate windings.NB: The information above is theminimum which must be decided bythe user, all the following require-ments may remain unspecified unlesscircumstances demand otherwise,always remembering that special

features can add considerably to atransformer's cost.Regulation (usually MaximumValue): The regulation is defined asthe difference between a secondaryterminal voltage on open circuit andthe secondary terminal voltage atrated full load current.

Maximum permissible Temperat-ure rise: This is often decided by themanufacturer rather than the user asit may depend on the materials used.Higher standard temperature risesare associated with lower ambienttemperatures.

RMSINPUTVOLTAGE

RATED INPUT VOLTAGE

0 EMS EXCITATION CURRENT

Fig. 1. Plot of excitation currents vs. RMS inputvoltage for typical transformer. The transformershould not be operated for long periods abovethe.knee" of this curve.

Input Current (or Excitation orMagnetising Current): The no loadinput characteristic is shaped as inFig. 1 and care should be taken not touse the transformer for long periods


with voltages much higher than the"knee" of the curve.Electrical requirements: Limitationsto distortion of secondary waveform,any special phasing requirements etc.Insulation requirements: The basicstandard requirement is for a 2kVRMS test between the input andoutput windings and between anywinding and the core if accessible.Impregnation etc: Transformerswithout hygroscopic materials (thosethat absorb moisture) are oftenvarnish dipped while those usingabsorbent materials such as paper arevarnish impregnated. Both of theseprocesses are effective for minimisinglamination vibration and sealingagainst ingress of moisture.Dimensions: Any limiting dimen-sions and/or fixing centres.Construction: Some of the commonalternatives are described below.

What CoreInterleaved laminations are widely

used for small power transformers,the most common shape being theno -waste "E" and 'I' in which the 'I'sare cut from the 'E's (see Fig. 2) andthe coils assembled over the centrelimb (shell type construction). Theseare available in .50mm and .355mmthickness in variousrolled silicon iron and in 0.355 mmgrain -orientated silicon iron.

1/.// //A \

A2

Fig. 2. No -waste E and I construction oftransformer laminations.

Toroids and 'C' cores are madeof 0.355 and 0.10 mm thickness, thethicker material being used in the50-60Hz devices. Toroids have ahighly efficient magnetic circuit andby virtue of their circular shape, lowleakage flux. They are sometimeschosen because they can be used tomake a "low profile" i.e. low heighttransformer.

Because the cost of toroidaltransformers can be three times thatof an E and I laminated transformer, acompromise between the two whichis sometimes used for low profileunits uses U and I laminations withthe coils on the long limbs of the 'U".(Core type construction).

Winding Things UpMoulded bobbins are widely used

for smaller transformers. They havethe advantage that they can bewound on high speed machines.Insulation thickness between wind-ings and core and between windingscan be assured. The winding spacefactor (ratio of area occupied byactive copper and total winding area)is high and terminal tags can bemounted on the bobbin cheeks.Certain bobbins may be fitted withshrouds encasing the windings andgiving good mechanical and electricalprotection.

Ending It AllThe cheapest terminations are solder

tags on the bobbin cheeks. Forapplications where solder connec-tions are not convenient terminalblocks can be mounted on thetransformer. For larger transformersterminal panels with turret lugs orbolted connections are used.

Mounting UpMounting brackets are available

for the range of standard no -waste Eand I laminations. They take the formof 'U' clamps with two hole fixingwhich are crimped on to the smallersizes (up to about 50VA) and flangesand frames secured to the largertransformers with core bolts andproviding four fixing slots on each oftheir four sides (universal mounting).At the small end of the range (up toabout 5VA) pin terminations can beused for PCB mounting.

Electrical PerformanceIn its simplest form a transformer

consists of an input and outputwinding magnetically coupled withan iron core. The windings representan impedance in series with the load

and the core can be considered to bean impedance shunting the load. Thewinding impedances cause voltagedrops proportional to the load currentand a watts (copper) loss proportionalto the square of the load current. Thecore impedance does not directlyproduce a voltage drop but isassociated with an energy (iron) lossapproximately proportional to thesquare of the volts per turn for a fixedsupply frequency. The total losses(copper and iron) determine theoperating temperature rise of thetransformer which is usually the mostimportant factor limiting the use ofthe transformer.

Watts A VAAlthough the transformer total

losses depend on both voltage andcurrent, they are independent of thephase factor. For this reason trans-formers are rated in maximum VAand not in watts although withresistive loads VA = watts.

Transformer windings also have"self inductance" which can bethought of as a reactance in serieswith the winding resistance andthe load and is usually referred to asthe "leakage reactance". This doesnot usually effect the performance ofsmall power transformers (belowabout 100 VA size) particularly whenused with resistive loads.

Physical PerformanceAs transformers increase in VA

rating and physical size, the workingflux density and the winding currentdensity are reduced, but even over arelatively large range of sizes, thevariation is small enough to assumethat they are constant.

With this premise, it is interestingto consider the effect on variousparameters of change in physical sizefor the same overall shape.

Fig. 3. A collection of some of the more common transformer types Some of the wide varietyof constructions and terminations available can be seen in this photograph.


We can show that1) The regulation of small trans-

formers with resistive loadsdecreases in inverse ratio to theincrease in any linear dimensionand

2) The reactive voltage dropincreases while the resistive dropdecreases linearly with dimen-sions.Figure 4 shows the relationship

between transformer VA rating,volume (or weight) and regulations.The volume here is the length xwidth x height, not the displace-ment. This is based on mainstransformers using E and I no wastelaminations and operating at 50 Hz.It is often possible to increase theoutput current of a power transformerbeyond the rated value if one canaccept a temperature rise higher thanthe designed value. Overloading thetransformer in this way will, however,cause the output voltage to fallbecause of the increased voltagedrops in the windings.

Trying TimeThe following tests can be used to

establish basic transformer charac-teristics.Turns Ratio: Apply a known voltage,less than the rated value, to theprimary winding and measure thesecondary voltage. Care should betaken, especially with transformersbelow about 20VA rating, that theinstrument used does not impose asignificant load on the transformer."Excitation Characteristic Connectas in Fig. 5 and apply the ratedinput voltage to primary terminalsand measure input current andvoltage.

72.1.g1 11W°,2,!:'

Fig. 5. Connections for the excitation oropen -circuit test. The rated input voltage isapplied to the primary and the excitation currentis shown by A.

Winding Resistance Measure theprimary and secondary DC windingresistances with a multimeter orWheatstone bridge.Phasing. Where windings can beinterconnected e.g. with series/pa-rallel designs, it is important toestablish the relative polarity ofterminations. This can be done byconnecting the windings concerned inseries, applying an alternating voltage

VOLUME WEIGHTCCs KG

REGULATION %

5.0-1300

120C - Fig. 4. Graph1100 - showing relation -1000

40-a0 ship between

transformer VA900 - rating and both800 3.0

40,oC,

S3 -0`''

4..43

25 volume (orweight) and regu--

700 -0k oC, - 20 lation. These cur -

600 - -0. ves are based onE and I no -waste

500 - 2.00 - 15 laminations ope-

40C - rating at 50Hz.

?00

200

- 1.0

iREGULATION55oC TEMP

510

-100

RISE

I I i I I I I I 1 I

e0 20 40 60 80 100 120 140 160 180 206 OUTPUT VA

to one and measuring the overallvoltage (Fig. 6). If this measuredvoltage is greater than the appliedvoltage, then the windings are inphase. Conversely, if the measuredvoltage represents the difference ofthe two winding voltages the connec-tion is in anti -phase.

It Takes All SortsTransformers Feeding Rectifiers.

A common application for smalltransformers is to supply full waverectifier circuits including capacitorinput filters. The most common arethe bridge and bi-phase circuitsshown in Fig. 7.

For the same power rating, thetransformer for the bi-phase circuit

Fig. 6. Connections for the relative polarity test.

will be larger than that for the bridgecircuit because its secondary produ-ces twice the voltage and carriescurrent during each half cycle only.Ideally the secondary winding for thebi-phase transformer occupies V 2times the space of the primarywinding. Although transformer costis higher, rectifier costs are lower forthe bi-phase circuit.

The relationship between theaverage DC voltage and the RMSsecondary voltage is complex and isdependent on the smoothing capacit-ance, the supply frequency, thetransformer series impedance and theload impedance. Curves illustratingthis and other relevant relationshipsare published by rectifiermanufactu-rers but neglect the effect oftransformer leakage reactance whichmay be significant on some largertransformers. Because the waveformof the transformer current is very'peaky' the effective reactive volt dropis greater than may be expected byconsidering RMS values.Autotransformers have a singletapped winding to provide bothinput and output circuits. Withtransformation ratios near unity,autotransformers can be much smal-

FULL WAVECAPACITIVE INPUT FILTEP

dui

BI PHASE CIRCUIT

LOAD

FULL WAVE BRIDGECAPACITIVE INPUT FILTER

BRIDGE CIRCUIT

Fig. 7. Two of the most common rectifier circuits for use with capacitive input filters.


ler than similarly rated double -woundtransformers.

A disadvantage of autotransfor-mers is that there is a direct electricalconnection between primary andsecondary circuits so that both circuitsshare a common relationship to earth.Isolating Transformersusually have a 1:1 transformationratio and are provided specifically toelectrically isolate the secondarycircuit from any earth connection inthe primary circuit e.g. 'mains'circuits.Inverter Transformers (e.g.for switched mode powersupplies). These usually operate in thekilohertz range of frequencies and aresupplied with square wave -formvoltages.High Impedance Transformers areused for a variety of purposes a fewof which are mentioned below.Short -Circuit Proof transfor-mers are designed to continue inoperation without damage when thesecondary terminals are short-circuit-ed. Small transformers (below about5VA size) are sometimes made withsufficiently high winding resistancesto restrict the short circuit current butwith larger transformers an adjacentwinding structure is used with anintermediate magnetic shunt. Thisgives an output characteristic as

OUTPUTVOLTS

OUTPUTCURRENT

Fig. 8. Relationship between output currentand output volts of high reactance transformerwith resistive load.

Ar

shown in figure 8resistive loads.High frequency I ransformers.

The foregoing is concernedwith transformers operating only at aconstant supply frequency and withsinusoidal waveforms. Transformersused in communication circuits arerequired to handle a wide range offrequencies and waveforms, al-though any repetitive waveform canbe expressed as a series of sine wavecomponents. Such transformers areoften used in an impedance matchingrole. It is well known that to transferthe maximum amount of energy into aload from a voltage source the loadimpedance should equal the sourceimpedance.

when used with

SCREENINGStray magneticfields produced by

power transformers can cause hum inhigh gain amplifiers in the samelocality. Screening around the powertransformer is not normal because alarge percentage of the stray flux,which is emitted in all directions,would strike the screen at right anglesand pass through it rather than bediverted. On the other hand inputs(e.g. microphased transformers) areoften enclosed in a screen of magneticmaterial to reduce pick-up.

PRODUCTION METHODSCoil winding techniques and

machinery have improved immenselyin recent years. Unfortunately it is notalways possible to make the best useof these improvements which aremainly geared to high volumeproduction of standard products.Although some degree of standardi-sation in small transformers has beenachieved equipment designers stillexpect transformers to be tailor-made,often in small quantities, to theirparticular electrical and dimensionalrequirements.

Summarising, before seeking aspecial transformer, consider first ifreadily available standard transfor-mers can be used. It will often becheaper to use two or more standardtransformers than one special unit.

IT'S A DOGS LIFE!

Mighty mongrel strikes again!

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Invest in an ETI binder. You know it makes sense.

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ELECTRONICSBY EXPERIMENTIAN SINCLAIR'S SERIES IS DESIGNED TO IMPART THEORETICALKNOWLEDGE THROUGH SIMPLE PRACTICAL EXPERIMENTS.

Many experienced constructorswith several acres of transistorcircuits behind them still fight a

little shy of using digital integratedcircuits The reasons for this are notdifficult to see. Most of the transistorcircuits with which an experimenterlearns his trade are fairly simple andshow rather well how a transistorworks, giving a feeling of confidenceto the user.

The many excellent projects usingdigital integrated circuits which havebeen published do not give any suchhelp to the constructor, however.They may be comparatively easy to

they mayeven be reasonably easy to under-stand, but they do not give theconstructor the experience whichenables him to design confidentlywith ICs.

This series is intended to remedythat deficiency, so that the reader willgain a firm grasp of the principles ofdigital IC behaviour, how they work,and also a considerable amount of"hands-on" experience on a boarddesigned to make experimenting withdigital ICs particularly easy. We shallconfine ourselves to the smaller scaleICs so that nothing as involved as amicroprocessor will be used - thecomponents however are chosen sothat they give a good range ofexperience with some useful devices.

One and noneWe can assume that any reader of

ETI will already have some know-ledge of what digital circuits areabout, but perhaps a very briefreminder may be of some use. DigitalICs are made up from transistorcircuits of very high gain, designed torun with inputs and outputs which cantake up only two possible states whichwe call 1 and 0. In most applications,0 will mean a voltage very near toearth potential, and 1 near to the fullsupply rail.

The ICs we shall use in this coursewill be from the well-known TTLseries, developed by Texas, and alsoavailable from several other manufac-turers. There are several reasons forthis: the devices are readily availableand at very low prices and advertisedin ETI, they are much less easilydamaged electrically than the alterna-tive CMOS.

Going places with nothingWhen an input of a TTL gate is left

open -circuit it automatically reverts toa "1". The reason for this is that theinput to TTL gates is to one emitter ofa multiple -emitter transistor whosebase is connected through a limitingresistor to the +5 V line. Leaving aninput o/c means that the emitterterminal will take up the same voltageas the base terminal. This cannot bedone when CMOS devices are used.

For our course on digital electro-nics we shall need seven digital ICsand one "jumbo" display, a fullinventory of semiconductors beingshown in the parts list and in additionwe shall also need a few other

Fig. 1. The method of attaching components tothe Blob Boards. The "leg" can be simply bentto one side and then solder "blobbed" over thelead to hold it. Since the boards are tinned, andthe leg ought to be, a sound joint is ususallyobtained.

assorted components as notedtherein. Where a source of 5 V supplyis not available, a stabiliser can beincluded on the board, so that theexperiments can be carried out usinga car battery or any dc supply in the 6V to 12 V range. Note that the currenttaken will be up to 350mA.

Heart to heartThe heart of the whole project is

the circuit board on which the ICs andall other components can be mount-ed. This is one of the series of "BlobBoards" in this case the ZB-8-IC. BlobBoards consist of wide strips of tinned.copper on the usual insulating board;and their main feature is that com-ponents are mounted on the sameside of the board as the strips.

This, of course, is not a newprinciple in digital IC construction,since this method has been used forsome time where digital ICs aremounted on double -sided boards.

Housing and boardingThe ZB-8-IC as its name suggests,

has mounting pads for eight ICs,including the display which we havespecified. The suggested layout forthe ICs is shown in Fig. 3, where wecan see that the top left hand cornerhouses the 7414 Schmitt inverter,and the 7400 Nand gate; the top righthand corner has the two 7476 J -Kflip-flops. At the bottom left handcorner, we have a 7494 shift registerand the 7490 decade counter. Thebottom right hand corner contains the7447 BCD -7 segment decoder -driverand the display. All of the ICs haveconventional DIL fourteen or sixteenpin bases, but the display has a basewhich is an eighteen pin type withseveral pins omitted, so that this willjust fit the pads on the board. Thespacing between the lines of pins(0.6-) is a little on the large sidecompared to the other ICs, but with


2

6

9

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

2

3

4

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

Fr- girm re--irmII II.=111E111=

ow

A B C D E F G H I J KLMHOP 0 FIS,TUVB/ X

Fig. 2. Above: This is the track pattern for the 2B -8 -IC used in this series. Note the wire linkswhich need to be made in order to more easily facilitate application.Fig. 3. Below: Components in place on the board. Note that unlike our usual overlays, the tracksare on the SAME side as the components.

4 7400

111101011 MEM4 =411iONNI=Mgm

749. 7490

AB C D E F G H I

ionc-mra.

7476 747

K IAA NOP 0 0 S T U V

care it can be accommodated. In thecircuits which we are using we shallnot normally need the decimal pointon the display, but its connection mayas well be made just in case.

Before any experiments are startedthen, it is advisable to solder all theICs and the display on to the board, sothat this does not have to be donewhen it becomes cluttered by othercomponents. Since each circuitmounts on to pads which are isolatedunless other connections are made,no harm is done by leaving an ICsoldered on to the board.

YZ

It is for this reason, incidentally,that it is not desirable to use CMOScircuits in such a project, since theprotection diodes built into CMOS ICswill operate only when the powersupplies are connected.

In the prototype, the lines runninground the edge of the Blob -boardwere used for supplies, the outer line

Fig. 4. Top Right: The layout for the digital TTLseries. This is looking down at the device fromabove. Usually, but NOT always power isapplied to pin 14 and pin 7 is earthed.Fig. 5. Bottom: Positioning the ICs ontoBlob -Board pads. Make sure the legs line up.

taken as the positive 5 V line, and theinner as earth. It is quite convenientalso if the shorter lines running acrossthe board between each pair of ICpads are also used as 1 and 0 lines aswell. The vertical lines at the centre ofthe board may also be used. If a

stabilised 5 V supply is available foroperating the board then little elseneeds to be done other thanconnecting the power pack to thelines at the edge of the board.

Stable linesIf a stabilised supply is not

available, however, a stabiliser shouldbe built on to these lines. A suitablecircuit is shown in Fig. 7 using aBD131 and 2N697, both of whichare readily obtainable.

It is extremely important that TTLcircuits should not be operated atvoltages above 5.25 V AT ANY TIME,.since the inputs to TTL circuits are tothe emitters of transistors, with thebases connected to the positivesupply. If the inputs to the emittersare earthed (at OV), too much currentwill flow in the base -emitter junctions,though if all the inputs are earthed,over -voltage is much less likely tocause much harm.

Led about the boardAbove and below each mounting

.pad there are several short padsusually three horizontal and twovertical, and these are very useful formounting components such as LEDs,which are used to indicate the state, 0or 1, of any output. Note that on mostLEDs there is a flat portion of theplastic case near the leadout wireswhich indicates which leadout wire is

PIN 14

INDEXMARK

6C

7C

8C

9C

10C

11C MEW12C

13C

PIN 8

6F

7F

8F

9F

1OF

11F

12F

13F


HOW IT WORThe action of the circuit is as follows. The

connection of the 1k resistor between thecollector and the base of the BD131normally ensures that the BD131 remainsconducting, but the 4.3 V zener diode ZD1will set the voltage at the base of the 2N697at about 4.3 volts less than the voltage at theemitter of the BD131. The 2N697 will start toconduct when its base voltage is approxi-mately 0.6 V positive to its emitter voltage,that is when the emitter of the BD131 is atabout 4.9 V positive.

An increased voltage here will cause morecurrent to flow in the 2N697 (each 80 mVincrease of voltage at the base of aconducting transistor causes the collectorcurrent to rise tenfold), drawing currentthrough the 1k resistor and thereforelowering the voltage at the base and emitterof the BD131; in this way the circuitstabilises at about 4.9 - 5.0 V. The secondzener diode, ZD2 is a 5.6 V type which is asafety measure should the BD131 ever fail toa short circuit. In the event of such failure,ZD2 could absorb the extra current until thepower supply fuse melted. If a battery isused as a source, a 500 mA fuse should beincluded.

Later models of the ZB-8-IC Blob Board may have a different tracklayout to that shown here. This should only affect the positioningof the voltage stabiliser components.

+Ve UNREGULATED

+5V REGULATED

2N697

METAL FACE

BD131

Fig. 7. Above: Circuit diagram for asuggested power supply to run the experi-ments, and, Fig. 8, below, a layout to build thiscircuit onto the board itself.

the cathode. Since we are using theLEDs to light on a "1- state, thecathode of each LED is connected toearth, and the anode through a

limiting resistor to the IC output. Thisresistor value is higher than we wouldnormally use, but suits this applica-tion, as we do not want the LEDs todraw too much current from the ICoutputs. When we come to use thedisplay, we shall also use large valuelimiting resistors.

With all the ICs mounted in place,we are ready to start our work.

Fig. 6. Identifying led connections hascaused many a paralysed moment of doubt -look for the flat bit, if there's one presentthen 'your problems are over.

FLATPORTION

REG. UNREG.

C_

P

L

Note: Only the essential basiccomponents are listed here. Forvarious additional suggested experi-.ments, additional resistors andcapacitors will be needed; thesevalues will be critical.

SEMICONDUCTORS1 x SN7414N1 x SN7400N2 x SN7476N1 x SN7494N

1 x SN7490N1 x SN7447N

1 x 747 Display

PARTS L STCOMPONENTS NEEDED

FOR THE SERIES

OTHER COMPONENTS1 x 0.1uF1 x 1.0uF1 x 10uF1 x 100uF1 x 680uF1 x 1000uFAll the above 10V working, or more.10 x 470R resistors, 0.1 25W or more6 Miniature push-button switches(Sintel)5 metres of single -core wire

STABILSER COMPONENTS1 x 2N6971 x BD1311 x 4V3 Zener Diode1 x 5V6 Zener Diode1 x 270R 0.5W1 x 1k, 0.5W

BOARD1 ZB-8-IC Blob -Board

For a few applications in later parts ofthis series, a silicon NPN transistormay be used as an alternative to somelong stretches of wiring (to connect areset terminal on a counter). For thisapplication, any working small signaltype is suitable.


DIGITAL ELECTRONICS BYEXPERIMENT PART 2

The is we have chosen to intro-duce TTL is the SN 7414 Schmittinverter, placed at the top left

hand side of the blob -board. (As allthe TTL series start with 'the lettersSN, we shall omit these in future, andrefer, for example, to the 7414.)

R1

IN

The circuit of an inverter is that of ahigh -gain inverting d.c. amplifier (Fig.1), with the input at the emitter of atransistor and the output from a

single -ended push-pull stage which iscapable of passing of up to 16mA ineither direction (to + 5 V or to earth).This type of design, typical of TTL

la)

"Valve salesman were you? I used to sell computer time."

circuits, has several important impli-cations for us.

Source or sinkOne important result is that the

input impedance is fairly low whenthe input stage is conducting. If theinput is left floating, the connection ofthe base of the first transistor to + 5 Vwill ensure that the emitter terminalwill also be at high (+ 5V) voltage: Thefirst transistor will be cut off in thisstate. The normal action of an inverteris that a high (or "1") input producesa low ("0") output, so that Q, isswitched on by the high voltage at thecollector of Q,, and connects theoutput terminal to earth through 04.As mentioned above, this will allow acurrent of up to 16mA to pass from apositive source; in TTL language, theoutput stage will sink a current of upto 16mA.

Thank you fans

When we connect the input of theinverter to earth (0), what we aredoing is to earth the emitter of Ql,with the base still connected, throughits current limiting resistor, to + 5 V.When this is done, a current of about1.6 mA (set by the value of thelimiting resistor) will flow from base toemitter, and it is very important thatany resistance between the emitter(input) and earth should be smallenough to prevent the emitter voltagerising above about 0.5V in normaluse. This is ensured when we drive aTTL input from the output of anotherTTL device, since a TTL output cansink a current of up to 16 mA, thecurrent from ten inputs, without theemitter voltages rising too high forreliable operation. This is referred toas a "fan -out" of ten at the output.

Since in these circuits we areinterested only in high and low signallevels, we must make sure that thereis no uncertainty about either of these

IN OUT

(b)

Fig. 1. A typical TTL inverter circuit (a). Thevalue of R1 is about 3k, to limit the base currentto 1.6mA. (b) Symbol.


+Ve

>A

L2J

levels, and the usual TTL limits are:maximum of 0.8V for the low;minimum of 2.2 V for the high. Weprefer if possible not to approachthese limits too closely, and if we drivea TTL input from any other type ofoutput, we must be sure that thesource impedance of the driver outputwill be low enough to allow a currentof 1.6mA to be sunk at a voltage levelof 0.5V or less; this corresponds to anoutput impedance of 300R or less.

Starting work

Ensure that the 1 and 0 lines onyour blob -board are fully linked upand, if you are using it, connected tothe stabilised supply. Join + and -leads to the power supply. If you havea separate stabilised supply, theseleads, which should be colour coded,will connect directly to the 1 and 0lines on the board. If you are using thebuilt on stabiliser, the leads shouldrun to the stabiliser input.

With no other connections made(none of the ICs wired to 1 or 0 lines)ensure that the voltage between lines1 and 0 is between 4.75 V and 5.25 Vwith the supplies on. Switch off again.This check should be repeatedwhenever the board is used from avariable voltage supply, since TTLcircuits will be damaged if any input istaken to 0 with the applied voltage toohigh.

Four for four uses

Connect the supplies to the 7414,pin 14 to +5V, pin 7 to earth. Theseconnections, like all the connectionswhich follow, are made by solderingshort lengths of insulated wirebetween pads on the blob -board, asshown in Fig. 3. These connections,once made, can be left permanently.

Fig. 4. LED indicator circuit.

E0_

LI I

Fig. 3. Connections to +and - lines using wires.This also shows the LEDand its limiting resistor(Fig. 4) in place.

11

Fig. 2. Pin -out of the SN7414NHex Schmitt inverter.

-Ve

1

111

1F

ED

5B

5C ..INOT USED

18C

7414

13B13C

1-1PIN 7 TO EARTH

I LI

(With no other connections made, theIC will draw a current of about 85mA.)

Now connect a 47OR resistor andan LED to form the circuit of Fig. 4.This is done by tinning each end of theresistor and LED leadout wires, andthen butting these tinned wires, inturn, against the blob -pad andtouching wire and pad with a hot ironuntil the lead "blobs" into place. Forthis particular joint, we can use aspare pad, as shown in Fig. 3, withthe resistor connected from pin 2 ofthe 7414 to the spare pad, and theLED connected from the spare pad tothe 0 line. Note That the LED case isusually marked with a flat section at

PIN14

7F TO +5 V

F

the wire which should be connectedto the 0 line.

The LED will now light when theoutput of No 1 inverter (there are sixinverters in the pack) is high. Switchon - the LED should remain unlit,since with the input, at pin No 1,floating high, the output will be low.Now check what happens when pin 1is temporarily earthed through a wirelink (no need to solder) placed withone end on the pin 1 blob -pad and theother end on the 0 line.

Bridge over troubled padsRemove the wire, and try bridging

between the blob -pad for pin 1 and


C1680 u

136/7777

R1470R

C1

VALUES

0 IC PIN NUMBERS

8C BLOB-BOARDREFERENCE POSITIONS

1000u

100u

10u

1u

100n

10n

1000p1Hz 10Hz 100Hz 1kHz 10kHz 100kHz 1MHz

Fig. 6. Oscillator circuit, with a graph of approximate frequency against capacitor value. The FREQUENCYfrequency changes considerably when the operating voltage is changed, also as the resistor value isvaried.

the 0 line with low value resistors,starting with 220R and working up.What is the maximum value ofresistance which will allow the LED tolight?

Schmitten with complexity

The actual circuit of the 7414 ismore elaborate than the outline which

5V

OUTPUTVOLTAGE

Fig. 5. Schmitt Trigger. (a)Symbol. (b) Typical circuit. (c)Graph of output voltage plottedagainst input voltage.

L OILER UPPER

INPUTVOLTAGE

has been shown in Fig. 1. Theseinverters are Schmitt trigger inverters,indicated by the symbol of Fig. 5(a),in which some positive feedback isused to make the changeoverbetween 1 and 0 very much morerapid than that of an amplifier alone.

A simple discrete Schmitt triggercircuit is shown in Fig. 5(b), with thepositive feedback applied by using acommon load, R2, for the twoemitters. With the base of Q, at 0, thecollector of Q, will be at 1, and Q2 willbe conducting, with its base voltage ata level decided by the values of R, andR2, say 1.3V for the sake of anexample.

The emitter voltage will be about0.6V (since we are using silicontransistors) less than the base voltageof Q2. If we now slowly increase thevoltage at the base of Q1, nothing willhappen until we reach a level of 1.3Vin our example, at which level Q, willstart to conduct.

When this happens, the voltage atthe collector of Q1 starts to. drop,reducing the base voltage of Q2. Sinceevery 80 mV drop on base voltagecauses collector current to reduce toone tenth of its previous value (a

useful rule and true for all silicontransistors), Q, will rapidly cut off,with the current now switching to Q,because of the positive feedbackthrough the emitters.

If the base voltage of Q, is reducedagain, it must be to a value less thanthe base voltage of Q2 before Q2 canconduct again.

In this way, there is a voltagedifference or hysteresis between theswitchover voltages in either switch-ing direction, which is indicated on agraph of output voltage against inputvoltage in Fig. 5(c). It is the shape of

this graph which is used as the symbolfor a Schmitt stage.

Slow, slow, quick quick .. .

Since the normal type of TTL circuitconsists of a very high gain d.c.amplifier, there is a risk of positivefeedback, causing high frequencyoscillations, if the amplifier is everoperated, even momentarily, in a

linear region, that is with the inputbiased so that the output voltage isbetween 1 and 0, or slowly changing.There is no problem if the changebetween 1 and 0 is fast, 30 ns or so,but slow in this context can mean 1as!

Slowly changing waveforms aremost likely to be found when othercircuits such as photocell amplifiers,microswitches or tacho-generators areconnected to TTL inputs. This is aninterface problem. Using a Schmittstage at the input solves this,assuming we have a low enoughimpedance to drive the Schmitt, sincethe Schmitt action will give a 30 nsrise or fall time at its output for any

Fog. 7. Switch de -bouncing circuit.

9A

ICllu

1013

+5 V

OUT

-Ve0


type of input, however slowlychanging. Once the Schmitt hastriggered, a comparatively largevoltage swing is needed to make itchange back. A Schmitt stage withhigh input impedance is also available(SN72560).

They call it de bounce

One of the unique features of thistype of stage is that it can very simplyact as an oscillator or as a switchde -bouncer. Oscillator action isachieved by connecting a resistor ofbetween 330R and 820R betweenoutput and input, with a capacitorbetween input and earth. The circuit isshown in Fig .6. The output waveformis a square wave with very short riseand fall times, and unequal mark andspace times.

Fig. 8. Layout of theoscillator circuit onthe Blob -board.

When mechanical switches areused to provide waveforms for TTLcircuits, contact bounce may causeproblems. It occurs as contacts close,and causes a TTL input to be leftbriefly floating during the time ofthe bounce.

The effect of this can be to causeseveral output pulses from the switchwhere only one is intended. This isharmless if the switch is simply settingd.c. levels, but causes errors if thepulses are being counted. To de -bounce a switch, the circuit of Fig .7can be used. The principle is that thetime constant is longer than thebounce time of the switch, so that thevoltage change when the contactsbounce is small, less than thehysteresis of the Schmitt circuit,hence no change in the trigger outputwhen the bounce occurs.

Fig. 9. Showing inverter action. One section ofthe 74 14 is used as the oscillator, and the nextsection as an inverter.

470R

4C

4B LED2

Back to the Blob -Board

Using unit 1 of the 7414, make upan oscillator using a 680R resistorand a 680 p.F capacitor as shown.Keep the connections previouslymade to the LED, since this can nowbe used to check that the oscillator isworking.

R2D1150R 1N914

1\AACR1470R

7C

Cl680u

13B

8C

Fig. 10. Modification of the oscillator circuit forequal mark -space ratio This is not needed forany of the applications in this series.

Estimate the frequency by count-ing the number of LED flashes in oneminute, and then dividing the numbercounted by 60. Demonstrate theinverter action by using unit 2 asshown in Fig. 9. Wire a connectionfrom pin 2 to pin 3 of the IC, and a470R resistor from pin 4 to a sparepad. Connect another LED betweenthis pad and earth to indicate whenunit 2 output is high. Switch on again,and the two LEDs should blinkalternately.

The oscillator can be modified forequal mark -space ratio by using thecircuit of Fig.10. Some trial and erroris needed to find the correct resistorvalue.

Organ Bank

Note that the 7414, with its sixseparate inverter circuits, can be usedas the oscillator for an electric organ.Two 7414s will give a basic twelvenote scale, and dividers can be usedto produce lower frequencies.

Later in this series, the 7414 unitswill be used as oscillators to provideslow clock pulses, as inverters, and asswitch de -bouncers. The connectionsmade during this month's experi-ments can be left in place.



Agate circuit, in general, is a circuit which will allow asignal to pass for a time defined by another signal,often a rectangular pulse (Figure 1a). In linear

circuitry we need linear gates which do not affect theshape of the signal which is gated, but in digital circuitryall the signals are steady voltage levels, 1 or 0, or fasttransitions between these levels, so that speed of opera-tion is important and no linear action is needed. Ideally, aperfect switch is also a perfect digital gate.

Logic gates are of two basic types, the AND and the ORtype. The simplest examples of each have two inputs andone output, though up to 13 inputs are found in sometypes. Taking the two input AND gate, the output is a logic1 when, and only when, both inputs are also at logic 1 (Aand B are at 1); the output is zero for any other combina-tion of inputs. The two input OR gate gives a logic 1

output when either input is a logic 1, or when both are atlogic 1 (A or B or both).

AMIN _P&L_

I Q

(a)

A

D QAND OR

(b)

Fig. 1. Gates. (a) General gating action (b) Logic gate symbols

AND-GATE OR-GATE

B

1 1

Q A B Q

1 0 0 01 0 0 1 1

0 0 0 0 0

tat tt»

Fig 2. Truth tab/es (a) AND -gate. (b) OR -gate

These actions can be summarised in a truth tablewhich shows at a glance what combinations of inputsand outputs are possible. Fig 2 shows the truthtables for the AND and OR gates. Truth tables, thoughuseful, become rather bulky when the gate has a largenumber of inputs, so that a better way of memorising theaction is to remember that only when all inputs are 1 isthe output of the AND gate 1, and only when all inputsare zero is the output of the OR gate zero.

NAND and NOR gates have outputs which are theinverse of the AND or OR gates respectively, as the truthtables of Fig.3 show; internally these gates are AND /ORgates with inverters at the outputs. Another gateencountered at times is the exclusive -OR (XOR) whichhas the truth table and symbol shown in Figs. 3c, d. Notethat the action is that of the OR gate, except that theoutput is 0 when both inputs are 1.

Working over a 7400

The second IC we shall deal with in this series is a7400 quad NAND gate. This consists of four separatetwo -input NAND gates, and like all the other ICs used inthis series is a TTL circuit. An unconnected input willtherefore float to logic 1, and will need a current of 1.6mA to be sunk to hold it down to logic 0.

Start work on this gate by connecting the powersupply leads. Pin 7 is taken to the negative line by a wireconnection, and pin 14 is similarly taken to the +5 Vline. The connections to the gates are shown in Fig.4; weshall start by using gate 1.

Connect a 470R resistor between pin 3 and a sparepad, as shown in Fig. 5. Now connect another LEDbetween the spare pad and the zero line to act as anindicator to light when the output is at logic 1- we couldobtain inputs by soldering in wires, but this is rathertedious.

Wire up the switches as shown in Fig. 5, wiring theterminals directly to the -0- line and the spare pads.Since these are press -to -make switches, their effect willbe to give a logic 0 when pressed, the input to whichthey are connected will then float to logic 1 when theswitch is released.

Miniature slide switches were tried, but found toshort 1 to 0. With the switches in place, check the truthtable for a NAND gate, using the LED to indicate thestate of the output. The truth table should agree withthat of Fig. 2a.

Now investigate the effect of adding an inverter, byjoining a wire from pin 3 of the 7400 to pin 1 of the7414, using the LED which is connected to pin 2 of the7414 as the output indicator (Fig. 6). This connection,


NAND-GATE' NOR-GATE X-OR GATE

A B A B A B

0 0 1 0 0 1 0 0 0

0 1 1 0 1 0 0 1 1

1 0 1 1 0 0 1 0 1

1 0 1 1 0 1 1 0

(a) (b) (c)

(d)

using the switches to provide inputs to the 7400, shouldgive the truth table for an AND gate.

We find, however, that if we invert each input beforeapplying to the 7400 inputs (Fig.7) that we do notobtain an AND gate this -way. What truth table do wefind?

To try it out, connect the switch outputs to theinverter inputs instead of to the 7400, one to pin 1 andthe other to pin 3 of the 7414. Join pin 2 of the 7414 topin 1 of the 7400 and pin 4 of the 7414 to pin 2 of the

SW1

2H 5H

Fig. 5. Gating action. Above the circuit andbelow the practical layout. Note that use ismade of the fact that a floating :maw is at logic"1". The input is earthed (0) when the push-button switch is pressed. Miniature sliderswitches were tried, but were found to shortmomentarily between the 1 and 0 positions

LED

7G

8G

9G

13G

0

9G

\'S 1

18G4

7J

Fig. 3. Truth tables. (a) NAND -gate. (b) NOR -gate. (c) X -OR -gate. (d).Symbol for the X -OR -gate.

Fig. 4. Pin -out diagram for the 7400.

7400, using single strand insulated wire. Use the LEDwhich is connected to pin 3 of the 7400 as an indicator.

Having done this, could you design a NOR gate, andconstruct one? Try out your circuit and draw up a truthtable.

The exclusive -OR circuit needs rather more thought.One possible circuit is shown in Fig.8. Construct this,using the 7400 and 7414 units, and check that the truthtable agrees with that of Fig.3c.

Combinational Logic

Circuits which contain only logic gates are calledcombinational logic circuits, because the output canalways be predicted from the combination of inputswhich is present. As we shall see later in this series, thereare circuits in which the previous inputs matter as muchas the present ones. Combinational logic circuits obeythe rules of Boolean algebra, which will not be dealt withhere, but have been discussed in ETI.

Because the output can always be predicted from theinputs which are present, logic gates can be used forcontrol circuits. We can, to take a simple example,control the heating of a house by having logic gatescontrol the circulating pump (or fan), by way of athyristor or triac.

The inputs to the gates will be the signals from roomthermostats, perhaps an outside thermostat, a boilerthermostat, a hot-water tank thermostat, and a

timeswitch or two. There will be another output from thegates to control the operation of the boiler.

For such a system, logic gates easily carry out ANDand OR actions which would need much more wiring

Fig. 6. Using a NAND -gate and an inverter to make an AND -gate.

A

2H

SW1

B

470R

2G

/ 1/

10C

470R

5C

LED2

5F3


and space to carry out with relays, but the full advantageof using logic gates is obtained when all the thermostatsand other signal generating equipment and timing arealso electronic.

Bawdy WorkAn application of gating is shown in Fig.9, using the7414 and 7400 to make a gated oscillator circuit. Twosections of the 7414 are used as oscillators, one at anaudio frequency of about 1 kHz and the other at a muchslower rate, and the outputs of the oscillators are takeneach to one gate input of the 7400. When the slowoscillator input is high, the output of the NAND gate willbe the high frequency square wave, since with one inputat 1, the output is the inverse of the other input.

When the output of the slow oscillator is at logic 0,there is no oscillator output from the 7400, because theoutput is set to logic 1. The output can be detected eitherby feeding it to an amplifier, or by using high resistanceheadphones connected through a capacitor, or by usinga capacitor and a 1k resistor in series with a smallearpiece from a transistor radio.

Could you now design and construct a circuit whoseoutput was a two-tone oscillation (HI -LO -HI -L0-).Remember that the output of the NAND gate in Fig.9was a logic 1 when not oscillating. Do NOT be temptedto combine the outputs of two gates by joining outputpins, this will BURN OUT YOUR IC, because very largecurrents will flow if one output is at 1 and the other at 0.One possible scheme uses three of the 7414 inverters asoscillators and one as an inverter, with three NANDgates also used..

Fig. 7. What is the truth table for this circuit?

Fig 8. An exclusive -OR gate built from NOR -gates and inverters.

9B/7777

4 701

IF B 1 AND C 1, THEN A CHANGEOF A FROM1 TC 0 CAUSES A BRIEFPULSF AT 0

Fig. 9. A gatedoscillator. (a) Circuit.(b) using anearphone to detectthe note. (c)Connecting theoutput to anamplifier.

Fig. 10. Race hazards. If weimagine that lines B and C areboth at one, then the changefrom A = 1 to A = 0 should

A cause no change in the output.Because of the delay in the

A inverter, however, A goes lowjust before A goes high sothat there is a narrow negativepulse developed at the output.This could cause problems if acounter were being driven fromthe output.

Racy Hazards

One problem of combinational logic circuits is theshort but measurable time delay (some 30 - 80 ns)which occurs in a gate, which can cause momentaryspikes to appear in the outputs. A circuit which can givesuch a problem is shown in Fig.10. Imagine that B and Care both 1 and that A is changing from 1 to 0. With Band C at 1, the output of the circuit is A or A, and sinceis obtained from an inverter it will arrive at the OR gate alittle later than A. Momentarily, then, A will be at 0, andtwill still be at 0, so that the output will dip to 0, andthen rise to 1 when A arrives. The pulse will be veryshort, but not too short for a counter to detect andregister. Race hazards will not affect any of the circuits inthis series, and the avoidance of race hazards is a topicwhich is beyond the scope of our work at present.



In this part of our series we shall lookinto sequential logic by using the7400 IC.Set the IC up on the board to make a

circuit using two of the logic gates asshown in Fig. 1. The gate with its out-put taken to the LED should have itsspare input marked R, while the spareinput to the other gate should bemarked S.

Fig. 1. Cross -coupled NAND gates forming anR -S

This circuit is a flip-flop, as you mayhave guessed from the cross -connection of inputs and outputs.Complete the table shown in Fig. 2,and note that the output for R = 1, S =

1 is not the same in each case.

Sequential Logic

The R -S flip-flop, as this is called, is anexample of a sequential logic circuit, inwhich the output depends on the se-quence of signals at the input - in otherwords, the state of the output dependson the previous signals as well as thepresent ones. Strictly speaking this cir-cuit is more of a latch, a circuit whichtemporarily stores an output while bothinputs are high. Note that in normaluse, we want two outputs Q and Q to becomplementary (Q is always the inverseof Q) so that the input R = 0, S = 0must not be used, since this givesQ = Q = 1.

In logic circuits, clocked flip-flopsare much more common. A clockedflip-flop changes state only when a

R S

0 1

1 1

1 01 1

Q

Fig. 2. Part ruth table for R -S flip-flop. Whenyou complete the table, taking readings fromyour blob -board circuit, be sure to work througheach state in sequence.

timing, or clock pulse is received. Thisis done by combining the flip-flopaction with gating so that the signal in-puts have no effect until the gating(clock) pulse arrives.

One type of clocked flip-flop is theD -type, and a typical truth table is

shown in Fig. 3. In this type of circuitthe signal (0 or 1) which is present atthe D (for Data) terminal is transferredto the output at the clock pulse, andremains unchanged until the datachanges and the clock pulse arrives.

Clocked Flip -FlopThe type of flip-flop chosen for thisboard is the J -K flip-flop. This is a

more versatile device which combinesclocking with gating to achieve a widerange of actions. On the type we havechosen, the SN7476, the action is thetype known as "Master -Slave", whichmeans that the input signals are accept-ed on the leading edge of the clockpulse, but the outputs do not changeuntil the trailing edge comes along.This avoids problems which wouldoccur if outputs were connected back tothe inputs, as we shall see later.

The J -K flip-flop has five inputs andtwo outputs. The inputs are labelled J,K, Clock, Set and Reset (the Reset issometimes called clear, and the Setterminal is sometimes called preset).The outputs are Q and Q, with Q always

the inverse of Q. We shall check theaction of the J -K flip-flop using signalsgenerated on the board.

From previous work you shouldhave available one section of the 7414connected as a low speed oscillator. Thisprovides an ideal slow clock pulse, andyou should already have an LED con-nected to the output of the 7414 tomonitor this pulse.

SET(PRESET)

RESET(CLEAR)

Fig 4 J -K flip-flopsymbol

Double Flip -FlopsThe connection diagram of the 7476 isshown in Fig. 5. From this you will seethat the 7476 contains two J -K flip-flops which are completely indepen-dent. For the first series of practicalexercises we shall use only one half.

Solder connections from pin 13 ofthe 7476 to earth, and from pin 5 tothe +5 V line. Now solder an insulatedwire connection from the clock oscil-lator output to pin 1 of the 7476, sothat flip-flop number 1 is activated.

Connect pins 4 and 16 to earth sothat J = 0 and K = 0, and connectswitches so that the reset pin (pin 3)and the set pin (pin 2) can be connectedmomentarily to earth as needed. The

D SIGNAL Q BEFORE CLOCK 0 AFTER CLOCK

0 0 00 1 01 0 I 1

1 111

1

Fig 3 0 -type flip-flop and truth table Note that, unlike the R -S flip-flop, changes take place onlywhen the clock pulse arrives.


K Q a-k77

1 1 1 2 2

16 15 14 17171 12 1711

1.1

rrin

RESET SETK a

CK

SET RESET

2 2

FTI

Li Li jJ SET1 2

CK1 SET1 RESET1

+Ve CK2

Fig 5 Pinout of the SN74 76 dual master -slave J -K

circuit is now as Fig. 6 , and the appear-ance of the board is shown in Fig. 7.

Now connect a resistor from pin 15(Q) to a spare pad, and an LED fromthe spare pad to earth. This LED willindicate the state of the output fromthe flip-flop at Q.

Switch on, and look at the LED.Using the SET switch, set the output togive logic 1 (This happens when theSET switch is returned to 0, whateverthe clock pulse is doing at the time).When the switch is changed back again,does the output change at once? Orwhen a clock pulse arrives?

These changes and others to followmay be easier to observe if the clockpulse is very slow, and a 1 000 uF, orgreater, capacitor may be used in theoscillator circuit. Later, a "debounced"switch will be used.

Complete the sequential truth table,in which Qn-1 is the value of Q justbefore the clock pulse arrives, and Q,is the value of Q just after the endof the clock pulse (the 1 to 0 change).Can you decide when the change, if any,occurs? Is it on the leading or the trail-ing edge of the clock pulse?

Now switch off, and disconnect oneend of the link between K pin (pin 16)and earth, so allowing K to float to 1.Now we have J = 0 and K = 1. Switch

CLOCK PULSEFROM OSCILLATOR

Fig. 6. Circuit for checking J -K action, see textfor details.

RESET2

on and observe the output. Change theoutput by using a switch (which onewill you use SET or RESET?). Does theclock pulse affect the output after theswitch has been returned to normal?

PUSH TO

SET RESET

J-0K-0

o(b) 0

0 , STATE OF 0 10 OR Ti BEFORE CLOCK PULSE

Or. - STATE OF 0 100R 1) AF TER CLOCK PULSE

Fig. 7. (a) The layout on the board, with the LEDin position(b) Form of part truth table.

Switch off again and reverse theconnections so that J = 1 and K = 0, andrepeat your readings. Enter all the read-ings on the sequential truth table ofFig. 8.

J=0K=1

Qn -1 On

0

1

2=1K=0

From these exercises you wifound that the action of the J -K flip-flop can be controlled by the J and Kinputs, which act to force the outputto either 1 or 0 when the clock pulsearrives. The SET and RESET pins actindependently of the clock, making theoutput go to 0.or 1, and holding it thereuntil the reset or set voltage rises to 1again, when the next clock pulse willcause whatever output is forced by theJ and K voltages.

TogglingWith the power off, disconnect thewires from both J (pin 4) and K (pin16). Switch on again, and observe boththe output and the clock LEDs. Nowcomplete the truth table of Fig. 8 (c). Inthis arrangement the J -K flip-flop is act-ing as a divide -by -two stage, for there isone complete output pulse for each twocomplete input pulses - we say that theflip-flop is toggling. At any time duringthis action, the output may be forcedto 1 or 0 by the action of the SET orRESET pins, but it will revert to thetoggling action when the SET or RESETis released.

Try applying a clock pulse obtainedfrom a switch, as in Fig. 9 (a). Wire theswitch to the board and replace theconnection between the 7414 clockgenerator and the flip-flop with a con-nection from the switch output to theflip-flop clock input. Turn on the 5 Vsupply, and use the switch as a slowclock generator. You will probablyfind that the output is erratic, some-times seeming not to change the out-put when the switch is operated.

This is caused by switch contactbounce.

De -Bounce De SwitchWith power off, rewire the switch with aresistor and a capacitor to one of thespare sections of the 7414, as shown inFig. 9 (b). This is a simple de -bouncingcircuit.

Solder a resistor and an LED to theoutput of the 7414 in the usual way toshow the state of the clock pulse, andconnect the output also to the clockinput of the 7476. You should find thatthe action is perfect, and the very slowclocking which is now possible willshow that the changes which take placeat the output do so when the clockpulse goes low, that is, from 1 to 0.

on - 1 Qn

0

1

Fig 8. Rema ning tru h tables for J -K action

J=1K=1

on - 1 Qn

0

1


(a)

PUSH BUTTON// SWITCH

PUSH BUTTONSWITCH

TO CLOCKINPUT

TO CLOCKINPUT

Fig. 9. (a) Using a push-button switch as a clockpulse supply.(b) A debounced switch circuit.

Note that other flip-flop types may nothave the same sequence of actions.Some, for example, are edge triggered,meaning that all the flip-flop actiontakes place on the leading edge of theclock.

When you are using flip-flop circuits,you must be careful to use the sametype of flip-flop as that specified, sincecircuits which suit one type may notsuit another. In particular, the 7476"Master -Slave" type of flip-flop has aParticularly complex action.

In essence, the action is that on theleading edge of the clock, the infor-mation which is present (1 or 0) at theJ and K inputs is stored and once theclock pulse has reached its 1 value,these inputs are locked out, meaningthat changes in J and K will now haveno effect. At the trailing edge of theclock pulse, the flip-flop action takesplace to change the output. The reasonfor this construction is that severaltypes of circuits, some of which weshall build in this series, use feedback

Fig 10 Truth table for J -K flip-flop

(a Complete truth table

J-K FLIP-FLOP

connections between the output of theflip-flop and its J or K inputs.

If all the action of the flip-flophappened at the leading edge of theclock, such feedback would causeindeterminate action - any change inQ would cause a change in J or K,which might cancel the effect on Q,and the flip-flop would probablyoscillate at the high frequency. Becauseof the Master -Slave action, this does nothappen - the changes in Q happen atthe trailing edge of the clock pulse, bywhich time the J and K inputs arelocked out and their voltages cannotaffect the action until the leading edgeof the next clock pulse.

InvestigationYou should already have one sectionof the 7414 set up as a high frequencyoscillator with earphones, or similar, todetect the output note. What is theeffect of leading the output of the 7414oscillator to the clock terminal of the7476 with J = 1 and K = 1? Listen tothe output wave from Q and compareit with the signal from the oscillator.

Can you now design an "octave"oscillator? This circuit will use a singleoscillator, but its output will be alter-nately at oscillator frequency, then athalf oscillator frequency (one musicaloctave below) according to the input tothe gate. The gate input could then beobtained from another slow oscillator.

Finally, Fig. 10 (a) shows the com-plete truth table for the 7476. Fig. 10(b) shows a changes truth table, inwhich the settings of J and K to pro-duce certain changes (or non -changes)are listed. In the last table, X means"don't care", signifying that the valuemay be 1 or 0, and the action will bethe same. Check that this last tableagrees with the full table of Fig. 10 (a).

You may want to copy these tables,since we shall refer to them severaltimes in Part 5 of this series.

(b) Shortened truth table for changes only

INPUTS OUTPUT OUTPUTJ K Q BEFORE CLOCK Q AFTER CLOCK0 0 0 0

0 0 1 1

0 1 0 0

0 1' 1 0

1 0 0 1

1 0 1 1

't 1 0 1

1 1 1 0

J K en -1 on0 X 0 01 X 0 1

X 1 1 0X 0 1 1

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We have seen in this series howthe toggling action of a 7476J -K flip-flop, which' occurs

when J = 1 and K= 1, gives an outputpulse train at half the frequency of theinput clock pulses. We can use thisoutput as the clock pulse for a secondflip-flop, and we will make up a circuitto find the practical outcome of this.

Frequency Divider

With power to the board switched off,set up the first flip-flop as before withJ=1, K=1. Connect a wire link from pin15 (Q1) to pin 6 (CK 2), and attach a

resistor and LED in the usual way to pin11 (Q2) and a spare pad. This LED willindicate the state of the output of thesecond flip-flop whose J and K pins canbe left floating.

With power applied, the outputpulses from Q2 should now be at onequarter of the frequency of the oscill-ator so that this complete circuit is adivide -by -four, producing one completepulse at the output for each group offour complete clock pulses into pin 1.This is shown in the clock pulse diagramof Fig. 1(b).

With the supply disconnected again,connect up both halves of the second7476 as shown in Fig. 2, so that we nowhave four toggling flip-flops in sequence.

CLOCKIN

_t-_-L-Lr-u-CLocK

Q1

Q2

Fig. 1. Cascading 7476 J -K flip-flops.(a) Circuit.(b) Pulse diagram.

CLOCKIN

Connect a resistor and LED in the usualway onto the final Q output.

Can you predict what the countnumber of this circuit will be? (Thecount of a circuit is the number ofcomplete pulses in to give one completepulse out.) Using the slow clock pulsefrom the 7414 oscillator, count inputpulses for one complete output pulse (0to 1 to 0), and draw a clock pulsediagram.

Asynchronous Counters

The type of circuit described above is afrequency divider, with each stagedividing the clock frequency by two. Itcan also be thought of as a scale -of -twocounter, with a serial input and a

parallel binary output.Let us explain this.The pulses into the first clock input

need not be at a steady rate, so long aseach is separated from the next. This isa serial input - meaning one after theother. The output of each flip-flop canbe read, by means of an LED attachedto each Q output, for example, andsince all can be read together, this is aparallel set of outputs. Our counter,therefore, has serial input and paralleloutput.

More important, if we started puttingthe pulses into the input when theoutput of each flip-flop was zero (thecounter cleared, or reset), we could tellhow many pulses had appeared at theinput if we stopped counting at somestage.

If we label our flip-flops A, B, C, andD (Fig. 2), with A the flip-flop at the

Fig. 2. Fourcascaded flip-flopsformed from thetwo 7476s.

5

135

13

4

input and D at the other end of the line,then we could also label B as 2, C as 4,and D as 8. We are able to do thisbecause, starting at zero, QB will go to 1after two input pulses (and back to zeroon pulse number four), QC will go to 1after four input pulses (and back to zeroat eight), and QD will go to 1 after eightpulses, returning to zero at the sixteenth

pulse. We would expect, for example,that after seven pulses QD=O, QC=1,QB=1, and QA=1 because 4+2+1=7.

PULSES QA QB QC QD0 0 0 0 01 1 0 0 02 0 1 0 03 1 1 0 04 0 0 1 05 1 0 1 06 0 1 1 07 1 1 1 08 0 0 0 1

9 1 0 0 1

10 0 1 0 1

11 1 1 0 1

12 0 0 1 1

13 1 0 1 1

14 0 1 1 1

15 1 1 1 1

16 0 0 0 0

Fig. 3. Truth table for four cascaded flip-flops.

68ELECTRONICS CIRCUIT DESIGN - WINTER 1980

This circuit is a binary asynchronouscounter - binary because the countingis carried out in the scale of two insteadof the more familiar ten, and asyn-chronous because the flip-flops are

being clocked at different rates. Thetruth table of Fig. 3 shows the relationbetween the binary figures (the outputsfrom the Q terminals) and the numberof pulses in (using decimal figures).Note that this arrangement counts to15, and that all the flip-flops reset tozero on the sixteenth pulse.

Fig. 5. A scale -of -five counter.

CLOCKIN

Four -Stage Counter

Set up a four stage asynchronouscounter on your board with a resistorand LED to indicate the state of each Qoutput. Label the LEDs to avoid con-fusion - QD furthest from the pulseinput should be labelled 8, QC labelled4, QB labelled 2, and QA labelled 1.

Take the oscillator output through agate which can be controlled by a

switch, and connect the reset terminals(pins 3 and 8 of each 7476) to anotherswitch so that all the outputs can bereset to zero by pressing the switch toconnect the reset pins to the 0 V line.Now apply power and check that thecount sequence is as shown in the truthtable of Fig. 3 when the gating switch isON. Try switching the gate off andresetting.

Switch off the power and alter theconnections between flip-flops A, B, C

and D so that OA is connected to clockB, OB to clock C, and QC to clock D.Leave the LED indicators connected tothe Q outputs as before (Fig. 4). Nowswitch on, and start the count. What is

happening now?Could you, not necessarily using only

the ICs on the board, design a counterusing two 7476s which would counteither up to 15 and reset, or down tozero (resetting) according to the pos-ition of a single switch, or the voltage

on a gate? The number of gates neededmakes this impossible on our board.

Fig. 4. Cascading from the terminals - what does this counter do?

1/47400'

Interrupted Counts

We seldom want a counter which countsup to 15 and then resets to zero. We

may want a decimal counter (0 to 9 andthen reset to zero), or a counter whichstops at some definite count, or whichcounts to some number, resets to zeroand then stops. These operations can beachieved by using the J and K terminalsof the flip-flops together with gates.

Suppose, for example, that we wantto count up to four, reset to zero at thefifth pulse, and then start again. Whatwe need is some way of detecting theoutput at a count of five and using thisto operate a reset. Detecting a count offive is easy enough since it is whenQD=0, QC=1, QB=0, and QA=1. We candetect this by taking the Q outputs

from C and A and connecting themto the inputs of a NAND gate, as shownin Fig. 5. When QC=1 and QA=1, theoutput of the NAND gate will be zero.The simplest and most obvious way touse this is to connect the output of theNAND gate directly to the reset line ofthe flip-flops, replacing the reset switchwe used previously.

Set up this circuit on your board.Use wire connections from QC and OAto the inputs of one of the 7400 NANDgates, and disconnect the switch fromthe reset line. Now switch on, with theslow oscillator input to the flip-flop firstclock, and observe the count.

Can you now design a counter usingfour flip-flops which would reset at thetenth inward pulse? This will be a

scale -of -ten (decimal) counter. Re-

member that ten in the binary scale iswhen QD=1, QC=0, QB=1, and QA=0.If, for any reason we want to use aseparate switch -operated reset with thiscounter, we shall have to arrange aninput through either an OR gate or aNOR gate as shown in Fig. 6.

Fig. 6. Using a push-button reset with thecircuit of Fig. 5. This could be implementedin several other ways.

Fig. 7. A "ripple counter". This type of counter can suffer from "race hazards".

CLOCKIN

1t

0 WHEN Ani AND Hnl


CLOCKIN

J

A B

J J Q

C

1.70R

LED 'A

470R

LED '13'

1/4 7400

RESET

470R

LED 'C'

Mr/

Ruined By RippleFig. 8. What does this counter do? Build thecircuit on your blob -board and draw up atruth table.

We can use this gating system to con-struct asynchronous counters whichreset at the highest designed countnumber, but the system runs intoproblems with large count numbers andwith high speed operation. For example,

CLOCKthe first stage counter runs at the speed IN

of the input pulses, and if these pulsesare fast, then we may find "RaceHazards" - problems caused by thetime delay in each flip-flop.

To take an example, we may bedetecting the state 10000001. Now the1 on the flip-flop H (Fig. 7), called "TheMost Significant Figure", appeared justafter the count had been 01111111, and

Fig. 9. What does this circuit do? Try to findout in theory, and then build the circuit onthe blob -board.

if there is a time delay in the systemflip-flop A may have gone to zero, to 1and back to zero again before the clockpulse to flip-flop H has had time towork its way through all the stages inthe counter. This time delay, caused bythe need for a change to ripple throughall the flip-flops, gives us the name"Ripple Counter", and can causemiscounting at high speeds.

Leaving this problem aside for themoment, our simple asynchronouscounter has used the reset line for itsreset action. For other types of countinterruption we can make use of the Jand K terminals of the J -K flip-flop,which is why they are provided. Con-struct the circuit of Fig. 8 on yourboard. Can you predict what willhappen? Try it out and draw up a counttable.

Now try the circuit of Fig. 9. Canyou predict what will happen when thisis switched on? Try it and see if youwere correct.

Could you now design and try a

ripple counter which could start at anybinary number selected by switchesconnected to the SET terminals of theflip-flops, then count down, stopping atzero, but leaving the reset terminals freeto be used with a switch?

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Ripple counters are useful andsimple, but they are not ideal forhigh counting speeds, nor for

large counter chains. The problemarises from the use of the output of:each flip-flop as the clock for the nextfli-flop, so that changes must "ripplethrough" all the stages of the counter.This, as indicated in the previous sec-tion, causes difficulties with time de-lays.

Although these delays are notlarge, perhaps 60 nS or less per flip-flop, they accumulate to a significantamount over a large number ofcounter stages and can cause the.racehazards mentioned earlier.

Synchronous CountersA different principle is used forsynchronous counters. The inputpulses are used to clock each flip-flopof a chain, hence the name synchro-nous. The count sequence is thendetermined by voltages applied to theJ and K terminals, and these voltagesmust be obtained in such a way thatany given count on the flip-flop willcause the J and K voltages to be set tothe voltages needed to change to thenext digit up or down.

This is much more easily illustratedby an example which we can test onour board. In this example we shallfollow the pattern of design steps(with some modifications) which isusually used for synchronouscounters.

IN

LED B

FINAL VALUESJA=KA=1

JB=KB=QA

A B J K VALUES

COUNT Q PRESENT Q NEXT 0 PRESENT Q NEXT JA KA JB KB

0 0 1 0 0 1 X 0 X

1 1 0 0 1 X 1 1 X

2 0 1 1 1 1 X X 0

3 1 0 1 0 X 1 X 1

Fig. 1 (Above) A simple synchronous counter, no J -K connec-tions shown.

(a) Circuit. Note that the input clock is taken to each stage.(b) Table of changes, with J and K values for the changes.

Basic Two -StepLet us imagine a very basic counterusing two flip-flops and resetting atthe count of four. We must start by CLOCKmaking a table showing the count, the IN

present state, and the next state foreach flip-flop. This means that foreach number of the count we list thevalue of Q (1 or 0) and also the valueto which Q will change at the nextcount. For example, when the count is1 (01), the next count is 2 (10) andboth outputs will change -A from 1to 0, and B from 0 to 1. On the nextcount (3), A changes from 0 to 1, andB does not change. The completetable for two flip-flops is shown in Fig1(b).

o-RESET

470R

LED

Fig. 2 (Above). Complete two -stage synchronous counter circuit,with J -K connections shown. Try this out on your blob -board.


Now we have to decide what volt-ages are needed at J and K of eachflip-flop to carry out the changes frompresent state to next state. Here wehave some options - for example, ifwe want to change from 1 to 0, wemay have J =K= 1, or J = 0 and K= 1;either state will carry out the change.When this is possible, we can writeJ =X, K=1, where X means don'tcare, since either value of J is equallysuitable.

Add more columns to the table toindicate these values of J and K foreach flip-flop, and we are ready, tostart designing. The object now is toobtain the J and K voltages for eachflip-flop from somewhere else in thecircuit in such a way that all the J andK voltages are correct for each stageof the count. The formal method ofdoing this involves a technique calledKarnaugh mapping, but is seldomnecessary for only a few counterstages. It is rather difficult to apply fora large number of stages, so only the'intuitive' look -and -see method will bediscussed here.

Table TalkAt the zero count, Qa= 0, Qb= 0 andthe change at the end of the clockpulse will be from Qa =0 to Qa = 1.This will happen if Ja = 1 and forKa = 0, or Ka= 1 . We therefore fill in a1 in the Ja column, and an X (eithervalue) in the K column.

Still at the zero count, Qb = 0 anddoes not change at the end of theclock pulse. This can be done ifJb =0, Kb = X, so that these values 0and X appear in the Jb and Kb col-umns.

These columns are filled insimilarly for each change listed -remembering to use X in any casewhere a value is unimportant - usingthe J -K table that we used in Part 4 ofthis series of articles.

We can now inspect the compli-cated tables to see if any values can befixed or derived from values of Qa orQb. The tables for Ja and Ka are easilydealt with - since the values areeither 1 or X, we can use 1 for all thesevalues, and make Ja = 1, Ka = 1, asfor the ripple counter. The Jb, Kbtables are slightly more involved, butfor each definite value of one quantity(J or K) there is an X for the other, sothat we can again connect J and K.We then find that the values of J andK are identical to the values of Qa, sothat Jb and Kb can be connected toQa.

IN

J AND KCONNECTIONSTO BEDETERMINED 470 R

LED 'C'

COUNTPRESENTQA QB QC

NEXTQA QB QC JA KA JB KB

FIRSTJC KC

FINALJC KC

0 0 0 0 1 0 0 1 1 QA QA 0 X 0 01 1 0 0 0 1 0 1 1 QA QA 0 X 0 02 0 1 0 1 1 0 1 1 QA QA 0 X 0 03 110 001 11QAQA1X114 0 0 1 1 0 1 1 1 QA CIA X 0 0 05 1 0 1 0 1 1 1 1 QA QA X 0 0 06 0 1 1 1 1 1 1 1 QA QA X 0 0 07 1 1 1 0 0 0 1 1 QA QA X 1 1 1

JC=QA AND QBKC=JC

Fig. 3 (Above). A three -stage synchronous counter.Top: (a) Circuit, J and K connections still to be determined.Bottom: (b) Table of changes, showing how J and K values are

determined.The "first" Jc-Kc table shows possible values of Jc and Kc, the

"final " table shows the most convenient values to use.

For practical work on synchronouscounters it is useful to have a clockpulse line, and one of the spare lineson the board can be used. Connect upthe circuit as shown, with a slow clockpulse taken to each clock input, andwire connections linked from Qa to Jband Kb. Use LEDs as before to checkthe state of each flip-flop output.Connect a common reset line to eachflip-flop and to a switch so that thecounter can be reset. Switch on and,check that the count is correct andthat resetting to zero is possible.

Third Stage DevelopmentLet us now extend this to a third stage,building on what we have done be-fore. Once again we can build up atable of values of Q, J and K for eachstage, but we have made life easier forourselves by having done the twostage counter, so we can ignore theJa, Ka and Jb, Kb columns and con-centrate on the Jc, Kc column.

Using the same principles as be-fore, we fill in the values of J and Kwhich will be needed at each clockpulse or flip-flop, concentrating on thenecessary values, and putting an X

72 ELECTRONICS CIRCUIT DESIGN -- WINTER 1980

where the value is immaterial. Whenwe do this (Fig. 3b) we find two im-portant states. One is at the count of3, where Jc must change from 0 to 1;the other is at the count of 7 when Kcsimilarly changes from 0 to 1.

The change of Jc from 0 to 1 oc-curs when the count changes to 110so that we could use an AND gateconnected to Qa and Qb. The outputof this gate will be zero for any countup to 2 and then will be 1 at a count of3. It will change to zero again tobecome 1 at the count of 7, but thevalue of Jc is unimportant beyond thecount of 3 anyway.

Looking at Kc we find that theimportant value of 1 occurs at a countof seven when Jc may also be 1. Wecan therefore connect Jc and Kctogether and feed from an AND gatesupplied with Qa and Qb.

Third Stage On BoardMaking up a three -stage synchronouscounter on the circuit board needssome additional connections. Sincewe are not using AND gates, the gateused will have to be made up from aNAND gate and an inverter. As the7400 contains four two -input NANDgates and the 7414 contains six in-verters, one of which is used for theclock oscillations, there is no shortageof gates. We are working with a lowfrequency clock, so there should beno ill-effects caused by the number ofwires soldered across the board, but ahigh speed counter would have to bebuilt on a PCB designed for the pur-pose, using copper tracks on eachside and with decoupling capacitorsbetween +ve and -ve lines close toeach flip-flop.

Can you now go one step further todesign a four stage synchronouscounter and try it out on the board?

Twisted LogicA different type of synchronouscounter is shown in Fig. 5. This is aJohnson, or 'twisted -ring', counterand consists of four flip-flops con-nected so that the output of one drivesthe J and K inputs of the next. Threeof the connections are made up with Qto J and Q to K, but the feedbackconnection is made with Q to K and Qto J - hence the alternative name oftwisted -ring. Remembering that Q isalways the inverse of Q, can you planout the values of Q and Q for eachcounter? Use the table headings

IN

Fig. 4 (Above). The circuit of the three -stage synchronous counter.Try this out on your blob -board.

CLOCKIN

NO RESET LINE SHOWN

CLOCKJBQA

KBQA

JCQB

KCQB

JDQC

KCQC

KAQD

JAaD

0

1

2

3

45

6

7

shown in Fig. 5(b) and remember thatQa=Jb, Qb=Jc, Qc=Jd, Qd= Kaand so on.

A Johnson counter uses a com-pletely different count sequence fromconventional binary counters, and themaximum count number is twice thenumber of flip-flops. The counters aresynchronous, very easy to design andalso very simple to decode for usewith lamp indicators.

Build up the four stage (count of 8)Johnson counter of Fig. 5(c) on yourcircuit board and check that yourcalculations are correct.

Fig. 5. A Johnson counter of fourstages.

Top: (a) The circuit, note the"twisted ring" connection.

Bottom: (b) Table to complete sothat the counter action can be predict-ed.

Below: (c) Truth table. Build thecircuit on your blob -board and com-plete this table.

COUNT A B CD0

1

2

3

45

6

7



The 7490 decade counter is asingle -chip counter containingfour flip-flops and various

gates, which are arranged so thatfrequency division and decimal coun-ting can be carried out. To make thecounter more versatile, one flip-flop isseparately connected so that it can beindependently used as a scale -of -twocounter and the remaining three flop -flops are gates so that they act as ascale -of -five. The two sections of thecounter can be connected together indifferent ways, either as a divide -by -ten circuit, or as a decimal counterwith BCD outputs.

INA NC Oa QdrfinQb Qc

14 13 12 11 10 9 8

74 9 0

1 2 3 ,4 5 6 7

IN RO RO NC + R9 R9B (1) (2) (1) (2)

Figure 1. Pinout of 7490 Decade counter.

Twos Into TensBCD - meaning Binary -Coded -Decimal - is a form of binary codewhich is particularly useful if decimalnumbers have to be displayed. In a

t

1 1 0 1 0 1OVES

01101

CLOCKPULSESIN

CLOCKPULSESIN

BCD count, each figure of a decimalnumber is represented by its binaryequivalent, so that the number 85(decimal) becomes 1000 0101,binary 8 and binary 5. Although moreconvenient, because each BCD

ti

"uS

"They obviously met through a computer dating bureau"

Figure 2. Connections forfrequency division by ten- note that the symboldoes not show the truepin positions.Figure 3. Connections forBCD counting, with resetswitch. The reset pinmust be kept at logic zerofor counting, and taken tologic 1 for reset, so thatan inverter must be usedalong with the push-button switch.

Fi

A

G

dp DFigure 5. Arrangement of segments in aseven -segment display. The decimalpoint, which may be on the other side ofthe figure, is always energised separately,often from a range switch.

1B

IC

counter can then drive a display unit,this form is longer than a pure binarynumber (binary 85 = 1010101, onlyseven figures), and BCD numbers arenot so simple to add and subtract aspure binary numbers.

BCD in PracticeConnect the power supplies to the7490 with pin 10 to earth and pin 5to +5 V. Pins 2 and 7 should also be


CLOCKPULSESIN

IN Qa Ob Oc OctA

INRg

470R

ti

470R

tib

1.70R

GC 1

470R

Figure 4. A terminated count. At some stage in the count, the gate will forcethe counter to reset. When does this happen?

Number/Character a b c d a f 9---0 x x x x x x

2 x x - x -3 x x - x

4 x

5 a - a x6 a

7 x x x - - _ -8 x x x x z x x

9 a

010) a

1111 x x x x - - -u112) - a

51131 x x- x - a a

Etuo - - a x a a a

Blank 115) - - - - _ _ _

x - lit- - unlit

earthed for most of the experimentalwork in this section, although we mayuse pin 2 later for resetting to zero.Now connect LEDs and their limitingresistors, using the spare pads on theboard, to Qa on pin 12 and Qd on pin11. Connect the clock pulse from theslow oscillator to input A (pin 14) andby watching the clock LED and theLED connected to pin 12 (Qa), notethe action of this section of thecounter.

Switch off, transfer the clock pulseinput to input B on pin 1, and switchon again, watching the clock LED andthe Qd LED on pin 11. Note that thecounter will operate only if the resetpins are earthed. There are two pairsof reset pins, each pair being inputs toan AND gate which operates the reset.Pins 2 and 3 are the reset to zero pins,and earthing either of them enablesthe counter. If both are allowed to

A B C Dabb c d ef g

0 0 0 0 0 0 0 0 0 0 0 1

1 1 0 0 0 1 0 0 1 1 1 1

2 0 1 0 0 0 0 1 0 0 1 0

3 1 1 0 0 0 0 0 0 1 1 0

4 0 0 1 0 1 0 0 1 1 0 05 1 0 1 0 0 1 0 0 1 0 06 0 1 1 0 1 1 0 0 0 0 07 1 1 1 0 0 0 0 1 1 1 1

8 0 0 0 1 0 0 0 0 0 0 09 1 0 0 1 0 0 0 1 7 0 0

Figure 6 ( eft) Truth table for figure andcharacter displays.Figure 7 (above). Truth table for acommon -anode display, figures only.

float to logic 1, or are taken to logic 1,the counter resets to zero. Pins 6 and7 also act through an AND gate, butwith both high the reset is to BCD 9(1001) rather than to zero.

To use the 7490 as a frequencydivider (Fig. 2), we connect Qd (pin11) to INa (pin 14) and take the clockpulse to INb (pin 1). The output willappear at Qa, on pin 12, and the stateof this output is monitored by an LEDalready. Connect up the clock pulsefrom the slow oscillator on the board,and by counting pulses, confirm thatthe correct division ratio is beingobtained.

For a BCD count, the connectionsmust be changed around (Fig. 3). Wenow need LED indicators on the Qb(pin 9) and Qc (pin 8) outputs as well

as on Qa (pin 1 2) and Qd (pin 1 1), andthe cross -connections are different,

with Qa connected to input B and theclock inpUt taken to input A on pin 14.Label the LEDs as A, B, C, and D, andswitch on, noting the values at eachstage of the count. Use de -bouncedswitch as a clock supply if the oscilla-tor is too fast to follow. Note that inthe circuit of Fig. 3 a reset switch hasbeen used; because we are usingpush -to -make switches, an invertermust be used as shown.

Because the 7490 is on a singlechip it may be convenient to adapt itfor counts of less than 10, rather thanuse separate flip-flops. This is madeeasier by the arrangement of the resetlines, connected through AND gates.Ignoring the reset -to -nine pins, wecan arrange for pin 2 to be driven by agate whose output must be zeroduring the count, rising to 1 at the endof the count. Pin 3 must be kept high,or the count will not be interrupted.

Try the circuit of Fig. 4 - can youwork out what the count figure willbe? Connect up and try the circuit out.

DisplaysThough several other forms of dis-play exist, the most convenient typefor use with TTL circuits is the seven -segment LED display. The type usedfor this board, the BI-PAK DL747(Jumbo) is one of the largest displaysof this type available at the time ofwriting, and has been selected fromthe point of view of easy reading at adistance. If any other type is sub-stituted, care will have to be takenwith the pin connections, since thereare several pinout standards for thistype of display.

As the name suggests, the seven -segment display consists of sevenLEDs made in one chip in thearrangement of a figure -of -eight, asshown in Fig. 5. The letters allocatedto the strips are also shown (fortun-ately these are standardised).

Looking at the arrangement of thesegments, we can draw up a table ofthe segments that will have to beactivated (ON) for each number wewant to display. F;g. 6 shows such a

OUTPUTS

a b d e

16 15 14 13 12 11 10

74 47

1

2 3

5 67LAMP B/RB RB " "TEST IN/ ININPUTS1-1LIINPUTS

OUT

Figure 8. Pinout of 7447 BCD to 7 -segment decoder -driver.

ELECTRONICS CIRCUIT DESIGN -- WINTER 1 980 75

table for the numbers 0 to 9, and alsosome of the other characters whichcan be obtained. We now have totranslate this ON /OFF table intoterms of logic 1 and 0.

The next step depends on the typeof display that is being used - com-mon cathode or common anode. Asthe name suggests, the commoncathode display has all of the LEDcathodes connected together to logic0, and each anode must be taken tologic 1 to be illuminated. To preventexcessive current flowing - becausethe normal forward voltage across theLED is less than the +5 V of the logiccircuits - we must wire a limitingresistor in the connection to eachanode. We cannot use one singleresistor in the cathode lead, as thiswould cause the brightness of thedisplay to alter according to thenumber of segments lit.

The other possibility is to connectthe anodes of the LEDs together andtake the cathodes out to separatepins. In this common -anode type ofdisplay, the segments will be lit whentheir respective cathodes are at logiczero, and once again limiting resistorsmust be used between each cathodeand the TTL driving stage.

The type of display specified forthis board is a common anode type,with several of the pins on the displayconnected to the common anode.Only one of these pins need be con-nected to the 5V line.

DecodersTo obtain a decimal readout fromthe BCD output of the 7490 counter,a decoder stage is needed with thetruth table shown in Fig. 7.

The type used here is the 7447BCD -to -seven segment decoder/ -driver, which has output stages oftransistor collectors with no loads. Inthis eay, the combination of LED andlimiting resistor acts as load for thecollectors of the output transistors inthe 7447.

Care should be taken that the out-puts of a 7447 are never connecteddirectly to the +5 V line, as excessivecurrents could flow if the decoderwere operated.

In use, the segment output pins ofthe 7447 are connected through thelimiting resistors to the segment pinsof the display. The values of thelimiting resistors used will determinethe brightness of the display. For the7447 display we can use 150 R res-

istors, but 470R resistors have beenspecified on our board to ensure longlife and to cut down current con-sumption. If other displays are used,470R should also be suitable - ingeneral the small displays need lesscurrent, and so larger values oflimiting resistors should be used thanwith larger displays. If a commoncathode display, such as the MAN -3types, had been used, the 7448 de-coder would have been needed.

Now connect up the display andthe decoder on your board, noting theconnection diagram of Fig. 9. In the

SV

ALL RESISTORS1.70R

Figure 9. Connection of 7447 to display -not that the arrangement on the board istidy as the diagram would suggest!

prototype boards, the very small res-istors used for limiting could bepassed under the body of the display,so avoiding long paths around it. The+5 V supply is taken to pin 16 of the7447, and earth is taken pin 8. Theoutputs of the 7447, all on the sidefacing the display, and marked on thecircuit diagram with small letters, aretaken through the 470R limiters tothe correspondingly lettered pins ofthe display. The inputs indicated bythe capital letters A,B,C and D on pins1,2,7 and 6 of the 7447 are for theBCD input from a 7490 and should beconnected to the appropriate Q out-puts from the 7490 counter.

Testing and BlankingNote that pin 3 of the 7447 islabelled "lamp test."' Taking this pinto logic 0 illuminates all segments ofthe display irrespective of what stagethe count has reached, and is a usefulcheck on the operation of the display.For example, an operator can checkthat a steady display of 3 is not justa display with two segments faulty.

Pins 4 and 5 on the 7447 are forblanking, used mainly when the dis-play is one of a set, to suppress zerosoccuring before the first significantfigures and after the last one. Whenpin 4 is low, the display is blankedout, though counting is unaffected.

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76 ELECTRONICS CIRCUIT DESIGN -- WINTER 1980


Ashift register is a set of flip-flops, each of which can be setby its PRESET terminal to

store a 1 or 0, so that the completeset stores a "'word," (completenumber). For example, four flip-flopscould store numbers such as 0101,1000, 1101, and so on. In addition,we can apply clock pulses to all ofthe flip-flops and so cause the storednumbers to shift from one flip-flop tothe next in line on each clock pulse;several designs make this possible ineither direction (right -left shift).

Fig. 2 shows an example of this inaction. We start with the number1010 stored, so that LEDs on the Band D outputs will be lit. The input ofthe first flip-flop is connectedwith J = 0; K=1, so that at the clockpulse its Q output will change tozero. The two outputs of the firstflip-flop, however, are connected tothe J and K inputs of the next flip-flop in line (compare the Johnsoncounter, which is very simplyobtained from a shift register). WithJ =1 and K=0 on the second flip-flop, from the outputs of the first, theclock pulse will cause the output offlip-flop C to change from 0 to 1.

Similarly, with Jb=0, Kb= 1, flip-flop B is forced to change from 1 to0, and flip-flop A is forced to changefrom 0 to 1. The effect is as if a zerohad been forced in at the left-handside and has caused all of the storednumbers to shift one place along.

A Simple Shift RegisterUse the two 7476 J -K flip-flops(Fig. 2) on your blob -board to makeup a four -stage shift register. Con-nect the clock inputs to one of thespare pads of the blob -board, andrun a line from this pad to the output

0 =1 0=00- 0

0CLOCK PULSES IN

J 0C

0 =1 0=0

J 0B

(7)

CLOCK PULSE OD OC OB OA

0 1 0 1 0

1 0 1 0 1

2 0 0 1 0

3 0 0 0 1

4 0 0 0 0

J 0A

K

(a)

Fig 1. A shift register made up from J -K flip-flops. (a) Arrange-ment of the flip-flops. (b) Truth table, showing the effect ofclock pulses.

°CLOCK

J 0

CK 0

74 76

CK C

7476

CK

-CK A

IN

RESET

A

/77nm

Fig 2. Connections of 7476 flip-flop to form a shift register onthe 8 -IC Blob -board.

"Now you try and work out a problemwithout looking at the keyboard."


of the slow oscillator or the de -bounced switch. Blob short connec-ting wires from each Q output to thenext J input, and from each Q outputto the next K input. Blob a wire fromJa to the earth line, leaving Kafloating. Connect the reset pins to areset line (a spare blob -pad) and soto the reset switch so that pressingthe reset switch will earth the resetpins. Finish off by connecting LEDsand resistors so that the state of eachQ output can be read.

Now switch on. One or more ofthe LEDs may light, but can be ex-tinguished by using the reset switch.Now set up a number by using thepreset terminals. By temporarilybridging from each preset pin toearth, using a wire bridge, set two ofthe flip-flops to 1, preferably so that1010 is stored. Now apply clockpulses and observe what happens;this is easier to follow if the de -

bounced switch is used.Now switch off, and disconnect

Ja from earth. Connect Ja to Qd andKa to Qd. Switch on again, reset,and set to a display of 1010 again.Now apply clock pulses. What hap-pens? Can you see the possibleapplications for storing a sequenceof operations, such as a traffic lightssequence?

Types of Shift RegisterThe shift register made up using7476s can be used as a PISO orSIPO type. PISO means parallel in,serial out; the information is set upon each flip-flop, perhaps at thesame time, and is read out insequence, one digit for each clockpulse. In a SIPO shift register (serialin, parallel out), a number of clockpulses equal to the number of flip-flops is applied at the same time as avarying signal (0 or 1) applied at theinput J -K terminals, starting with anempty register. With the registerfilled, the voltages at the Q terminalscan be read (using LEDs for example)in parallel. Each type is important;we need numbers in parallel formoperations such as addition, but inserial form for transmitting down asingle wire, or for recording on tape.We can, of course, have SISO (serialin- serial out) and PIPO (parallel in -parallel out) shift registers, and a setof flip-flops can be arranged to act inany one of these ways.

The 7494 Shift RegisterThis has been chosen as oneexample (Fig. 3) of the very widevariety of shift registers that areavailable. Like most integrated shift

lA

SEAL MI 11111rakINPUT FP -

CLEAR

Note In operation. Clear, PI:11 and P82 terminals should be low.To clear all stages, take clear terminal to 1To enter, take one pre.entry terminal to 1

Fig 4. Schematic diagram of the 7494 shift register. Compare the number offlip-flops gates and inverters in this single chip with the number of packagesneeded to make this from 7400's and 7476's.

o --oPR2

o-oPRI

o ---oCLEAR

7414 SERIALENTRY

PRI74 94

LEAR

21

A BCDA BCD

0 1 0 1 0 1 1 0

2A PR2 28 2C /Tin 20 CLEAR 0/P

A 18 IC I 4. PRI SERIAL CLOCKINPUT

Fig. 3. Pinouts of the 7494

registers, it is constructed using theclocked S -R type of flip-flops, but theaction is the same as that of our J -Kflip-flop model; the schematic of theIC is shown in Fig. 4. Four flip-flopsare used, with a common clock toeach, and a clear input which willreset each flip-flop. A serial input isalso available.

The interesting feature of the7494, however, is the gated parallelinputs labelled 1 A, 2A, 1 B, 2B andso on. These act through a set ofgates on to the preset inputs of theflip-flops, so that they are indepen-dent of the clock pulses. The gatingis arranged so that either one or the

Fig 5. Connecting up the 7494 on theblob -board. Note that inverters have to beused on each switched line, as the presetand clear lines must be held at logic 0 fornormal operation.

other set of inputs can be "read"into the register. For example,imagine that the inputs with the 1

prefix are each connected to a signalinput, 0 or 1, and that the inputswith the prefix 2 are each connectedto another set of signals. We. can usethe pins marked preset 2 and preset1 .now to select which set of inputs ischosen and placed in the register.Imagine that preset 1 is at logic 1

and that preset 2 is at logic 0. Be-cause of the inverters connected tothe preset inputs, all the inputs withthe 1 prefix are gated through to theOR gates which control the flip-floppresets. Because all the inputs withthe 2 prefix are gated out, there willno input from these gates. Theopposite process takes place if pre-set 2 is at logic 1 and present 1 is atlogic 0. Note that these inputs mustbe operated so that both do not enterat the same time. The inputs shouldremain at logic zero during normaloperation.

The output from the register isfrom pin 9, and will consist of onebit, 0 or 1 for each clock pulse fed into the clock input, and at the leadingedge of the clock.


Blob -board WorkConnect the supply lines to the7494, +5 V to pin 5 and earth to pin12. Now blob a connecting wirefrom the output of the debouncedswitch to the clock input of the 7494on pin 8. Connect the preset 1 pin(pin 6) to an inverter whose input isfrom a push-button switch so thatthis pin can be momentarily set to 1;leave the other preset entry pin (pin15) earthed. Now set up signals toenter on the 1 -set of inputs, A, B, C,D on pins .1, 2, 3 and 4. Forexample, we can connect pins 1 and3 to logic 1, and pins 2 and 4 to logic0, so setting up the number 1010.This will be entered when the Pr1pin is momentarily set to 1 by theinverter and switch, and the flip-flops will be set up to the number1010.

Detector Work

We can detect this only at theoutput, (since we cannot connect tothe Q outputs of the intermediateflip-flops) by connecting an LED andlimiting resistor to the output pin,pin 9. Now blob a connection fromthe serial input, pin 7, to earth, sothat as each clock pulse arrives azero is fed into the first stage of theregister. This ensures that the reg-ister stores 0000 after four clockpulses.

One ClockNow switch on, and press theenter switch briefly. Use the clockswitch to apply four clock pulses,

and note the output on each pulse.The contents of the register shouldnow be 0000, so that further clockpulses will not produce any "1"output. Another entry can be madeby pressing the entry switch at anytime. By connecting the second setof entry pins, and using the secondpre -enter (Pr2) pin, we can enteranother number. Connect up thesecond set of entry pins (16, 14, 13,11) to give another number, andconnect up the Pr2 (pin 1 5) terminalto the output of another spare in-verter. Connect another push-buttonswitch between the inverter inputand the earth line, and try out thecircuit again, entering the secondnumber (after clearing) by pressingthe enter switch momentarily. Checkthat this number is then read out atthe output when the register isclocked.

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ELECTRONICS CIRCUIT DESIGN -- WINTER 1980

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Arithmetic Unitsso far, the work which we havecarried out on ther blob -boardhas covered gating, flip-flops, BO

counter and display stages and theuse of a register. Within the limita-tions of 8 IC's, we cannot, of course,hope to cover every possible prin-ciple of digital electronics, and theIC's which were selected for theboard were designed to reflect theapplications of digital electronicsmost often seen in publishedcircuits.

The two important topics ofarithmetic and memory have notbeen specifically mentioned, partlybecause small projects seldom needarithmetic or memory (and largeprojects can make use of the moreflexible facilities of a microprocesser,particularly if this incorporates amemory) and partly because thebuilding blocks of arithmetic units(gates) and some types of memory(flip-flop) have been covered.

Nevertheless, in this last part weshall look at some Of the circuitry wehave not covered previously, andalso at some systems which can betried out in the board. In addition, itis useful to note that the board cannow act as a very useful intermediateunit for experimental work on moreadvanced systems, since it can pro-vide up to six clock oscillators, fourflip-flops, four NAND gates, oneregister, and a complete circuit -and-

display for one set of BCD digits.

AddingBinary addition can be serial orparallel, of which parallel addition ismore common. The half adder hasthe truth table in Fig. 1 and is usedfor the least significant digits of twonumbers. Its output will be the sum(the digit which will appear in the

AO

HA

AO BO SO CO

o 0 0 oo 1 1 01 0 1 0

1 1 0 1

SO

CO

Fig 1. Half -adder symbol and truth table.

Al

B1

CO

FASi

C1

Al B1 CO S1 Cl0 0 0 0 01 0 0 1 00 1 0 1 01 1 0 0 1

0 0 1 1 01 0 1 0 1

o 1 1 0 1

1 1 1 1 1

Fig. 2. Full adder symbol and truth table.

final figure) and the carry which willbe added to the next significant fig-ure. The full adder circuit is used forall the next stages of the adder unitand has three inputs and two out-puts; its truth table is shown in Fig.2. The inputs to the full adder are thetwo digits A,, B,, and the carry Cofrom the previous half -adder stage.The outputs once again are the sumand another carry C, which is takento the next stage. The total numberof adding stages which will be ne-eded must equal at least the totalnumber of binary digits in the sum ofthe numbers.

Half -adders Sand full adders canbe made up using gates (Fig. 3) butonce the principles have beenchecked it is easier to use IC's madefor the job. The 7482 is a two bit fulladder, whose internal circuitry, withtruth tables, is shown in Fig. 4. Fromthe diagram, we can see that theinputs are Co from the previoushalf -adder (which would be either anintegrated full adder with no carryinput, or made up from gates) andthe second significant digits A, andB,. The sum of this stage is obtainedat the terminal marked S1, and thecarry is internally connected into thesecond stage of the adder, whoseinputs are B2 and A, with outputssum S2 and carry C2. The next stepup is the 7483, which is a four -bitadder and any requirements greaterthan this is dealt with by arithmeticunits of much greater complexity.

In general, if more than a simpleaddition is needed, it is moreeconomic to use LSI arithmeticunits.Memories

Memory units which are used indigital work come in severalvarieties. One class of memory is thevolatile memory, based on flip-flops,which is cleared wherever power isswitched off; this type could be used

80ELECTRONICS CIRCUIT DESIGN -- WINTER 1980

in pocket calculators. Non-volatilememories are the types using pre-setregisters (such as read-onlymemories or ROMs) or which usemagnetic tapes or cores or othertypes of storage which are noterased when power is switched off.A simple type of volatile memory is aSISO shift register with its outputconnected back to its input so thatthe information is read back in afterone complete set of clock pulses;this type of memory can only deliverits contents in the order in whichthey are stored. If the register has

parallel outputs with gates, how-ever, it becomes possible to findwhich digit (0 to 1) is stored in eachflip-flop, so that, in the language ofcomputing, random access is pos-sible. This is a simple random accessmemory (RAM).

At this point it is worth pointingout that most memories in generaluse permit random access. The typeof memories which we refer to asRAM are random access memorieswhich can be written as well as readwhen suitable inputs are applied.

CO

Al

81

(b)Al 82-

C1HA81

CO A2-HASi

Fig. 3. Above: Adders (a) Half -adder circuit, using NAND -gatesand inverters. (b) Full adder, using half adders and OR -gate.

Fig. 4. Right: (a) Schematic of 7482 two-bit full adder. Noteagain the advantages of medium scale integration. (b) Truthtable.

Fig. 5. Below: SISO shift register connected as a memory - theinformation must be read out in serial form.

A B C

oCLOCK

OUT

(a)

They should properly be called ran-dom access read /write memories.Read only memories are usually alsorandom access, but the informationwhich is stored has been put thereeither by the manufacturer (in thedesign stage) or by the user (as withPROM) when the memory is firstused. In the older types of PROM,using fusible links, the memory can-not be altered once programmed,except by fusing a few more links.The more modern UV erasablePROM's permit complete erasureand re -programming.

))

))

(b)

)

TRUTH TABLE

Si

S2

C2

INPUTS OUTPUTSco=o CO = 1

Al 61 A2 B2 S1 S2 C2 S1 S2 C2

0 0 0 0 0 0 0 1 0 0

1 0 0 0 1 0 0 0 1 0

0 1 0 0 1 0 0 0 1 0

1 1 0 0 0 1 0 1 1 0

0 0 1 0 0 1 0 1 1 0

1 0 1 0 0 1 0 1 1 0

0 1 1 0 1 1 0 0 0 1

1 1 1 0 0 0 1 1 0 1_

0 0 0 1 0 1 0 1 1 0

1 0 0 1 1 1 0 0 0 1

0 1 0 1 1 1 0 0 0 1

1 1 0 1 0 0 1 1 0 1

0 0 1 1 0 0 1 1 0 1

1 0 1 1 1 0 1 0 1 1

0 1 1 1 1 0 1 0 1 1

1 1 1 1 0 1 1 1 1 1


D1 02 D3 04 AO AI A2 A3 CS ON1

OFF

ONSET A OFF

A0 AI A2 A3AMBER 1

ON

OFFI IGREEN 1

ONOFFRED 2

SET B AMBER 2ON

OFF

ON

I/O 16, 4 RAMGREEN 2 i OFF

YY 03 04

CLOCK

MEASURE/BLANK

HOLD

RAM and AddressFor either type of memory, the in-puts will consist of address lineswhich locate positions in thememory. We can think of these ad-dress lines as grid lines on a map,with each pair of crossing lineslocating a point. When a point isaddressed by voltages on the lineswhich 'cross' at the point, then theoutput will be the digit, 0 or 1,stored at that point.

As an example of addressing,Fig. 6 shows the arrangement of the7489 RAM which is a 64 bitmemory which uses four rows of 16columns of storage. The rows areaddressed by the inputs D,, D2, D3,D4, so that a four bit word can beread into each of sixteen columns.The columns are addressed by an-other four -bit word which is decoded(1011=column 11;0110= column.6) by a decoder stage which thendrives the column.

To write, a four -bit word is placedon the D inputs, and the write gate is

RESET/BLANK

DETECTOR A

DETECTOR

LOGIC

LIGHTS A DETECTOR GA ,;',1`.74GVEIrrW17.7.CAUSE SWITCHING SO THAT SET LACONTROLS LICHT 2, AND SET 0 CON-TROLS LIGHT 1 A COUNT OF THREE

LIGHTS B ?1:011I'LLTWAHW:WITrIVRTInONSET A

Fig. 6. Above left: 7489 RAM schematic, showing addressingsystem for 16 4 -bit words.

Fig. 7. Below left: Pulses for frequency meter. During themeasure/blank cycle, the input frequency being measured isgated to the counter, but the display is blanked out. During thehold cycle, the display is on, showing the count, but the displayis blanked out. During the hold cycle, the display is on, showingthe count, but the input frequency is gated out, so that thereading is steady. On the reset/ blank cycle, the counter is resetand the display is blanked. If the repetition rate is more than50 Hz or so, there is no flicker.

Fig. 9. Above: Priority traffic lights problem. This scheme givespriority (long term period) to the longer line of traffic, asmeasured by the pulses from the detector pads.

activated, with the appropriate col-umn slected by A0-A3. To read, nosignal is present on the D lines, andselection of a column places a four -bit word on the output Q1 -Q4.

Suggestions for Future BoardWorkFigure 7 shows the sequence ofpulses which are needed by afrequency meter. The system here isthat pulses are counted for one unit,count is held on display, thencleared so that the system can becleared for another (updating) count.The ICs on the board enable you totry this system out for one digit ofcounter.

Figure 8 shows the pinout of the74141 BCD -decimal decoder. ThisIC, not used on our board, can beconnected to the BCD output of the7490 and will give outputs on tenpins, according to the state of thecount. The active state isrepresented by a zero output on apin, so that a zero output on the '7'

OUTPUTS OUTPUTS

'0"1' '5"4' GND '6"7"3"

D + C

OUTPUTS INPUTS INPUTS OUTPUT

Fig. 8. Pinout of the 74141 BCD -Decimaldecoder.

pin (pin 10) represents a count of 7,and so on. Using this, could youdesign a ten -note jingle player?

Finally, Fig. 9 shows the opera.tion of priority traffic lights. Theselights operate with a longer redphase on one set than on the other,but this can be reversed if more thanthree vehicles cross a detector stripduring the long red period on one setof lights. This scheme needs a clockpulse, counters, register and gates,could you make one?


GAIN CONTROLTim Orr takes a detailed look at how gain can be controlled by another electronicsignal, be it squarewave, sinewave or voice signal. This leads to some interestingcircuits - from ducks to filters!

There are many cases in signal processing where thecontrol of the gain is necessary. Some commonexamples are automatic volume controls in cassette

recorders and in the IF sections of radio receivers. Also inprofessional audio equipment there is a whole range ofcompressor, expander, limiter and noise gate deviceswhich find great use in recording and broadcast studios.Maybe you have wondered how the volume of the musicdrops when the DJ starts to talk and then fades up over upagain when he stops. This process, known as voice over or"ducking"' uses voltage control of gain.

Noise reduction systems such as Dolby and dBXemploy voltage controlled amplifiers. Synthesisers andsound processors obtain effects such as ring modula-tion, automatic panning, frequency shifting, dynamicfiltering, tremolo and envelope shaping also by the useof this technique.

Gaining gainThere is a wide variety of methods which can be used toobtain the gain control. This can be anything fromconstructing the variable gain element yourself frombasic parts, to buying an IC or module designedspecifically to solve your particular problem. Generally thesolution is some sort of compromise, because unfortun-

Fig. 1

INPUTS

A

B

MULTIPLIER

OUTPUT(AxBxk)

k 15 a constant

4

PRODUCT OF A 8. BLIES WITHIN Ti-4IS AREA

ately the problem of making high performance controlledgain cells (multipliers), is rather difficult and therefore theIC's tend to be rather expensive.

However with a bit of care a cost effective solution canusually be produced.

A good example is the AGC in a transistor radio. Thetransistors in the IF section have an hie that varies widelywith the magnitude of their collector current. Thus, bysticking three transistors in series it is possible to varytheir overall gain by about 40 dB, (x100), merely bycontrolling their collector currents. The AGC stops theaudio output of the radio from varying as the radioreception conditions alter..

Electronic multipliersWhen it is required to control the level of one signal withthat of another, an electronic multiplier is used. Thisprocess is analogous to arithmetic multiplication. If inputA is positive, Fig. 1 , and input B is positive then theproduct (the output), will also be positive. If A goesnegative then (he product will be negative. If both A andB are negative then the product will be positive thuspreserving the arithmetic rules.

If A and B are limited to be only one sign each then

Fig. 2+VCC

INVERTINGINPUT

CURRENTMIRRORS

-VccLeft: the princ"ple behind electronic multipliers. The graphshows the possible outputs for a variety of combinations of inputpolarities.Above: Internal workings of a CA3080, an Operational Tran-conductance Amplifier. Say that too fast and you'll need a newset of teeth.


the multiplier is known as a one quadrant multiplier.That is the product can only lie in one quadrant. If A canbe both +ve and -ve, and B only of one sign then themultiplier is known as a two quadrant multiplier. This iswhat is called an amplitude modulator. The audio signalwhich is bipolar is A and the control voltage is B.

If A and B can be both +ve and -ve, the product canlie anywhere in the four quadrants and hence themultiplier is known as a four quadrant multiplier. Thistype of device is found in frequency shifters and ringmodulators.

CA3080 - An OTA!The CA3080 is a two quadrant multiplier, or to give it itsfull title, it is an Operational TransconductanceAmplifier. It has a differential input and a single quad-rant current input known as !ABC, (amplifier bias current),Fig. 2. The differential transistor pair is used to steer theI ABc current between the two transistors Ql, Q2. There is

a region where the input differential voltage is linearlyproportional to the percentage of current steered betweenthe two transistors. This voltage region is fairly small,being about 20mV, but using the CA3080 in this areathen a reasonably linear 2 quadrant multiplier can beobtained.

What has happened is the I ABC current has beenmultiplied by the input voltage. The product is thedifference between the two collector currents. Thisdifference is extracted by the use of mirrors, currentmirrors that is. The current mirrors can be attached toeither the +ve or the -ve supply rail.

They have two terminals, and whatever current flowsinto one terminal, then the same flows into the other,which is why they are called mirrors.

What we want to do is take the difference betweenthe collector currents of Q1 and Q2, 1,1 is reflected frommirror Y and then from mirror X and then appears at theoutput. IC, is reflected from mirror Z and then appearsat the output. The two currents are subtracted fromeach other and the output current is thus (Ic2-1c,),which is the product of !ABC x V,, x K, where K is a,constant. Note that the I, current is also reflected froma current mirror on the negative rail.

The CA3080 is a low cost two quadrant multiplierand can be used to perform a wide variety of multiplica-tion functions. The linearity of the device holds true forI ABC variations of over three decades. When using thisdevice keep 'ABC below 0.5 mA.

VCA Using CA3046 Array

V CONTROL

100k

14

12 01

T47k

220n

AUDIOINPUT±5V

IC1

47k

47k10/0

47k

03 043

22k

100k10/0

1EE

68k

IC2

33k

+15V

-15V

OUTPUT

NOTE01-5 TRANSISTORARRAY are CA3046IC1,2 are 741D1 is IN4148

The CA3046 is an array of 5 transistors which are all wellmatched and relatively cheap. Q3, 4 forms the differentialtransistor pair, IC1 controls the current and IC2 extracts thedifferential output current and turns it into an output voltage.The audio input is inserted into the base of Q3 but alsoconnected to this node is the emitter of Q2. Q2 and Q5 serve to

predistort the input signal, but they distort the signal theopposite way to which the multiplier distorts it. This is known asdistortion cancelling, and it allows a larger signal level to beapplied to the multiplier for the same percentage of distortion atthe output. The larger input signal allows a higher signal to noiseratio to be obtained. Transistor 01 is used to bias the bases ofQ2, 5 to a suitable operating region.

Stereo Voice Over (Ducking)

Circuit for Disco Unit

The circuit operation is as follows. The microphone signalcomes via RV1.This pot sets the sensitivity of the circuit to themicrophone signal. If it is too sensitive the unit will be 'ducking'every time the DJ breathes. IC5 is an amplifier and filter. Thefilter has been specifically tailored to fit the characteristics ofspeech, thus making the ducking unit less sensitive to spuriousnoise. IC2, 3 forms a precision full wave rectifier, the output ofwhich is low pass filtered and then fed to IC4. This wave form isthe envelope of the microphone input signal.

IC4 is a peak, negative going, voltage detector with a gain of x5. When the DJ begins to speak, IC4 goes negative and in doingso pulls the base of 01 negative. When the DJ stops speakingthe base of 01 rises back towards 0 V with a time constantdetermined by CA or CA + CB.

This is the release time and it controls the speed with whichthe faded down music comes back to full volume. Q1 is anemitter follower and is job is to rob current from the gain cells inthe NE570.

This current sets the volume of the two music channels. Whenthe base of 01 is pulled down to the negative rail, the amount ofrobbed current is maximum, and when no current flows into pins1 and 16 of the NE570 and all of it flows into 01, then both musicchannels are turned off.

To set up PR1, put a large signal into the microphone channel,set RV2 so that it is a short circuit and then adjust PR1 so that thetwo music channels just close off. PR2 and PR 3 should beadjusted so that pins 7 and 10 of the NE570 are both +6 V.


MIC.SIGNALINPUT(1Vpp)

RV1

10klog

LEFTMUSICINPUT( 1 Vpp)

RIGHTMUSICINPUT(1Vpp)

220n 47k

22n( 3 50 Hz)

//7//THRESHOLDSENSITIVITY

220n 22k

f/J//

+12V

22k

PR1 10k

+12V

100k PR2100k

220n 33p DC BIAS

Ham'1u0.-- -II- 7

47k

3r

--AA--

100n

2

AG

5

/71;CR

tR6+

CRT

///// 100n_L

A D4154.

220n

/7777

/T/22k 14+__AG

Vref

ICI

Vref

- -12 -- 1047k

33p

I I

2700 (3kHz)

220k

22k IC5

NOTE

IC1 IS NE570IC2,3.4,5 ARE 741ALL DIODES 1N414801 IS BC212

GAIN

+20dB

-DI

2u2

13 +12VVcc

GND//)//

_ _J 2u2

100k

100k

1 LEFT OUTPUT

11 RIGHT OUTPUT

PR3100kDC BIAS

47k

ANN100k

OP AMP POWERED FROM ±12V

350Hz 3kHz FREQUENCY

/7r/7

100k

2V7

00 dB

DUCKINGLEVEL

-6dB

RV2

22klin

OV

oi)-s-s-/IIIIg17.:4VELOPE

CB MI1.1.1u0

/7J//

D3

CW

CCW

27k

01

CA220n -12V

SWITCH CLOSEDSLOW RELEASE


Track and HoldIn this example the CA3080 is used as a current controlledswitch. When the control voltage is high, 'ABC is maximum, (0.44mA) and the OTA gain is maximum. The voltage at pin 2 of IC1adjusts itself so that it is the same as that on pin 3, this being dueto the 100 per cent feedback via the high input impedance

-+ 5V (or TTL10k SIGNAL)

- - OV CONTROLNOTEIC1 is CA3080IC2 is CA3101 is BC212

voltage follower 1C2. When the control voltage is OV, 'ABC is zeroand hence the gain of the OTA is zero. Therefore no currentcomes out of its output and so the voltage at the output of IC2remains frozen (Hold mode). The maximum differential inputvoltage is 5 V and this must not be exceeded. The capacitor Cshould be selected to suit the speed of the operation.

Vin

V CONTROL

V OUt

HOLD HOLD

yin 1u0

2u2

/4771H -

15k 15k

r

/I/1u0

V ref

Clever Fuzz Box

2u2

8k2 18k

14

AG

IC1a _ __J 2u2LG1iT-Vcc 4 ND

M/77+12V /7777

'41M

18k

18k

18k

1u0

IC2

\--POWEREDFROM OV8.12V

14- - -15n - -

AG

IC1b

330p

24\7/Ic

12-

Vref

Fuzz boxes are used by guitarists to produce harmonic distortionand sustain. If you want to produce only the distortion, butretain the original envelope of the signal then this is the circuitfor you.

IC1 is a 2:1 compressor as described previously. This pro-duces a relatively high level signal which then drives IC2, whichis a x 50 amplifier with diode clamping. 1C2 produces thedistorted (fuzz) found. This is then fed into the IC3 gain cell, the

10

output of which drives the op amp. This gain cell is driven by therectified original signal (low pass filtered at 1k5 Hz), so that thedistorted sound is given the envelope characteristics of theoriginal sound.

If a fuzz sustain sound is required rather than a dynamic fuzzthen 1C3 could be modified (by the inclusion o' a clamped highgain amplifier driving pin 15) so that it acts as a low levelexpander. This will squelch the noise at the end of the fuzzperiod.


Four Quadrant MultiplicationRA

15k

100R

39kV y -VW

100k

100kDC OFFSET

( Vy REJECTION)

Vx

100k

NOTE

iCi is CA3080IC2 is 741

111411f1.111,!.p.1

1 Ya i

Vy

OUTPUT

Vx.Vy

0 VoutBy using a few circuit tricks, the CA3080 can be made toperform 4 quadrant multiplication. In fact the CA3080 performs2 quadrant multiplication and the trick is to move the axis on themultiplying graph. If we ignore the RA resistor chain then wehave a 2 quadrant multiplier circuit similar to that shownpreviously. Imagine that V, is a 1 kHz sine wave 1 Vptp and V, isat OV. The output of IC2 is a sine wave of fixed amplitude. Nowif we connect RA, and adjust the balance control, it will bepossible to cancel out the output, because the signal comingfrom ICI is out of phase with that from the RA resistor chain. Sowith V, set at 0 V there is no output for IC2. If V, goes + ve, theoutput of IC1 will become greater than the current via the RAchain and the output of IC2 will grow.

If V. goes-ye the current through the RA chain will exceedthat from IC1 and the output of IC2 will grow, the phase beingopposite to that when V was a sinewave from an oscillator, thenthis circuit could be used to generate ring modulation effects.

When V. is set to OV there may be some V, breakthrough andthis can be minimised by adjusting the V, rejection preset.

OUTPUT

yin

Ox -6V1 E +6V

A BCOGAIN1 0 0 0 OdB

0 1 0 0 -6dB

0 0 1 0 -12dB

0 0 0 1 -18d0

POWERED BY ±6VNOTEICI is 4016IC2 is 741

Vout

Voltage Controlled [Switched) Attenuator

The CD4016 is a quad analogue transmission gate. That is, it is aquad voltage controlled switch. When the control is high theswitch is ON, having an effective resistance of about 400R.When the control is low the switch is off and it looks like a100M resistor. Thus by using 4016 switches it is possible to'Switch' the voltage gain of an amplifier. The resistors in thisexample are selected to give 6 dB changes in gain.

10k

10n

FilterA state variable filter produces three outputs: highpass, band-pass, and lowpass. It is thus a very versatile filter structure, evenmore so if the resonant frequency can be varied. This frequencyis linearly proportional to the gain of the two integrators in thefilter. Two CA3080's, (IC2, 4) have been used to provide thevariable gain, the resonant frequency being proportional to thecurrent IA. Using 741 op amps for IC3 a control range of 100to 1, (resonant frequency) can be obtained. If CA3140's are usedinstead of 741's then this range can be extended to nearly10,000 to 1.

10n

10 LP

NOTE

IC1,3,5 are 741IC2,4 are CA3080

CONTROLS FREQUENCY


Markspace Modulated Universal Filter

10k

10kINPUTINPUT

IC1

-0 -

10k

MARK /SPACE7iRATIO

ifilf50%

I 0"/OV

+3V (V ref )

OV

820p

IC7

/HI/

10 kM

470R

RQ

IC 5a

HP

10k

/7777

10n

IC2 IC5b

10k

ALL OP AMPSPOWERED FROM ±6V

+ 3VV CONTROL

2k7

2 k 7

1.46kHz

RESONANTFREOUENCYORFILTER

-*BP

MARK/SPACEMODULATION

10k

C

10n

IC3

NOTEALL OP AMPS ARE 741OR 141 RC4136IC5a,b ARE 1/4 4016IC6 IS LM339IC7 IS CA3140Fo MAX = 1.4 6 kHz

10k0 20RO

OUTPUTS BP, LP, HPD1, D2 ARE 1N4148

LP

0HzOV

+Vcc (+6V)

+3VVref

10n

47k

IC6a

106

4 k7

D1

+Vcc

4k7

D2

+ 3VV CONTROL

20 k Hz TRIANGLEIt is possible to change the gain of an amplifier by effectivelyaltering the input resistor. This can be done by markspacemodulating a voltage controlled switch in series with theresistor.

When the markspace ratio is low, the switch is OFF most ofthe time and the effective resistance is large. When themarkspace ratio is high the switch is ON most of the time and theeffective resistance approaches that of the series resistor.

Having generated a mark space control waveform, it ispossible to gang up together literally hundreds of voltagecontrolled switches. This enables large numbers of variables tobe simultaneously changed.

The circuit is a markspace modulated universal filter IC1-5 andthe markspace generator itself IC6-7.

IC6-7 forms a triangle square wave oscillator. IC7 is anintegrator whose output ramps up and down between OV and a+ 3 V reference. IC6a,b,c are all fast comparators. IC6a, 6b detect

V CONTRO L 0-.1-3V

4k7 +Vcc (+6V,

1100n

I /7)77

100n

T-Vcc (-6V)

CA3140 & LM339POWERED FROM Vcc

+Vcc

4 k7

when the integrator output reaches 3V and OV respectively. Theoutputs of IC6a, 6b are used to flip over a schmitt trigger IC6c,which then drives the integrator. Thus the integrator output rampsup and down between OV and +3 V at a rate of 20 kHz.

It is important that the frequency of the markspace oscillatorbe relatively high. As a rule of thumb it should be 21/2 times thehighest frequency components of the signals that you hope toprocess. The triangle output is fed into IC6d's inverting input,the control voltage into the non inverting input. The output ofIC6d is the markspace modulation which is used to drive theswitches IC5a, b. The filter resonant frequency is directlyproportional to the mark space ratio that drives these switches.

The LM339 is a quad package, and so is the 4016 andso can be the op amps (use RC4136). Thus the whole circuitcan be realised with only 4 IC's. Also the mark space oscillatorcan be used to drive other independent comparators.


Two Channel Low Level Expander/Noise Gate

NOTE

1C1 IS 1'2 NE570

1C2 IS CA3140D1,D2 ARE 1N4148

56k+12V

THRESHOLD RA jRB

-36dBM(33mVpp) I 30

-46dBM(10mvpp) h100-56 dBM(3.3mVp'p) 300

WWI01111.

\--(POWERED FROM OV 812V)

EFFECT OFVARYINGRA /RB RATIO

2:1 SLOPE

1:1 SLOPE

THRESHO

DECREASING RC(RC=10M) (RC 100k)

It is often required that a rather noisy signal be cleaned up a bit.This is not possible to do continuously, but it is possible to cleanup noise in what was initially the gaps. The results of thiscleaning up process can quite often be heard when telephoneconversations from "foreign correspondents" are broadcast.

By turning down the signal level in the gaps, (by performing alow level expansion) the perceived sound quality improvesdramatically.

The circuit performs just such an expansion. The input signalpasses through the variable gain cell and then appears at the opamp output. The gain of the gain cell is controlled by the signalcoming from IC2. This is a high gain amplifier with diodeclamping, so that the output swing is limited to about 1 VO ptp.Therefore for input signals of 10 mV pp to 10 V pp, the output of1C2 remains at about IVO ptp to 1V2 ptp.

So, for this range of input voltages the gain of the gain cellremains roughtly static. Now when the input level drops below10mV, the output of IC2 will start to fall and so will the gain ofthe gain cell. This produces a 2:1 downwards expansion curve,which means that the output then gets quieter at a rate fasterthan the input. To accentuate this effect, a bleed resistor canbe placed in parallel with Cr.

The resistor robs some of the current that would haveotherwise gone to the gain cell and causes the input output curveto roll off much more rapdily at low signal levels. Also, by varyingthe resistor ratio of RA / RB, the expansion threshold level can bealtered.

22k THD TRIM

THD

- TRIM

3(14)+-VVV"

8(9)

AG

22k

V\Ar33p

22k*-V\A/L---1

/1/1/I

6(11) 5 (12)

_____205)V ref

I C 1

1

IOP

L_.1 (16) 4 GND 13 Vcc

t____, Cr /7777

2u2

/7777

N

+10OUTPUTLEVEL 0

10

20

- 30

-40

50

60dBM 70

7(10).OUTPUT

TuO 10

100k

+12V

-70-60-50-40-30-20-10 0 +10dBM INPUT

LEVEL

Incredibly Simple Compressor

Not all gain control systems need be complicated or indeedactive. One product which I saw advertised was a compressor tohelp prevent loudspeaker overloads. All it was was a lightbulb inseries with the loudspeaker. When the power exceeds a certainlevel, the lamp will turn on, glow, its resistance increasesdramatically and hence a bigger percentage of the power output isdissipated in the lamp. A nice, simple solution, but I think it wouldrequire some experimentation to find the right sort of carheadlamp bulb!

LIGHTBULB

cr)

0Ce cc

W'4

POWERAMPLIFIER

LLI

a -Li'

00LOUDSPEAKER >_,

OUTPUT VOLTAGE


A 22 k 22k

Switched Frequency Low Pass FilterIn this example the effective resistance is switched by using4016 gates. The filter is a lowpass Butterworth and by turninggates A or B ON or OFF the cut off frequency can be altered. Thisallows the filter control to be physically remote or even to becomputer controlled. Mark Space modulation of A and B wouldenable continuous control over the cut off frequency.

B

V in

6k

IC1a

IC1b

IC1c

IC id

A

B

Fc

22k

POWERED BY ±6V

0 0 0OFF ON OFF ON

OFF OFF ON ON

5001-4 1kHz 2kHz 2.5kHz

22k

15n

39k

Eik822k

15n

VoutV in

Vout

500Hz 1k0 2k5 FREQUENCY2k0

Basic Limiter CircuitMost professional limiter circuits use a FET as the variable gainelement. Relatively low distortion with a reasonable signal tonoise ratio can be obtained. A basic limiter circuit is shown, thisbeing no different to previous circuits except for the variable gainelement.

When a relatively small voltage (20 mV) is applied to thedrain source of a FET, it acts like a fairly linear resistor. As thegate source voltage is varied, this resistor (RDS) also varies.

In fact the channel resistance RDS is inversely proportional togate source voltage V05. When V.. is oV, then RDS is at itsgenerally minimum resistance (R0N which can be as low as 5R,but it is generally more like 100R. When V exceeds the pinchoff voltage (Vp or V off) the channel resistance goes up toseveral hundred Megohms. So a junction FET can be used as avoltage controlled resistor, except that R and V (OFF) tendto vary widely from device to device. However with a bit ofperseverance suitable devices can be selected and made towork.

One circuit trick that greatly reduces distortion is shown here.Half of the audio signal at the drain of the FET is presented to thegate. This is superimposed on top of the control voltage andproduces a distortion cancelling effect. Distortion levels below0.1 % can be achieved using this technique.

AUDIO 47kSIG -110-NANN-----, AIN

D

MI/

OUTPUT

P 110.

--111. OUTPUT

LEVELDETECTOR

ATTACKRELEASETIMECONSTANTS

INPUT

MATCHEDNPN PAIR

NOTE

IC1 is 74103 isBC1132

-12V

15k 2°/.

OUTPUT

VCONTROL

+3V OFFOV = ON

Transistor VCA

A circuit similar in operation to a CA3080 can be constructedwith a matched pair of transistors and an op amp. Transistors Ql,2 form a differential transistor pair which is used to steerwhatever current is available between the two collectors, just asin the CA3080. the difference between the collector currents isequal to the product of the input voltage times the current Itimes a constant. This difference is extracted by the differentialamplifier IC1. The current I is controlled by 03. As the controlvoltage goes positive, Q3 robs most of the current flowing downthe 39k resistor, and hence IEE and the output of IC1 decrease.


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BectreicCircuit

Design

SdectedMO from

ti.AUTUMN

1979

toWodoctiossSince

Ell was originallylaunched

in 86t8.111April

1500 pageshave

been devotedto this in recent

years

972 we have of

nearlyS000 pages

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the first of a seriesof three

whichwilf

pioiectsof course.

In our historywe have

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Althoughsome

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matter;much

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bring togetherthe best 250-300

of these.

the best of theseproiects

in lop Pro\ectsNo1 -No

, wethey have only been included

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'age

CircuitsBook No

and No2 and our beginners

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We hopethat the contentshelp

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have also reprintedthe ec:fips

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m

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Electronics-lts-Easy

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for Motors. . . . . 54

A desurteature

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The theoryand practical

appticatIons

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" . . . .. . .

ten circuitsfor this verse

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43CM

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. 27

PracticalGuide

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Explatongthe Onctptes

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