Electrical Overstress (EOS) || EOS Program Management

11 EOS ProgramManagement

In this chapter, Chapter 11, the issue of establishment of electrical overstress (EOS) programmanagement is discussed. In order to minimize and mitigate EOS problems, it is important toeliminate the sources and origins of EOS events, as well as manage the environment in which itoccurs.

11.1 EOS AUDITS ANDMANUFACTURING CONTROL

To have a successful electrical overstress (EOS) program, it is important to establish anauditing process to evaluate conformance on establishing the manufacturing environment,with continuous evaluation. Today, there is more focus on electrostatic discharge (ESD)auditing and manufacturing control, and significantly less for EOS [1,2]. Today, there aremany reference books for ESD [2–11], electromagnetic interference (EMI), and electro-magnetic compatibility (EMC) [11–17]. Additionally, there are many standards andpublications for ESD, EMI, and EMC [20–49].

To avoid EOS issues in the manufacturing and assembly process, it is necessary to haveaudits, manufacturing controls. There are three types of ESD audits that are practiced today[1,18–19]. A first audit type is program management audits, which evaluates implementationplans, requirements, and verification practices. This first audit is typically driven by an ESDteam and management. A second type of audit is geared toward quality process control andstatistical process control issues. This second audit type is driven by manufacturingoperations personnel on a daily, weekly, or monthly basis. The third type of audits is workplace audits that include electrical measurements and satisfying ESD standards. This thirdtype of audit utilizes the ESD measurement equipment and ESD manufacturing standardsdiscussed.

Today, there are existing auditing processes for ESD, such as ANSI/ESD S20.20-2007Protection of Electrical and Electronic Parts, Assemblies, and Equipment [18,19], alsoknown as “S20.20.” To have a successful ESD training and auditing process, a program is

Electrical Overstress (EOS) : Devices, Circuits and Systems, First Edition. Steven H. Voldman.� 2014 John Wiley & Sons, Ltd. Published 2014 by John Wiley & Sons, Ltd.

needed that covers all employees; and comprehensive ESD training can include tutorials,demonstrations, video training, and other educational means.

Figure 11.1 shows an example of an EOS control program.For EOS controls in the semiconductor manufacturing environment, to make an EOS

protective area (EOS-PA), we must address additional issues typically not regarded as ESDconcerns. These include issues such as follows:

Figure 11.1 An EOS control program

286 EOS PROGRAMMANAGEMENT

� Power distribution noise

� Power distribution transients and spikes

� Grounding quality

� Ground loops

� Electromagnetic interference (EMI)

� Electromagnetic compatibility (EMC).

A second distinction between the EOS and ESD audits and controls is the EOS issueextends beyond semiconductor manufacturing.

11.2 CONTROLLING EOS IN THE PRODUCTION PROCESS

Controlling electrical overstress (EOS) in a production area is best achieved by identification ofthe production process steps, and what are the sources of EOS phenomena within that specificprocess step. Once the sources are understood, then they can systematically be addressed.

Soldering irons are a leading cause of EOS concerns in production areas. Soldering ironscan have the following EOS concerns [35–37]:

� Loss of ground connection

� Reversal of ground and neutral

� Noise on the ground line

� Noise on the power line

� Switching spikes

� Tip oxidation.

These concerns can be addressed by verification of electrical connections, evaluation ofnoise on power lines, and cleanliness of solder iron tips. A second source of EOS is on powertools. A third item is power supply commutation. These issues can change temporally, orwith changes in the equipment. Hence, to control the EOS sources in a production sector, it iscritical to take measurements and establish an EOS audit program.

11.3 EOS AND ASSEMBLY PLANT CORRECTIVE ACTIONS

Controlling electrical overstress (EOS) is achieved in assembly plant by establishingcorrective actions [35–37]. Corrective actions to control EOS can be as follows [37]:

� Noise filters on incoming ground lines

� Noise filters on power lines

EOS AND ASSEMBLY PLANT CORRECTIVE ACTIONS 287

� Equipment conformance requirements

� Equipment non-conformance de-qualification

� EOS qualifying of an assembly line to a given EOS limit

� EOS current-limiting protection devices for products on the assembly line

� EOS voltage-limiting protection devices for products on the assembly line

� EOS audits.

11.4 EOS AUDITS – FROMMANUFACTURING TO ASSEMBLYCONTROL

A key distinction between an electrical overstress (EOS) audit and control program andelectrostatic discharge (ESD) audits and controls is the EOS issue extends beyond thesemiconductor manufacturing to the assembly and final shipment of a system. A key problemin the semiconductor industry today is that the responsibility of the semiconductor facilitiesends at the shipment of the semiconductor chip to the customer. The semiconductor componentmay be sensitive to electromagnetic interference (EMI), EOS, and have other electromagneticcompatibility (EMC) issues. To have a successful EOS program it is important to establish anauditing process that extends beyond the semiconductor or component assembly.

The extension of audit and controls for EOS must extend into the assembly ofsemiconductor chips and components, with the printed circuit boards (PCBs), sub-assemblies, and final systems. First, an EOS audit is needed for program management audits,which evaluates implementation plans, requirements, and verification practices in theintegration of semiconductor components with PCBs, sub-assemblies, and systems. Asecond type of EOS audit should address quality process control and statistical processcontrol issues on a regular basis to monitor conformance to the desired EOS procedures; thisshould be evaluated by manufacturing operations personnel on a daily, weekly, or monthlybasis [1,37]. Finally, an EOS audit that evaluates the incoming EMI sources, grounds, groundloops, and electrical connections of equipment and power is needed in the assemblyenvironment, including electrical measurements. EOS training can include tutorials,demonstrations, video training, and other educational means. For EOS controls in theassembly and system environment, to make an assembly EOS protective area (EOS-PA), thepower distribution, transients, spikes, grounds, ground loops, grounding quality, electricalmeasurement of cables, to power cords should be evaluated.

11.5 EOS PROGRAM –WEEKLY, MONTHLY, QUARTERLY,TO ANNUAL AUDITS

To have a successful electrical overstress (EOS) program it is important to have a verificationin time, to guarantee that the environment does not change in time [1]. This would includeaudits of the incoming power sources, tools, and equipment in the manufacturing environ-


ment and assembly facilities. To establish an auditing process to evaluate conformance in acontinuous evaluation, it is necessary to have weekly, monthly, and annual audits of theproduct, as well as the facilities which may be prone to EOS.

An EOS audit geared toward quality process control and statistical process control issueson a daily, weekly, monthly, quarterly, and annual basis is a good procedure to maintainmanufacturing and assembly integrity [1,37]. It is important to track and document theequipment incoming power, noise, and EMI in the manufacturing and assembly environ-ment, as well as maintain a record of the audit process. As part of the evaluation, the EOSrobustness of the incoming product (e.g., semiconductor components to printed circuitboards) can also be tested to determine changes in the manufacturing product reliability andquality. EOS measurement that include both electrical measurements and satisfying of ESDand EOS standards.

For evaluation of the temporal changes in the EOS in semiconductor manufacturingenvironment, and assembly, many factors can be evaluated:

� Cable integrity

� Cable connectivity

� Ground socket and connectivity

� Power distribution transients and spikes

� Grounding quality

� Noise from incoming power [37]

� Noise with noise filters [37]

� Filter integrity [37]

� EMC/ESD scanning results [2,40–46].

11.6 EOS AND ESD DESIGN RELEASE

In semiconductor components, conformance to electrical overstress (EOS) and electrostaticdischarge (ESD) design rules is key in the design release process [2,6,10]. For ESDverification of the semiconductor chip product design release process, it is important toinclude representation from semiconductor process, device design, circuit design, andcomputer aided design (CAD) teams. An ESD design release process should contain some ofthe following items [2–8,10]:

� On-chip ESD protection

� On-chip power rail requirements for ESD

� On-chip interconnect width requirements for ESD

� Technology design manual ESD ground rule conformance

EOS AND ESD DESIGN RELEASE 289

� ESD design rule check (DRC) results

� ESD layout versus schematic (LVS) results

� ESD electrical rule check (ERC) results.

11.6.1 EOS Design Release Process

For electrical overstress (EOS), it is important to include representation for various membersof the design team in the release and signoff process. In the EOS design release, there aremembers of the team from application engineering, product definition, device design, circuitdesign, packaging, and reliability engineering. An EOS design release process shouldcontain some of the following items:

� Package EOS requirement

� Bond wire EOS requirement

� On-chip EOS protection


� On-chip power rail requirements for EOS and ESD

� On-chip interconnect width requirements for EOS and ESD

� EOS robustness of technology elements

� Product – Application EOS and ESD compatibility

� Product – Technology EOS and ESD compatibility

� EOS design rule check (DRC) results

� EOS layout versus schematic (LVS) results

� EOS electrical rule check (ERC) results.

By establishing a good semiconductor chip release process, the risks for EOS can bereduced for semiconductor manufacturing release. Figure 11.2 shows an EOS design releaseprocess.

11.6.2 ESD Cookbook

In the product definition, design integration, and planning stage, many corporations havedeveloped “cookbook” documents for electrostatic discharge (ESD) circuit design teams.An ESD cookbook can be used by the entire team to avoid design implementation errorsand insure product success. By establishing a good product release process, the risks forESD can be reduced for semiconductor manufacturing release and ESD robustness inthe field.


Whereas an ESD design manual may refer to the different ESD design, an “ESDcookbook” will provide information of correspondence between circuit type and theprotection elements. An ESD cookbook should contain the following:

� Guideline on how to use the document

� ESD specification requirements for qualification

� ESD models

� ESD specification references

Figure 11.2 An EOS design release process


� On-chip ESD protection schematic library

� On-chip ESD layout library

� On-chip power rail requirements for ESD

� On-chip interconnect width requirements for ESD

� Guard ring placement and definition

� On-chip ESD power clamp placement

� Table of pin types.

Where many of the items are self-explanatory, one of the most critical issues in an ESDcookbook is the inter-relationship and compatibility of the ESD solutions used for specificpin types. Hence, the Table of Pin Types is the key core of the ESD cookbooks.

11.6.2.1 Table of Pin Types

The Table of Pin Types is the most critical element of the ESD cookbooks. This sectionidentifies the type of pin and the power domain of the pin; for the specific pin type, a specificrecommendation of what ESD solution is needed. In this section, the pin type identifies theCadence library element cell name, circuit schematic, and the connectivity. For example, thepin types would be segmented by power domain (e.g., 2.5V, 5.0V, and high voltage domain).Additionally, there is segmentation of analog, digital, and high voltage circuitry. Circuitfunctions of inputs, outputs, and bi-directional are segmented for the different ESD and EOSsolutions (Figure 11.3).

Figure 11.3 An ESD cookbook


In the end, clear guidelines are set for the circuit design teams so that the correct ESDcircuit is used for the specific circuit to avoid mismatch between the product applicationvoltage tolerance of the elements, and proper “turn-on” of the different ESD elements for thespecific circuit.

11.6.3 EOS Cookbook

In the product definition, design integration, and planning stages, many corporations havedeveloped “cookbook” documents for circuit and printed circuit board (PCB) design teams.An EOS cookbook can be used by the entire team to avoid design implementation errors andinsure product success.

By establishing a good product release process, the risks for EOS can be reduced forsemiconductor manufacturing release and EOS robustness in the field. Whereas an EOS orESD design manual may refer to the different EOS and ESD designs, an “EOS cookbook”will provide information of correspondence between circuit type and the protectionelements. An EOS cookbook should contain some of the following items:

� Guideline on how to use the document

� EOS specification requirements for qualification

� EOS and ESD models

� EOS and ESD specification references

� Off-chip EOS protection solutions library

� Advantages and disadvantages of different EOS protection solutions

� Off-chip EOS protection layout

� Off-chip EOS guidelines

� PCB EOS protection solutions





� On-chip ESD layout



� Guard ring placement and definition

� On-chip ESD power clamp placement





� Table of pin types.

One of the most critical issues in an EOS and ESD cookbook is the inter-relationship andcompatibility of the EOS and ESD solutions used for specific pin types. Hence, the Table ofPin Types is the key core of the EOS and ESD cookbooks.

11.6.3.1 Table of Pin Types

The Table of Pin Types is the most critical element of the EOS and ESD cookbooks. Thissection identifies the type of pin, and the power domain of the pin; for the specific pin type, aspecific recommendation of what EOS and ESD solution is needed. In this section, the pintype identifies the Cadence library element cell name, circuit schematic, and theconnectivity. For example, the pin types would be segmented by power domain (e.g., 2.5V,5.0V, and high voltage domain). Additionally, there is segmentation of analog, digital, andhigh voltage circuitry. Circuit functions of inputs, outputs, and bi-directional are segmentedfor the different ESD and EOS solutions. In the end, clear guidelines are set for the circuitdesign teams so that the correct EOS and ESD circuit is used for the specific circuit to avoidmismatch between the product application voltage tolerance of the elements, and proper“turn-on” of the different EOS and ESD elements for the specific circuit (Figure 11.4).

Figure 11.4 An EOS cookbook


11.6.4 EOS Checklists

In product definition, design integration, and product release, it is very important to establisha checklist for providing electrical overstress (EOS) product robustness. EOS checklists canbe used in the product release and signoff process.

An electrostatic discharge (ESD) checklist for a product release is commonly in thedevelopment of semiconductor components. Figure 11.5 is an example of an ESD checklist.

In the product signoff and release process, there are members of the team that are fromapplication engineering, product definition, marketing, device design, circuit design,packaging, reliability engineering, quality engineers, functional test engineers, and manage-ment. An EOS checklist must be understood by the entire team to avoid designimplementation errors and insure product success.

An EOS checklist for a product release should contain some of the following items(Figure 11.6):

� EOS environment and application requirements

� ESD environment and application requirements

� Product specifications and EOS implications

Figure 11.5 An ESD checklist


� Off-chip EOS protection solutions

� Printed circuit board (PCB) EOS protection solutions

� PCB electrical characteristics










� Design rule check (DRC) results

Figure 11.6 An EOS checklist


� Layout versus schematic (LVS) results

� Electrical rule check (ERC) results

� Functional test results

� ESD test results

� EOS test results

� System assembly procedures

� Manufacturing audit results

� Signoff release of all organizations (e.g., technology, product definition, quality).

By establishing a good product release process, the minimization of EOS losses can bereduced for semiconductor manufacturing release and EOS robustness in the field.

11.6.5 EOS Design Reviews

As part of the semiconductor chip release process, an electrical overstress (EOS) designreview should be part of the process. In an EOS design review, the review process shouldevaluate the following:

� EOS environment and product compatibility

� Package compatibility

� Wirebond current handling capability

� EOS protection device – signal pin compatibility

� EOS protection device and ESD protection device compatibility

� EOS design rule checking (DRC) results

� EOS layout versus schematic (LVS) results

� EOS electrical rule check (ERC) results

� Electro-migration maximum current density compatibility.

In the EOS design review process, visual inspection of traces on the printed circuit boardand interconnect wiring levels to improve the maximum current carrying conditions is valu-able to build EOS robust products.

11.7 EOS DESIGN, TESTING AND QUALIFICATION

As part of a qualification and release of products, electrical overstress (EOS) evaluationshould be part of the release process.

EOS DESIGN, TESTING AND QUALIFICATION 297

EOS design qualification should include the following:

� EOS protection device electrical characterization

� EOS protection device test results

� Electrical characterization of EOS protection with printed circuit board (PCB), sub-assembly, and components

� ESD/EMC immunity and susceptibility scanning [40–47]

� RF immunity scanning

� EMI emission scanning

� Resonance scanning

� Current spreading scanning

� Current reconstruction and system vulnerability analysis

� EOS testing to existing standards

� EOS testing to product environment conditions.

11.8 SUMMARY AND CLOSING COMMENTS

In Chapter 11, an electrical overstress (EOS) program management process is discussed. Thechapter will demonstrate topics on design reviews, checklists, corrective actions, and thedesign release process to guarantee EOS robust products. By establishing an EOS protectivearea, EOS event minimization and mitigation can occur. This will lower the risk tocomponents, printed circuit boards, sub-assemblies, and systems.

In Chapter 12, EOS in future structures and nano-devices will be discussed. The chapterwill discuss EOS issues in magnetic recording, FinFETs, graphene, carbon nano-tubes, tophase change memory. EOS in silicon interposers and through silicon vias (TSVs) in 2.5-Dand 3-D systems will also be discussed.

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Electrical Overstress (EOS) || EOS Program Management