Electrical Overstress (EOS) || EOS Failure Analysis

4 EOS Failure Analysis

Failure analysis is a very important process for the evaluation of electrical overstress (EOS)failures to determine the root cause of failure and provide the corrective action in design,manufacturing, or production environments [1–7]. EOS, latchup, and electrostatic discharge(ESD) failures occur in components and systems [8–14]. In this chapter, the failure analysisprocess, as well as a plethora of failure analysis tools will be discussed [15–53].

4.1 ELECTRICAL OVERSTRESS FAILURE ANALYSIS

EOS failure mechanisms can occur from electrical over-voltage (EOV), electric over-current(EOC), and electrical over-power (EOP). These conditions can lead to melted packages,blown single component capacitors and resistors, ruptured packages, blown bond wires,cracked dielectrics, fused and melted metal layers, and molten silicon.

Failure analysis of components and systems involves investigation, science, andexperience. As a failure analysis matures, the failure analyst’s experience will allow fasterresolution of the root cause and solution. A failure analyst is like a forensic investigator whomust find the problem and resolve the case for each product failure. This is important in theproduct development of semiconductor components where the answer will be required priorto undergoing the next “design pass.” Time is limited between design passes to allow shortercycles of the design for release and volume ramping into production.

The steps of the failure analysis process are (Figure 4.1) [1–6]:

� Information gathering

� Failure verification

� Failure site identification and localization

� Root cause determination

Electrical Overstress (EOS) : Devices, Circuits and Systems, First Edition. Steven H. Voldman.� 2014 John Wiley & Sons, Ltd. Published 2014 by John Wiley & Sons, Ltd.

� Feedback of root cause

� Corrective action

� Documentation reports

� Statistical analysis, record retention and control.

Information Gathering

In the information gathering process for evaluation of EOS events, there are many elementsto acquire and assemble to get a coherent view of the failure:

� Failure facility or field location: Where was did the failure occur? Did it occur inmanufacturing, production, or the field? What stage of the process did this occur? Whattools did the product undergo in manufacturing? What is the yield history of the differenttools? In semiconductor manufacturing and assembly, there are yield analysis experts whoknow how to determine the path of the hardware and where yield losses occur. Yield expertswill also have inspection history and qualification of the tools, stations, and environmenthistory.

Figure 4.1 Failure analysis process

ELECTRICAL OVERSTRESS FAILURE ANALYSIS 103

� Failure determination method: How was the failure discovered? It is important todetermine the root cause of how it was found. Thermal stress? Electrical measurements?Visual signature? Electrical characteristics?

� Visual Signature: From visual inspection, are there any signs of a failure or defect? This ispossible on printed circuit boards (PCB), plastic molding (in the forms of discoloration,molten package, holes, and bubbles in the package).

� Electrical signature: From the electrical signature, what is the type of electrical signature?Short? Open? IDD leakage? I-V characteristic shift? VDD-VSS resistance?

� Product Description and Datasheet: Knowledge of the product description, function, andelectrical parameters is important for evaluation of the product. It is important to understandthe functional blocks in the physical design.

� Comparative Study: It is valuable to evaluate examples of good product and to comparethe electrical response of good versus bad part numbers. For visualization of the electricalcharacteristics it is a good practice to have the data overlaid, or together in a report.

� Database Review: It is valuable to evaluate and review the product history in terms oftemporal variation and statistical parameters. It is important to evaluate the site-to-site,wafer-to-wafer, lot-to-lot, and foundry-to-foundry differences within a manufacturingenvironment or assembly facility. This may provide a clue to the source of the problem.

� Electrical Test Simulation: A means to verify and re-simulate the event is important tosee if the failure mechanism can be repeated and show the same electrical signature orvisual signature. For example, a key question is to determine whether the event is ESD, orEOS. ESD tests (e.g., HBM, MM, CDM, IEC 61000-4-2, HMM) can be performed totry to replicate the electrical and visual signature. To determine if it is latchup, JEDEClatchup testing can be completed, where the current is increased to failure. For EOS,a series of electrical simulations can be performed for different current magnitudes andpulse widths.

Failure Verification

A goal of failure verification is to determine whether one can reproduce the failure. This canbe completed by product test and re-test. Re-testing is important, since some failures recover,or never really occurred. A percentage of field returns at times never repeat the failuresignature. Comparative testing of good/bad product can also be performed for the verificationprocess. This can be done by over-stress test simulation on untested or “good” parts.

Both non-destructive and destructive testing methods exists for failure verification [6].Non-destructive testing methods are:

� Optical inspection

� Acoustic microscope

� X-ray inspection

� Pin-to-pin testing

104 EOS FAILURE ANALYSIS

� Pin-to-rail testing

� Parametric functional testing.

Failure Site Identification and Localization

For the identification of the failure site within the system, this can be done by either visualexternal inspection or internal inspection. For visual inspection, one can look for thefollowing visual damage signatures:

� Package lead damage

� Foreign material

� Cracks

� Package discoloration

� Corrosion.

For internal inspection, the following visual damage signatures are:

� Melted metallurgy

� Cracked inter-level dielectrics

� Molten silicon.

Root Cause Determination

The root cause of a failure can be determined by evaluation of the manufacturing andproduction center records and processes, the electrical and/or visual signatures, evaluation ofthe circuit schematics and design layout, and test simulation. Once the root cause isdetermined, it is important to review the results and draw definitive conclusions.

Feedback of Root Cause

Once the root cause is determined, it is important to provide feedback to the manufacturing,production, design, reliability, and quality teams. Review of the results and conclusions shouldbe reviewed with the complete team to close the issue and establish corrective actions.

Corrective Action

Corrective actions can be taken to avoid repeating the event after its root cause is determined.The corrective action can be the chip design (e.g., design layout and/or circuit),manufacturing tooling, or production processes. It is also important in the case of acorporation with a high “re-use” of circuit blocks to prevent EOS-sensitive or ESD-sensitiveblocks from being used in other products until the corrective actions are completed.


Documentation Reports

Documentation of the results in a report is important for EOS control program management.To have a good EOS control program, documents may be a source of learning for futuredesign reviews, checklists, procedures, and audits.

Statistical Analysis, Record Retention, and Control

Statistical analysis and record retention are important for an EOS control program and tomaintain an EOS Safe Protected Area.

4.1.1 EOS Failure Analysis – Information Gathering andFact Finding

In the process of information gathering and fact finding, it is important to have a clearunderstanding of the goals and objectives of the discovery process [6]. These goals andobjectives should be set forth at the beginning of the process. The information gatheringprocess should include the following:

� Manufacturing history of the product

� Field history of the product

� Exact nature of the failure

� Environment of the product failure

� Visual signatures of the failure

� Electrical signatures of the failure.

In the manufacturing history, it is important to have information on which specific toolsthe failed samples traversed. Knowing the tool history may be critical to any EOS events in agiven tool or module of a manufacturing line.

In the field history, it is important to document the environmental conditions of the failedproduct. EOS, or thermal overstress, can be associated with conditions in the field, and henceit is important in the information gathering process to verify evidence of the environment. Aknowledge of the performance in the field of a given product (e.g., number of hours) can alsoprovide information of whether it was EOS, latent parts, or reliability wear-out mechanisms.

4.1.2 EOS Failure Analysis – Failure Analysis Report andDocumentation

An important step in the evaluation of the electrical overstress (EOS) is communicating thesteps of the failure analysis process, results, root cause, and corrective actions. This isimportant for resolving the issue and fixing the design or manufacturing process.


In an EOS failure analysis (FA) report, a few key questions are:

� Who is the audience?

� Who will be reading the report?

� What should be the length of the report?

� What should be included?

� Does the report include explanation of what happened?

� Does the report include explanation of why it happened?

� Is the report complete and answer all questions?

� Does the report explain the root cause?

� Does the report explain the corrective actions and avoidance?

� What happens to the report when it is completed?

It is important to write an EOS FA report where one knows the audience. In semiconductorchip designs, the audience may be the layout engineer, circuit designers, team lead, andmanagement. In some organizations, only the reliability, quality, and field engineers read thereport. In some corporations, failure analysis reports are generated and they are filed in acabinet. Generating reports is a waste of resources if no one reads it and no actions are takento address the issue. A key point is to write the report toward the intended audience.

It is important to write a report, so that it is clear, definitive and brief. If the report is toolong and too complex, it will not be read. For example, if the audience are chip designers, thenit should include layout, pictures of the failure mechanisms, and corresponding layout, as wellas electrical signatures. Circuit designers are also busy and want to focus on the chip designand circuits; hence, it should be clear and to-the-point directed toward addressing the solution.

Failure analysis reports are best if they are short in length. It is a good suggestion tostructure the report with a fixed format, to ease the focus and time to read the report. Asuggested format is as follows:

� Brief Executive Summary to highlight the problem and corrective action (e.g., a paragraphor half a page).

� Abstract Section discussing the failure, FA test technique applied, FA test technique results,root cause conclusion, and corrective action.

� Body Section for in-depth analysis highlighting all details.

� Root Cause Analysis Section concluding the cause of the EOS failure.

� Corrective Action Section providing suggestions for design layout, circuit solution,manufacturing fixes, and/or production issues.

� Appendix including images and photographs, visual signature, electrical signatures, I-Vplots, and other important results.


Last, in the end, report writing for failure analysis of EOS events is only valuable if thereport is read, understood, and preventive actions are taken. It is important to store thereports for simple access and availability to all members of the product cycle. Some resolu-tions also may include customer information notes and suggestions for the product usage.

4.1.3 EOS Failure Analysis – Failure Site Localization

In the failure analysis process, it is important to determine the failure site location. In thelocation identification process, it is key to identify the failure point and be able to establishthe spatial correspondence of the failure to the device, circuit, or component. By establishinga one-to-one correspondence of the layout failure point and the circuit schematic, the visualsignature and the electrical signature can be combined to understand how the failureinfluences the electrical circuit.

Failure site identification is both a process and art form where the failure analyst mayremove films and layers and look for the defect. The success is dependent on the skill of thefailure analyst and the tool that he chooses to perform the work.

4.1.4 EOS Failure Analysis – Root Cause Analysis

In the failure analysis process, a key objective is to determine the root cause of the failure.After the visual signature and the electrical signature are defined, this still does not provideevidence of the root cause that led to the failure. One of the key parts of the discoveryprocess is to determine why the electrical failure occurred and what was the source or originof the event that led to the failure.

4.1.5 EOS or ESD Failure Analysis – Can Visual Failure AnalysisTell the Difference?

A common question that arises is: from the failure analysis can one determine if the rootcause of the failure is electrical overstress (EOS) or electrostatic discharge (ESD)? Toresolve this question is dependent on the visual failure signature.

There are certain categories of failures that ESD does not typically cause, and EOS eventsdo cause. Failures that typically are caused by EOS phenomena but not ESD are as follows:

� Printed circuit board (PCB) damage

� Package molding damage

� Package pin damage

� Wire bond damage.

Figure 4.2 is an example of package pin damage due to EOS. From the package damageand package pin, it is clear that the region underwent significant currents leading to failure.


Today, PCBs, packaging, and wire bonds do not typically fail due to an ESD event causedby human body model (HBM), machine model (MM), or charged device model (CDM)events. Figure 4.3 is an example of a wire bond failure.

There are also failure types associated with long time constant pulses. Phenomenaaffiliated with long pulse width significantly longer than the thermal diffusion time constantof the structure are prone to thermal transport, heating, and electro-migration. Henceprocesses that involve material transport, thermal stress, and mechanical stress are moreaffiliated with EOS. Packaging ablation is associated with both thermal and mechanicalstress (Figure 4.4).

Mechanisms associated with reliability wear-out are also typically EOS-related. EOSevents can shorten the reliability lifetime of components, leading to an early wear-out andinducing shifts in the reliability “bath-tub” curve of a component. As discussed in the priorsections, this will be a larger issue as advanced components are scaled.

Figure 4.2 EOS package pin failure

Figure 4.3 EOS wire bond failure


Where it is hard to distinguish between EOS and ESD is in the failure signature of acomponent. Both EOS and ESD can introduce “on-chip” failure mechanisms whose visualfailure signature are similar. Both EOS and ESD can create the following failures:

� Dielectric breakdown

� Inter-level dielectric cracking

� Metal failures

� Molten semiconductor damage.

At times, failure analysts distinguish these events based on physical size. Typically, EOSevents create a larger failure damage, and more distributed through the semiconductor chip;but this is dependent on the ESD event type.

Figures 4.5 and 4.6 are EOS due to plasma arcing within a semiconductor manufacturingetch process.

CDM damage area is small and localized when it is a dielectric; CDM damage is notsmall when it is in interconnects (e.g., wiring and buses). CDM events are on the nano-second time scale and will not allow significant heat transport during the event. CDMdamage will be evident in the following circuitry (Figure 4.7) [7–8,11–14]:

� Receivers

� Pass-transistors

� Support functions

� ESD networks.

Figure 4.4 Package ablation due to EOS


ESD HBM and MM events can also have a small localized damage pattern when it occursin a small element, or a poorly designed larger element that does not distribute the energyand power within the circuit element. Well designed circuit elements which incorporate goodESD layout design practices will actually demonstrate larger failure patterns. HBM and MM

Figure 4.5 Plasma arcing in semiconductor manufacturing

Figure 4.6 Plasma arcing of stacked via structure in semiconductor manufacturing


events also do not cause dielectric failures in well designed and ESD protected circuitry.ESD events can cause failures in the following [7–8,11–14]:

� Receiver support circuitry

� Off-chip driver (OCD) NFET

� Off-chip driver (OCD) PFET

� ESD elements

� Interconnects

� Contacts

� Vias.

Figure 4.8 is an example of a copper interconnect after an electrostatic discharge (ESD)event. The coloration is associated with the cracking of the inter-level dielectric (ILD).Thermal stress at the interconnect-dielectric interface leads to insulator cracking.

Based on prior studies, an experienced failure analyst team appears to be able todistinguish between EOS and ESD events better than 80% of the time, but not always. As aresult, it is important to try to use both the visual failure signature and the electrical failuresignature to verify the root cause. Additionally, it is important to try to simulate the eventthrough ESD testing and EOS testing studies.

4.2 EOS FAILURE ANALYSIS – CHOOSING THE CORRECT TOOL

One of the critical decisions in the failure analysis process is choosing the correct tool to findthe visual signature of failure. Some of the key choices one must make are the following:

Figure 4.7 Charged device model (CDM) ESD failure


� Should I use a destructive or non-destructive failure analysis technique?

� Does the failure occur in the chassis, printed circuit board, or component?

� What is the feature size of the component where the failure occurs?

� What tool provides the most information?

� How much time do I have to perform the failure analysis?

� What is the tool availability and schedule?

The choice to use destructive or non-destructive techniques will be influenced by thelocation of the failure and physical size of the damage. The tool choice is influenced onwhere the failure is in the system.

Given that the failure occurs within a semiconductor component, the tool of choice maybe dependent on the size of the features in the component. There are some tools that providemore information than others, but take much more work and time. So, part of the failureanalysis process is the practical limit of time to perform the analysis, preparation time forthe sample preparation, and tool access and availability. Hence, the tool decision is a balancebetween the technical tool-of-choice, how much information is yielded from a given tool,and the practical tool availability.

4.2.1 EOS Failure Analysis – Non-Destructive Methods

Non-destructive testing failure analysis allows for maintaining the EOS field failure withoutdestroying the original sample. It also allows for a multiple number of techniques to beapplied to the same sample. Non-destructive testing can utilize the following [1–6]:

� Optical inspection

� Acoustic microscope

Figure 4.8 Copper interconnect from electrostatic discharge (ESD) event

EOS FAILURE ANALYSIS – CHOOSING THE CORRECT TOOL 113

� X-ray inspection

� Electrical measurements.

For external optical inspection, many observations can be seen:

� Package molding damage

� Lead damage

� Foreign material

� Cracking

� Molding discoloration

� Corrosion

� 2.5-D systems visual wire bond

� 3-D system package delamination between semiconductor chips.

For acoustic microscopes, sonar is used. Acoustic microscopes can be used for observingEOS-related plastic delamination and die separation for the package, manifesting itself as [6]:

� Top die delamination

� Paddle damage

� Moisture intrusion into leads

� Thermal and electrical voids

� Moisture pockets (leading to corrosion and package “pop-corn” cracks).

For x-ray inspection, this methodology can view EOS-induced bond wire integrity, leadframe damage, and die placement issues.

4.2.1.1 EOS Failure Analysis – X-Ray Scanning

X-ray scanning is a non-destructive failure analysis technique which allows for evaluation ofinternal structures that are not visible in semiconductor packages [6]. Electrical overstress(EOS) can introduce damage inside a package associated with delamination, to bond wiredisplacement, melting or cracking; these are visible using x-ray imaging techniques. X-raytomography techniques can provide 2-D and 3-D x-ray images that are not possible to isolatewith other failure analysis methods. X-ray tomography techniques are suitable to determineif the EOS event introduced the component failure.

4.2.1.2 EOS Failure Analysis – Scanning Acoustic Microscopy

Electrostatic discharge (ESD) events typically do not create printed circuit boards or packagefailures, whereas the likelihood is significantly higher for electrical over-current (EOC) and


electrical over-voltage (EOV) events. Electrical overstress (EOS) can impact the reliabilityof microelectronic packages. EOS can introduce thermo-mechanical stress which can lead tode-lamination, voids, and cracks in semiconductor component packaging. One techniqueused is scanning acoustic microscopy (SAM) [1–6].

SAM is a non-destructive failure analysis tool for the evaluation of EOS-related packageand printed circuit board (PCB) damage [6]. Scanning acoustic tomography can be used forreliability, quality, and failure analysis.

4.2.2 EOS Failure Analysis – Destructive Methods

Some failure analysis methods for electrical overstress (EOS) evaluation are destructiveprocesses. Destructive physical analysis includes [1–6]:

� Delayering processes

� Etches

� Stains

� Scanning electron microscopes (SEM)

� Focused ion beam (FIB)

� Cross sectioning.

For the identification of foreign material, failure methods include the following:

� Auger electron spectroscopy

� Energy dispersion

� Transmission electron microscope (TEM)

� Secondary ion mass spectroscopy.

4.2.3 EOS Failure Analysis – Differential Scanning Calorimetry

A destructive failure analysis technique that can be used for printed circuit board (PCB) orassembly level is the differential scanning calorimetry (DSC) technique [6]. DSC measuresthe temperature-dependence of the excess heat capacity of a system due to thermal phasetransitions. Heat capacity curves that undergo such transitions contain information on theenthalpy and entropy of these transitions.

Thermal expansion due to electrical overstress or thermal stress can lead to boardlevel failures. EOS events or lack of cure of the printed circuit board can contribute tothe failure mechanisms. Thermal stress can occur due to thermal expansion from asoldering process. In the differential scanning calorimetry technique, important variablesare the following:


� Glass transition temperature (Tg)

� Degree of cure.

In the DSC method, with the evaluation of the glass transition temperature and the degreeof cure, it is possible to determine whether the printed circuit board has seen a thermaloverstress from soldering or EOS.

4.2.4 EOS Failure Analysis – Scanning Electron Microscope/Energy Dispersive X-ray Spectroscopy

The scanning electron microscope/energy dispersive x-ray spectroscopy (SEM/EDS)technique can be used for electrical overstress (EOS) evaluation [6]. Typically, the SEM/EDS technique is used in assembly level failures, but it can also be utilized for printed circuitboard (PCB) evaluation. Given that an EOS failure is an assembly or board level failure, thismethod may be of value for visual as well as elemental evaluation.

Scanning electron microscope (SEM) spectroscopy will provide a visual image of thefailed region. Energy dispersive x-ray spectroscopy (EDS) can provide the materialproperties of the elements found in the region of the failure. EDS will determine informationon contaminants or corrosion products. A key question that arises from this method iswhether there is a distinction between the elemental species in the failed sample versus a“good” sample. A second key question is the same elements present in the failed region alsopresent in non-failing regions of the same sample. Hence this method is highly dependent onunderstanding the materials in the contaminated and non-contaminated regions. This methodcan be used to distinguish whether the assembly or printed circuit board is related tocontamination, corrosion, or EOS.

4.2.5 EOS Failure Analysis – Fourier Transform InfraredSpectroscopy

Fourier transform infrared (FTIR) spectroscopy is a destructive failure analysis techniqueused for evaluation of organic-based contamination [6]. Electrical overstress (EOS) can berelated to an organic contamination leading to a high resistance short. In Fourier transformspectroscopy, the measurement technique collects the spectral emissions. The emissionspectra is collected based on measurements of the coherence of a radiative source. Theradiative source emissions are collected using time-domain or space-domain measurementsof the electromagnetic (EM) radiation or other type of radiation. In this technique, a Fouriertransform conversion transforms the raw data into an emissions spectrum.

The FTIR spectroscopy method is utilized for failures at the assembly level. Thetechnique is best applied by providing a comparison analysis of the failed location and thenon-failed location, or a failed sample and non-failed sample. In this fashion, the organicmaterial that is not supposed to be present can be separated from the organic material that issupposed to be there. This method may be valuable to sort out if EOS, EOV, EOC, or EOPplays a role in the failure.


4.2.6 EOS Failure Analysis – Ion Chromatography

A failure analysis technique for evaluation in the assembly level and board level fordetermination if failures is associated with contamination or ion–ion based failures ision-exchange chromatography, also known as ion chromatography (IC) [6]. Ion-exchange chromatograph is a process that allows the separation of ions and polarmolecules based on their charge. This method is used to determine if the failure isassociated with surface conduction leading to a high resistance shorting mechanism.Contamination of ions can lead to an electrical failure signature that may be believed tobe associated with electrical overstress (EOS); this method may be a good technique torule out EOS event resistive shorts. This method would not be used typically on acomponent level, or ESD analysis.

To evaluate the electrical failure, it is important to have a control sample for comparativeanalysis. In this way, the ionic levels of a “good” specimen can be compared to the “failed”specimen. The failure signature on the printed circuit board (PCB) can be evaluated over theentire surface (e.g., global contamination), or localized regions where the concern may bepresent in the electrical signature. If it is found that the “bad” specimen is globallycontaminated and the electrical resistance is evaluated, then it can be ruled out as not anEOS. If the failure is localized and evaluation shows filamentation, spiking, dielectricrupture, and ionic contamination, then it is possible that electrical over-current (EOC),electrical over-voltage (EOV), or electrical overstress (EOS) is involved.

4.2.7 EOS Failure Analysis – Optical Microscopy

One of the most common FA techniques for the evaluation of ESD events is the opticalmicroscope (OM) [7]. Optical microscopes use visible light; they are simple and lowcost. Historically, they were the most commonly used tool for evaluation of ESDevents. With magnification capability, it was adequate to use optical microscopes todetermine metal failure, inter-level dielectric (ILD) cracking, contact melting, andsilicon damage [7].

The majority of ESD FAwas performed using OM combined with de-layering processes.For example, to evaluate failures in silicon, removal of all insulator films allowed for a rapidevaluation of ESD damage that occurred in the silicon devices. ESD diode failures such asmetal wiring, contacts, silicide, metallurgical junction, and anode-to-cathode damage isobservable with OM [7,11–14]. ESD MOSFET failure such as metal, contacts, silicides, andMOSFET source-to-drain failures are all observable with OM [7,11–14]. Hence, the majorityof ESD failures are observable with OM and de-layering (Figure 4.9).

One of the limitations with OM is the ability to observe dielectric failures in the MOSFETgate structure. Fortunately, these events occur in a limited number of incidents. Chargeddevice model (CDM) events can induce dielectric failures in MOSFETs, polysilicon-boundgated diodes, gated buried resistors, and metal–insulator–metal capacitor structures [7,11–14]. A second limitation today is due to the metal levels and “fill shapes.” Today, with manylevels of metal interconnect and fill shapes, it is more difficult to visualize the damagewithout de-layering the sample.


4.2.8 EOS Failure Analysis – Scanning Electron Microscopy

The scanning electron microscope (SEM) is commonly used for ESD FA [7,25,26].The SEM images the same surface using a high energy beam of electrons. The electronbeam (e-beam) is swept rapidly in a raster scan pattern. The interactions of the e-beam andthe atoms on the surface provide information about the surface topography and electricalconductivity. In this method, back scattering occurs in the e-beam, where the image iscreated from the back scattered electrons.

4.2.9 EOS Failure Analysis – Transmission Electron Microscopy

The transmission electron microscope (TEM) is a electron microscope tool used in ESDfailure analysis [7]. The TEM technique utilizes a beam of electrons that impinges on a thinfilm specimen. Whereas an SEM uses the scattered electrons, in TEM microscopy theelectrons are transmitted through the sample. The sample must be very thin to allowtransmission of the e-beam. ATEM image is formed from the electrons transmitted throughthe sample and magnified and focused by an objective lens; this image appears on animaging screen. Imaging electronics, monitors, film, sensors, or charged coupled device(CCD) cameras are used to store the image. Because of the difficulty of sample preparation,TEM analysis is time-consuming and difficult; although difficult, TEM tools are used toevaluate changes in the material properties after ESD events. For example, TEM analysis ofinterconnect films and silicide films demonstrates changes in crystal structure after ESDstress (Figures 4.10 and 4.11).

Figure 4.9 Bond pad and interconnect failure using optical microscope


Figure 4.10 Transmission electron microscope (TEM) of interconnect pre-ESD stress

Figure 4.11 Transmission electron microscope (TEM) of interconnect post-ESD stress


4.2.10 EOS Failure Analysis – Emission Microscope Tool

Emission microscope (EMMI) tools take advantage of the electro-luminescentcharacteristics of silicon devices [5,7,9,10,12,27–33]. Emission microscopes were veryimportant in the understanding of ESD device operation and for observing defects. Oneof the advantages of emission microscopy is it allows visualization of the region ofinterest without delayering or destroying the sample. For ESD FA, the evaluation of theelectro-luminescent characteristics in both forward and reverse bias states provideinformation about defects, faults, failures, and device operation. Photons are generatedas a result of electron-hole pair (EHP) recombination and generation. As a minoritycarrier recombines with the majority carrier, a photon is emitted in EHP recombination.Avalanche breakdown also leads to the photon generation. As a result, electro-luminescent evaluation can be used for both forward bias current flow and reversebreakdown phenomena. Additionally, photon emission can be used to find oxide anddielectric failures. CDM events can introduce “pin hole” defects. Oxide defects can beobserved using electro-luminescent techniques.

The EMMI tool was developed for the imaging of semiconductor defects. SomeEMMI tools utilize an optical microscope system and an image intensifier. The imageintensifier magnifies the signal coming from the optical microscope, whose output issent to a charged coupled device (CCD) camera. The output of the CID or CCD camerais connected to an image processing computer. The output is then transferred to acomputer display for visualization. In the visualization software, both two-dimensionaland three-dimensional mappings are available; sectional views of the three-dimensionaldata is possible to produce two-dimensional images. In recent years, enhancements havebeen made using cryogenically-cooled back-thinned CCD cameras, as well as to thesoftware acquisition system.

4.2.11 EOS Failure Analysis – Voltage Contrast Tools

Active voltage contrast (AVC) techniques can be used to evaluate electrical overstress (EOS)failure mechanisms associated with “opens” and “shorts” [15]. Passive voltage contrast(PVC) is limited for large structures, chains, and complex connectivity. An advantage ofAVC techniques is improvement of contrast and clearer distinction to determine opens,shorts, or defective structures for the larger defects or complex circuits.

AVC can use a dual beam system, where one beam serves to bias one end of a chain, andthe other end for ground. In this fashion, a larger voltage differential is observed.

4.2.11.1 EOS Failure Analysis – PVC Tool

Voltage contrast techniques can be used to evaluate electrical overstress (EOS) failuremechanisms associated with “opens” and “shorts.” Voltage contrast techniques include bothPassive voltage contrast (PVC) and Active voltage contrast (AVC) [15].

The PVC technique does not connect the substrate or die to power supplies or signals. ThePVC method for failure localization on semiconductor circuits is based on contrast


differences between “dark” or “light” elements to determine whether an element isgrounded, reversed biased, or floating. A focused ion beam or a electron beam is used tocharge physical structures, and the response of the signal is imaged using a detector. Thesources for irradiation are focused ion beam (FIB) for ions and scanning electron microscope(SEM) for electrons.

For EOS failure analysis, PVC can be used to evaluate shorted connections, open circuits,gate dielectric breakdown leakage, and leaky metallurgical junctions [15].

4.2.11.2 EOS Failure Analysis – AVC Tool

Active Voltage Contrast (AVC) techniques can be used to evaluate electrical overstress(EOS) failure mechanisms associated with “opens” and “shorts.” PVC is limited for largestructures, chains, and complex connectivity. An advantage of active voltage contrasttechniques is improvement of contrast and clearer distinction to determine opens, shorts, ordefective structures for larger defects or complex circuits.

AVC can use a dual beam system, where one beam serves to bias one end of a chain, andthe other end for ground. In this fashion, a larger voltage differential is observed.

4.2.12 EOS Failure Analysis – IR Thermography

Infrared thermography (IRT) is a non-destructive failure analysis technique based onemitted infrared radiation [28–30]. Thermal imaging cameras detect radiation andproduce thermal images, known as thermograms. Thermograms produce images fromelectromagnetic radiation in the range of 9000–14,000 nm (i.e., 9–14mm). Thermalimaging cameras exist for responsiveness to longer wavelengths (mid- and long-wavelength infrared) using more exotic compounds (e.g., InSb, InGaAs, HgCdTe) andQWIP focal plane arrays (FPAs). Using backside imaging and InSb thermal detectors,improved imaging potential is possible for smaller defects; today, this is a limitation ofthis technique for advanced technology nodes.

With the scale of the thermal image in tens of microns, it is suitable for the analysisof electrical overstress (EOS) events in semiconductor chips. EOS events can besignificantly large areas of the same scale. Examples of EOS events observable with IRthermography are:

� Printed circuit board (PCB) mappings

� Semiconductor device mapping.

For refined IRT, smaller failure defects are possible. Examples of ESD damage, EOSevents, or manufacturing defects are observable with IRT:

� Metal wiring short circuits

� Contact hole abnormalities

� Oxide breakdown.


4.2.13 EOS Failure Analysis – Optical Beam Induced ResistanceChange Tool

Electrical overstress (EOS) failures can occur in the interconnects of a semiconductorcomponent. Component level EOS failures can occur in bond wires, bond pads, interconnectwiring, vias, and contacts. EOS events can lead to both opens and shorts in metal structures.Additionally, EOS-induced electro-migration (EM) can lead to voids in the wireinterconnects, vias, and contacts. A component-level failure analysis technique used forevaluation of interconnect failures is the optical beam induced resistance change (OBIRCH)imaging technique [15].

OBIRCH is a semiconductor failure analyzer where a scanning laser can find thedefective vias, contacts, and metal film from the front side or from the back side of acomponent. In this technique, OBIRCH imaging uses a laser beam to induce a thermalchange in the device. A constant voltage is applied to the device under test (DUT). A regionof the component is selected and a laser beam is used to scan that area. In this method,changes in electrical voltage or changes of current can be monitored. The input current beingdrawn by the device is monitored; when a change in current occurs, the position of the laseris recorded and marked on the image of the device.

EOS events can lead to “opens” or “shorts.” When the laser beam strikes a location whichdoes not contain an “open,” a good thermal response exists; in this case, the change inelectrical resistance is small. In areas containing ESD events, EOS events, or EOS-inducedvoids, thermal transmission is impeded, resulting in a larger change in resistance. Themagnitude of the resistance change is recorded and displayed on the image of the device,where the region of failure is indicated by a bright spot (Figure 4.12).

4.2.14 EOS Failure Analysis – IR-OBIRCH Tool

Using a laser with a 1300 nm infrared (IR) wavelength, this technique can be extended intothe IR spectrum, for the IR optical beam induced resistance change (IR-OBIRCH)methodology [15]. With the use of an IR laser, no OBIC signal is produced in thesemiconductor component. The advantage of the IR laser is this method can be used forbackside observations. A limitation of non-IR sources is the inability to look on the backsidethrough heavily doped substrate wafers. Using the IR scanning laser, this method allows foranalysis of a wider number of product applications.

Figure 4.12 OBIRCH failure analysis tool


4.2.15 EOS Failure Analysis – Thermally Induced VoltageAlteration Tool

One ESD FA methodology used is a method known as thermally-induced voltage alteration(TIVA) [34–40]. The TIVA method was first developed by E. Cole, Jr. [34–40]. Additionally,current-induced voltage alteration (CIVA) was also developed [34–40]. For ESD analysis,the TIVA method is valuable since it can analyze both open-circuit and short-circuit states.ESD defects can be both open circuit events (e.g., metal failure) or short-circuit events (e.g.,metallurgical junction failure). The TIVA method can be used from both front side- andsubstrate-side analysis; this is advantageous since ESD failures can occur in thesemiconductor device or interconnects. Another advantage for ESD evaluation is that it isnon-destructive. In addition, it is a full chip methodology; in ESD failures, some failuresoccur on the chip peripheral, but also internal failures can occur. For failures internal tothe semiconductor chip, the failure cannot be observed from terminal measurements in theI/O pad.

In the TIVA apparatus, a focused laser beam is scanned over the interconnect metalpattern. A direct current (i.e., a constant current biasing) is also applied to the semiconductorchip sample. With the application of a constant current bias, and the laser beam, localizedheating occurs in the conductors. With the localized heating, an thermo-electric potentialchange (i.e., the Seebeck effect) occurs in the conductor with an open-circuit defect. With ashort circuit, a resistance change occurs. In both cases, the power demand of thesemiconductor chip is altered and measurable (measured as a voltage change in constantcurrent mode). By simultaneously monitoring the supply voltage and the position of the

Figure 4.13 Atomic force microscope (AFM)


scanning laser beam, an image can be spatially defined and identified. An advantage of theTIVA methodology is that it addresses “shorts” and “opens,” and a strong voltage signal ismeasurable. In many circuit techniques, the signal magnitude may be tens to hundreds ofmillivolts, whereas in this method the voltage signal is higher. Figure 2.2 shows an exampleof utilization of the TIVA apparatus for an ESD event. In the figure, an ESD failure is evidentin the region of the TIVA signal.

4.2.16 EOS Failure Analysis – Atomic Force Microscope Tool

Atomic force microscope (AFM) tools have a significant value for ESD FA [43–47]. AFMtools can provide topography, electrostatic potential, and doping profile analysis. For ESDevents, the AFM has value to study the topography before and after ESD events. Topographymaps can provide detailed analysis of ESD failures in MOSFET source, drain, and gateregions. Topography maps can show the regions of molten regions of the device after ESDfailure. Figure 4.13 shows a high level diagram of an AFM tool. The AFM tool has a fineprobe tip which is brought close to the sample to sense topography, electrostatic potential, orcapacitance coupling. The probe tip is scanned across the two-dimensional surface toprovide a visual mapping of the region of interest.

Figure 4.14 is an example of an AFM image of a series cascode MOSFET after MOSFETsecond breakdown. The atomic force microscope tool utilized was a Kelvin force probemicroscope (KPFM). The KPFM tool produces both topography and electrostatic potential.In the figure, the KPFM image shown is a topography map.

4.2.16.1 Two-dimensional Atomic Force Microscope

FA is difficult when the ESD failure is in a region of significant topography. Even anatomic force microscope (AFM) tip cannot reach regions of high aspect ratio. Regionsthat have a sloped sidewall are difficult to map when the side edge of the AFM probetip prevents the probe tip to reach the edges and corners. A solution to address thisissue is usage of a two-dimensional (2-D) AFM probe tip [45]. Figure 4.15 shows anexample of a scan with an AFM probe tip, known as a “boot tip.” The 2-D AFM boottip has an “anvil” shape; a flattened bottom region, and the corners are extendedextends laterally outward. This “boot” shape or anvil shaped tip allows for measurementin both a vertical and lateral dimension. The probe tip is suitable to evaluate sidewallslopes of a MOSFET gate sidewall and bipolar emitter structures [46,47]. In isolationregions, it can evaluate both STI and deep trench (DT) regions [46,47]. For ESDevents, the 2-D AFM boot tip has been used for evaluation of failure mechanisms forSTI-bound pþ/n� well diodes, STI-defined lateral pnp devices, and MOSFET linewidth variation effects on MOSFET snapback [11].

Figure 4.16 is an example of the first usage for evaluation of ESD failures in STI-bounddiodes [11]. In order to map the damage of the STI-bound diode, the STI and all insulatorswere removed. The 2-D probe tip was lowered into the STI cavity. In the damaged region,molten silicon was evident at the bottom of the STI region between the pþ anode and thenþ n� well cathode regions.


4.2.17 EOS Failure Analysis – Super-Conducting QuantumInterference Device Microscope

Super-conducting quantum interference device (SQUID) microscopes were first intro-duced in the 1960s [41,42]. J.E. Zimmerman was a co-inventor of the radio-frequencySQUID. The SQUID microscope detects magnetic flux. The SQUID microscope consistsof a super-conduction ring structure with one or two Josephson junctions. The SQUIDtool is capable of detecting magnetic fields to 2 pico-Tesla and has demonstrated theability to measure in the 100 femto-Tesla levels. For semiconductor analysis, SQUIDtools are suitable for the evaluation of magnetic fields induced by current flowing in a

Figure 4.14 Atomic force microscope mapping of an ESD event


Figure 4.15 Two-dimensional boot tip for an atomic force microscope (AFM)

Figure 4.16 Two-dimensional boot tip AFM mapping of an STI-defined diode structure


semiconductor component; therefore it is suitable as a current imaging failure analysismethod. The SQUID microscope is a non-destructive FA tool. The Scanning SQUIDmicroscope (SSM) is a current imaging tool which can be used for packaging or chip-level electrical shorts; the SSM can be used as a means for ESD and latchup failureanalysis. The SSM measures magnetic field patterns and converts them into images. In asemiconductor chip, currents must be established in the semiconductor chip. By scanninga magnetic sensor over the surface of the semiconductor chip, an image is producedwhich is a map of the recorded magnetic field strengths. The recorded magnetic fieldstrength contours are created to form the imaging map. ESD and latchup failures can leadto electrical shorts that introduce high currents. For failure analysis, the regions thatintroduce the high currents during biasing can be used to determine the location of theESD or latchup events (Figure 4.17).

4.2.18 EOS Failure Analysis – Picosecond Imaging CurrentAnalysis Tool

Static emission microscopy has been used since the early 1990s as a method ofobserving failure modes in integrated circuits of many types. Many common failuremodes result in an abundance of hot electrons, which in turn cause large numbers ofnear-infrared (NIR) photons to be emitted. When the circuit is imaged under amicroscope, this NIR emission is readily detectable by a CCD or similar device.Although little or no dynamic information is available, the confirmation and location ofthe defect is an enormous benefit.

Figure 4.17 Example of SQUID failure analysis of a latchup event


Picosecond imaging circuit analysis (PICA) is used for time-resolved PEM [48–51].PICA has been used extensively for characterization, timing verification, and FA of CMOSVLSI circuits. Mechanically, a PICA system may closely resemble a static emissionmicroscope (EMMI tool), the difference lying in the use of a detector capable of resolvingsingle photons on a picosecond time scale. The resulting periodic photon emissions aredetected and correlated with a trigger such as a circuit output, divided clock, or a testeroutput signal. In the imaging PICA system used in the test setup, the DUT is observed via amicroscope objective. The spatial resolution of the imaging PICA system is a function of thespatial resolution of a Mepsicron detector and the optical properties of the microscope(Figure 4.18).

4.2.18.1 Transmission Line Pulse Picosecond Imaging Current Analysis Tool

By synthesizing the PICA tool methodology with a high current pulse source methodology, anew method for evaluation of ESD and latchup events can be established [52,53]. Thesynthesis of the transmission line pulse (TLP) method and the PICA method allows for theextension of the ESD TLP methodology to terminal currents and spatial and time domainanalysis for electrical characterization and reliability analysis, and the high current pulsedsource extends the utilization of the PICA methodology for failure analysis on wafer andchip levels. Additionally, it allows for visualization of ESD and latchup events (e.g.,animation in a picosecond time regime).

Figure 4.18 Picosecond imaging current analysis (PICA) tool


Since photon emission in PICA is a statistical process, it is necessary to collect time-correlated photons over many cycles of a periodic stimulus/response. If the response to aTLP-like condition is to be measured with PICA, a pulse train must be continuously appliedto the DUT. Care must be taken to ensure that a persistent mode of failure such as latchup orESD latent damage does not occur, as in that case the periodic nature of the DUT responsewould be destroyed, and the resulting time-averaged data would not reveal the onset of thelatchup event.

Figure 4.19 shows a block diagram of our TLP-PICA system for the simultaneous spatialand temporal resolution of optical emission from an integrated circuit. Here, the sample isexcited by an HP8114A in current pulse mode.

The resulting TLP-PICA system can be run according to a number of different test modes.Test methods can be formed which vary the sequence of pulse train variables: pulse number,pulse height, pulse rise time, and different stress increment levels. The methodology alsoallows for evaluation of the terminal current, voltage, and leakage across the DUT [52,53].

4.3 SUMMARY AND CLOSING COMMENTS

In Chapter 4, failure analysis methods for the evaluation of electrical overstress (EOS) eventswere discussed. Techniques, tools, and methods were reviewed for both non-destructive anddestructive methods. The chapter also highlighted the process of failure analysis to determinethe root cause of the failure.

Figure 4.19 Transmission line pulse – picosecond imaging circuit analysis (TLP-PICA) tool

SUMMARY AND CLOSING COMMENTS 129

In the next chapter, the discussion will address test simulation of EOS events. In Chapter5, EOS and ESD testing techniques and testing standards are discussed. EOS testing methodsdiscussed include system level tests, such as IEC 61000-4-2, and transient surge standardsrelevant to EOS (IEC 61000-4-5).

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Electrical Overstress (EOS) || EOS Failure Analysis