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Electrical Characterization and Reliability Group
Evaluation of Charge Trapping Measurements and Their Application to High- Gate Stack Evaluation
Evaluation of Charge Trapping Measurements and Their Application to High- Gate Stack Evaluation
IEEE Electron Device Society Meeting
Chadwin D. Young
SEMATECH, the SEMATECH logo, International SEMATECH, and the International SEMATECH logo are registered servicemarks of SEMATECH, Inc. AMRC, Advanced Materials Research Center, ATDF, the ATDF logo, Advanced Technology Development Facility, ISMI and International SEMATECH Manufacturing Initiative are servicemarks of SEMATECH, Inc. All other servicemarks and trademarks are the property of their respective owners.
Introduction/MotivationIntroduction/Motivation• Hf-based films are currently being studied to
replace SiO2 gate dielectrics in future technology nodes
• A major issue with high- transistors is trapped charge
• The high- film quality and its impact on device performance (i.e., Id-Vg and mobility) is being investigated– Bulk traps, trapped charge (Kerber, Zhu, and Young)– Phonon scattering (M. Fischetti, E. Cartier, et al)– Crystallization of the high-, inducing charges
(Yamaguchi, Bersuker)– Impact of metal gate (Intel’s IEEE Electron Device Letter)
• Measurements methodologies are needed to qualitatively and quantitatively determine trapped charge in high- gate stacks
Introduction/MotivationIntroduction/Motivation
• Vt instability and device performance degradation have been extensively studied in high- gate stack structures– Fast transient charge trapping of substrate
injected electrons is a major contributor to the instability and degradation
• Charge trapping during conventional DC measurements prevents evaluation of the intrinsic properties of high- dielectrics
• Previously reported pulsed I-V results may still be subject to fast transient charging (previous minimum charging time: 5 s at SEMATECH)
Introduction/MotivationIntroduction/Motivation
• Need to ensure proper evaluation of the threshold voltage shift (Vt)
• Need to understand the effect of charge trapping on the extraction of intrinsic mobility
• Need to understand the impact of fast transient charging on the reliability assessment of high-
ObjectiveObjective• To evaluate several charge trapping
measurement methodologies– Capacitance-Voltage hysteresis – “Stress and Sense” (CVS w/ C-V around Vfb)– Fixed and Variable Amplitude Charge Pumping– Fast Transient (Single Pulse)
• Measurements were done on various hafnium-based gate stacks– MOCVD and ALD type dielectrics– Varying physical thickness– Polysilicon electrode and metal gate
• Show and discuss the results of these measurements
C-V HysteresisC-V Hysteresis • Voltage sweep methodology shows that as the sweep widens, so does the hysteresis
• Notice the –1 V discharge condition (up traces identical)
• Self-consistent methodology must be used to avoid examples shown
– electric field strength should be fixed
-1.0 -0.5 0.0 0.5 1.0 1.5 2.00
1
2
3
4
5
C
apac
itan
ce [
pF
]
Gate Voltage [V]
-1 to 1 V 1 to -1 V -1 to 1.5 V 1.5 to -1 V -1 to 2 V 2 to -1 V
C-V Sweep
Hf Silicate (20% SiO2)
Freq = 100 kHz
-3 -2 -1 0 1 2
0
20
40
60
80
100
120
Freq = 100 kHz4 nm ALD HfO2
Cap
acit
ance
[p
F]
Voltage [V]
Inv to Accum Accum to Inv
Vfb = 191 mV
-3 -2 -1 0 1 2
0
20
40
60
80
100
Vfb = 105 mV
Cap
acit
ance
[p
F]
Voltage [V]
Inv to Accum Accum to Inv
Freq = 100 kHz4 nm ALD HfO2
C-V Hysteresis Comparison-Metal v. PolyC-V Hysteresis Comparison-Metal v. Poly
• There is a reduction in V with a metal gate• Notice that the inversion regime shows a larger
hysteresis in each case
-2 -1 0 1 20
1
2
3
4
5
EOT = 2.26 nm
V = 198 mV
V = 375 mV
O3/MOCVD 6 nm HfSixOy/NH3 700oC/Poly
Cap
acit
ance
[p
F]
Voltage [V]
Accum to Inv Inv to Accum
-2 -1 0 1 20
1
2
3
4
5
6
7
V = 83 mV
O3/MOCVD 6 nm HfSixOy/NH3 700oC/TiN/Poly
Cap
acit
ance
[p
F]
Voltage [V]
Accum to Inv Inv to Accum
V = 104 mV
EOT = 1.73 nm
CVS with Interspersed CVCVS with Interspersed CV
• There is a time delay between stress and C-V allowing relaxation of some of the trapped charge
• In addition, CV is taken around Vfb which de-traps some substrate injected electrons
switch matrix connection
V
Time
stress CV with
forward & backward voltage sweep
Optional IV
switch matrix connection
switch matrix connection
stress CV with
forward & backward voltage sweep
Optional IV
switch matrix connection
stress CV with
forward & backward voltage sweep
Optional IV
connection switch matrix
connection V
Time
Injected Charge, Qinj [-C/cm2]
0.001 0.01 0.1 1 10T
rap
ped
Ch
arg
e D
ensi
ty,
Nt [
#/cm
2]
-1.2e+11
-1.0e+11
-8.0e+10
-6.0e+10
-4.0e+10
-2.0e+10
0.0
O3/ALD HfO2 "thin"/N2 SI
Substrate Injection for ALD HfO2 Substrate Injection for ALD HfO2 • Interspersed C-V
measurements– Positive flatband shift
indicating a net negative trapped charge
– Notice the hysteresis widen as the stresses continue signifying electron trapping
• Plot of Nt vs. injected charge, Qinj
• Noise here suggests an unstable extraction of Vfb based on CV up-traces being so close together
ALD HfO2ALD HfO2
Voltage [V]
-1.00 -0.95 -0.90 -0.85 -0.80 -0.75 -0.70 -0.65
Ca
pa
cit
an
ce
[F
]
3e-12
4e-12
4e-12
5e-12
5e-12
5e-12
6e-12Initial CV
CV After Stress1
After Stress9
CV After Stress18
Voltage [V]-2 -1 0 1 2
Cap
acit
ance
[F
]
0.0
1.0e-12
2.0e-12
3.0e-12
4.0e-12
5.0e-12
6.0e-12
7.0e-12
Positive Vstress
Initial Data for NCSU CVC
ALD HfO2
Inset: Pre-stress C-V datafb
oxt V
q
CN
Substrate Injection for MOCVD HfSixOySubstrate Injection for MOCVD HfSixOy
• Interspersed C-V measurements – Positive flatband shift
indicating a net negative trapped charge
– Notice the hysteresis widen as the stresses continue signifying electron trapping
• Notice larger Vfb shifts than the previous example– Trapped charge is retained
longer than ALCVD• Larger quantity of
trapped charge 0.1 1 10 100-9.00E+011
-8.00E+011
-7.00E+011
-6.00E+011
-5.00E+011
-4.00E+011
-3.00E+011
-2.00E+011
Tra
pp
ed
Ch
arg
e D
en
sit
y,
Nt [
#/c
m2 ]
Injected Charge, Qinj [-C/cm2]
Substrate Injection MOCVD Hf Silicate
-0.95 -0.90 -0.85 -0.80 -0.75 -0.70
4.20E-012
4.40E-012
4.60E-012
4.80E-012
5.00E-012
5.20E-012
5.40E-012
5.60E-012
5.80E-012
6.00E-012
6.20E-012
C
ap
ac
ita
nc
e [
F]
Voltage [V]
Initial CV CV after stress1 CV after stress5 CV after stress12 CV after stress19
(+) Vstress
Substrate InjectionMOCVD Hf Silicate
Charge Pumping MeasurementsCharge Pumping Measurements
• Charge pumping measurement:- Fixed Amplitude (FA) interface traps, Nit, Vbase is stepped- Variable Amplitude (VA) bulk traps, Nt, Vtop is stepped- rise and fall times tr and tf = 100 ns- traps fill from S/D during tr, empty into substrate during tf
• Charge pumping current is given by
f= freq, A= channel area, Nit= interface trap density
Vfb
Vt
Icp
Vbase
Icp
Vtop
Fixed-Amplitude (FA) CP Variable-Amplitude (VA) CP
Vfb
Vt
Icp
Vbase
Icp
Vtop
Fixed-Amplitude (FA) CP Variable-Amplitude (VA) CP
A
S D
Gtr tf
VaVbase
Vtop
A
S D
Gtr tf
VaVbase
Vtop
tr tf
VaVbase
Vtop
itcp qfANI
Charge Pumping (CP) on Various Gate StacksCharge Pumping (CP) on Various Gate Stacks • FA CP and VA CP are
done to assess trapping in the hybrid stack
• FA CP shows relatively low Nit values for all hybrid stacks
• VA CP shows the 30/15 hybrid with the highest trapping density at Vtop < 1V
• Thinner hybrid stacks suggest lower trapping densities
– However, scaled stacks “takes off” at 1.5V and beyond (see next slide)
– Interpretation of the data is not straightforward…
-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0
1010
1011
1012
Fixed Amplitude CPVamp = 1.2 V
Vbase = -1.5 to 0 V
Freq = 1 MHztr, tf = 100ns
Variable Amplitude CPVbase = -1 V
Vtop = -1 to 2 V
Freq = 100kHztr, tf = 100ns
Nit
or
Nt [
#/cy
cle*
cm2 ]
Vbase [V] or Vtop [V]
30/15 Hybrid 20/15 Hybrid 15/15 Hybrid
30 Å HfO2 20 Å HfO2 15 Å HfO2
15 Å HfSixOy
15 Å HfSixOy15 Å HfSixOy
30/15 Hybrid
20/15 Hybrid15/15 Hybrid
Si Substrate
SiO2 IL 10 Å
30 Å HfO2 20 Å HfO2 15 Å HfO2
15 Å HfSixOy
15 Å HfSixOy15 Å HfSixOy
30/15 Hybrid
20/15 Hybrid15/15 Hybrid
Si Substrate
SiO2 IL 10 Å
30 Å HfO2 20 Å HfO2 15 Å HfO2
15 Å HfSixOy
15 Å HfSixOy15 Å HfSixOy
30/15 Hybrid
20/15 Hybrid15/15 Hybrid
Si Substrate
SiO2 IL 10 Å
Variable Amplitude CP Current and Gate Leakage CurrentVariable Amplitude CP Current and Gate Leakage Current
• Gate leakage is present in accumulation from gate to substrate• In inversion, leakage component flows from source/drain to gate
– Indirectly measured by enhancement in Icp due to enhanced carrier supply (enhanced injection)
– S/D leakage current goes in the opposite direction of measured Icp, therefore not “directly” measured
-1.0 -0.5 0.0 0.5 1.0 1.5 2.0
10-15
10-14
10-13
10-12
10-11
10-10
10-9
10-8
10-7
10-6
Variable Amplitude CPVbase = -1 V
Vtop = -1 to 2 V
Freq = 100kHztr, tf = 100ns
I S/D
or
I cp [
A]
Vtop [V]
1 MHz 100 kHz 10 kHz
closed symbols: S/D Leakageopen symbols: Icp
Icp
I(d,g)I(s,g)
INV
Icp
I(d,g)I(s,g)
ACC
Ig
Charge Pumping for Process CharacterizationCharge Pumping for Process Characterization
3.5 nm HfSiO (20%) – 700C/800C N2O PDA
Reduced Nt values and flatter Nt –Vpeak curves suggest that the higher temperature N2O PDA increases the interfacial layer thereby increasing the tunneling distance to traps in this silicate gate stack.
Fixed Base, Variable Amplitude Charge Pumping (into inversion)
-1.0 -0.5 0.0 0.5 1.0 1.5109
1010
1011
1012
nFET W/L = 10/1 m
Vbase = -1.0V
Nt [
#/cy
cle*
cm2 ]
Vpeak [V]
1 MHz N2O 800oC
100 kHz N2O 800oC
10 kHz N2O 800oC
1 MHz N2O 700oC
100 kHz N2O 700oC
10 kHz N2O 700oC
DigitizingO-scope
PulseGenerator
RL
VDD
VD
Vg
Pulsed Transient Charge Trapping Measurement SetupPulsed Transient Charge Trapping Measurement Setup
• Single Pulse Input:
Width: 5s< tPW < 100 s
Rise, Fall times: tR=tF= 5-100 s
• RL typically ~ 300 ohms
• VDD typically 100 mV
• Output VD pulse is digitized as 5000 readings versus time
• ID-VG and ID- time plots formed from
ID (0.1V) = 0.1 * (VDD/VD – 1)/RL
• Device W/L and series resistance normalization applied as needed
Transient Charging in High- Gate StacksTransient Charging in High- Gate Stacks• “Single Pulse” Id-Vg
characteristics for different inversion biases illustrating increased trapping (Vt shift) with increased inversion bias from substrate injected electrons for nMOS and negligible trapping for pMOS at these bias conditions
• The included nMOS DC ramp Id-Vg result demonstrates the effect of charge trapping during the slower measurement
-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.00
100
200
300
400
500
pMOS nMOS 1 to -1.5 V -1 to 1 V 1 to -2 V -1 to 1.5 V 1 to -2.5 V -1 to 2 V 1 to -2.7 V -1 to 2.2 V
nMOS DC Id-V
g
1nm SiO2/3 nm HfO
2 Stack
Dra
in C
urr
ent
[A
]
Gate Voltage [V]
PW
tr
tf
Vg Pulse Height
tr, t
f = 5 s; PW = 100 s
nFET W/L = 10/0.5 m Vd = 0.1V
tr t
f
Vt shift
Plausible Charging ModelPlausible Charging Model
• The inversion channel electrons are lost due to tunneling through the interfacial layer and into the high- trap sites
• Thinner interface layers result in faster trapping
• Substrate injected electrons result in the decreased drive current and mobility seen in conventional DC measurement techniques
Gate Stack Conduction Bands Substrate Injected Electrons
High- Layer
1nm SiO2
Layer
Single Pulse Output Data and AnalysisSingle Pulse Output Data and Analysis
• Ih this case, the Vt is measured at 50% of the max Id on 10 m x 1 m nFETs
– The Vt is a composite effect of trapping and de-trapping• Charge trapping increases with increasing inversion bias• Note that the vertical drop at Vg = 2.5V on the Id-Vg curve is
associated with the droop at the top of the Id – time current pulse.
0.0 0.5 1.0 1.5 2.0 2.5 3.00
50
100
150
200
250
300
350
tf
tr
tftr
PW
Dra
in C
urr
ent
[A
]
Gate Voltage [V]
Vg = -1 to 2.5 V
PW = 100 str, tf = 5s
PWVt
0 50 100 150 200 2500
50
100
150
200
250
300
350
PW = Pulse Width
Vg = -1 to 2.5 V
PW = 100 str, tf = 5s
Dra
in C
urr
ent
[A
]
Time [s]
tftr
PW
tr tf
max Id
Measurement ComparisonMeasurement Comparison
• CVS with interspersed CV, variable amplitude charge pumping, and fast transient single pulse
• MOCVD Hafnium silicate of varying physical thickness, all with poly electrode– 2.5, 3.5, 4.0, 4.5 nm
Variable Amplitude Charge PumpingVariable Amplitude Charge Pumping
-1.0 -0.5 0.0 0.5 1.0 1.5 2.0109
1010
1011
1012
Vbase = -1.0V
Nt [
#/cy
cle*
cm2 ]
Vtop [V]
4.5 nm Silicate 4 nm Silicate 3.5 nm Silicate
• Variable amplitude CP was set up to mimic the single pulse as close as possible
• The trapped charge value is take on the final pulse (i.e., -1 to 2 V)
• Remember: Charge pumping measures a recombination current
2.5 kHz
100s 100s 100s 100s
Single Pulse MeasurementsSingle Pulse Measurements
0.0 0.5 1.0 1.5 2.0 2.50
20
40
60
80
100
120
140
160
180
200
220
240 O3/4.5 nm Silicate
Charging Time = 100 s
Dra
in C
urr
ent
[A
]
Gate Voltage [V]
Vg = 1 V
Vg = 1.5 V
Vg = 2 V
Vg = 2.2 V
0.0 0.5 1.0 1.5 2.0 2.50
20406080
100120140160180200220240260280300
O3/4 nm Silicate
Charging Time = 100 s
Dra
in C
urr
ent
[A
]
Gate Voltage [V]
Vg = 1 V
Vg = 1.5 V
Vg = 2 V
Vg = 2.2 V
0.0 0.5 1.0 1.5 2.0 2.50
20406080
100120140160180200220240260280
Charging Time = 100 s
Dra
in C
urr
ent
[A
]
Gate Voltage [V]
Vg = 1 V
Vg = 1.5 V
Vg = 2 V
Vg = 2.2 V
O3/2.5 nm Silicate • Single pulse measurement– 10x1 Transistors– tr, tf, PW = 100 s– Pulse base = -1 V
• Hysteresis reduces as the nominal physical thickness reduces
• Time settings used may still have some transient chargeing in the results
Comparison ResultsComparison Results• Due to relaxation and
measuring around Vfb for the CVS with CV technique, trapped charge is lost
• Single pulse values for Vt show that ~100 mV shift equates to ~1E11/cm2 trapped charge
• Variable amplitude CP is on the same order of magnitude but 4x-5x less than single pulse
• All samples have O3 interfacial layer
For comparison, trapped charge is assumed to be at the silicon substrate interface
1011
1012
1013
20% SiO2 HfSixOy Nominal Physical Thickness
Vstress = 2V
Nt a
t S
i In
terf
ace
[#/c
m2 ]
Single Pulse @ tr, tf, PW = 100s
Var Amp CP @ 2.5 kHz w/ tr, tf = 100s
CVS with CV @ 0.16 sec CVS with CV @ 205 sec
TooLeaky
Ultra-short Pulse I-V Characterization of the Intrinsic Behavior of High- Devices
Ultra-short Pulse I-V Characterization of the Intrinsic Behavior of High- Devices
ApproachApproach• System: Hafnium-based gate dielectric
stacks with polysilicon gates• Method: Ultra-short pulse I-V technique
in the nanosecond range • Goal: Illustrate negligible charge
trapping with improved measurement performance through the use of an ultra-short pulse-based I-V technique
– The findings presented herein suggest that the nanosecond capability provide close-to-intrinsic properties of high- gate stack structures over the previous mentioned time settings
Effect of Interfacial Layer on ChargingEffect of Interfacial Layer on Charging
• In order to achieve EOTs below ~0.8 nm, scaling of the interfacial layer (IL) may be required
• This reduces the tunneling distance to the high- bulk traps
• Trapping may occur on the rise time of the pulse which has typically been assumed to be void of trapping
0.0 0.5 1.0 1.5 2.00
50
100
150
200
250
300
350
400
tr
tr
PW
Dra
in C
urr
ent
[A
]
Gate Voltage [V]
Rise Time of Pulse 5 s 100 s 1 ms DC Ramp
• HF Last Interface Treatment• Physically ~0.4-0.6 nm thick IL• Nitrogen baring IL
High-: 5 nm ALD HfO2
Nanosecond Pulse Set UpNanosecond Pulse Set Up
• In order to ensure “close-to-intrinsic” properties of high- stacks, an ultra-short pulse I-V capability with faster acquisition times is required
Vd
Output
Vg
Input
Vd
Output
Vg
Input
Trigger
Scope
Pulse Generator
4200-SCSDC bias/Control
GP
IB
Trigger
Digital O-Scope
Pulse Generator
Bias Tees
Vg
Vd
4200 – SCSDC bias/Control
VDD
Pick-offTee
Trigger
Scope
Pulse Generator
4200-SCSDC bias/Control
GP
IB
Trigger
Digital O-Scope
Pulse Generator
Bias Tees
Vg
Vd
4200 – SCSDC bias/Control
VDD
Pick-offTee
ApplicationsApplications
Single Pulse
Id – Vg
Id – Time
Ramped Pulse I-V
Id – Vg
Id – Vd
= Data points are averaged here for ramped pulse I-V
Time
Vg
Vd
Time
Vg
Vd
tr tr
Vg
Vd
tr tr
Vg
Vd
Benchmark/Calibration of a 35 ns Pulse WidthBenchmark/Calibration of a 35 ns Pulse Width
0.0 0.5 1.0 1.5 2.00
100
200
300
400
500
600
700
ISSG SiO2 Control
nFET W/L = 10/0.5mVd = 100mV
35 ns Pulse, tr = tf = 2ns
DC Ramp
Dra
in C
urr
ent
[A
]
Gate Voltage [V]
a)
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.60
50
100
150
200
250
300
350
Vg = 0.5 V
Vg = 1.0 V
Dra
in C
urr
ent
[A
/m
]
Drain Voltage [V]
DC Ramp Pulse
Vg = 1.5 V
b)
• Benchmark and calibration were carried out on a SiO2 control oxide– Pulse width = 35 ns, rise and fall times = 2 ns– Ground-Signal-Ground (G-S-G) probes, connections, and
devices were used
Ramped Pulse Id-Vg Ramped Pulse Id-Vd
Drive Current DegradationDrive Current Degradation• Pulsed Id versus time
characteristics illustrating the degradation in drive current over time due to channel electron trapping into the high-
– a) Pulse width = 50 ns– b) Pulse width = 100 s,
50 s, and 10 s– Charge trapping
degradation of Id can be seen
0 50 100 150 200
0.0
0.2
0.4
0.6
0.8
1.0
0.0
0.2
0.4
0.6
0.8
1.0
b) tf
tr
PW
No
rmal
ized
Dra
in C
urr
ent
Time [s]
Pulse Width 100 s 50 s 10 s
tr
Id Degradation due to charge trapping
tf = t
r = 5s
50 ns pulse width, tr = t
f = 25ns
a)
Expanded Ultra-Short Pulse ResultExpanded Ultra-Short Pulse Result
0 50 100 150 200
0.0
0.2
0.4
0.6
0.8
1.0
0 20 40 60 80 100
0.0
0.2
0.4
0.6
0.8
1.0
tftr
PW
No
rma
lize
d D
rain
Cu
rre
nt
Time [ns]
Vg = -1 to 2.5 V
PW = 50 nstr, tf = 25 ns
N
orm
aliz
ed D
rain
Cu
rren
t
Time [s]
Note: Time scale difference
• Pulsed Id versus time characteristics illustrating no observable degradation in drive current over time due to the lack of channel electron trapping in the high-
• No Id degradation seen in the thin interfacial layer sample (right)
30 40 50 60 70 80 90 1000
50
100
150
200
250
300
350
400
450
tf
tr
PW
Dra
in C
urr
ent
[A
]
Time [ns]
Vg = -1 to 2 V
PW = 45 nstr, t
f = 20 ns
HF Last Interface Treatment
Comparison of “Old” to “New” Comparison of “Old” to “New”
• Single pulse charge trapping measurement on HfSixOy NMOS transistors:
– Rise and fall time of the pulse is 25 ns and the pulse width is 50 ns with no hysteresis in two Id-Vg curves using the ultra-short pulse set up
– Rise and fall time of the pulse is 5 s and the pulse width is 5 s with hysteresis and “noise” in the Id-Vg curves using the set up previously reported
0.0 0.5 1.0 1.5 2.00
50100150200250300350400450
O3/4.5 nm HfSixOy
nFET W/L = 10/0.5 mVd = 100 mV
tftr
PW
Dra
in C
urr
ent
[A
]
Gate Voltage [V]
Vg = -1 to 2 V
PW = 5 str, tf = 5 str tf
0.0 0.5 1.0 1.5 2.00
50100150200250300350400450
O3/4.5 nm HfSixOy
nFET W/L = 10/0.5 mVd = 100 mV
tf
tftr
PW
Dra
in C
urr
ent
[A
]
Gate Voltage [V]
Vg = -1 to 2 V
PW = 50 nstr, tf = 25 nstr
Old New
Application of Ultra-short Ramped PulseApplication of Ultra-short Ramped Pulse
0.0 0.4 0.8 1.2 1.6 2.00
50100150200250300350400450500
1nm SiO2/3 nm HfO2 Stack
nFET W/L = 10/0.5mVd = 100mV
35 ns pulse, tr = tf = 2ns
Dra
in C
urr
ent
[A
]
Gate Voltage [V]
DC Rampa)
0.0 0.4 0.8 1.2 1.6 2.00
50
100
150
200
250
300
350
b)
Dra
in C
urr
ent
[A
/m
]
Drain Voltage [V]
35 ns Pulse, tr = tf = 2ns
DC Ramp
Vg = 1.8 V
Vg = 1.4 V
Vg = 1.0 V
• 35 ns pulse width saturation current of this high- sample has increased by as much as 40% at high Vg over conventional DC
Summary ISummary I• C-V hysteresis is good for qualitative
understanding of trapping that is occurring
• ‘Stress and sense’ loses trapped charge in the Vfb measurement– ‘Stress and sense’ with Id-Vg to monitor threshold
voltage shift is somewhat better• Variable amplitude charge pumping could
be an excellent process monitoring tool for measuring the trapped charge
• When properly done, Pulse I-V is an excellent benchmark in measuring and quantifying trapped charge in high- gate stacks
Summary IISummary II
• Thin interfacial layers result in faster trapping, thereby reducing the time for the onset of transient charging
• A unique nanosecond regime pulse I-V measurement allows close-to-intrinsic characterization of high- gate stacks due to no observable trapped charge in pulsed I-V characterization
• Ultra-short pulse I-V demonstrates significant improvement in high- device performance when compared to DC methods
Comparison of “Trap-Free” Mobility Extraction Techniques for High- Gate Dielectrics
Comparison of “Trap-Free” Mobility Extraction Techniques for High- Gate Dielectrics
OutlineOutline• Introduction/Motivation• Approach• Mobility Extraction Techniques
– Split C-V– NCSU CVC and Mob2d– Kerber, et al, pulsed mobility extraction– Combine pulsed Id-Vg with CVC and Mob2d
• Application/Evaluation of Mobility Extraction Methods
• Summary
ApproachApproach
• System: Hafnium-based gate stacks and control SiO2
• Method: Various mobility extraction algorithms:– Conventional split C-V ( benchmark)– NCSU CVC and Mob2d– Kerber, et al, pulsed mobility methodology– NEW Combine Pulsed Id-Vg, CVC, and
Mob2d• Goal: To evaluate and compare “intrinsic”
mobility extraction techniques in the presence of trapped charge
Split C-V Mobility ExtractionSplit C-V Mobility Extraction
-0.5 0.0 0.5 1.0 1.50
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7
0.0 0.5 1.0 1.5 2.00
2
4
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8
10
12
14 4T Silicate/NH3 700oC PDA
nFET W/L = 20/20m
Vd = 40 mV
Vd = 20 mV
Dra
in C
urr
en
t [A
]
Gate Voltage [V]
C
apac
itan
ce [
pF
]
Voltage [V]
Inversion C-V
Qinv
• Measurements– Separately measured inversion and depletion C-V characteristics at
100 kHz on W/L = 20/20 m– Integrate C-V curve (area under the curve) to obtain Qinv and Qb
– Channel conductance from differential Id-Vg measurements at 20 mV and 40 mV
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
0
50
100
150
200
250
Mobility Universal
4T Hf Silicate/NH3 700oC PDA
Eff
ecti
ve M
ob
ilit
y [c
m2 /V
*sec
]
Effective Field [MV/cm]
inv
mVdmVd
invd
deff QmV
II
QL
WV
I
1202040
osi
invb
eff
QQE
2
0.0 0.5 1.0 1.5 2.0105
106
107
108
109
1010
1011
1012
1013
1014
N
inv
[#/c
m2 ]
Gate Voltage [V]
Split CV N inv
Mob2d N inv
Split CV and Mob2d DifferencesSplit CV and Mob2d Differences
• Split C-V Ninv does not approach zero
• Since Qinv is in the denominator, mobility goes to zero (Id is small)
• Difference in Mob2d model Id to measured Id creates the up-turn in the low field regime0.0 0.5 1.0 1.5 2.0
10-12
10-11
10-10
10-9
10-8
10-7
10-6
10-5
10-4
Dra
in C
urr
en
t [A
]
Gate Voltage [V]
Id
Id model
0.2 0.4 0.6 0.8 1.0 1.2 1.4
0
50
100
150
200
250
300
350
Eff
ecti
ve E
lect
ron
Mo
bili
ty [
cm2 /V
*sec
]
Effective Field [MV/cm]
Split CV Fit to gd Fit to gm Universal
CVC and Mob2d2nm SiO2 Control
20 x 20 m2
Kerber Mobility ExtractionKerber Mobility Extraction
• Technique directly measures Ninv and uses pulse Id-Vg data
• Ninv is extracted by taking advantage of the geometric component in charge pumping measurements– Measure Icp using fast rise, fall times and long
channel device (Icp includes Ninv and Ntrap)– Use proper CP methodology to extract Ntrap
– Subtract Ntrap to leave only Ninv
• Pulse Id-Vg data collected• Calculate the Eeff and eff
NEW: Pulsed Id-Vg with CVC and Mob2dNEW: Pulsed Id-Vg with CVC and Mob2d
• CVC provides EOT (Cox), substrate doping (Nsub), and poly doping (Npoly) to Mob2d for the mobility extraction– C-V hysteresis data should be evaluated by CVC
to determine if there are any differences in extracted Cox, Nsub, and Npoly
– Nsub from CVC should be robust since Cmin is not significantly affected by trapped charge
– Cox is extracted from the depletion and accumulation where trapped charge is minimal
Pulsed Id-Vg with CVC and Mob2d (cont.)Pulsed Id-Vg with CVC and Mob2d (cont.)
• CVC on forward and backsweep C-V data shows no significant change in Nsub, Cox, Npoly
• A “trap free” Id-Vg curve is done with the pulsed measurement
• With CVC of the transistor and pulsed Id-Vg of a 10x1 m2 transistor, Mob2d can be executed to provide a “trap free” mobility
CVC Model Accum to Inv
0
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8
-2 -1.5 -1 -0.5 0 0.5 1 1.5 2
Voltage [V]
Cap
acit
ance
[p
F]
Series1Series2
cvc model parametersEOT = 16.3 Å
Nsurf = 4.86E17 /ccVfb = -0.844 V
RMS fit error = 2.4%Npoly = 7.38E19 /cc
CVC Model Inv to Accum
0
1
2
3
4
5
6
7
8
-2 -1.5 -1 -0.5 0 0.5 1 1.5 2
Voltage [V]
Cap
acit
ance
[p
F]
Series1Series2
cvc model parametersEOT = 16.6 Å
Nsurf = 5.64E17 /ccVfb = -0.805 V
RMS fit error = 3.2%Npoly = 7.13E19 /cc
Accumulation Inversion Inversion AccumulationO3/3 nm ALD HfO2/Poly
CVC/Mob2d With Pulsed Id-Vg on 2 nm SiO2CVC/Mob2d With Pulsed Id-Vg on 2 nm SiO2
0.2 0.4 0.6 0.8 1.0 1.2 1.450
100
150
200
250
300
350
Eff
ecti
ve E
lect
ron
Mo
bili
ty [
cm2 /V
*sec
]
Effective Field [MV/cm]
Conventional Pulsed w/ Mob2d Universal
2nm ISSG ControlConventional 20x20Pulsed on Normalized 10x1Dimensions in m
CVC and Mob2d
• Demonstration of CVC/Mob2d with Pulsed Id-Vg on control SiO2 sample yields excellent agreement with CVC/Mob2d with DC Id-Vg
CVC/Mob2d Extraction and Kerber (cont.)CVC/Mob2d Extraction and Kerber (cont.)
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
0
50
100
150
200
250
300
350
400
Eff
ecti
ve M
ob
ility
[cm
2 /V*s
ec]
Effective Field [MV/cm]
Split CV Mob Kerber Pulse Mob CVC/Mob2d Pulse Mob Universal
O3/MOCVD 20/15 Hybrid Stack/Poly
NH3 700oC PDA
• Excellent agreement between CVC/Mob2d and Kerber
• High field mobility is quite close to the universal electron mobility for the particular samples shown
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
0
50
100
150
200
250
300
350
400
Eff
ecti
ve M
ob
ility
[cm
2 /V*s
ec]
Effective Field [MV/cm]
Split CV Mob Kerber Pulse Mob CVC/Mob2d Pulse Mob Universal
O3/MOCVD 15/15 Hybrid Stack/Poly
NH3 700oC PDA
SummarySummary
• CVC and Mob2d on 2 nm SiO2
– Split C-V and Mob2d eff vs. Eeff ~ same in the high field while split C-V is shifted and lower in the low field regime
• NEW - Pulsed Id-Vg with CVC/Mob2d– Requires only two measurements (C-V and pulsed
Id-Vg)– Simple, automated analysis/extraction verified on
SiO2
– Excellent agreement when benchmarked with Kerber for high- samples used
Threshold Voltage Instability: Electron Trapping
0 1000 2000 3000 4000-150
-100
-50
0
50
100
150
200
1000sec Vg=-0.5V
2nd CVS stress1~1000sec
1000sec Vg=-0.5V
Vt (
mV
)Stress time (sec)
1st CVS stress1~1000sec
Initial
De-trapping Vg=-0.5V
0 1000 2000 3000 4000 50000.4
0.5
0.6
0.7
0.8
Vt (
V)
Stress time
De-trapping Vg=-1V (10sec)
MOCVD HfSiO(20%) Vg=2.2V 1,000sec
Reversible and repeatable electron trapping
Sim et al, SSDM 2004
Minimal trap generation: filling pre-existing traps
Trapping processes:Fast initial – Slow long stress
ReferencesReferencesA. Kerber, et al, presented at INFOS, Barcelona, Spain, pp. WS1-5, June 2003
G. Groeseneken, et al., "A reliable approach to charge-pumping measurements in MOS transistors," IEEE Transactions on Electron Devices, vol. ED-31, pp. 42-53, 1984.
C.D. Young, et al., “Charge Trapping and Mobility Degradation in MOCVD Hf Silicate Gate Dielectric Stack Structures,” presented at ESC Conference, Orlando,FL, Oct. 12-16, 2003.
Y. Zhao, C.D. Young, and G.A. Brown, Semiconductor International, Oct. 2003, pp. 51
S. Zafar, et. al., Applied Physics Letters, Vol 81, No. 14, p. 2608, 2002
S. Zafar, et. al., Journal of Applied Physics, Vol 93, p. 9298, 2002
ReferencesReferences•[1] G. Bersuker, P. Zeitzoff, J. Barnett, N. Moumen, B. Foran, C. D. Young, J. J. Peterson, and P. Lysaght, "Interface-Induced Mobility Degradation in High-k Transistors," Japanese Journal of Applied Physics, vol. 43, pp. 7899, 2004.•[2] G. Bersuker, J. H. Sim, C. D. Young, R. Choi, P. Zeitzoff, G. A. Brown, B. H. Lee, and R. W. Murto, "Effects of Pre-existing Defects on Reliability Assessment of High-K Gate Dielectrics," Microelectronics Reliability, vol. 44, pp. 1509, 2004.•[3] G. Bersuker, J. H. Sim, C. D. Young, R. Choi, B. H. Lee, P. Lysaght, G. A. Brown, P. Zeitzoff, M. Gardner, R. W. Murto, and H. R. Huff, "Effects of Structural Properties of Hf-Based Gate Stack on Transistor Performance," presented at 2004 Spring Meeting of the Material Research Society, 2004.•[4] G. Bersuker, P. Zeitzoff, J. H. Sim, B. H. Lee, R. Choi, G. A. Brown, and C. D. Young, "Mobility Evaluation in High-K Devices," presented at IEEE Intl. Integrated Reliability Workshop Final Report, 2004.•[5] R. Choi, S. Rhee, J. C. Lee, B. H. Lee, and G. Bersuker, "Charge trapping and detrapping characteristics in hafnium silicate gate stack under static and dynamic stress," IEEE Electron Device Letters, vol. 26, pp. 197, 2005.•[6] J. R. Hauser, "Extraction of experimental mobility data for MOS devices," IEEE Transactions on Electron Devices, vol. 43, pp. 1981, 1996.•[7] A. Kerber, E. Cartier, L. Pantisano, R. Degraeve, T. Kauerauf, Y. Kim, A. Hou, G. Groeseneken, H. E. Maes, and U. Schwalke, "Origin of the threshold voltage instability in SiO2/HfO2 dual layer gate dielectrics," IEEE Electron Device Letters, vol. 24, pp. 87, 2003.•[8] A. Kerber, E. Cartier, L. Pantisano, M. Rosmeulen, R. Degraeve, T. Kauerauf, G. Groeseneken, H. E. Maes, and U. Schwalke, "Characterization of the VT instability in SiO2/HfO2 gate dielectrics," presented at 41st Annual IEEE Intl. Reliability Physics Symp. Proc., 2003.•[9] A. Kerber, E. Cartier, L. A. Ragnarsson, M. Rosmeulen, L. Pantisano, R. Degraeve, Y. Kim, and G. Groeseneken, "Direct measurement of the inversion charge in MOSFETs: application to mobility extraction in alternative gate dielectrics," presented at Symp. on VLSI Technology Digest of Tech. Papers, 2003.•[10] J. C. Lee, H. J. Cho, C. S. Kang, S. Rhee, Y. H. Kim, R. Choi, C. Y. Kang, C. Choi, and M. Abkar, "High-k dielectrics and MOSFET characteristics," presented at IEEE Intl. Electron Devices Meeting Tech. Digest, 2003.•[11] B. H. Lee, C. D. Young, R. Choi, J. H. Sim, G. Bersuker, C. Y. Kang, R. Harris, G. A. Brown, K. Matthews, S. C. Song, N. Moumen, J. Barnett, P. Lysaght, K. S. Choi, H. C. Wen, C. Huffman, H. Alshareef, P. Majhi, S. Gopalan, J. J. Peterson, P. Kirsh, H.-J. Li, J. Gutt, M. Gardner, H. R. Huff, P. Zeitzoff, R. W. Murto, L. Larson, and C. Ramiller, "Intrinsic Characteristics of High-k Devices and Implications of Fast Transient Charging Effects (FTCE)," presented at IEEE Intl. Electron Devices Meeting Tech. Digest, 2004.•[12] C. Leroux, J. Mitard, G. Ghibaudo, X. Garros, G. Reimbold, B. Guillaumot, and F. Martin, "Characterization and modeling of hysteresis phenomena in high K dielectrics," presented at IEEE Intl. Electron Devices Meeting Tech. Digest, 2004.•[13] C. G. Sodini, T. W. Ekstedt, and J. L. Moll, "Charge accumulation and mobility in thin dielectric MOS transistors," Solid State Electronics, vol. 25, pp. 833, 1982.
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Bennett, C. H. Lee, S. Gopalan, M. Gardner, P. M. Zeitzoff, G. Groeseneken, R. W. Murto, and H. R. Huff, "Charge Trapping and Mobility Degradation in MOCVD Hafnium Silicate Gate Dielectric Stack Structures," presented at 203rd Fall Meeting of the Electrochemical Society, Physics and Technology of High-K Gate Dielectrics - II, Orlando, FL, 2003.
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