Assoc. Prof. Dr. Mohamed Ragaa Balboul

ELCT 705 :Semiconductor Technology

Lecture 02: CMOS Process Flow (1)

Department of Electronic and Electrical Engineering

SemiconductorsSemiconductors are a class of materials which have the unique property that their electrical conductivity can be controlled over a very wide range by the introduction of dopants.

Silicon (as a representative semiconductor) has four electron in its outermost shell. These are the valence electrons since they are the participants in chemical reactions and chemical bonding.

Silicon Semiconductor Properties

Electron

Hole

Free Electron

Bound Electron

Eg

EC

EV

IntrinsicCarrier

generation

At temperature above absolute zero, thermal energy can break some of the Si-Si bonds. This creates both a free or mobile electron and a mobile hole.

The concentrations of electrons and holes are exactly equal in pure semiconductors are referred to as the intrinsic carrier concentration(ni)

In this case n =p, so it is true that np = (ni)2 = NC NV exp (-Eg /kT)

Dopant Atoms

VIII IV VI

II

Dopants are atoms that generally contain either one more or one fewer electrons in their outermost shell than the host semiconductor. They provide one extra electron (column V) or one missing electron (column III) (a “hole”) compared to the host atoms.

ND and NA are used to refer to the N-type (donor) and P-type (acceptor) concentrations, respectively.

Dopant Atoms and Energy Levels

Free Electron

Bound Electron

EC

EVEA

ED

P Doping

N Doping

Mobile Hole

The introduction of dopants is represented in the band diagram by the ED

(donor) and EA (acceptor) energy levels.

The energy difference between EV (EC) and EA (ED) represents the binding energy of the hole (electron) to the B (As) atom and is small in the case of a shallow acceptor (donor).

The pn Junction Diode

Physics of semiconductor devices.

NA p - type accepter concentrationsND n - type donor concentrations

2ln

i

DAbi

n

NN

q

kTV

bi

DA

DA VNN

NN

qW

2

All parameters are mainly dependent on NA and ND which should be perfectly controlled during fabrication.

Metal-Oxide-Semiconductor

The threshold voltage equals the sum of the flat band voltage, twice the bulk potential and the voltage across the oxide due to the depletion layer charge, or:

ox

fAs

fFBthC

qNVV

42

MOSFET is off MOSFET is on

Physics of semiconductor devices.

Metal-Oxide-Semiconductor

The two terms which are important NMOS and PMOS are the doping concentration in the silicon NA and the oxide capacitance Cox. Since Cox is

inversely proportional to the gate oxide thickness, it is clear that we must control this thickness in order to control the Vth.

The threshold voltage equals the sum of the flat band voltage, twice the bulk potential and the voltage across the oxide due to the depletion layer charge, or:

Physics of semiconductor devices.

ox

fAs

fFBthC

qNVV

42

Complementary Metal Oxide Semiconductor

What should you know? Physics of semiconductor devices.

Crystal growth, wafer fabrication and basic properties of silicon wafer.

Thermal oxidation and the Si/SiO2 interface.

Lithography.

Dopant diffusion.

Ion implantation.

Thin film deposition.

Etching.

Simple CMOS CircuitsTo build a simple inverter circuit, we need a technology that can integrate NMOS and PMOS devices on the same chip.

Process described here will require 16 masks and > 100 process steps.

PMOS

NMOS

Inverter circuit

Final CMOS Integrated Circuits

P -Type

N Well

NN

P+ P WellN+

Cross section of final CMOS integrated circuit. A PMOS transistor is shown on the left, an NMOS device on the right.

G G

D D

S S

Sub Sub

G GS D S D

Wafer Selection

Basic CMOS Process Flow

The beginning - Choosing a Substrate

Before we begin actual wafer fabrication, we must choose the starting wafers. In general this means specifying

Wafer type (P or N),

Resistivity (doping level),

Crystal orientation,

Wafer size,

Wafer flatness,

Trace impurity levels,

In most CMOS IC’s the substrate the substrate has a resistivity of (25-50 W cm) which corresponding to a doping level on the order of 1015 cm-3.

The major parameter we need to specify in the starting substrate is the crystal orientation. There are two principle Si crystal orientations that are used in IC’s (111) and (100).

Wafer Resistivity (doping level)

n electron concentrationsp hole concentrationsmn electron mobilitymp hole mobility

In general only one of the two terms in equation is significant since n » p in N-doped and p » n in P-doped silicon wafer.

Why (100) ?

(100) (111)

All modern Si IC’s are manufactured today from wafer with a (100) surface orientation.

The principal reason for this is that the properties of the Si/SiO2 interface are significantly better when a (100) crystal is used.

The key idea is that the electrical properties of this interface are intimately connected with the atomic bonding between Si and O when an SiO2 layer is thermally grown on Si.

It is found experimentally that there are fewer imperfections (unsatisfied bonds) on a (100) surface than on (111).

Wafer cleaning

1st Process Step

Wafer Cleaning

The wafers are first cleaned in a combination of chemical baths that remove any impurities from the surface.

RCA clean is “standard process” for front-end chemical cleaning.

1. Removal of the organic contaminants

2. Removal of thin oxide layer

3. Removal of ionic contamination

Si, (100), P Type, 25-50 Wcm

RCA Cleaning ProcedureH2SO4/H2O2

(120 -150 oC 10 min)

H2O/HF

(Room 1 min)

DI (Distilled) H2O Rinse

(Room 1 min)

SC-1 HN4OH/H2O2/H2O

(80 -90 oC 10 min)

DI (Distilled) H2O Rinse

(Room 1 min)

SC-1 HCI/H2O2/H2O

(80 -90 oC 10 min)

DI (Distilled) H2O Rinse

(Room 1 min)

Strips organics especially photoresist

Strips chemical oxide

Strips organics, metals & particles

Strips alkali ions and metals

Active Region Formation

2nd Process Step

Active Region FormationIn designing such circuits, it is usually assumed that the individual devices do not interact with each other except through their circuit interconnections.

We need to be sure that the individual devices on the chip are electricallyisolated from each other.

This is accomplished most often by growing a fairly thick layer of SiO2 in between each of the active devices.

SiO2 is essentially a perfect insulator and provides the needed isolation.

The regions between these thick SiO2 are called the “active” regions of the substrate.

Si, (100), P Type, 25-50 Wcm

Deposition of Thin SiO2 LayerThis process of locally oxidizing the silicon substrate is known as the LOCOS process (Local Oxidation of Silicon).

A thermal SiO2 layer is then grown on the Si surface by placing the wafers in a high-temperature furnace.

Si, (100), P Type, 25-50 Wcm

SiO2

The oxide growth rate is much slower in O2 compared to H2O, so higher temp. and/or longer time are required to grow the same oxide thickness.

A typical furnace cycle might be 15 min. at 900 oC in an H2O atmosphere.

The H2O ambient could be produced by boiling water.

It is more common today to react H2 and O2 in the back end of the furnace to produce H2O (cleaner method ).

Oxide could also be grown in a pure O2 ambient using a cycle of about 45 min at 1000 oC.

Thin SiO2 of about 40 nm

Deposition of Silicon Nitride

Si, (100), P Type, 25-50 Wcm

SiO2

Si3N4

The wafers are then transferred to a second furnace (CVD furnace) which is used to deposit a thin layer of Si3N4 (typically 80 nm). This deposition occurs when reactants line NH3 (Ammonia) and SiH4 (silane) are introduced into the furnace at a temp. of about 800 oC forming Si3N4.

3SiH4 + 4NH3 Si3N4 + 12H2

This deposition is done below atmospheric pressure (Pumps) because this produces better uniformity over larger wafer.

The deposition is done in Low Pressure Chemical Vapour Deposition (LPCVD).

The nitride layers deposited by such machines are highly stressed. This produces a large compressive stress in the underlying Si substrate which can lead to defect generation.

The stresses in the two layers in the two layers can partially compensate each other (relieve this stress).

Photoresist Coating

Si, (100), P Type, 25-50 Wcm

SiO2

Si3N4

Photoresist

The final step is the deposition of photoresist layer in preparation for masking.

Since photoresists are liquids at room temperature, they are normally spun onto the wafers.

The resist viscosity, time and the speed of spin determine the final thickness which is about 1mm.

After the photoresists is spun, it usually baked at about 100 oC in order to drive off solvents from the layer.

The potoresists are complex hydrocarbon mixtures.

Mask 1, LOCOS

Si, (100), P Type, 25-50 Wcm

SiO2

Si3N4

Photoresist

Photolithography

Si, (100), P Type, 25-50 Wcm

SiO2

Si3N4

Photoresist

UV-light

The resist is then exposed to ultraviolet (UV) light using a mask, which defines the pattern for the LOCOS regions.

The molecule in the resist which is sensitive to light, absorbs UV photons and changes its chemical structure in response to light.

Photolithography

Si, (100), P Type, 25-50 Wcm

SiO2

Si3N4

Positive resist

Removal of Photoresist

Si, (100), P Type, 25-50 Wcm

SiO2

Si3N4

The results of the photolithography is that the molecule and the resist itself dissolve in the developing solution.

Si3N4 Etching

Si, (100), P Type, 25-50 Wcm

SiO2

The Si3N4 is etched using dry etching, with the resist as a mask.

This is usually accomplished in a fluorine plasma (dray etching).

Si3N4 + 12F 3SiF4 + 2N2

Removal of Photoresist

Once the Si3N4 etching is completed, the resist can be chemically removed in sulfuric acid, or stripped in O2

plasma, neither of which significantly attacks the underlying Si3N4 and SiO2 layer.

Si, (100), P Type, 25-50 Wcm

SiO2

Thick SiO2 Layer Growth

Si, (100), P Type, 25-50 Wcm

The wafers are placed into a furnace at 1000 oC in an oxidizing ambient (H2O) for 90 min to locally grow about 500 nm (0.5 mm).

This grows a thick SiO2 layer locally on the wafer surface.

The Si3N4 layer on the surface prevents oxidation (H2O or O2) where it is present because it is very dense material.

Removal of Si3N4

Si, (100), P Type, 25-50 Wcm

The Si3N4 is stripped by hot phosphoric acid, which is highly selective between Si3N4 and SiO2.

The Si3N4 could also be removed using dry (plasma) etching.

Disadvantage of LOCOS (Bird’s Beak)

Si, (100), P Type, 25-50 Wcm

The oxidation which takes place during LOCOS process, extends for some distance under the Si3N4 edge; a larger surface region than the mask pattern.

The characteristic shape that this two-dimensional (2D) oxidation process produces is often called a bird's head or a bird beak.

The oxidation extends under the nitride edge because the oxidant can diffuse sideways as well as vertically through the pad oxide layer.

Alternative of LOCOS Process

In this process a combination of a thicker nitride (200 nm ), a thinner pad oxide (20 nm ) provides less of a pathway for lateral oxidant diffusion and a polysilicon layer which itself can oxidize along its edges during LOCOS producea much sharper transition between the oxidized and unoxidized regions.

Poly-buffered (SiO2, polysilicon, and Si3N4 ) LOCOS process:

Shallow Trench Isolation (STI): STI actually etches trenches in the silicon substrate between active devices and then refills them with SiO2.

Si, (100), P Type, 25-50 Wcm

Si, (100), P Type, 25-50 Wcm

Shallow Trench IsolationThe process begins the same way as the LOCOS process SiO2 (20 nm) and Si3N4

(100 nm) layers are thermally grown and deposited, respectively.

Then the nitride and oxide layers are etched using the photoresist as a mask.

The next step is to each the trenches in the silicon (often a bromine-based plasma chemistry is used) which are typically 0,5 mm.

The top and bottom corners of the trenches ideally need to be slightly rounded in order to avoid problems later in oxidizing.

Shallow Trench Isolation

Si, (100), P Type, 25-50 Wcm

The next step is to thermally grow (relatively at high temperature) a thin (10-20 nm) oxide on the trench sidewalls and bottoms. This process will help to round the corners of the trenches and to produces a better Si/SiO2 interface.

Then the deposition of a thick SiO2 layer using chemical vapor deposition. It is important here that the filling process not leave gaps or voids in the trenches, which could happen if the deposition closed the top part of the trench before the bottom parts were completely filled. High-Density Plasma (HDP) could be used in this application.

The final step in the STI process involves polishing the excess SiO2 off the top surface of the wafer using a technique known as Chemical Mechanical Polishing (CMP) in order to planarize the wafer surface.

Shallow Trench Isolation

Si, (100), P Type, 25-50 Wcm

The next step is to thermally grow (relatively at high temperature) a thin (10-20 nm) oxide on the trench sidewalls and bottoms. This process will help to round the corners of the trenches and to produces a better Si/SiO2 interface.

Then the deposition of a thick SiO2 layer using chemical vapor deposition. It is important here that the filling process not leave gaps or voids in the trenches, which could happen if the deposition closed the top part of the trench before the bottom parts were completely filled. High-Density Plasma (HDP) could be used in this application.

The final step in the STI process involves polishing the excess SiO2 off the top surface of the wafer using a technique known as Chemical Mechanical Polishing (CMP) in order to planarize the wafer surface.

N and P well formation

3nd Process Step

N and P Well FormationThe active devices are actually built in wells diffused into the surface of the wafer.

The doping levels in these wells are chosen to optimize the electrical properties of the active devices.

The NMOS device could actually be built directly in P substrate without adding the P well near surface.

The twin well process is much more common because the doping process use to produce the P well is much better controlled in manufacturing than the substrate doping.

The P well and N well doping concentrations are on the same order.

We can tailor the wells for the NMOS and PMOS devices individually to provide optimum device characteristics.

The well doping affects device characteristics such as the MOS transistor threshold voltage and I-V characteristics and PN junction capacitances.

Mask 2, P-Well Formation

Si, (100), P Type, 25-50 Wcm

Mask 2, P-Well Formation

Si, (100), P Type, 25-50 Wcm

Photolithography

UV-light

Mask 2, P-Well Formation

Si, (100), P Type, 25-50 Wcm

P-type Implant

First the photoresist is spun onto the wafer and mask 2 is used to expose the resist and to define the regions where P well are to be formed.

The P regions are crated by a process known as ion implanters, using a small linear accelerators.

A source of the ion to be implanted (boron) is provided, usually from gas. Positive charged ions (B+) are accelerated in an electric field to some final energy in keV.

To provide a uniform implant dose across the wafer electrostatic or mechanicalscanning is used. A dose of 5×1016 to 1017 cm-3 at energy 150-200 keV is used.

Mask 3, N-Well Formation

Si, (100), P Type, 25-50 Wcm

P-type ImplantN-type Implant

Photoresist and mask 3 are now used to define the regions where N wells will be placed. A source of the phosphors ions is implanted.

We would need to pick an implant energy sufficiently large that the P ions penetrated the thin and thick SiO2 layers (0.5 mm) on the wafer surface, but not so large that the beam penetrated through the photoresist (1 mm) which must mask against the implant.

Phosphorus is a heavier atom than boron (atomic mass 31 vs. 11), so high energy (300 – 400 keV) is required to obtain the same depth into silicon. The dose of the phosphors implant would typically be on the same order as the Boron.

Mask 3, N and P-Wells drive-in

Si, (100), P Type, 25-50 Wcm

P WellN Well

The wafer is next placed in a “drive-in” furnace which diffuses the wells to a junction depth of 2-3 microns.

The well drive-in step also repairs the damage from the implants restoring the substrate crystallinity. Since, an incoming ion with an energy of 100 keV can clearly collide with and dislodge silicon atoms (have binding energy 12 eV) in the substrate.

A typical thermal cycle might be 4 to 6 hours at 1000 to 1100 oC. The diffusion coefficient increase exponentially with temperature.

The depths they reach in this step will not be their final depths because all subsequent high temperature steps will continue to diffuse the dopants.