EL - 3 - 6

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INTRODUCTION________________________________________________________________________________________

The large-signal analysis of the differential amplifier showed that, although the

amplifier is essentially non-linear, it can be regarded as linear over a limited

operating range, that is, for small signals. In this lesson, we analyze the small-

signal behaviour of the amplifier using the h-parameter model to determine

how component and parameter values affect performance.

It is also shown how the properties of the current mirror can be used to

improve the differential gain of a single-ended output differential amplifier.

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YOUR AIMS________________________________________________________________________________________

On completing this lesson, you should be able to:

• sketch a simplified small-signal equivalent circuit of a differential

amplifier

• derive the small-signal differential and common-mode gains of a

differential amplifier from its equivalent circuit

• analyze the effects of a single-ended output upon the differential and

common-mode gains

• show how the performance of a differential amplifier can be

improved by the use of current mirrors.

1

Teesside University Open Learning(Engineering)

© Teesside University 2012

Steve

Rectangle

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STUDY ADVICE________________________________________________________________________________________

We are already familiar with the equation

By differentiating this equation with respect to VBE, we can obtain a

relationship between collector current and the dynamic base-emitter resistance

of a transistor.

Now, represents the base-emitter junction resistance of the transistor and

we will denote this parameter by re.

If we take the value of kT/e at room temperature as 25 mV and measure the

collector current in milliamperes, we get the very useful relationship:

This is the junction resistance as seen from the emitter. If this resistance is

reflected into the base, where the current is about hfe times smaller, we obtain,

approximately, the hybrid parameter hie. To achieve the conversion we

multiply re by hfe to give:

h h rie fe e=

rIe

C

= 25 Ω

dd

BE

E

VI

d

dE

BEs

BEE C

I

VI

e

kT

eV

kT

e

kTI

e

kTI= × × ⎛

⎝⎜⎞⎠⎟

= ≈exp

I I IeV

kTC E sBE≈ ≈ ⎛

⎝⎜⎞⎠⎟

exp

2



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(We have multiplied by hfe so that ibhie gives the same volt drop as iere, and so

the two resistances have the same effect, although they appear in different parts

of the circuit.)

The emitter resistance re is a very useful parameter as it is very easy to

evaluate, being determined by only two quantities, the collector current and the

operating temperature. For example, a transistor having a collector current of

1 mA, a current gain of 100 and operating at room temperature will have:

________________________________________________________________________________________

SMALL-SIGNAL ANALYSIS OF THE DIFFERENTIAL AMPLIFIER________________________________________________________________________________________

FIGURE 1 shows a differential amplifier circuit, while FIGURE 2 shows its

simplified, small-signal h-parameter model.

In drawing the equivalent circuit, the usual assumption has been made that, for

a.c. signals, the power supplies can be regarded as short circuits.

Also, in the interests of conciseness, we have labelled the input currents as

simply i1 and i2 rather than ib1 and ib2.

rI

IeC

C with expressed in mA= ( )

=

25

2511

25

100 25 2500

=

= = × =

Ω

Ωand ie fe eh h r

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FIG. 1

FIG. 2

RE

v1

RC RCvo

VE

i1

hie

hfei1 hfei2

vo2vo1

v2

i2

hie

RE

–VEE

+VCC

T2T1

v1v2

RC RC

vo

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Let's begin the analysis by establishing some basic relationships.

Applying Kirchhoff's voltage law to the inputs gives the following two equations:

Also, by Ohm's law, the collector voltages can be written in terms of the

collector currents:

From (3), making i1 the subject:

(a result we will use later)

Subtracting (2) from (1) gives:

and making i2 the subject:

i iv v

h2 11 2= –

–

ie

..................................................... 7( )

v v h i i1 2 1 2– –= ( )ie ........................................................ 6( )

iv

h R1 = o1

fe C

.................................................................. 5( )

v h R io1 fe C ..............................= 1 .................................. 3

o2

( )

=v hh R ife C .................................2 ............................... 4( )

v h i R i i h1 1 1 2 1= + +( ) +( )ie E fe ........................... 1

ie E fe

( )

= + +( ) +( )v h i R i i h2 2 1 2 1 .......................... 2( )

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To determine the double-ended differential voltage gain of the circuit

Subtracting (4) from (3) gives:

and, from (6), substituting for (i1 – i2) gives the 'double-ended' differential

voltage gain as:

That is:

We can now apply the relationship obtained in the study advice to express the

differential gain in terms of the base-emitter junction resistance:

Determination of the single-ended differential voltage gain of the circuit

Establishing this gain requires much trickier algebra, as we must obtain an

expression for just vo1 (or vo2) in terms of the input voltages. So take a deep

breath and here we go!

GR

rVDC

e

.................................= ........................ 8b( )

Gh R

hVDfe C

ie

.............................= ........................ 8a( )

v v

v v

h R

ho1 o fe C

ie

–

–2

1 2

=

v v h i i Ro1 o fe C– –2 1 2= ( )

6



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Substituting (7) into (1) for i2:

Making i1 the subject:

Now substituting for i1 from equation (5):

v

h R

v h h R v h R

h ho1

fe C

ie fe E fe E

ie i

=+ +( )( ) +( )1 21 1–

ee E fe

o1

fe C

ie fe

+ +( )( )

=+ ( ) +(

2 1

11 1 2

R h

v

h R

v h v v h– ))+ +( )( )

=+

R

h h R h

vv h h R v v

E

ie ie E fe

o1ie fe C

2 1

1 1 2–(( ) +( )+ +( )( )

1

2 1

h R h R

h h R hfe E fe C

ie ie E fe

......... 9( )

i h R h vv v

hh R

iv

1 11 2

1

2 1 1ie E feie

fe E+ +( )( ) = + +( )

=

–

11 21 1

2 1

h h R v h R

h R hie fe E fe E

ie E fe

+ +( )( ) +( )+ +( )

–

v h i R i iv v

hh

v h

1 1 1 21 2

1

1= + +⎛⎝⎜

⎞⎠⎟

+( )

=

ie Eie

fe

i

––

ee Eie

fe

ie

i R iv v

hh

v i h R

1 11 2

1 1

2 1

2

+⎛⎝⎜

⎞⎠⎟

+( )

= +

––

EE feie

fe E1 11 2+( )( ) +( )hv v

hh R–

–

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From the point of view of differential gain, this equation contains two terms :

(i) The differential term which gives the differential gain is:

If the other term could be reduced to zero (we will see how this might be done

later), the equation would become:

which gives a differential gain of:

(ii) An error term:

If, in equation (9), the two input voltages were equal, the differential term

would disappear and we would be left with:

vv h R

h R ho1fe C

ie E fe

................=+ +( )

1

2 1........................... 11( )

v h h R

h h R h

v h R

h R1 1

2 1 2ie fe C

ie ie E fe

fe C

ie+ +( )( ) =+ EE fe1 +( )h

Gv

v v

h R h R

h h R hVDo1 fe E fe C

ie ie E fe

= =+( )

+ +(1 2

1

2 1– ))( ) ( ) .............. 10

vv v h R h R

h h R ho1fe E fe C

ie ie E fe

=( ) +( )

+ +( )(1 2 1

2 1

–

))

v v h R h R

h h R h1 2 1

2 1

–( ) +( )+ +( )( )

fe E fe C

ie ie E fe

8



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We will have more to say about this error term shortly, but for the moment let

us return our attention to the differential gain.

By making a couple of reasonable approximations, much can be done to

simplify equation (10). To see how this might be done, let's put some values

in.

Calculate the differential gain, using equation (10), given that:

hie = 1 kΩ, hfe = 100, RE = 10 kΩ, RC = 20 kΩ.

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This calculation has been deliberately carried out in great detail in order to

make the required approximations stand out.

Simplify equation (10) by making the suitable approximations.

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Gh R h R

h h R hVDfe E fe C

ie ie E fe

=+( )

+ +( )( ) =+1

2 1

1 100(( ) × × × × ×+ × ×( ) +10 10 100 20 10

10 10 2 10 10 1 100

3 3

3 3 3 (( )

= × ×× × ×( )

= ×

101 2 1010 10 2 10 101

2 02 102

10

3 3 4

12...

.

021 10

999 5

9×

=

10



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Obviously we can say that (1 + hfe) ≈ hfe with only a 1% error or less. Also it is

apparent from the calculation that hie + 2RE (1 + hfe) ≈ 2hfeRE as hie << 2RE (1 + hfe).

Therefore:

Thus the differential voltage gain is approximated by:

A differential amplifier uses transistors having the parameters hfe = 200 and

hie = 1000 ΩΩ. If the collector load is 10 kΩΩ, calculate the differential voltage gain for

both double and single-ended outputs.

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Gh R

hVDfe C

ie

............................≈2

............... 12a

..........DC

e

( )

≈GR

rV 2...................................... 12b(( )

Gh R h R

h h R h

h RVD

fe E fe C

ie ie E fe

fe E=+( )

+ +( )( ) ≈1

2 1

hh R

h R h

Gh R

hV

fe C

ie E fe

Dfe C

ie

giving:

×

≈

2

2

11



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For a double-ended output,

For a single-ended output, the gain will be one half of this, i.e. 1000.

The snag with the single-ended output is that we loose half the gain. We shall

investigate shortly, though, a cunning technique which lets us have our cake

and eat it!

Common-mode gain

The differential amplifier, to be of any value, must have a high differential gain

and as low as possible common-mode gain.

First, let's consider the double-ended output.

If the circuit is exactly symmetrical (i.e. all the corresponding components and

parameters are equal), the common-mode output voltage (vo1 – vo2) will be

zero.

If the circuit is asymmetrical, as it has to be to some degree in practice, then a

common-mode output voltage will be produced. It can be shown that the

magnitude of this voltage (vocm) is given, to a good approximation, by

v v

h

h

h

h

R

R

h

h

ocm icm

ie1

ie2

fe2

fe1

C2

C1

ie1

ie2

=+

1

1

–

hh

h

R

Rfe2

fe1

E

C1

.................... ⎛⎝⎜

⎞⎠⎟

13( )

Gh R

hVDfe C

ie

≈ = × =200 10 0001000

2000

12



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where the number subscripts refer to each half of the circuit and vicm is the

common mode input voltage. It is immediately apparent that the higher the

value of RE the less the common mode output offset. For a good CMRR, we

need a high value of emitter resistor.

Now let's consider the single-ended output.

An output will obviously appear at the collector whenever the transistor

conducts. What we are interested in at this juncture is what the output will be

when the input voltages are equal.

For the circumstances under which equation (11) has been derived, what does the

voltage ratio represent?

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vvo1

1

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Equation (11) was derived from equation (9) by setting the differential input voltage

(v1 – v2) to zero. As the two input voltages are equal, the voltage ratio must represent the

common-mode gain.

Thus, for a differential amplifier with ideal components and an emitter resistor,

the single ended output common-mode gain is:

where vicm = v1 = v2.

Making any reasonable assumptions, show that the single-ended, common-mode gain

is approximately:

and hence show that the CMRR for the single-ended output of the differential

amplifier of FIGURE 2 is:

CMRR ............................fe E

ie

=h R

h............................ 16a

CMRR E

( )

=R

ree ............................................................ 16b( )

GR

RVCC

E

................................≈2

........................... 15( )

v

v

h R

h R ho

icm

fe C

ie E fe

..............1

2 1=

+ +( ) .................. 14( )

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Assuming that hie << 2RE (1 + hfe), equation (14) becomes:

and as hfe >> 1 we can say that:

and therefore:

Now, the common-mode rejection ratio is given by:

and using equations (12a) and (15):

Express in decibels the CMRR of a differential amplifier having a single-ended output

and perfectly matched transistors and collector resistors.

(RC = 10 kΩΩ RE = 20 kΩΩ hie = 1 kΩΩ hfe = 200)

If the quiescent collector current was doubled in value, what would be the new

CMRR?

CMRR fe C

ie

E

C

fe E

ie

E

e

= × = =h R

h

R

R

h R

h

R

r2

2

CMRR D

C

=G

GV

V

GR

RVCC

E

≈2

v

v

h R

R ho

1

fe C

E fe

1

2≈

v

v

h R

h R ho

icm

fe C

ie E fe

1

2 1=

+ +( )

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So, for this example:

If the quiescent collector current was doubled, the value of re would be halved

(re This would double the value of the CMRR to 8000 or 78 dB

Small signal analysis using constant current generator in the tail

The last example again serves to show that a high value of RE gives a good

CMRR. This requirement is best met by replacing the tail resistor by a

constant current generator. FIGURE 3(a) shows the equivalent circuit for such

a configuration.

FIG. 3(a)

RC RC

–VEE

hie hie

– I

vi1

vo

i1

hfei1 hfei2

vo2vo1

vi2

i2

( ).as CMRR E

E=

Rr

≈ 25IC

).

CMRR is or 72 dB.= × × =200 20 1010

40003

3

CMRR is D

C

fe C

ie

C

E

fe E

ie

= = ÷ =G

G

h R

h

R

R

h R

hV

V 2 2

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FIG. 3(b)

The constant current generator passes a constant direct current I. The ideal

current generator represents an open circuit, suggested by the dotted lines in

the equivalent circuit, and so, applying Kirchhoff's current law to the junction

of the emitters for the small signal currents, we obtain:

so forcing the conclusion that:

The use of the constant current generator in the tail gives the perfect small-

signal differential amplifier in that one current will be diminished by exactly

the same magnitude as the other is increased. When an emitter resistor is used

in the tail, this relationship is only approximate.

Applying Kirchhoff's voltage law to the inputs of the circuit (re-drawn in

FIGURE 3(b) ) gives:

v h i h i v1 1 2 2 0– –ie ie+ =

i i1 2= – ....................................................... 17( )

i h i i h i1 1 2 2 0= + + =fe fe

v1hie v2

hie

i2i1

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so that (using the relation of (17)):

Determine the single-ended differential voltage gain of the circuit.

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The potential at the collector of T1 is:

so that (from (18)) the differential gain is:

In the above example, in contrast to the derivation of equation (12), we have

not had to resort to making any approximations.

v

v v

h R

ho fe C

ie

1

1 2 2–=

v R h io C fe1 1=

v v h i h i h i1 2 1 2 12– –= =ie ie ie ...................... 18( )

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If the same signal is applied to both inputs, what will be the single-ended output

voltage? Hence comment on the CMRR.

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From equation (18), if v1 = v2 then the input current must be zero. Thus, there will be no

small signal output voltage. The common-mode gain will be zero, giving an infinite CMRR

(the best possible). This is assuming, of course, perfect circuit symmetry and an ideal

current generator (infinite output impedance).

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________________________________________________________________________________________

ACTIVE LOADS AND THE SINGLE-ENDED OUTPUT________________________________________________________________________________________

We have seen that a penalty paid for taking a single-ended output is the halving

of gain. It is possible, though, to replace the collector resistors by a current

mirror, which not only restores and even enhances the gain but is also much

easier to implement in integrated circuit form. The gain of the amplifier is

proportional to the collector load resistance, the larger the resistance the

greater the gain. But large value resistors are expensive in terms of silicon

'real estate'; not only do transistors occupy a much smaller area on the chip,

they are also easier to make.

FIGURE 4 shows the necessary circuit amendments to replace the collector

resistors by a current mirror. As transistors are active devices (in contradiction

to passive devices such as resistors), the load is called an active or dynamic

load. In FIGURE 4, we have also replaced the tail resistor by another current

mirror.

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FIG. 4

Why are pnp transistors used in the active load?

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The transistors are pnp type because the mirror is required to source a current to the two

amplifying transistors.

+VCC

–VEE

Current mirror:Constant current

generator

Current mirror: active load

Single-ended output

Differential amplifier:long-tailed pair

V2V1 T1 T2

I1 I2

T3 T4

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CIRCUIT ACTION

In order to appreciate the action of the circuit, we need to connect a single-

ended load to one of the collectors of the differential pair. This has been done

in the incremental model of FIGURE 5, where the transistors have been

represented by current generators. The current mirror forming the active load

is represented by current generators G3 and G4, the dotted line between them

intending to show that the current in G4 is controlled by that in G3. The model

is 'incremental' in the sense that only changes in current are considered, so that

the constant current generator in the tail represents an open circuit.

FIG. 5

Now allow the differential input voltage (V1 – V2) to the circuit to change by

∆V so as to produce a change in current ∆I1 from G1. The current from G3 will

also change by ∆I1 and since G3 forms the controlling half of a current mirror,

the current through G4 will be forced to change by ∆I1.

+VCC

V1

G3 G4

–VEE

hie V2hie

–

– –

– – RL ∆VL

∆ I2

∆ I1 ∆ IL

∆ I1

G1 G2

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State the relationship between ∆∆I1 and ∆∆I2. Hence, by applying Kirchhoff's current

law to the collector junction of G2, determine the change in load current in terms of

∆∆I1.

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The circuit forms the ideal differential amplifier so that the change in current through G2

will exactly counter that through G1. Thus ∆I2 = –∆I1.

Summing the change in currents at the collector of G2 :

∆I1 – ∆I2 – ∆IL = 0

and as ∆I2 = – ∆I1 :

∆I1 + ∆I1 – ∆IL = 0

so that:

∆IL = 2∆I1

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Thus, the change in load current is double the change produced in G1 (or G2

for that matter). Consequently, the change in output voltage ∆VL will also be

doubled. The active load has restored the voltage gain to that of a double-

ended output!

The active load also confers other advantages. The voltage gain is

proportional to the output load resistance RL. This resistance comprises of the

loading of the next stage, the output resistance of the amplifying transistor (T2

in this example) and the internal resistance of the current generator G4. These

three loads will act in parallel to produce an effective load of RL. The internal

resistance of the current generator will be the output resistance of the transistor

T4 and will be very high (megohms, in fact, for the very low currents at which

the input stage of an op-amp operates). The output resistance of T2 will be of

a similar order. So, providing the loading of the next stage is kept minimal, the

differential amplifier can be made to deliver a useful voltage gain (of the order

of 500).

We have already commented upon the impracticability of producing high-

valued resistors in integrated circuits. The active load solves the problem of

producing collector resistors by replacing them with a pair of transistors,

which are easier to produce and occupy much less area on the chip.

Stage loading on the output of the differential amplifier is minimized by

making it drive an emitter follower, which has a very high input resistance.

But, before we can move on to consider the next stage, we must look at some

of the problems of coupling d.c. amplifiers. This forms the opening topic of

the next lesson.

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NOTES________________________________________________________________________________________

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________________________________________________________________________________________

SELF-ASSESSMENT QUESTIONS________________________________________________________________________________________

1. FIGURE 6 shows a differential amplifier variation which uses just a

single collector resistor. All the transistors can be assumed to be identical

and the current mirror ideal.

FIG. 6

i) Sketch the amplifier's h-parameter equivalent circuit

ii) Derive expressions for the amplifier's:

(a) differential voltage gain

(b) common-mode voltage gain

iii) State which input is the non-inverting input.

2. FIGURE 7 shows the small signal equivalent circuit of a differential

amplifier with single-ended output. If it cannot be assumed that the

v1

RC

+VCC

–VEE

BA

vov2

ICONST

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transistors and collector resistors are identical, show that the common-

mode gain is approximately given by

FIG. 7

3. Show that, when symmetry is assumed, equation (19) above can be

simplified to equation (15), namely:

4. Calculate the common-mode gain of a single-ended output differential

amplifier using equation (19) and the component and parameter values

given below.

GR

RVCC

E

=

RC2 RC1

vo

hie2 hfe2i2 hfe1i1

i1hie1

RE

i2

v1v2

Gh R

h hh h

hR

VCfe1 C1

ie1 fe1ie1 fe2

ie2E

=+ +

⎛⎝⎜

⎞⎠⎟

............... 19( )

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hie1 = hie2 = 1 kΩ, hfe1 = hfe2 = 200, RE = 10 kΩ, RC = 20 kΩ

Hence, show that the simplification of equation (15) is valid.

5. A useful skill to develop is the ability to recognise particular circuit

shapes in a circuit diagram. This question gives you a little practice in

this art! FIGURE 8 shows again our internal circuitry of an op-amp. See

how many current mirrors you can spot.

FIG. 8

34Ω

34Ω39 kΩ

5 kΩ1kΩ

50kΩ

1kΩ

Offsetnull

Offset null/Comp–VCC

Inverting input Comp+VCC

Output

50kΩ 100 Ω

40kΩ

Non-invertinginput

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6. In the circuit of FIGURE 9, all the transistors have a current gain of at

least 100 and a minimum output resistance of 20 kΩ. Also, assume their

base-emitter voltages to be 0.7 V. The amplifier is to have a minimum

CMRR of 72 dB and a differential gain of at least 400. Determine:

(i) the tail current

(ii) a suitable value of RREF

(iii) the value of RC to make the quiescent output voltage 0 V

(iv) the differential gain for the value of RC calculated in (iii)

(v) the quiescent voltage at the collector of T3 with both inputs at

0 volts.

FIG. 9

–12V

+12V

RC

RREF

vo

v2v1 T2T1

T4 T3

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________________________________________________________________________________________

ANSWERS TO SELF-ASSESSMENT QUESTIONS________________________________________________________________________________________

1. (i) FIGURE 10 shows the equivalent circuit (your labelling may well be

different). The voltage across RC is shown negative as it is in the

opposite sense to the output voltage as shown in FIGURE 6.

FIG. 10

(ii) (a) Applying Kirchhoff's voltage law to the inputs gives:

from which:

Summing the currents at the emitter junction:

i h i i h i2 2 1 1 0+ + + =ie fe

v v h i i1 2 1 2– –= ( )ie ................................ 20( )

v h i h i v2 2 1 2 0– –ie ie+ =

v2

RC

i2

hie

hfei2 hfei1

–vo

v1

i1

hie

A B

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from which:

Substituting i1 for i2 in (20),

and, making i1 the subject,

Now, the output voltage vo is given by:

and, substituting from (21) for i1,

which gives a differential voltage gain of:

(The differential gain for this circuit is exactly the same as for one

having both collector resistors.)

Gv

v v

h R

hVDo fe C

ie

= =1 2 2–

–

––

v h Rv v

ho fe Cie

= × 1 2

2

–v h R io fe C= 1

iv v

h11 2

2=

–

ie

.................................... 21( )

v v h i1 2 12– = ie

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(b) The assumption of an ideal current mirror gives the relation:

as already established.

But also, from equation (20), when v2 = v1 then:

The only condition that satisfies both i2 = i1 and i2 = –i1 is

when i2 = i1 = 0. Thus there will be no small signal common-

mode output voltage and the common-mode gain is zero. (Note that

there will be a quiescent output voltage though!)

iii) Terminal A in FIGURE 6 is the non-inverting input.

2. Applying Kirchhoff's voltage law to the two input loops gives:

As hfe >> 1 for both transistors, we can make the approximation :

v h i R i h i h1 1 1 2= + +( )ie1 E fe1 fe2 ............................ 22

ie2 E fe1 f

( )

= + +v h i R i h i h2 2 1 2 ee2 ........................... 23( ) ( )

v h i R i h i h

v h i

1 1 1 2

2

1 1= + +( ) + +( )( )

=

ie1 E fe1 fe2

ie2 22 1 21 1+ +( ) + +( )( )R i h i hE fe1 fe2

i i2 1=

i i1 2=

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Under common-mode conditions, v1 = v2 = vicm, so that equations (22)

and (23) can be equated:

and so

The output voltage (vo) is given by:

from which:

(The minus sign has had to be included because of the way vo has been

defined.)

Substituting equation (24) into equation (22) for i2:

v h i R i hh

hh i

v

1 1 1 1= + +⎛⎝⎜

⎞⎠⎟

=

ie1 E fe1ie1

ie2fe2

icmm

icm ie1 E fe1

for a common-mode input

v h R h= + +hh

hh iie1

ie2fe2

⎛⎝⎜

⎞⎠⎟

⎛

⎝⎜⎞

⎠⎟1

iv

R h1 =– o

C fe1

..................................... 25( )

v R h io C fe1= – 1

h i h i

ih i

h

ie1 ie2

ie1

ie2

...............

1 2

21

=

= ........................ 24( )

h i R i h i h h i R i h iie1 E fe1 fe2 ie2 E fe11 1 2 2 1 2+ +( ) = + + hhfe2( )

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Now substituting for i1 from equation (25):

3. Equation (19) is:

4. Equation (19) is:

Gh R

h hh h

hR

VCfe1 C1

ie1 fe1ie1 fe2

ie2E

≈+ +

⎛⎝⎜

⎞⎠⎟

and when and C1 C2 fe1 fe2 ie1 ie2R R h h h h= = =, , tthen:

and, assuming

Cfe C

ie fe E

ie

Gh R

h h R

h

V =+ 2

<<

, as required.

fe E

CC

E

2

2

h R

GR

RV

,

≈

Gh R

h hh h

hR

VCfe1 C1

ie1 fe1ie1 fe2

ie2E

≈+ +

⎛⎝⎜

⎞⎠⎟

v h R hh

hhicm ie1 E fe1

ie1

ie2fe2= + +

⎛⎝⎜

⎞⎠⎟

⎛

⎝⎜⎞

⎠⎟×

–vv

R h

Gv

v

R h

h R hV

o

C1 fe1

Co

icm

C1 fe1

ie1 E fe1

( )

= =+ +

–

hh

hhie1

ie2fe2

⎛⎝⎜

⎞⎠⎟

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Substituting the values given,

Using the simplification of equation (15),

The simplification works because hie << 2hfeRE.

5. There are 5 current-mirrors in the circuit, as highlighted in FIGURE 11.

You might not have included the mirror in the bottom left hand corner, as

it is a modified form. This circuit element in fact forms the active load of

the differential amplifier and the extra transistor has been added to

improve still further the performance of this stage.

GR

RVCC

E2≈ = ×

× ×=20 10

2 10 101

3

3

GVC ≈ × ×

+ + ×⎛⎝⎜

⎞⎠⎟

×

200 20 10

10 20010 200

1010 10

3

33

333

6

3 3

6

6

4 10

10 400 10 10

4 104 001 10

0 9= ×+ × ×( ) = ×

×=

.. 99975

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FIG. 11

6. (i) The CMRR is given by:

CMMR = E

E

R

r

34Ω

34Ω39 kΩ

5 kΩ1kΩ

50kΩ

1kΩ

Offset null/Comp–VCC

Inverting input Comp+VCC

Output

50kΩ 100 Ω

40kΩ

Offsetnull

Non-invertinginput

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In this example the tail resistor RE is formed by the output resistance of

T3. Thus RE > 20 kΩ. We can now find re:

The relationship re = 25/IC enables the tail current to be calculated:

(ii) The current through RREF fixes the tail current.

(iii) The tail current splits into two to give each transistor a quiescent

collctor curent of 2.5 mA. For the output to be at zero volts, 12 volts

will have to be dropped across RC. Thus, the required value of RC is:

(iv)

This is comfortably above the minimum specified.

(v) The quiescent output voltage is 0 volts so the collector of T3 will be

0.7 volts below this, i.e. – 0.7 volts.

GR

rVDC

e

= =≈×2

48002 5

480

RC = = k12

2 5 104 8

3..

–×Ω

RREF = =24 0 75 10

46603

– .–×

Ω

IrCE

= = = mA25 25

55

rR

EE=

CMMR= =

20 104000

53× Ω

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________________________________________________________________________________________

SUMMARY________________________________________________________________________________________

For the differential amplifier with double-ended output, the differential gain is

given by:

and, for the single-ended output amplifier:

The ideal double-ended output amplifier will have zero common-mode gain.

The single-ended output amplifier will have a common-mode gain of:

giving a common-mode rejection ratio of:

CMRR ............................fe E

ie

=h R

h....................... 16a

or CMRR E

( )

=R

rre ........................................................ 16b( )

GR

RVCC

E

................................≈2

...................... 15( )

Gh R

hVDfe C

ie

............................≈2

........................ 12a

.DC

e

( )

≈GR

rV 2........................................................ 12b( )

Gh R

hVDfe C

ie

.............................= ........................ 8a

...DC

e

( )

=GR

rV ....................................................... 8b( )

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Current mirrors are used in the differential amplifier to:

(a) provide a near constant tail current which gives a much improved CMRR.

(b) provide an active load, so restoring the gain of the single-ended output to

its optimum value.

In integrated circuit technology, the use of current mirrors to replace large

value resistors not only improves performance but also makes manufacture

easier and reduces the area of silicon required.

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