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978-1-4244-1882-4/08/$25.00 © 2008 IEEE PROC. 26th INTERNATIONAL CONFERENCE ON MICROELECTRONICS (MIEL 2008), NIŠ, SERBIA , 11-14 MAY, 2008 EKV MOSFET Model Implementation in Matlab and Verilog-A G. Angelov, I. Panayotov, M. Hristov Abstract – The present paper presents a straightforward yet effective approach to implementing a MOS transistor compact model (EKV v.2.6) in two different environments – Matlab and Verilog-A. This is useful for circuit-level design purposes enabling the designer to manipulate open-source models having direct access to model equation sets and program structure. EKV v.2.6 is selected for its simple model core and efficiency in describing device behaviors. A comparison of the simulation results between the two model implementations as well as a comparison to a reference model (BSIM3v3) has been illustrated in details. I. INTRODUCTION The compact MOS transistor (MOST) model is at the core of circuit-level design of CMOS analog and radio frequency integrated circuits (RFICs) enabling the designer to efficiently achieve design goals. Accurate device modeling is at the core of correct design and analysis of electronic circuits especially the analog ones. With CMOS technologies passed the sub-100 nm dimensions the demand for robust, consistent, physics-based, flexible, and full-featured compact models has increased. And the availability of such compact models has become critical to the successful utilization of any circuit simulation tool. Traditionally, MOST device models that are built-in circuit simulators have been developed using general- purpose programming languages like C, C++, or Fortran. Thus, they are targeted specifically to the interface and internal data structures of their host simulator, and hence are inherently non-portable. Facilities for adding custom open models or user-defined models have been made available in some simulation environments, but such interfaces have typically been non-standard, non-portable, and inefficient. Under these conditions, modification/ optimization of a model or new model creation was thus a time-consuming and error-prone task. II. CONTEXT OF THE WORK A prospective comprehensive solution to the aforementioned gap between analog model development and its deployment could be the implementation of the models in analog HDLs such as Verilog-A/AMS. Initially conceived as a general-purpose analog modeling language, Verilog-A has over the past several years become increasingly viewed as a leading candidate for new compact model development [1]. The recent rise in interest for Verilog-A based compact model development has resulted in compiled solutions becoming available, with an ongoing emphasis on improved simulation performance. On the other hand, the general-purpose mathematical package Matlab is widely used in modeling various objects in engineering, mathematics, etc and in particular in transistor modeling. The high speed of simulation within Matlab is essential to the optimization process. It is suitable as platform to modify or optimize modeling structure and thus is capable of leading to real benefits to both device simulation and circuit design. The use of standardized, special-purpose analog HDLs such as Verilog-A and/or the general-purpose computational platforms such as Matlab allows device modelers and circuit designers to focus on their area of expertise, rather than on the underlying simulator-specific implementation details. This means that a model developer can focus on model behavior, and let the underlying implementation automatically take care of the simulator- specific details (such as matrix stamping and loading, analysis-specific data structures, symbolic derivative computation, etc.). The device modeling engineer is thus shielded from the idiosyncrasies and complexities of the various device interfaces in existence today. Furthermore, both environments Matlab and Verilog-A – offer direct access to their code and thus enable the designer to benefit the open source code structure. The open source model codes allow direct access to model equations and parameters which is essential to model power users and model developers. In this context EKV v2.6 MOST model is quite suitable as an implementation example in Matlab and Verilog-A as it provides accurate modeling with a small set of parameters. In Matlab the model could be tuned to best conform to a specific design need. Next, formulating the model in Verilog-A language enables its use in a CAD tool such as Cadence design framework as a standard cell. Thus the designer accesses model parameters directly within Cadence interface rather than modifying the model code itself. Besides, EKV model is developed to explicitly address many issues in modeling for submicron CMOS technologies and low-power low-voltage analog circuits [2]. G. Angelov, I. Panayotov, and M. Hristov are with the Dept. of Microelectronics, Faculty of Electronic Engineering and Technology, Technical University of Sofia, 8 Kl. Ohridski, 1797 Sofia, Bulgaria, E-mail: [email protected]

EKV MOSFET Model Implementation in Matlab and Verilog-A

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  • 978-1-4244-1882-4/08/$25.00 2008 IEEE

    PROC. 26th INTERNATIONAL CONFERENCE ON MICROELECTRONICS (MIEL 2008), NI, SERBIA , 11-14 MAY, 2008

    EKV MOSFET Model Implementation in Matlab and Verilog-A

    G. Angelov, I. Panayotov, M. Hristov

    Abstract The present paper presents a straightforward yet effective approach to implementing a MOS transistor compact model (EKV v.2.6) in two different environments Matlab and Verilog-A. This is useful for circuit-level design purposes enabling the designer to manipulate open-source models having direct access to model equation sets and program structure. EKV v.2.6 is selected for its simple model core and efficiency in describing device behaviors. A comparison of the simulation results between the two model implementations as well as a comparison to a reference model (BSIM3v3) has been illustrated in details.

    I. INTRODUCTION

    The compact MOS transistor (MOST) model is at the core of circuit-level design of CMOS analog and radio frequency integrated circuits (RFICs) enabling the designer to efficiently achieve design goals. Accurate device modeling is at the core of correct design and analysis of electronic circuits especially the analog ones. With CMOS technologies passed the sub-100 nm dimensions the demand for robust, consistent, physics-based, flexible, and full-featured compact models has increased. And the availability of such compact models has become critical to the successful utilization of any circuit simulation tool.

    Traditionally, MOST device models that are built-in circuit simulators have been developed using general-purpose programming languages like C, C++, or Fortran. Thus, they are targeted specifically to the interface and internal data structures of their host simulator, and hence are inherently non-portable. Facilities for adding custom open models or user-defined models have been made available in some simulation environments, but such interfaces have typically been non-standard, non-portable, and inefficient. Under these conditions, modification/ optimization of a model or new model creation was thus a time-consuming and error-prone task.

    II. CONTEXT OF THE WORK

    A prospective comprehensive solution to the aforementioned gap between analog model development and its deployment could be the implementation of the

    models in analog HDLs such as Verilog-A/AMS. Initially conceived as a general-purpose analog modeling language, Verilog-A has over the past several years become increasingly viewed as a leading candidate for new compact model development [1]. The recent rise in interest for Verilog-A based compact model development has resulted in compiled solutions becoming available, with an ongoing emphasis on improved simulation performance.

    On the other hand, the general-purpose mathematical package Matlab is widely used in modeling various objects in engineering, mathematics, etc and in particular in transistor modeling. The high speed of simulation within Matlab is essential to the optimization process. It is suitable as platform to modify or optimize modeling structure and thus is capable of leading to real benefits to both device simulation and circuit design.

    The use of standardized, special-purpose analog HDLs such as Verilog-A and/or the general-purpose computational platforms such as Matlab allows device modelers and circuit designers to focus on their area of expertise, rather than on the underlying simulator-specific implementation details. This means that a model developer can focus on model behavior, and let the underlying implementation automatically take care of the simulator-specific details (such as matrix stamping and loading, analysis-specific data structures, symbolic derivative computation, etc.). The device modeling engineer is thus shielded from the idiosyncrasies and complexities of the various device interfaces in existence today.

    Furthermore, both environments Matlab and Verilog-A offer direct access to their code and thus enable the designer to benefit the open source code structure. The open source model codes allow direct access to model equations and parameters which is essential to model power users and model developers.

    In this context EKV v2.6 MOST model is quite suitable as an implementation example in Matlab and Verilog-A as it provides accurate modeling with a small set of parameters. In Matlab the model could be tuned to best conform to a specific design need. Next, formulating the model in Verilog-A language enables its use in a CAD tool such as Cadence design framework as a standard cell. Thus the designer accesses model parameters directly within Cadence interface rather than modifying the model code itself. Besides, EKV model is developed to explicitly address many issues in modeling for submicron CMOS technologies and low-power low-voltage analog circuits [2].

    G. Angelov, I. Panayotov, and M. Hristov are with the Dept. of Microelectronics, Faculty of Electronic Engineering and Technology, Technical University of Sofia, 8 Kl. Ohridski, 1797 Sofia, Bulgaria, E-mail: [email protected]

  • BSIM3v3, being most comprehensive in describing device behaviors, is used as a reference for verification purposes. For circuit design purposes we have generated a cellview, which makes the Verilog-A EKV model applicable to the standard Cadence design flow.

    III. BRIEF EKV MODEL FORMULATION

    A primary concern for advanced MOST models is their physical basis. The charge-based model approach taken within the EKV model is itself based on a surface-potential analysis. The basic charge modeling approach [3], [4] allows physically consistent and accurate modeling of current, terminal charges and noise, without introducing artificial parameters besides the physical parameters of surface potential modeling. For many circuit applications, even at RF frequencies, operation in weak and particularly moderate inversion may offer a favorable trade-off among power consumption, linearity, matching, noise, and bandwidth. The charge-based approach offers suitable expressions for hand calculation, which a surface-potential only model cannot offer.

    EKV v2.6 model is described in detail in the literature [3], [5]. In EKV the gate, source and drain voltages, VG, VS and VD, are referred to the substrate in order to preserve the intrinsic symmetry of the device. Besides EKV proceeds from the pinch-off voltage VP(rather than the threshold voltage VTh). The EKV model is based on the charge-sheet linearization approach with the with the following essential characteristics: 1) Symmetric handling of source/drain effects combined with substrate reference, 2) Coherent charge-based modeling of static large-signal and dynamic small signal aspects including non-quasistatic aspects, as well as noise, 3) Analytical, continuous, physically correct description of weak, moderate and strong inversion and linear/saturation operation.

    Below we briefly provide the main equations and quantities of the model. The drain current ID, is expressed as

    ID = IF IR (1) where IF is the forward component of the current (independent of VD) and IR is the reverse component of the current (independent of VS). The currents (forward IF, and reverse IR) are obtained by integrating the inversion charge along the channel:

    2)(

    )( 2exp1ln

    t

    DSPSRF U

    VVII (2)

    with the thermodynamic voltage Ut = kT/q (0.026 V at 300q K) and

    22 tS UnI E{ specific current (3)

    effeffox LWC c PE transfer parameter (4)

    tP UPHIVn

    42GAMMA1

    slope factor (5)

    The gate-, source- and drain transconductances are defined as,

    G

    Dmg V

    Ig w

    w{ , S

    Dms V

    Ig w

    w{ ,D

    Dmd V

    Ig w

    w{ (6) where VG, VS, and VD are the respective voltages referred to the substrate.

    IV. RESULTS

    In particular, we simulate N-channel MOS transistors with respective channel length L and width W to obtain output, transfer, and transconductance characteristics.

    Fig. 1. Output characteristics simulated in Matlab with EKV v2.6 model for 0.0 V < VG < 3.0 V.

    Fig. 2. Output characteristics simulated with BSIM3v3 and EKV v2.6 models for 0.5 V < VG < 0.9 V.

    Based on the Matlab implementation of the EKV v2.6 model from [6] we have adapted it for this particular investigation (in Fig.1 we show, for example, the output characteristic of the EKV model); the same approach applies to the BSIM3v3 model. Afterwards we have

  • rewritten Matlab code in Verilog-A. A standard cell in Cadence Design Framework has been created from the Verilog-A module, ready for circuit design purposes.

    Verilog-A implementations are carried out using Verilog-A version 2.1 and not using the new Verilog-AMS 2.2 standard (the new version supports additional operators for compact modeling, e.g. ddx, that would have ease model development). This is due to the fact that our simulator does not support the enhanced features of the language.

    In the Figures 2-4 we show the simulated output and transfer characteristics obtained by the BSIM3v3 and EKV v2.6 Verilog-A implementations. The results show quite good agreement to each other. We have split the output characteristic in two (for 0.5 V < VG < 0.9 V and 1.0 V < VG < 3.0 V) to ensure better readability of the plots.

    Fig. 3. Output characteristics simulated with BSIM3v3 and EKV v2.6 models for 1.0 V < VG < 3.0 V.

    Fig. 4. Transfer characteristics simulated with BSIM3v3 and EKV v2.6 models for 0.0 V < VD < 3.3 V.

    In Figure 5 we have derived the transconductance using the embedded deriv function in Cadence Spectre here the match is very good as well.

    Fig. 5. Transconductance gmg characteristics simulated with BSIM3v3 and EKV v2.6 models.

    V. CONCLUSION

    To overcome the gap between model development and model implementation we suggest the following simple approach. First to use a general purpose program environment (Matlab) for modifying/adapting a compact model and next to code it in a HDL to make it ready-for-use in standard simulation tools like Cadence Design Environment. In this context we implement the well known EKV 2.6 model in Matlab, as a representative of C-like language, which is widely available, full-featured mathematical platform and on the other hand Verilog-A as a representative of HDLs, that are gaining popularity as a means for implementation of compact models.

    We have chosen EKV for its simplicity from mathematical point of view, and Matlab as widely adopted as computational platform.

    Following the approach we can first use Matlab to test and tune the model and then to transform it into Verilog-A to make it available for use in circuit simulations. Verilog-A implementations are performed using Verilog-A version 2.1 and not the latest version 2.2 which extends the support for compact modeling.

    The results obtained demonstrate the validity of the suggested open model implementation into an industrial CAD tool. Verilog-A code makes the model tool-independent the same code can be used in every simulator that supports the language. The fast and accurate simulations with comparable accuracy to commercial simulator models show the practical applicability of the method to optimization process. The main advantage is the method offers open source modeling and enables designers to directly access model equations.

  • ACKNOWLEDGMENT

    The present work is carried out within the framework of the Project BY-TH-115/2005.

    REFERENCES

    [1] Troyanovsky, B.; OHalloran, P.; Mierzwinski, M. Portable high performance models using Verilog-A, IEEE Conf. MTT, June 2003.

    [2] G. Angelov, T. Takov, and St. Risti "MOSFET Models at the Edge of 100-nm Sizes", Proc. of the 24th Intl. Conf. on Microelectronics (MIEL 2004), Ni, Serbia and Montenegro, Vol. 1, pp. 295-298, May 2004

    [3] Enz C. C.; Krummenacher F; Vittoz E. A., An Analytical MOS Transistor Model Valid in All Regions of Operation and

    Dedicated to Low-Voltage and Low-Current Applications, J.Analog Int. Cir. & Sys. Processing, Vol. 8, pp. 83114, 1995.

    [4] Enz, C. C.; Bucher, M.; Porret, A.-S.; Sallese, J.-M.; Krummenacher, F., The foundations of the EKV MOS transistor charge-based model, Workshop on Compact Models 5th Int. Conf. Modeling and Simul. Microsystems (MSM 2002), Puerto Rico, USA: San Juan, April 2002, 666669.

    [5] Bucher M.; Lallement C.; Enz C. C.; Krummenacher F., Accurate MOS Modelling for Analog Circuit Simulation using the EKV MOST Model, IEEE ISCAS 96, pp. 703-6 Vol.4, 1996.

    [6] Angelov G., Asparuhova K., MOSFET Simulation Using Matlab Implementation of the EKV Model, 15th Intl. Scientific and Appl. Science Conf. "ELECTRONICS ET2006", Sozopol, Bulgaria, Book 1, pp. 167-172, September, 2006. ISBN 954-438-564-9.