Eindhoven University of Technology

MASTER

Power supply current monitoring on assemblies

Kuyper, A.M.

Award date:1995

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EINDHOVEN UNIVERSITY OF TECHNOLOGYFaculty of Electrical Engineering

Department of Digital Information Systems

Final Thesis

Power Supply Current MonitoringOn Assemblies

byA.M. Kuyper

Supervisor (TUE): prof. ir. M.T.M. SegersSupervisor (Philips): ir. M.N.M. Muris

Eindhoven, May 1995

The Fa.culty of Electrica.l Engineering of Eindhoven University of Technology

does not accept a.ny responsibility rega.rding the contents of theses

Author A.M. Kuyper

Title Power Supply Current Monitoring On Assemblies

Supervisors Ir. M.N.M. Muris (Philips) & Prof.Ir. M.T.M. Segers (TUE)

Abstract

Manufacturers of assemblies like Printed Circuit Boards (PCBs) or Multi Chip Modules (MCMs)are strongly pushed to reach the 100% defect free target on supplied products. Testing is thusinevitable. To meet the test requirements of current and future high density and highly complexassemblies, current test methods have to be updated or new test methods have to be developed.

The test method Power Supply Current Monitoring (PSCM) looks very promising, and researchis started. This report presents the preliminary results of this research into the usability of PSCMfor detecting manufacturing defects on assemblies.

Abbreviations and aCrOl1.yms

ADVASICBTSLCMOSCPUDCDFTDSPEMCICLSMCMLEDPCBPSCPSCMRAMRDVSMDSRAMTAPTTL

Absolute Detect current ValueApplication Specific Integrated CircuitBoundary-scan Test Specification LanguageComplementary Metal Oxide SemiconductorCentral Processor UnitDirect (continuous) CurrentDesign For TestabilityDigital Sound ProcessorElectro Magnetic CompatibilityIntegrated CircuitLow-power Schottky TTLMultiChip ModuleLight Emitting DiodePrinted Circuit BoardPower Supply CurrentPower Supply Current MonitoringRandom Access MemoryRelative Detect current ValueSurface Mounted DeviceStatic Random Access MemoryTest Access Port [5]Transistor Transistor Logic

ii

Contents

1 Introduction

2 Theory

2.1 Direct versus indirect detection

2.2 Static fault detection ..

2.3 Dynamic fault detection

2.4 Calculation detection threshold

2.5 Conclusions .

3 Verification

3.1 Static fault detection.

3.1.1 Measuring method

3.1.2 CMOS assembly

3.1.3 TTL assembly .

3.2 Dynamic fault detection

4 Conclusions

4.1 Manufacturing defect (open/short) detection

4.2 Usability of PSCM and its future

4.3 Advice to continue .

Bibliography

A The literature search

A.l Selection criteria

A.2 Publications.

A.3 Conclusion

B Equipment list

C Diagrams

C.1 Static PSCM measure schematic diagram ., ...

C.2 Time dynamic PSCM measure schematic diagram

iii

1

3

3

4

7

7

7

9

9

9

10

14

21

23

23

24

25

27

31

31

31

34

36

37

37

38

C.3 CMOS PCB. 40

C.4 TTL PCB. 42

D Test sequence 43

D.I CMOS PCB. 43

D.2 TTL PCB .. 57

E Tables (IC PSC consumption) 64

E.I CMOS PCB. 65

E.2 TTL PCB .. 65

F Tables (measurements/estimations) 66

F.I CMOS PCB: Measured PSC, the fault free board . 66

F.2 CMOS PCB: Measured PSC, opens ......... 67

F.3 CMOS PCB: Measured PSC, signal shorts ..... 67

FA CMOS PCB: Measured PSC, power supply shorts 68

F.5 TTL PCB: Estimated PSC, opens and signal shorts 69

F.6 TTL PCB: Measured PSC, opens and signal shorts. 70

F.7 TTL PCB: Measured PSC, power supply shorts. 72

G Digital Audio Broadcast (DAB) 73

G.I Introduction. . 74

G.2 Measurements. 74

G.3 Conclusions .. 74

GA Table (IC PSC consumption) 76

G.5 PSC behavior (oscilloscope pictures) 77

H Contact test on assemblies (MCPs) 92

H.I Problem 92

H.2 Theory. 93

H.3 Measurements and verification 94

HA Solution 95

H.5 Tables. 96

iv

Preface

This report describes the major contents of my graduation project which has been performedduring the months September 1994 up to May 1995 at the Philips Nat.Lab, business unit ElectronicDesign and Tools (ED&T). This graduation project is the final stage of the training program tobecome an information technological engineer.

Acknowledgements

I could never have made this project to a success without the help of many people at PhilipsNat.Lab. I would like to thank Math Muris for his out standing support. I want to thank ReneSegers for making it possible for me to do my graduation project at the Philips Research Labo­ratories Eindhoven, NaLLab. Finally I would like to thank all the others who helped me but arenot mentioned above.

v

Chapter 1

Introduction

The highly competitive market asks for reliable products. To achieve this goal, every product mustpass several tests. These tests should be fast and have high fault coverage. It is generally believedthat these requirements can only be met if already during the design phase the product testabilityis taken into account. This is referred to as design for testability (DFT).

In complete products the major part of the faults are component functional defects and errorsduring assembly [2].

Boundary scan

The ever increasing scale of integration, Surface Mounted Devices (SMDs) and multilayer carriers,have challenged the in-circuit testing methods. As a result of this, bed-of-nails testers are no longerusable, because the area occupied by the test spots introduces a large overhead with respect tothe size of the integrated components.

But, boundary-scan testing gives a principal solution to in-circuit testing problems. Boundary-scanarchitecture is defined in the IEEE standard 1149.1 [5] and enables the utilization of non-contacttest methods.During the design process, each input and output pin of a (digital) electronic component can beprovided with a boundary-scan cell. These cells are, in normal operating mode, transparent; thecomponent operates according to its specification. In test mode, all cells are connected serially, toform a shiftregister. This shiftregister is loaded with test patterns. These test stimuli are appliedto the circuit under test. Then, the results are captured and shifted out of the boundary-scanchain and gathered by the tester for diagnosis.

However, the search for new test techniques or the update of existing test methods for future testrequirements is never stopped. One of the promising methods is Power Supply Current Monitoring.

Current monitoring

The method of measuring the quiescent (static) power supply current is not new. Already, themethod is used for assemblies as first overall test. For this test, a minimum and a maximum powersupply current (PSC) threshold are determined. Whenever the PSC consumption is outside theseboundaries the assembly is considered to be faulty. The method has also been used successfully forseveral years now, to obtain information about the quality and reliability of CMOS Ies [1]. It isa total observability method that directly detects many common manufacturing defects of CMOSICs. One of its major advantages is that test data is directly obtainable from the power supply

1

lines.

The question if it is possible to use the electrical current monitoring test method to detect man­ufacturing defects on assemblies (e.g. MCMs or PCBs), is investigated in this report. The usedmethod with respect to assemblies is referred to as Power Supply Current Monitoring (PSCM).The application area of PSCM must be sought especially in consumer electronics.

Task

My task consists of (1) a literature search on previous research concerning the usage of PSCM,(2) an investigation of the usability of PSCM, and if the results from part two are positive, (3)the development of a tool (hardware and/or software) for PSCM to detect and diagnose themanufacturing defects within the existing test environment.

Report

The first part of my task, the literature search, is discussed in appendix A and resulted in onepaper only. This similar research, written by M. Kiirkkiiinen et a1. [3], presented promising results.The results of the second part of my task are given in the following three chapters of this report:

theory (chapter 2),which identifies the manufacturing defects on assemblies and estimates their influence on thePower Supply Current (PSC) for two technologies of chips (CMOS and TTL).

verification (chapter 3),which analyses the PSC measurements of several assemblies and verifies the observationsmade in the previous chapter.

conclusions (chapter 4),which concludes this report with statements concerning PSCM and the possibility to developtools.

It is assumed that the reader has knowledge of assembly testing, boundary-scan and some practicalexperience in electronics.

2

Chapter 2

Theory

There are two major classes of manufacturing defects on assemblies: assembly defects and compon­ent functional defects [2]. Assembly defects can be categorized into solder defects and workmanshipdefects. Solder defects are typically opens or shorts of different forms. Workmanship defects in­clude wrong value component, reversed polarity, etc. This report will focus solely on solder defects:opens (disconnections) and shorts (bridges).

The Power Supply Current (PSC) consumption can be spilt into two categories: the static PSCconsumption and the dynamic PSC consumption [15]. The static PSC consumption is defined asthe PSC that flows through the total assembly when all logic are in a steady (quiescent/static)state. The dynamic PSC consumption is defined as the PSC that flows through the total assemblywhen the logic is functioning (dynamic).

The level of the PSC through the total assembly depends on the operational state. For example,more current flow through the component when electrically enabled, than when electrically dis­abled (e.g. 74BCT8244 [25]).

Of course, defects can have influence on the state of the assembly. A state change, as pointed out,can put the assembly into a different PSC consumption mode. Defects can only be detected whenthe change in PSC is larger than the general variation in PSC which is caused by (un)avoidablefactors (measuring accuracy, test method errors, etc.).

Since no simulation tool or associated simulation models are available which can simulate the PSCconsumption of an assembly, no information has been obtained from computer simulation. Alldata concerning the PSC consumption of assemblies are obtained from the component data-sheets(specs) and PSC measurements. This chapter estimates the PSC changes for opens and shortswith respect to two technologies, CMOS and TTL. These are the most common chip technologiesfor consumer applications.

2.1 Direct versus indirect detection

The change in PSC (with respect to the PSC consumption in the fault free situation) is causeddirectly and/or indirectly by a fault. The change is direct when the fault and the current changeoccur in the same net, and, the change is indirect when the fault and current change are in differentnets, of an assembly. An example of direct and indirect change in PSC (detection) is displayed infigure 2.1 and figure 2.2, respectively. Both figures show the PSC behavior for the fault free andfaulty situation.

In the situation as shown in figure 2.1, the PSC consumption difference between the two conditions,enabled and disabled LATCH, is large (the current consumption of a LED can be large, e.g. lOmAper LED). When the LATCH is enabled (E = 1), the short (at 03) is excited and the PSC

3

Vee ----~-__,1- LEDs

E=l

LATCH

E=O

E=1

E=O

I

Short Rs

00 f----+-::>t---,

01 f----+-::>t---1

02 1--+3>/---103 h-+3>/---1

10

11

12

13

>----'-----1 E

R.1..Buffer 1i

: :~~ ...

E

Fault free Short Defect

Figure 2.1: Direct detectable defect

consumption of the total circuit increases. Hence, the defect is detectable when the enable signalis set high. This detection is called direct detection: the actual defect is measured (defect andcurrent change occur in the same signal net).

E=OE=l

IOpen Defect

LEDsf10 00

11 01I E=1

I2 02

13 03

E

LATCHFault free

1-

R ,l.:Buffer !i

E ----{>-i. 'rOpenDefect

Vee ----....,..-,.------,

Figure 2.2: Indirect detectable defect

In the situation as shown in figure 2.2, an open between the buffer and the electrical enable signalof the LATCH causes the enable signal to be high (dashed pull-up circuit, the LATCH is alwaysenabled). The PSC consumption of the total circuit is then independent of the enable signal (E).Now, at "E=O" the PSC is high instead of low, the fault is detectable. This detection is calledindirect detection (assuming the open is not direct detectable): the indirect cause of the defectis measured, all LEDs are ON instead of OFF. Hence, the operational state of the circuit haschanged with respect to the fault free situation.

2.2 Static fault detection

Defects which are indirectly detectable cause the assembly to operate into a different PSC con­sumption mode and change the state in which the assembly is operating. Indirect static faultdetection depends totally on the schematic of the assembly. Because of the dependence of thelarge number of variables, no general observations with respect to the indirect detection of opensand shorts can be made. The theoretical observations with respect to the direct detection of shortsand opens (static PSCM) are:

• Opens are disconnections in the signal or power supply nets.

A signal net, figure 2.3, is typically a connection between an output driver and an inputbuffer. In general, there is a current flow between this output driver and this input buffer.The value and detection depends on the chip technology:

4

VddInternal

I I

1 I LogicI

-I I(L)I

I I

1 1r r

Inten1al I I1

_________ 1

\ I

Logic ' ~----------rII

II(H)II

Internal1

'II 'IILogic

Vss

Output driver Input buffer

Figure 2.3: Disconnection between a CMOS output driver and a CMOS input buffer.

CMOS: The maximum value for this current is 1fLA [23, 27, 28J (the maximum leakagecurrent h -will be much lower than this, typically several nano amperes-). The intro­duction of an open in this signal net decreases the total PSC by this amount. Directdetection of opens is therefore impossible due to the PSC variations between fault freecomponents/assemblies, which are larger than the leakage current.

TTL: The maximum value for this current is OAmA (input driven low, IIL) or 20fLA (inputdriven high, I lH ) [26]. The introduction of an open in this signal net decreases the totalPSC by this amount. This amount may be smaller than the variation in the total staticPSC over several identical TTL assemblies. Direct detection of opens may therefore bedifficult.

Opens in power supply nets to one or more chips decrease the static current consumption ofthe assembly (e.g. 8fLA for CMOS chips and lOrnA for TTL chips). However, CMOS chipswith input/output protection diodes may also operate without a power supply connectionbecause the power is delivered through the protection diodes (appendix H). This probablymakes detection very difficult. TTL chips do not consume power when one of its power ter­minals is disconnected. Direct detection of opens in the power supply nets on TTL assembliesshould therefore be possible.

• Shorts are unwanted connections between nets. Three classifications are made:

1. Shorts between two signal nets;

2. Shorts between a signal net and the power supply net;

3. Shorts between two power supply nets.

Ad 1) A short between two output drivers/signal nets, figure 2.4, which are driven to oppositelogic levels, causes a low resistance path between VDD (TTL: Vee) and Vss (GND). Thecurrent -Io(s) through this path is very large. The value of this current depends on the chiptechnology:

CMOS: The value of -Io(s) may differ for the two short-current flows (from the left tothe right output driver or from the right to the left output driver). The difference is

5

Vdd VddI II I

\ -I O(S) -10(S) "Internal "

,Internal... '"... ....

Logic '".... ... Logic

'" ", ,, \I I

'If 'If

Vss VssFigure 2.4: The switching tree of two CMOS output drivers which are shorted.

due to the used CMOS technology. The minimum value for this current is for example15mA [23, 27]. Shorts between two signal nets should therefore be directly detectableby PSCM.

TTL: This current is limited by the upper transistor (in general, the upper transistor cansource less current than the lower transistor can sink). The minimum value for thiscurrent is for example 15mA [26]. Shorts between two signal nets should therefore bedirectly detectable.

Internal

Logic

Vdd

j -1 0 (5)

Vss

Internal

Logic

Vdd

.- '.

.V10 (5)

_...L..-_

VSS

Vss-short Vdd-shortFigure 2.5: A CMOS output driver which is shorted to a power supply net. (*see text)

Ad 2) The current which is caused by a short between Vss /VDD and a high/low driven outputdriver is limited by the upper/lower transistor of the switching tree, see figure 2.5. The valueof this current 10 (s) depends on the electrical properties of the conducting transistor. Thedetection of this kind of shorts is similar to that of shorts between signal nets. Hence, shortsbetween a signal net and a power supply net are therefore directly detectable.

6

Ad 3) If two power supply nets carry the same voltage value, there is no current flow betweenthose nets. Hence, no direct detection is possible (in reality, there is a small current flowbecause both voltages will never be exactly the same, however, this current flow will be verysmall and hard to detect). The current flow through a short between two nets which are atdifferent voltage levels (e.g. VDD and Vss) is very large and directly detectable by PSGM.

As mentioned before, the lower transistor can sink more current than the upper transistorcan source, for TTL and some CMOS chip technologies. The lower transistor short currentis not specified by the manufacturers. The upper transistor short current is specified in thedata-sheet as (- )10s. However, not every manufacturer specifies (- )10s. If this is the case, thevalue of 10 (maximum output source or sink current) can be used as a first order estimate.

2.3 Dynamic fault detection

The dynamic PSC consumption of CMOS assemblies is an order of magnitudes higher than thestatic PSG (several amperes are possible). The leakage current also increases: due to the higheroperating frequency, the current flow through the gate capacitors increases [7]. The value of thisleakage increase is not specified in the data-sheets. Hence, no estimation can be made with respectto the detection of opens by dynamic PSCM. The increase in PSC caused by shorts remains large,but the dynamic PSC, as pointed out, can also be very large. Direct detection by dynamic PSCMcan therefore be very complex. The dynamic PSG of TTL assemblies is about the same order ofmagnitude as the static PSG of TTL. Hence, the static PSC observations are also valid for thedynamic PSG.

2.4 Calculation detection threshold

Since no simulation tool or associated simulation models are available which can simulate the PSGconsumption of an assembly, the data with respect to the PSG consumption is obtained from theelectrical current specifications of the assembly components or from PSC measurements on theassembly. The data can be absolute or relative analyzed. Absolute analysation uses the obtaineddata of the PSC consumption which has been obtained under several conditions (fault free andall possible defects). Relative analysation uses the difference between the PSC consumption inthe fault free situation and the PSG consumption when the assembly is faulty, under severalconditions. These relative values are obtained by subtracting the absolute PSG consumption ofthe fault free assembly from the absolute PSG consumption of the faulty assembly (all possibledefects are "inserted" on the fault free assembly).

The detection threshold can be categorized in (maximum or minimum) absolute detect values(ADVs) and relative detect values (RDVs). These detect values are valid for one or several op­erating states of the assembly. A maximum/minimum ADV is a absolute PSC value such thatdefects (all or particular type of defect) are detectable because the absolute PSC of the assemblyunder test exceeds/is below that assembly'defined maximum/minimum ADV. A RDV is a relativecurrent value such that the current change caused by the defects (the difference) is higher thanthat assembly'defined ROV. Each assembly has its own specific ADV(s) and RDV(s).

Hence, if the (relative) PSC of a faulty assembly is in the bandwidth of the maximum and minimumADV/ROV the fault is not detectable. Figure 2.6 explains ADV and ROV graphically.

2.5 Conclusions

By these theoretical observations, the expectance is that shorts are detectable for both CMOSand TTL assemblies, but opens will not be directly detectable by PSCM. This does not mean that

7

PSC

800

o

D.PSC

+50

-!<r.~~~~~~~~~~~~~~:::::~

Defect

2

identical

Fault Free :PSC range of a numberof fault free assemblies

Defect 1:Is within ADV rangeand for that reasonnot detectable

Defect 2:Is out ADV range andfor that reasondetectable

Defect 3 and 4:Is out RDV range andfor that reasondetectable

Fault

Free

Defect

3Defect

4

Figure 2.6: Absolute and Relative Detect current Value

opens are not detectable at all. An open is for instance detectable if it causes the assembly tooperate in an operating state at which the power consumption is some magnitude higher or lowerthan in the fault free situation, indirect detection.

8

Chapter 3

Verification

The static PSC measurements are concerned with the electrical current through an assemblywhen all logic are in a steady state [2]. The dynamic PSC measurements can be grouped intotwo classes. The first class, level dynamic PSC measurements [2], is concerned with the level ofPSC through an assembly when the logic is functioning. The second class, time dynamic PSCmeasurements [2, 6], is concerned with the PSC timing relationships, e.g. switching moments andswitching spikes, when the logic is functioning. PSC measurements of the second class are verycomplex because the components (logic) are switching in very short time intervals. Assemblies, ingeneral, contain several capacitors (current buffers) which obscure these switching signals in thepower supply current.

As pointed out in the introduction of this report, the purpose of PSCM lays in consumer applica­tions. CMOS and TTL are the most common chip technologies for consumer applications. Severalarbitrary CMOS and TTL assemblies were chosen, some of which are described in appendix Cand G. These assemblies were subjected to static and dynamic PSC measurements to identify theability of PSCM to detect opens and shorts. These measurements were analyzed and the resultsof this analysis is verified with the results obtained from the theoretical (specs) observations donein the previous chapter.

In this chapter, the PSC measuring results which were obtained during this research is discussedwith respect to two demonstration PCBs (CMOS and TTL PCB). The conclusions drawn forboth PCBs are nearly all true for compatible assemblies: CMOS PCB versus CMOS assembliesand TTL PCB versus TTL assemblies. Results and conclusions which differ from the results andconclusions with respect to both PCBs will be pointed out. The chapter consists of two sections,the first section, static fault detection, analyses the static PSC measurements. The last section,dynamic fault detection, presents a (time) dynamic PSC measurement.

3.1 Static fault detection

This section analyses the results of the static PSC measurements and verifies the measured res­ults with the PSC estimations (specs, appendix E). PSC consumption estimation of an assemblycan be calculated from the specs (data-sheets) of its components, assumed that the specs of thecomponents contain adequate information.

3.1.1 Measuring method

Figure 3.1 displays the simplified measuring diagram for the static PSC measurements, the realmeasuring diagram is discussed in appendix C.1).

9

+Tester

;>.:c Test vectorsS &0<I.l Test response<I.l PC<:

Figure 3.1: Static PSC measurement diagram.

Almost all tested assemblies were equiped with boundary-scan chips. The inputs and outputsof these boundary-scan chips are accessible by means of the boundary-scan protocol [4, 5]. Theassemblies can be put into a particular operational state by loading the related test (binary) vectorinto the boundary-scan chain (cells) of these chips. The assembly under test is injected by severaltest vectors [5]. Each test vector puts the assembly into a different operating state. This changein state can cause a change into a different PSC consumption mode, see previous chapter.

The injection of test vectors is done by a vector blaster (Tester 1, appendix B). The blaster shiftsthose vectors through the boundary-scan chain of the on board or external boundary-scan chips(DIOSes), and starts each set of test vectors with a "reset". A test cycle may consist of several testvectors. The reset initializes the (TAP) controller of the boundary-scan chips. This is detectableas a short steep drop in the PSC, and is taken into account in the (time dynamic PSCM) analysis.

The test vectors are injected one by one for several conditions: fault free, opens and shorts. For eachcondition is the set of test vectors repeated. The PSC consumption of the assembly is measuredafter a test vector has been shifted through the boundary-scan chain and the logic is in steadystate.

The voltage across the assembly must be kept constant during all measurements to prevent anystrange PSC behavior in the measuring results, such as random switching of components. Also,special care must be taken with the used measuring equipment. The measuring equipment has farfrom negligible influence on the PSC measurements. The current sensor, for instance, can have alarge influence on the measured value of the PSC through the assembly under test. If the PSCconsumption of the assembly increases then the voltage across the internal resistance of the currentcensor increases. This increase in voltage decreases the voltage across the assembly and changesthe PSC through the assembly. The large influence of the current sensor on the PSC is eliminatedby the construction of a current sensor which reduced the voltage across the assembly no morethan a few tens of milli volts under all conditions.

3.1.2 CMOS assembly

This subsection starts with a brief description about the demonstration CMOS PCB and howopens and shorts were introduced.

The CMOS PCB consists of eight pull-up resistors, eight octal buffers and four static randomaccess memories (SRAMs). Appendix C.3 displays the board layout and the schematic diagram.All ICs are CMOS and run on 5 Volt DC typo This board is a random access memory boardwhich can be connected to almost every central processor unit (CPU). The busses are directlyaccessible by flat cable connectors. These connectors are connected to two external boundary-scanchips (DIOSes) [4, 5, 11]. The bidirectional ports of these DIOSes are thus connected to the inputsand outputs of this board. The board can be put into a particular operating state by loading the

10

related test (logic) vector into these DIOSes by means of the boundary-scan protocol [4, 5].

At power-on, the SRAM's memory cells are loaded by the initial load sequence: the cells aredefined before the tests were started. Arbitrary switching (PSC distortions) by the cell logic isthen eliminated. The initial load sequence can be found in appendix D.l.

Opens are created by removing jumpers. These jumpers are marked by an F which is followed bya number, see appendix C.3. A screwdriver is used to insert shorts between several pins of the ICson the PCB. Appendix D.llists one of the sets of test vectors (test sequence).

PSC estimation with respect to the specs

The maximum static PSC estimation of the demonstration CMOS PCB are calculated accordingto the equation 3.1. The schematic diagram and component layout of this board are displayed inappendix C.3) and the direct current (DC) parameters of the components (specs) are listed inappendix E.l.

PSG = (the current consumption of the four SRAMs)+(the current consumption of the eight latches & decoder chips) (3.1)+(the current consumption of the eight pull- up resistors)

The maximum static PSC of this CMOS PCB is between 72Il-A (typ. 4x2+8x8) and 500Il-A (max.4x100+8x8). For each active pull-up circuit (resistors rl ..rS) 500ll-A (5V/10kf!) must be added tothe total current. The maximum static current of this board is 4.5mA (5000+8x500Il-A). DetailedPSC estimations are not possible for this board because the specs are inadequate.

Observations concerning opens and shorts

The introduction of an open changes the PSC by the amount of the leakage current only (directdetection). The leakage current of the components on this board is maximal1ll-A. This amount isvery difficult to detect in relation to the large maximum static PSC (4.5mA). The PSC consump­tion measured at different moments in time for identical conditions shows already some variation.This variation is in general several magnitudes higher than this leakage current. Direct detectionof opens is therefore impossible.

Shorts on the other hand create a low resistance path between VDD and Vss. The current changewhich is caused by this path is large (larger than 15mA) and should be detectable.

Measuring results

Part of the PSC measurement results are displayed in figure 3.2 (fault free and opens, data isdisplayed in appendix F.l and F.2, respectively) and figure 3.3 (shorts, appendices FA and F.3).

Opens

Figure 3.2 shows one set of PSC measurements with respect to several opens for two test vectors.To keep the measuring accuracy in the PSC high (lOll-A max.), no pull-up circuitry are activatedduring the open detection tests. Also plotted in this figure are the minimum and maximum PSCaccording to the specs and the measured minimum and maximum PSC for the fault free boardunder the same test conditions. According to the specs and the measurements the variation isvery large (specs 500Il-A and measured 150jLA). The large variation in the specs is caused by thelarge variation in current consumption for the PCB components as listed in the data-sheets. Thespec values are therefore not accurate enough to determine or calculate the detection threshold(s).

11

=

uA

500

200

150

100

50 -=

=..-

= =

[-=- -=

Fault freemin/max

JOE

ADR14

DQ7

!CS (globale)

DQ7 (globale)

Spec Read vector Write vector

Figure 3.2: The (variation in) static PSC consumption for opens and the fault free condition, nopull-up circuit is activated (CMOS PCB)

The measured PSC values, in case of an error, are all within the fault free PSC variation. Directdetection of opens is therefore impossible. Other sets of PSC measurements in relation to opensare also within the related fault free PSC variation. The large fault free PSC variation is probablydue to two problems:

The environment The primary cause of this problem is EMC which is induced in the connections(flat-cable) between the board, tester and measuring equipment. This induction drops theoutput voltage of the octals by 0.4 Volt maximal. This voltage drop decreases the inputvoltage levels of the SRAMs. This changes the PSC through these SRAMs. Furthermore, insome cases the board even oscillates.This problem can be limited by shielding and shortening the connections and grounding theassembly under test.

The temperature The current consumption depends on the thermal condition of the chips. Forexample, the difference between two identical measurements taken at large time intervals islarge (cold chip versus warm chip and warm chip versus warmer chip: the current consump­tion decreased lOO/LA maximal in four hours time, see column 1 and 2 of appendix F.l).The influence of this problem can be limited by waiting for several hours before the firstmeasurement and waiting several minutes before each measurement. The current throughthe chip and the temperature of the chip will then be stabilized (a change of 20/LA maximalin three hours, see column 4, 5 and 6 of appendix F.l). However, the difference in PSCbetween identical measurements at the same related moment in time remains large.

No actual data have been obtained with respect to this temperature problem, but severalfactors point to temperature effects.

The influence of these problems, especially the last one, could only be limited, not totally elimin­ated. The EMC problem could not be solved totally during this investigation, because no redesignof the assemblies was possible. The measuring time concerning the open measurements is verylarge (four to seven hours, of which three to four hours stabilize time). For this reason is the openmeasurement only done once for several assemblies. Table 3.1 shows the defect (all opens) jumpersand their (real) detection method on the demonstration CMOS PCB.

12

Detect2 ~

Table 3.1 Inserted opens of CMOS PCB and their detect results

FOI A15 - In setup, not connectedF02 A16 - In setup, not connectedF03 ALE - In setup, not connectedF04 CSI Chip Select Disabled or enabled RAMI NFOSI WE Write Enable No distinction between read and write NF061 OE Output Enable No distinction between not-selected and read NF071 ADR14G Address bit 14 Possible wrong memory cell addressed NF08 ADR14 Address bit 14 Possible wrong memory cell addressed NF09 WE Write Enable No distinction between read and write NFlO OE Output Enable No distinction between not-selected and read NFll DQ7 Data bit 7 Possible wrong data bit 7 NF121 DQ7G Data bit 7 Possible wrong data bit 7 N

~ Jumper I Signal net I Description I Remarks

Notes:

1. These opens are in global signal nets (signals to all chips). The other defects arelocal (signals to Static RAMI).

2. None of the opens could be detected, because of the two problems. (N stands forNOT detectable)

Shorts

rnA

60

50

40

30

20

10

SpecDatasheets

VssShort

11IIIII

VddShort

___ JIlIIIL _

SignalShort

Fault freeminimax

SRAMsminimax

OCTALsminimax

24 rnA (min. short)

14 rnA (max ADV)

4 rnA (Fault free)

Figure 3.3: The (variation in) static PSC consumption for shorts (CMOS PCB)

In general, at (more complex) CMOS assemblies is the detection of shorts also influenced by thetwo problems, see appendixG. In case of the demonstration CMOS PCB, the detection of shortsis not influenced by the two problems. This is because of the very large difference between themaximum fault free PSC consumption and the minimum short current. The current increase, fig­ure 3.3, is more than six times higher than the maximum static PSC (measured maximum valueis 4mA, all pull-up circuits activated).If the short is inserted between two output drivers of different chips, the current increase is de­termined by the output driver which is driven high, see chapter 2.

13

Figure 3.3 shows the PSC behavior of the CMOS PCB for Vss, VDD and signal shorts, see previouschapter for a description about these shorts. The current change caused by the VDD-short is largerthan that of the current change caused by the Vss-short and the signal-short. This is because thelower transistor of the switching tree of the output driver can sink a higher current than the uppertransistor can source, see chapter 2. The measured short currents are displayed in appendix FAand F.3.

The large variation in the specs is caused by the large variation in current consumption for thePCB components as listed in the data-sheets. The spec values are therefore not accurate enoughto determine or calculate the detection threshold(s).

In this case, the short detection is rather simple. All shorts (shorts between signal nets and shortsbetween a signal net and the power supply) elevate the current consumption above a certainmaximum current value (maximum ADV, see chapter 2). The maximum ADV is determined at14mA (the value between the maximum PSC of the fault free board, 4mA, and the minimum shortcurrent, 24mA). In this case the RDV is almost equal to the maximum ADV, ::::::12mA (the valuebetween the maximum PSC variation of the fault free board, 3mA, and the minimum relativeshort current, 24-4 = 20mA).

3.1.3 TTL assembly

This subsection starts with a brief description about the demonstration TTL PCB and how opensand shorts were introduced.

The TTL PCB contains eight LEDs, three TTL chips (74LS04, 74LS139 and the 74LS157)and three TTL boundary-scan octals (74BCT8244). The schematic diagram is displayed in ap­pendix CA. All chips are TTL and run on five volt. The inputs and outputs of the board and theboundary-scan octals are directly accessible by flat cable connectors. The inputs and outputs areconnected to an external boundary-scan chip (DIOS) [11]. The inputs and outputs of the octalsare accessible by means of the boundary-scan protocol [5]. The board can be put into a particularoperating state by loading the related test vector into the three octals and DIOS.

Opens and shorts are created on this board by removing or placing jumpers. The jumpers aremarked by an X which is followed by a number, see appendix CA. Appendix D.2 lists the essentialsets of test vectors (sequences).

PSC estimation with respect to the specs

The PSC estimations of the TTL PCB are based on the static PSC consumption as observed inthe Vee-line of the power supply. These estimations are calculated per test vector as follows: thetotal value of the static quiescent currents of all chips is added to the value of the input currentsof each chip. For several conditions, fault free and for several defects, the estimation is calculated.The following issue must be kept in mind during the calculations: defects in the test signals, whichare powered by a secondary power supply, are not detectable if they are driven high (see previouschapter). The estimations can be found in appendix F.5.

Observations concerning opens and shorts

Two observations can be made from these calculated estimations. First, the shorts should bedetectable by static PSCM because of the large increase of PSC (e.g. 100mA). Second, openschange the PSC through the board too little to be detected. Open X4 decreases the PSC by atmost 1.8mA when its net is driven low and open Xl decreases the current by as little as 20JLAwhen its net is driven high, the real current change will be much lower. Direct detection of opensis therefore very difficult.

14

Moreover, the calculation/determination of a detection threshold for shorts is not unambiguouswith respect to the specs. There is a very large difference between the minimum and maximumPSC estimations for the detection thresholds and detection test vectors (test operating states ofthe board). Specs are therefore not accurate to calculate the detection threshold and not adequateto determine the detection vectors.

Table 3.2 shows the defect jumpers and their potential detect method.

Table 3.2 Inserted defects of the TTL PCB and their potential detect method

XOl (0) U12(lO) U13(13) U13(13) high, U13(12) 0X02 (S) U12(12) U12(1l) U13(lO) and U13(6) equal SX03 (S) U12(9) U1(7) BST_GATE and U13(8) opposite SX04 (0) Ul(8) U21(15) U21(15) and U3(17) high, U21 disabled 0/1

U3(17) 0/1X05 (0) U1(9) U3(16) U3(16) high 0X06 (0) U12(7) U2(20) U2(20) high 0X07 (S) U3(5) U3(7) LED3 = LED4 = U3(5) and U3(7) SX08 (S) U21(4) U21(7) U3(22) and U3(23) equal SX09 (S) Ul(9) Ul(8) BST..sEL1 and FBST_I equal S/I

Ul(9) UI(IO) FBST_I and FBST_2 equal S/IXIO (0) Ul(12) TMS-B UI(12) high, VI and U2 in bypass mode 0/14

X1l5 (S) Ul(19) Ul(20) UI(19) and UI(20) equal SXI2 (S) UI(23) UI2(9) UI(23) = INO and UI2(9) SXI3 (S) U1(IO) UI(15) UI(15) = IN7 and UI(lO) SXI4 (S) UI2(12) UI(ll) operating mode/outputs U2 changed 16

XI5 (S) U2(2) U3(2) U21(2) = U2(2) and U3(2) SXI6 (S) UI(ll) U2(1l) operation mode/outputs U2 changed 16

XI7 (S) UI(ll) U3(1l) operation mode/outputs U2 changed 16

~ Jumperl I Defect between2 I Remarks I Detect3 ~

Notes:

1. The jumper in question inserts an open (0) or a short (S).

2. x(y) means pin y of IC x, for example UI(lO) means pin 10 of UI.

3. The defect can be detected using direct open detection (0), direct short detection(S) and/or indirect detection (I). More information can be found in chapter 2.

4. This defect changes the mode in which the TAP controllers [4, 5] of the boundary­scan chips are operating. All boundary-scan chips, except for the last boundary­scan chip U3 (which drives the LEDs, appendix Co4), are set in the bypass modewith all outputs high (transparent, lowest current state).

5. The defect is not detectable, because the inputs are powered by a secondary powersupply and the PSC is measured in the positive power line, see also chapter 2 andappendix F.6.

6. These defects change the mode (TAP controller, input and outputs) in which theboundary-scan chips are operating. In the used measuring method, these defectsare not directly detectable (TDO is in tristate). Moreover, the operating state inwhich the PCB is set is determined by the previous operational state.

Measuring results

The PSC consumption of the fault free board (demonstration TTL PCB) and in case of opensand shorts is displayed in figure 304, 3.5 and 3.6. The measuring data is displayed in appendix F.6

15

and F.7).

Opens

rnA

Spec MeasuredVector 2

250

200

150

100

50 j .. _ c••• ,

Spec MeasuredVector I

II

- .... J

r:J...•..•..•.••.....•.•...LiJ

•D

III

Fault free PCBminimax

Open (Xl)minimax

Open (X4)minImax

All opensminImax

Figure 3.4: The (variation in) static PSC consumption for opens (TTL PCB)

Figure 3.4 shows for two conditions (two test vectors) the variation in theoretical and measuredPSC values for the fault free board and several opens. The difference, O.2mA typically, betweenthe PSC consumption of the fault free board and the PSC consumption caused by the openconnections is very small for both theoretical (specs) and measured values. Moreover, this differenceis smaller than the measuring equipment accuracy (O.3mA maximum). Also, PSC consumptionmeasurements at different moments in time for identical conditions show some variation. In general,this variation is larger than this difference. For this reason, direct detection of opens is impossible.

rnA

180.0

120.0

60.0

30.0

=

Spec Measured ..Interconnect test vector 17

Fault free & opensmin/max

BST-open (XIO)min/max

Short (X9)minimax (vector 17)

BST-short (X14)min/max (vector 17)

45.0 rnA (min. ADV)

Figure 3.5: The (variation in) static PSC consumption for boundary-scan open (TTL PCB)

The boundary-scan open X10 is detectable, because of the large negative change in PSC consump­tion (25niA), see figure 3.5. This defect changes the mode in which the TAP controllers [4, 5] of

16

the boundary-scan chips are operating. All boundary-scan chips, except for the boundary-scanchip U3 (which drives the LEDs, see appendix CA), are set in bypass mode with all outputs high(transparent, lowest current state). U3 is controlled by its own control signals. The PSC of thetotal PCB is therefore determined by the state in which U3 is operating (between 30 and llOmA).In this case the defect can be detected by choosing a test vector which has a larger PSC value inthe fault free condition (for example test vector 17, 60mA). The defect can therefore be detectedby using a minimum ADV of 45mA.

Shorts

rnA

300

250

200

150

100

50

direct detection

indirect detection--"""Ill= Max.

ADV

Fault free & opensmin/max

Short (X7)min/max

Short (X9)min/max

BST-short (XI4)(sequence depended)min/max

Spec MeasuredInterconnect test vector 14

Figure 3.6: The (variation in) static PSC consumption for shorts (TTL PCB)

Figure 3.6 plots the theoretical PSC values against the measured PSC values for several shortsand the fault free board. This figure shows that the difference between the minimum and max­imum theoretical values is very large. This large difference is due to the large variation in currentconsumption of the PCB components as listed in the data-sheets. Spec values are therefore notaccurate to determine the detection threshold(s).

Furthermore, the figure also shows that the measured PSC values caused by shorts are higherthan the PSC consumption in the fault free condition. The shorts X7 and X9 are shorts in theoutput drivers of the boundary-scan octals. The short X14 shorts a signal net with a boundary­scan control signal. This changes the test vector and control vector patterns which are shifted intoU2 when the signal net is driven low. The shorts X7 and X9 are directly detectable and X14 isindirectly detectable, see also table 3.2. The detection of these shorts is quite simple. These shortselevate the current consumption above a certain maximum current value (maximum ADV).

The table in appendix F.6 shows that all shorts in the TTL PCB increase the PSC several tens ofmilli amperes. The shorts are detectable by PSCM using a subset of the interconnect test vectors(e.g. test vectors 6,8 and 10, figure 3.7) and a maximum ADV of 120mA. However, the change inPSC which is caused by the shorts X14, X16 and X17 depends on the previous operating state(s)of the PCB. This must be taken into account when the ADV is calculated/determined and makesthe determination which test vectors to use and the calculation of (a) detection threshold(s) (ADVor RDV) quite complex. The RDV for this board, figure 3.8, is determined at 20mA.

Table 3.3 shows the defect jumpers and their actual detect method.

17

Table 3.3 Inserted defects of the TTL PCB and their detect results

XOI (0) U12(1O) U13(13) U13(13) high, U13(12) NX02 (8) U12(12) UI2(1l) U13(lO) and UI3(6) equal 8X03 (8) U12(9) Ul(7) BST_GATE and U13(8) opposite 8X04 (0) Ul(8) U21(15) U21(15) and U3(17) high, U21 disabled N

U3(17) NX05 (0) Ul(9) U3(16) U3(16) high NX06 (0) U12(7) U2(20) U2(20) high NX07 (8) U3(5) U3(7) LED3 = LED4 = U3(5) and U3(7) 8X08 (8) U21(4) U2l(7) U3(22) and U3(23) equal 8X09 (8) Ul(9) Ul(8) BST..sELl and FBST_l equal 8

Ul(9) Ul(lO) FB8T_1 and FB8T_2 equal 8XlO (0) Ul(12) TMS..B Ul(12) high, Ul and U2 in bypass mode IX1l4 (5) Ul(19) Ul(20) Ul(19) and Ul(20) equal 8X12 (8) Ul(23) U12(9) UI(23) = INO and U12(9) 8XI3 (8) UI(lO) Ul(15) Ul(15) = IN7 and ,Ul(lO) SX14 (8) U12(12) UI(ll) operating mode/outputs U2 changed 85 /1XI5 (8) U2(2) U3(2) U2l(2) = U2(2) and U3(2) 8X16 (8) Ul(ll) U2(ll) operation mode/outputs U2 changed 85 /1XI7 (8) Ul(ll) U3(ll) operation mode/outputs U2 changed 55/1

~ Jumperl I Defect between2 I Remarks I Detect3 ~

Notes:

1. The jumper in question inserts an open (0) or a short (8).

2. x(y) means pin y of IC x, for example Ul(lO) means pin 10 of UI.

3. The defect can be detected using direct open detection (0), direct short detection(8) and/or indirect detection (1). The character "N" means that that particulardefect could not be detected by P8CM. More information about direct and indirectdetection is found in chapter 2.

4. The defect is not detectable, because the inputs are powered by a secondary powersupply and the PSC is measured in the positive power line, see also chapter 2 andappendix F.6.

5. The boundary-scan chips do not comply with the boundary-scan architecturestandard [5J with respect to the states ofTDO; TDO never goes in tristate. Hence,defect X14, X16 and X17 are direct and indirect detectable. The operating statein which the PCB is set is determined by the previous operating state.

18

*

Arbitrary vector

I_________ J~------------j\I)'1

~.... ...L.I RDV

~

*

Short (XI2) II Short (XIS)

Short (X13) II BST (XI6)

BST (XI4) II BST (XI7)

* *

Detect vector 3

.;:;.

**

liilill=::;:'

I:f:'

*

IDetect vector 2

~&.~

~

*

lliI:~il

* = adv detectable

Detect vector 1

_ Golden + open II Short (X7)

_ Short (X2) II Short (X8)

II Short (X3) II Short (X9)

'0 '"rj

~&G'(l) ~

A-Cilpo C».....(l) :;1

g f-3 rnA~f-3

~ t"'C. "tl~(:) 200~t:O0'-'< ~~ ~

160t:r-po ........ A-'0 (l)po ~

.... (l)~n

120_. ~n -,~ 011>=='.... :E~g: 80~~

<: t:r.... ~ (l)co .... no po 40.... n~

11>....(l)

A-

>t;j<:"tlen(:)

e.~

rn:Et:rg:~....(l)

=='0....A-Uj'I

rnA * = adv detectable

Short (X9)

RDV

I*

Arbitrary vector

. - - - . . . . ..

** *

Detect vector 3

Short (X12) • Short (XIS)

Short (X13) III BST (X16)

III BST (X14) II BST (X17)

***

;;:.;.*

Detect vector 2

II Short (X7)

emlli1W Short (X8)

*

40~ 11:..111'::::1. I'~

-.. -- !!llljll~1 .....-

6J]@IDj Short (X2)

ITTIIIlllillil Short (X3)

80

Detect vector 1

160

120

200

t:' 'Tjro ....roOClp..~ro ...p..ro

O'~... co-..o 1-3~1-3;t'"'P"'"'C:lg (")-ttln -o(§ ~... ~Il' ......

0Cl -~p..

ro-ron...O·t:'

~.-P"-l-,j P"o ro

n

~~

~rop..

§-<:0'...ro

~~-o~

----m-oo00

<~-oU1

3.2 Dynamic fault detection

+r--......I

+

Scope

Figure 3.9: Dynamic PSC measurement diagram.

The method proposed by Arguelles et al. [6] presents a different way to test circuits. The methodthey used, was the analysis of the transient or dynamic PSC behavior (time dynamic PSCM) formixed signal rcs. This method and level dynamic PSC measurements are used in this section todetect defects on assemblies.To be able to detect the smallest dynamic current change and the switching spikes, and also limitthe external influence of the measuring equipment, an amplifier is used (the amplifier has highslew rate and high input impedance).

The dynamic detections (level and time dynamic PSCM) of manufacturing defects are checked forone assembly only. The results presented in this section are from the demonstration TTL PCB(schematic diagram is displayed in appendix CA). Figure 3.9 displays the simplified measuringschematic diagram (the real diagram is discussed in appendix C.2).

The input and output drivers (test signals) from the tester (Tester 2, appendix B) are powered bya secondary power supply and the PSC values are measured in the Vee-line of the PCB. Opensand shorts are therefor not detectable in these test signals, see chapter 2. The reason why thisapproach is chosen is to limit the interference of the tester signals (TDI, TDO, TMS, OUTO-7, ... )in the measured dynamic current values.

Figure 3.10 shows the behavior of the PSC through the board without and with two particularinternal opens X4 and X5, respectively. These patterns were obtained by continuously applying(injecting) two test vectors. These two vectors drive the net at which the opens are introduced tohigh and low, respectively. These opens change the PSC pattern, see the dips in the X4 and X5pattern in relation to the fault free pattern.

Figure 3.11 shows the real PSC signal. The alternate basic current signal is due to the large powerconsumption variation of the boundary-scan chip Dl when its outputs toggle between logic levels.The pattern in figure 3.10 is superimposed on this basic current signal and is due to the currentconsumption of the boundary-scan chips shifting the test vectors through the boundary-scan chain(the response of X4 is later, seen in time, than the response of X5, this complies with the order inwhich the responses of X4 and X5 are shifted through the boundary-scan chain [25]). The opensXl and X6 are not detectable because the current change (74LS-chip, OAmA) caused by thesedefects is much lower than that of the opens X4 and X5 (74BCT-chip, ImA). All defects in theboundary-scan lines [4, 5] and all shorts were detected by level dynamic PSCM only.

No actual switch moments (e.g. spikes) were measured or detected because the measuring fre­quency, which could be obtained with the available equipment, was to low. The CMOS PCB andseveral other assemblies were checked by a tester capable of running at lOMHz. The TTL PCB

21

vt ftJ ,', ~V ~ ..(j(~t

I I I I

~::: ~tI I I

I II I

~t

Fault free

OpenX4

OpenX5

Figure 3.10: PSC pattern fault free versus opens X4 and X5.

PATTERN*

-iBASIC

CURRENT

OFFSET

-t

Figure 3.11: PSC behavior. (* see previous figure)

and also other assemblies were controlled by a tester which was connected to the parallel port ofa computer. In all cases the measuring frequency was 25000 measurements per second or lower;in case of the CMOS PCB, each measurement needed approximately 400 clock cycles. Dynamicmeasurements are typically run at IMHz or higher [15]. Moreover, the capacitors on the assembliesand test equipment are also large, filtering the high frequencies (e.g. spikes).

22

Chapter 4

Conclusions

The conclusions with respect to the detection method discussed in this report, detecting manu­facturing defects with the use of Power Supply Current Monitoring (PSCM), are discussed in thischapter.

The direct current (DC) parameter accuracy from the data-sheets of the assemblies' componentsare not sufficient to estimate the PSC consumption of the assemblies and to calculate the detectionthresholds. Therefore, data concerning the PSC consumptions of the assemblies (PSC consump­tion for several defects, PSC variation between identical assemblies, etc.) must be obtained frommeasured PSC values of "golden assemblies" (totally fault free assemblies).

4.1 Manufacturing defect (open/short) detection

Several assemblies were subjected to static and dynamic PSC measurements to identify the abilityof PSCM to detect opens and shorts. No dynamic PSC measurements could be done, becausethe measuring frequency which was obtainable with the available measuring equipment duringthis research, was to low. The measuring frequency was about 25000 measurement per second.Dynamic measurements are typically run at 1MHz or higher [15]. The following conclusions canbe made with respect to static PSCM:

• Direct detection of opens is impossible by static PSCM for CMOS and TTL assemblies.The reason for this is, the PSC change which is caused by opens is negligible in relation tothe absolute static PSC of these assemblies. Moreover, the PSC consumption measured atdifferent moments in time for identical conditions (fault free and defects) shows already somevariation. This variation is in general higher than this change. Direct detection of opens istherefore impossible.

• Shorts are directly detectable by static PSCM. However, the current increase which is causedby these defects must be higher than the measuring equipment accuracy and higher than thevariation between identical measurements (at identical assemblies and under identical testconditions). If this is the case, the detection of shorts can done by using absolute (ADV) orrelative (RDV) detection values (see chapter 2), depending on behavior of the PSC at thetest operating states (the used test vectors).

The ability to calculate a maximum or a minimum ADV depends on the PSC behavior at thedetection test operation states of the golden assemblies. If the variations in PSC of the fault freeassemblies is low and the changes in PSC caused by the defects exceeds this variation an ADVcould be calculated. If this is not the case, then the RDV tool should be used as the detection

23

method (scale enlargement). However, this measuring tool is much more complex than the toolused by ADV. The determination of the test vectors which are to be used for the detection andthe calculation of the detect threshold can be quite complex, when the change in PSC depends onthe previous states.

Furthermore, controllability of the signal nets from and to the assembly components is requiredto put the assembly into different operating states to be able to detect the defects.

4.2 Usability of PSCM and its future

PSCM is usable to detect shorts both directly and indirectly, and to detect opens indirectly. Dataof the assembly components in the data-sheets is not accurate enough to determine or calculatethe detection thresholds, hence golden assemblies are required to obtain the PSC information. Forthis reason is it very difficult to develop automatic tools for PSCM. Also, (remote) controllabilityof the assembly logic is required to be able to detect the manufacturing defects. The followingstatements must hold to be able to make use of PSCM:

• PSCM can be used for small assemblies. Automatic tools are not jet available, the test vectorgeneration and determination and the calculation of the detect thresholds must be done byhand. Therefore, PSCM is only economical for small assemblies.

• To detect opens there must be large current differences between states. Results in this re­port have shown that opens are not direct detectable, hence, opens must be made indirectdetectable (Design for Testability).

• Controllability of the signal nets from and to the assembly components is required. Thecontrollability can be achieved structurally, e.g. boundary-scan, or functionally. A good ex­ample of functional testing by PSCM is the pager marketed by Philips. Its a small PCB witha processor which has direct access to all components of this PCB. The processor excitesthe signal nets to activate several conditions (e.g. the display on/off, the pager on/off, ... ).When these conditions do not occur, caused by a defect, the change in PSC consumption issignificantly. Therefore, almost all defects are detectable by PSCM for this pager (yield of95%).

From the measurements (especially, measurements on CMOS circuitry) in this report can beconcluded that environmental conditions (EMC) but also the warming-up of the assembly itselfinfluence the measuring results significantly. Furthermore, TTL components are currently replacedby CMOS counterparts, for example HCT technology, because of the improved characteristics. Thismeans that for practical usage of the PSCM method actions have to be taken to eliminate theenvironmental influences. These problems increase the measuring time and test costs significantly.

From the results presented in this report, it can be concluded that static PSCM is not capableof replacing the existing logic level testing methods (observing logic values of lCs). This methodcould complement the existing logic level testing methods and it is a go/nogo method. To diagnosethe defects, e.g. locate the defects, another test method is necessary; there are to many factors ona assembly which change the PSC consumption. The classification of PSCM with respect to othertest methods and its application area is for further study. The problems stated in the previousparagraph must be eliminated to make this method economical and costly efficient.

Taken the investigation results in consideration, it was not useful to start tool development beforethe mentioned problems with this method are solved.

24

4.3 Advice to continue

• Define more accurate component specification.

• Solve environmental problems.

Automatic tools can now be developed. However, the problems concerning opens still exist.

My task stated in the introduction of this report has been performed for several TTL and CMOSassemblies. I hope that the results obtained during my work and the analysis performed give anaccurate picture of the ability of the investigated test method to detect manufacturing defects byusing Power Supply Current Monitoring (PSCM).

25

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27

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[18] Eerenstein, L.A.RDAB PRODUCT RANGE (DSP Structural Test)Philips Electronics, Report DAB452-HSTDSP, 1995

[19] Biewenga, A.DAB PRODUCT RANGE (Structural Test)Philips Electronics, Report DAB452-HSTHW, 1995.

[20] Delaruelle, A, and J. HuiskenFADIC123 APPLICATION NOTEPhilips Research Laboratories, 1995.

[21] Delaruelle, A. and J. HuiskenSIVIC APPLICATION NOTEPhilips Research Laboratories, 1995.

[22] Data-sheet: AD847 (Operational AmplifierVoorraadmap Nat.Lab.

[23] Data-sheet: HE4000B Logic family CMOSPhilips Semiconductors, 1992.

[24] Data-sheet: 74F Fast TTL Logic serie (ICI5)Philips Semiconductors, 1988.

[25] Data-sheet: 74BCT8244Texas Instruments, 1989.

[26] Data-sheet: 74LS Logic serie (IC09)Signetics Logic Products, 1985.

[27] Data-sheet: 74HCT Logic serie (IC06)Philips Semiconductors, 1993.

[28] Data-sheet: J-LPD Static Random Access MemoryNEC.

[29] Data-sheet: DATA SHEET BOEK (DUTCH)NL: Elektuur 1986, ISBN 90-70160-24-2.

28

[30] Data-sheet: 424400-60LNEC Dynamic CMOS RAM

[31] Data-sheet: DSP56156 Technical Data SheetMotorola Semiconductor, 1992

[32] Data-sheet: GAL16V8Lattice Semiconductor, 1993

[33] Data-sheet: M27C512Signetics, 1989

[34] Data-sheet: MAX232AMAXIM Integrated Products, 1992

[35] Datasheet: MCM6206CJ15Motorola FAST SRAM DATA

[36] Datasheet: MSM51257ALLOKI Semiconductors

[37] Datasheet: P87C528EBAA Micro controller (IC20)Philips Semiconductors, 1993

[38] Datasheet: PCF8574T (IC21a)Philips Semiconductors, 1989

[39] Datasheet: SAA2501 DAB decoderPhilips Semiconductor, 1995

[40] Data-sheet: SCC2692AC Data communication products (IC19)Philips Semiconductors, 1994

[41] Data-sheet: ST24C04MLISGS-THOMSON Microelectronics, 1993

[42] Data-sheet: TDA1543AT, SA5230 Linear products (ICll)Philips Semiconductors, 1991

29

Appendix A

The literature search

This appendix presents the results from the first part of my task, the literature search. Publicationson the subject, Power Supply Current Monitoring, are recently written. In agreement with mysupervisor is the period, over which is searched, determined from January 1988 up to September1994 (so far the primary and secondary sources were updated).

The first section of this appendix lists the selection criteria. This is followed by a section whichlists the search strings per source and the publications found (words between square brackets arethe fields on which is searched). The last section of this appendix gives the conclusions.

A.I Selection criteria

A publication was added to the literature list when it complied with at least one the followingcriteria:

1. The publication must contain information about testing assemblies, Printed Circuit Boards(PCBs) or Multi Chip Modules (MCMs), by measuring the power supply current.

2. The publication which refer to direct current (DC) parameters (power consumption, leakage,threshold, short current, ... ) of assemblies.

A.2 Publications

Inside Philips

Source: The OPC, 'Online Publieks Catalogus' is the catalogue of the library of Philips ResearchLaboratories Eindhoven and is a part of the BAS, 'Bibliotheek Administratie Systeem'. The cata­logue gives an overview of the available books, journals, reports (internal) and reprints (externalpublications of employees).

31

Reports Nat.Lab.Description:

These are the internal Nat.Lab. reports starting from 1984 and the research reportsfrom other labs which were given to Philips.

Search keywords/phrases: [title, keywords]MCM, multichip, param*, PCB, printed circuit, test and current.

Search (medium) period:(OPC) 1984 - September 1994

Found:none.

Reprints Nat.Lab.Description:

External publications of researchers from Nat.Lab., starting from 1984.

Search keywords/phrases: [title, keywords]MCM, multichip, param*, PCB, printed circuit, test and current.

Search (medium) period:(OPC) 1984 - September 1994

Found:none.

Journals PhilipsDescription:

Article collection of the Philips Research Lab.

Search keywords/phrases: [title]MCM, multichip, param*, PCB, printed circuit, test and current.

Search (medium) period:(OPC)

Found:none.

Outside Philips

CompendexDescription:

Technics, particularly mechanical engineering.

Search string: [A: title, word/phrase, B: authors]A) multichip, multi-chip, pcb, mcm, module, printed circuit, board

result previous search limited to: testresult previous search limited to: current, param?

B) kearkkeainen, karkkainen, tiens?, weissenfelt

Search (medium) period:(CD-ROM, Dialog) 1986 - 1994

Found:none.

32

Current Contents (Engineering, Technology & Applied Sciences)Description:

Current Contents (CC) is published weekly and contains references to several thou­sand articles from journals/ magazines and books. CC is updated at about the sametime the articles are written, hence CC is truly up to date.

Search keywords/phrases: [title, keywords]MCM, multichip, parm*, PCB, printed circuit, test and current.

Search (medium) period:(ONLINE) issues 18/38, 2 May 1994 - 19 September 1994

Found:none.

Dissertation abstractsDescription:

Dissertations out of the USA.

Search string: [A: title, abstract, classification, free terms, B: authors]A) (mcm or pcb or (circuit board) or multichip or module) and (parameter or

current) and test.B) kearkkeainen or karkkainen or tiens? or weissenfelt.

Search (medium) period:(CD-ROM, ProQuest) 1988 - June 1994(PART-B) January 1986 - December 1987

Found:none.

INSPECDescription:

This documentation information system contains information concerning physics,electric and information theory (computer) articles (references).

Search string: [A: title, abstract, classification, free terms, B: authors]A1)DE(electric current) and DE(testing) and (DE(parameter estimation) or

DE(multichip modules) or DE(printed circuit testing))A2)(mcm or pcb or (circuit board) or multichip or module) and (parameter orcurrent) and test.B) kearkkeainen or karkkainen or tiens? or weissenfelt.

Search (medium) period:(CD-ROM, ProQuest) 1989 - March 1994(ONLINE) 1988

Found:1994, "Boundary scan testing combined with power supply current monitoring"written by Karkkainen et al. [3]. The references given by this paper refer to paperswith no information concerning the subject of this literature search.

33

NTISDescription:

Report literature with respect to technical reports written in the USA.

Search string: [title](multichip or multi-chip or pcb or mcm or module or (printed circuit) or board)and (current or param*) and test*

Search (medium) period:(CD-ROM, SPIRS) 1988 - September 1994

Found:none.

Science Citation IndexDescription:

Documentation information system on technical science.

Search string: [A: title, B: authors]A) param* and (mcm or multichip or multi-chip or module or pcb or board or (printed

circuit) )B) kearkkeainen or karkkainen or tiens* or weissenfelt

Search (medium) period:(CD-ROM, lSI) January 1988 - June 1994

Found:none.

VUBISDescription:

Online library catalogue of the TU Eindhoven and other connected library centers.

Search keywords/phrases: [A: title, keyword, B: authors]A) printed circuit, current & test(ing), circuit & (MCM , PCB, test)B) kearkkeainen, karkkainen, tiens*, weissenfelt

Search (medium) period:(ONLINE) - September 1994

Found:none.

A.3 Conclusion

The literature search presented one (recent) publication only. The search of publications prior (2years) to the agreed search period (January 1988 up to September 1994) was without result. Thepublication, paper [3], states that if boundary scan testing is combined with power supply currentmonitoring, following advantages are reached:

1. Application area and test coverage of standard test patterns are enlarged.

2. Fault identification properties are improved.

3. Overloading due to test bus fail functions, wrong stimulus or physical defects is quicklydetected with current monitoring.

4. Analog circuitry tests are possible ifanalog voltage are suitable to be controlled via boundary­scan path.

34

However, the paper, proves and explains only a part of the third advantage. The other advantagesare not described and proven within the text. Moreover, the results presented in this paper arealmost all related to special instances of certain defects (defects in the boundary-scan chain) orpower supply net defects. Defects in the signal nets are not considered. Also, there is no referencesto the measuring circuit and used equipment (equipment parameters: internal resistance, measureresolution, ... ).

Other publications written by these authors, and mentioned references to and from these publica­tions did not contain any information about the subject. The authors are normally not concernedwith test methods, but more with the design of simulation models and the bonding process.

The information from the paper is not adequate to state general conclusions about the abilityof PSCM to detect manufacturing defects on assemblies (especially PCBs). Many questions andsolutions had to be worked out in the secondary part of my task, the investigation of the usabilityof PSCM. This part is structured as follows:

1. The search for the possible manufacturing defects on assemblies.

2. The simulations and/or measurements of power supply current on different assemblies forseveral chip technologies.

3. The analysis of the results from these simulations or/and measurements.

4. Conclusion concerning the ability of PSCM to defect manufacturing defects on assemblies.

35

Appendix B

Equipment list

Power supplyPhilips PE4818 (no. 0.8543)Philips PE1542 (no. OM.03.1424)

Programmable power supplyPhilips PM2813 (30V/10A/60W)

MultimeterPhilips PM2502 (no. CFT.BC.09103, deviation = 1.5% full-scale, RA/V = 40kn)Philips PM2527 (no. OM.03.1424, deviation = 0.15% + digit, Rv = 10Mn)

OscilloscopeTektronix 2430A (no. 615501, memory scope, R; = IMn)Philips PM3540 (no. CFT 0.619, logic scope, Zi = lOMn/20pF)

Tester 1Philips PM3720 boundary-scan tester [13] &Philips PF2111/10 digital I/O scan module [11] &Philips PF2130/10 ttl/cmos TAP POD boundary scan tester

Tester 2Philips PM3705 boundary-scan controller [12] &Philips PF2111/10 digital I/O scan module [11]

Tester 3Philips PM3720 boundary-scan tester (blaster) [13] &Philips PF2111/10 digital I/O scan module (2 x) [11] &Philips PF2130/10 ttl/cmos TAP POD boundary scan tester (2 x)

36

Appendix C

Diagrams

C.l Static PSCM measure schematic diagram

Two methods [8) can be classified to measure the current through electrical components or as­semblies. Which method is to be used, depends on the internal resistance of those components orassemblies in relation to the internal resistance of the measuring equipment. The error which ismade can be characterized into two categories. The error caused by the chosen method is calledthe method error. The second category of error results from read errors (parallax) and equipmentaccuracy. When the right equipment and method is chosen for a given situation, then, in general,the method error will be negligible or a correction factor can be calculated.

~ Ix~

+Vx

Tester>-::a Test vectors

8 &CI.)

'" Test response'" PCV <t::

Figure C.l: Static (quiescent) current measurement diagram

The first method, shown in figure C.I, is used to measure a large current consumption. The methoderror is calculated by the following equations:

{Ix = I - ~v E[ = ~v ,see figure C.IVx = V Ev =0

(C.I)

The digital multimeter (PM2527), see appendix B, is used as a voltmeter. The internal resistanceof this voltmeter (Rv ) is 10M!"!. The voltage (Vx) across the boards (CMOS and TTL PCB) ismaintained constant at 5 Volt throughout all measurements. The maximum method error (E[)is 0.5JLA (5V110M!"!, E v = 0). With respect to the measurements done in this report, all meas­urements except for the open measurements on the CMOS PCB, the method error is negligible(versus ImA and higher).

37

1=1x~

v;>,:0 Test vectorsE~<Il Test response

<

Tester

&

PC

Figure C.2: Static (quiescent) current measurement diagram

The second method, shown in figure C.2, is used to measure a small current consumption. Themethod error is calculated by the following equations:

{Ix = I E[ = 0 ,see figure C.2Vx = V - I X RA Ev = I X RA

(C.2)

The analogue multimeter (PM2502), see appendix B is used as a currentmeter. The internalresistance of this currentmeter (RA) is at most lOn. The maximum method error (Ev) is 10 x Imax •

With respect to the open measurements on the CMOS PCB, the method error (3.2mV maximal)is negligible (versus 5 Volt).

C.2 Time dynamic PSCM measure schematic diagram

+5V

Tester

Test vectors t:Q

& u"-

Test response ~E-

PC

+12V

-12V

Figure C.3: Dynamic (transient) current measurement diagram

The dynamic PSC behavior is displayed onto an analogue oscilloscope (Philips PM3540, see ap­pendix B). This type of scope has great difficulty to display small fast changing voltage signals.To be able to detect the smallest dynamic current change, an amplifier (AD847, data-sheet [22]) isused between the current sensor, current-to-voltage convertor, and the scope. The current sensor

38

consists of a resistor (R15) which is placed in the ground power-supply line of the TTL PCB, seefigure C.3. The value of this resistor is O.15D (5W, ±10%). The variation in the voltage across theboard (5 Volt typ.) is very small due to the low sensor resistance. The voltage across the currentsensor is amplified by a factor 1001 [9]. The relation between the PSC through the board and thisamplified voltage is captured in the following equation:

I = Uscope ~ Uscope

1001 x 0.15 150

To limit the influence from the environment, the amplifier is placed close to the TTL PCB.

39

(C.3)

(1.~

(1

~o00

1:1(1to

[!][!]GND VCC

244

OCTAL5~

RAM2

GGVCC RAMIRAMl

•• F1 A15

•• F2 A16

•• F3 ALE

~ },~"~,•• F4 CS1+ •• F5 WE

EPROM 1A141 { : ~~~~~~~~ .. F60E

• } SRAM IA141 •• F? ADR14G

EPROM /lpp) { : R1 ... R8 •• F8 ADR14 RAMl

•• F9 WE RAMl

•• FlO OE RAMI

•• Fll DO? RAM1

•• FI2oo?G

•• NOT USED•• NOT USED

OCTAL2.r-

'Tj

0DMUXI

ot;' G"~,, .. '"0>::0-; CS0(2) •• CSI(2)Cl)

138 CS0(3).. CSI(J)0~ CSO(4) •• CSH4)

MA15 •• MOIl GND •• GND0 MA16 •• M0I2~ MADE •• M0I30 MWE •• M0I4 OCTAL3en

MOE •• M0I5~

MALE •• M0I6 SRAM EPROM BOARD0,;,. tl:l MAO •• MOl?0

MAl •• M0I8 Alex Biewengat"' MA2 •• Mool~ 28 October 19940 MA3 •• Moo2>:: MA4 •• Moo3<T

~ MA5 •• Moo4

S MA6 •• MOOS

0 MA? •• MD06l:l MGll •• MOO?

I3~JADRI(81 •• ADRK8)en

<T GN •• Moo8 ADRI(91 •• ADRK910-;

II' GN •• GND ADRI(lOl •• ADRK101<T

0' ADRll1ll •• ADRK11ll:lADRI(12) •• ADRI(12)

ADRI(13) •• ADRI(131ADRI(14) •• ADRK141

GND •• GND

m6

'---­

-....I+~

'\TnI'm '·.rib ~ iii~

I: ::.. ..n .... ..

'"....•n.....H

U:~~~$l$l:t!**!$ttt=====i~. :0""'--

RAM!.m..~.-------

r[~~~~~!i;~I~"AI

•it .,1.. ..,. ....n .... .... '".....

I II to "~:.:

OCTALS DCTAL6

~.I§.~

RAM2 RAMJ RAM1

=olieEll !!OliOON =ol.!1lQIJ?~T l2 -9~T CJ J?~T C'1

OMUXI

OCTALJ OCTAL1

I

vee

1

,0:

LATCH I

OCTAL2.,~~....

•• ;FJlIIII....~.,.•

~~~~ ~~ ell T C12 II: =-~~ ..

L "'----=- .I~~\.

",. ..11••1; 5·~111g7 J ~ ~ -'a On, " JUMper

.. ".: ~1~lj ~.. ~ PHILIPS PR' EINDHOVEN: • ... RESEARCH EOtT

• ..._ LABORATORIES '"

vee

1

OCTAL I

RIO~lIlN 116~i8N ~O ~l18N 1'0.l.!8l14 1'0.l.!llIlH t£J l.!llI»l_9=T cs _9=T II; _9i.'!T r:r _9=T III _9=T C9 -9=T Cli

-=-L

vee

vee

1

"%jQq'~...(1)

0C11

0~0UJ

"'00

,j:>. to...... -

0~'...S0..(1)

S0l:lCIl...-....'"....0'l:l

Iii

6neetnllMlW'IlI'l..tlotrd.drt:lIina Pert I ....

O.. iQf'lrlr : BiMlenQI h-ojllCt; IiIslonLest Updlt. ; TI... : 2:26:85 Pft o.t. Frideu. Octoblar la. 1991

Philip. (Cll,lat.u· boar4)

~III ~:;;.;:U.~~~~gll~~~IIJI'I {"d ~ .

>"

s:l.9...,CIl.......,~o~

"'0

~~

.'!'t'~op.....:I

~.0c.)Q)....~~

....1.0

"

JS 15­35 1)015 1135 •35 •35 535 ,35 I

35 15"S 13JS 11JS •35 •35 5,. ,35 1

rool

TOO_II

lA'lA'

IJ2 ~t~~,At'A''A''AO,.,.

150 'nIS.89 I

35. Fm=ill35 •35 •35 , 0--=----,

~:U8....

3516~"5 14JS 12 I,,5 10

vee

.10 ~J.10 ll-

v~e

.,. 1 :=::t

I~ HII I I. I II DD I W i I

~u~

t-:l~~

~.U

Appendix D

Test sequence

D.l CMOS PCB

This board is a random access memory demonstration board. The busses are directly accessible byflat cable connectors. These connectors are connected to two external boundary-scan chips [4, 5, 11](DIOSes), in which the test vectors are loaded. The bidirectional ports of these DIOSes are thusconnected to the inputs and outputs of this board.

The test vectors define the addresses on the address bus, the control signals and the data onthe data bus, hence the board can be put in particular operating states. These vectors are sentfrom the computer [10] to the vector blaster (see appendix B, tester 1). The blaster sends thisinformation by means of the boundary-scan protocol to the digital I/O scan module [ll] whichconsists of two boundary-scan chips (DIOSes).

The used application files, in BTSL format, are listed at the end of this appendix section. Thetest vectors have the following layout (position description):

(1) Signal Write Enable (MWE, SRAMs)(2) Signal Output Enable (MOE, SRAMs)(3) Signal Data Bus Enable (MG1I1, OCTALS)(4..7) Signal Chip Select (MCS4..MCS1, SRAMs)(8..22) Signal Address Bus (MA14..MAO, SRAMs)(23..30) Signal Data Bus (MD8..MD1, SRAMs)

The following two examples show the test sequence for a static open detection and for a staticshort detection, respectively. Each test sequence consists of six test vectors. The first three vectorsrepresent a write cycle and the last three vectors represent a read cycle.

Open detection (open in the data bus to/from SRAM1 ):

No. Enable Chip select Address Data1) UUD UUUD DDD DDDD DDDD DDDD UUUU UUUU2) DUD UUUD DDD DDDD DDDD DDDD UUUU UUUU3) UUD UUUD DDD DDDD DDDD DDDD UUUU UUUU4) UUU UUUD DDD DDDD DDDD DDDD HHHH HHHH5) UDU UUUD DDD DDDD DDDD DDDD HHHHHHHH6) UUU UUUD DDD DDDD DDDD DDDD HHHH HHHH

Short detection (short between data line 0 and 1 of SRAM1 ):

43

No. Enable Chip select Address Data1) UUD UUUD DDD DDDD DDDD DDDD UUUU UUUU2) DUD UUUD DDD DDDD DDDD DDDD UUUU UUUD3) UUD UUUD DDD DDDD DDDD DDDD UUUU UUUU4) UUU UUUD DDD DDDD DDDD DDDD HHHH HHHH5) UDU UUUD DDD DDDD DDDD DDDD HHHH HHHL6) UUU UUUD DDD DDDD DDDD DDDD HHHH HHHH

Initial load application file

SYNTAX_VERSION 1.0DESIGN ALABSX2REVISION UNKNOWNTEST inter

CONFIG conf-lFREQ = 10000SERIAL_CHANNEL TAPl

TIMING = 0DIOS_l EXTEST

END_CHANNELEND_CONFIG

ACCESS_DESCRIPTIONCONFIG conf-l

USE AEND_CONFIG

END_DESCRIPTION

ACCESS_TABLEMWE AMOE AMGI1 AMC54 AMCS3 AMCS2 AMCSl AMA14 AMA13 AMA12 AMAll AMAlO AMA9 AMA8 AMA7 AMA6 A

MA5 AMA4 AMA3 AMA2 AMAl A

MAO AMD8 A

(NNNNNNNN NNNNNNNN NNNNNNNN NNHXHXHXHXHXHXHX HXHXNNHX HXNNNNNN NNNNNNNN)

(NNNNNNNN NNHXHXHX HXHXHXHX LXLXLXLXLXLXLXLX HXHXHXHX HXHXHXHX HXHXHXHX)

TAPl DIOS_1 14 W 10;TAPl DIOS_l 16 W 9;TAPl DIOS_l 36 W 60;TAPl DIOS_2 6 W 31;TAP1 DIOS_2 4 W 17;TAP1 DIOS_2 2 W 22;TAP1 DI05_2 0 W 23;TAP1 DI05_2 52 W 15;TAP1 DI05_2 50 W 38;TAP1 DI05_2 48 W 39;TAP1 DIOS_2 46 W 40;TAP1 DI05_2 44 W 41;TAP1 DI05_2 42 W 42;TAP1 DI05_2 40 W 58;TAP1 DI05_1 34 W 61;TAP1 DIOS_1 32 W 62;TAP1 DIOS_1 30 W 63;TAP1 DIOS_l 28 W 53;TAP1 D105_1 26 W 55;TAP1 DI05_1 24 W 56;TAP1 D105_1 22 W 57:TAP1 D105_1 20 W 8;TAP1 DI05_2 22 W 57

44

A TAPl D105_2 38 R 59;MD7 A TAP1 D105_2 20 W 8

A TAP1 D105_2 36 R 60;MD6 A TAP1 D105_2 18 W 9

A TAPl D105_2 34 R 61;MD5 A TAP 1 D105_2 16 W 10

A TAP1 D105_2 32 R 62;MD4 A TAPl D105_2 14 W 11

A TAP1 D10S_2 30 R 63;MD3 A TAPl D105_2 12 W 28

A T~l D10S_2 28 R 53;MD2 A TAP1 D105_2 10 W 29

A TAP1 D10S_2 26 R 55;MDl A T~l D10S_2 8 W 30

A T~1 D105_2 24 R 56;

DATAU5E_CONF1G conf-l

o USE A (UUDDDDDDDDDDDDDDDDDDDUUUUUUUUU)1 USE A (DUDDDDDDDDDDDDDDDDDDDUUUUUUUUU)2 USE A (UUDDDDDDDDDDDDDDDDDDDUUUUUUUUU)3 USE A (UUDDDDDDDDDDDDDDDDDDUDUUUUUUUU)4 USE A (DUDDDDDDDDDDDDDDDDDDUDUUUUUUUU)5 USE A (UUDDDDDDDDDDDDDDDDDDUDUUUUUUUU)6 USE A (UUDDDDDDDDDDDDDDDDDUDDUUUUUUUU)7 USE A (DUDDDDDDDDDDDDDDDDDUDDUUUUUUUU)8 USE A (UUDDDDDDDDDDDDDDDDDUDDUUUUUUUU)9 USE A (UUDDDDDDDDDDDDDDDDUDDDUUUUUUUU)10 USE A (DUDDDDDDDDDDDDDDDDUDDDUUUUUUUU)11 USE A (UUDDDDDDDDDDDDDDDDUDDDUUUUUUUU)12 USE A (UUDDDDDDDDDDDDDDDUDDDDUUUUUUUU)13 USE A (DUDDDDDDDDDDDDDDDUDDDDUUUUUUUU)14 USE A (UUDDDDDDDDDDDDDDDUDDDDUUUUUUUU)15 USE A (UUDDDDDDDDDDDDDDUDDDDDUUUUUUUU)16 USE A (DUDDDDDDDDDDDDDDUDDDDDUUUUUUUU)17 USE A (UUDDDDDDDDDDDDDDUDDDDDUUUUUUUU)18 USE A (UUDDDDDDDDDDDDDUDDDDDDUUUUUUUU)19 USE A (DUDDDDDDDDDDDDDUDDDDDDUUUUUUUU)20 USE A (UUDDDDDDDDDDDDDUDDDDDDUUUUUUUU)21 USE A (UUDDDDDDDDDDDDUDDDDDDDUUUUUUUU)22 USE A (DUDDDDDDDDDDDDUDDDDDDDUUUUUUUU)23 USE A (UUDDDDDDDDDDDDUDDDDDDDUUUUUUUU)24 USE A (UUDDDDDDDDDDDUDDDDDDDDUUUUUUUU)25 USE A (DUDDDDDDDDDDDUDDDDDDDDUUUUUUUU)26 USE A (UUDDDDDDDDDDDUDDDDDDDDUUUUUUUU)27 USE A (UUDDDDDDDDDDUDDDDDDDDDUUUUUUUU)28 USE A (DUDDDDDDDDDDUDDDDDDDDDUUUUUUUU)29 USE A (UUDDDDDDDDDDUDDDDDDDDDUUUUUUUU)30 USE A (UUDDDDDDDDDUDDDDDDDDDDUUUUUUUU)31 USE A (DUDDDDDDDDDUDDDDDDDDDDUUUUUUUU)32 USE A (UUDDDDDDDDDUDDDDDDDDDDUUUUUUUU)33 USE A (UUDDDDDDDDUDDDDDDDDDDDUUUUUUUU)34 USE A (DUDDDDDDDDUDDDDDDDDDDDUUUUUUUU)35 USE A (UUDDDDDDDDUDDDDDDDDDDDUUUUUUUU)36 USE A (UUDDDDDDDUDDDDDDDDDDDDUUUUUUUU)37 USE A (DUDDDDDDDUDDDDDDDDDDDDUUUUUUUU)38 USE A (UUDDDDDDDUDDDDDDDDDDDDUUUUUUUU)

45

39 USE A (UUDDDDDDUDDDDDDDDDDDDDUUUUUUUU)40 USE A (DUDDDDDDUDDDDDDDDDDDDDUUUUUUUU)41 USE A (UUDDDDDDUDDDDDDDDDDDDDUUUUUUUU)42 USE A (UUDDDDDUDDDDDDDDDDDDDDUUUUUUUU)43 USE A (DUDDDDDUDDDDDDDDDDDDDDUUUUUUUU)44 USE A (UUDDDDDUDDDDDDDDDDDDDDUUUUUUUU)45 USE A (UUDDDDDDDDDDDDDDDDDDDDDDDDDDDD)46 USE A (DUDDDDDDDDDDDDDDDDDDDDDDDDDDDD)47 USE A (UUDDDDDDDDDDDDDDDDDDDDDDDDDDDD)48 USE A (UUUDUUUDDDDDDDDDDDDDDUHHHHHHHH)49 USE A (UDUDUUUDDDDDDDDDDDDDDUHHHHHHHH)50 USE A (UUUDUUUDDDDDDDDDDDDDDUHHHHHHHH)51 USE A (UUUUOUUDDDDDDDDDDDDDDUHHHHHHHH)52 USE A (UDUUDUUDDDDDDDDDDDDDDUHHHHHHHH)53 USE A (UUUUDUUDDDDDDDDDDDDDDUHHHHHHHH)54 USE A (UUUUUDUDDDDDDDDDDDDDDUHHHHHHHH)55 USE A (UDUUUDUDDDDDDDDDDDDDDUHHHHHHHH)56 USE A (UUUUUDUDDDDDDDDDDDDDDUHHHHHHHH)57 USE A (UUUUUUODDDDDDDDDDDDDDUHHHHHHHH)58 USE A (UDUUUUDDDDDDDDDDDDDDDUHHHHHHHH)59 USE A (UUUUUUODDDDDDDDDDDDDDUHHHHHHHH)60 USE A (UUUDUUUDDDDDDDDDDDDDUDHHHHHHHH)61 USE A (UDUDUUUDDDDDDDDDDDDDUDHHHHHHHH)62 USE A (UUUDUUUDDDDDDDDDDDDDUDHRHHHHHH)63 USE A (UUUUOUUDDDDDDDDDDDDDUDHHHHHHHH)64 USE A (UDUUDUUDDDDDDDDDDDDDUDHHHHHHHH)65 USE A (UUUUOUUDDDDDDDDDDDDDUDHHHHHHHH)66 USE A (UUUUUDUDDDDDDDDDDDDDUDHHHHHHHH)67 USE A (UDUUUDUDDDDDDDDDDDDDUDHHHHHHHH)68 USE A (UUUUUDUDDDDDDDDDDDDDUDHHHHHHHH)69 USE A (UUUUUUODDDDDDDDDDDDDUDHHHHHHHH)70 USE A (UDUUUUODDDDDDDDDDDDDUDHHHHHHHH)71 USE A (UUUUUUDDDDDDDDDDDDDDUDHHHHHHHH)72 USE A (UUUDUUUDDDDDDDDDDDDUDDHHHHHHHH)73 USE A (UDUDUUUDDDDDDDDDDDDUDDHHHHHHHH)74 USE A (UUUDUUUDDDDDDDDDDDDUDDHHHHHHHH)75 USE A (UUUUOUUDDDDDDDDDDDDUDDHHHHHHHH)76 USE A (UDUUDUUDDDDDDDDDDDDUDDHHHHHHHH)77 USE A (UUUUDUUDDDDDDDDDDDDUDDHHHHHHHH)78 USE A (UUUUUDUDDDDDDDDDDDDUDDHHHHHHHH)79 USE A (UDUUUDUDDDDDDDDDDDDUDDHHHHHHHH)80 USE A (UUUUUDUDDDDDDDDDDDDUDDHHHHHHHH)81 USE A (UUUUUUODDDDDDDDDDDDUDDHHHHHHHH)82 USE A (UDUUUUODDDDDDDDDDDDUDDHHHHHHHH)83 USE A (UUUUUUDDDDDDDDDDDDDUDDHHHHHHHH)84 USE A (UUUDUUUDDDDDDDDDDDUDDDHHHHHHHH)85 USE A (UDUDUUUDDDDDDDDDDDUDDDHHHHHHHH)86 USE A (UUUDUUUDDDDDDDDDDDUDDDHHHHHHHH)87 USE A (UUUUDUUDDDDDDDDDDDUDDDHHHHHHHH)88 USE A (UDUUDUUDDDDDDDDDDDUDDDHHHHHHHH)89 USE A (UUUUOUUDDDDDDDDDDDUDDDHHHHHHHH)90 USE A (UUUUUDUDDDDDDDDDDDUDDDHHHHHHHH)91 USE A (UDUUUDUDDDDDDDDDDDUDDDHHHHHHHH)92 USE A (UUUUUDUDDDDDDDDDDDUDDDHHHHHRHH)93 USE A (UUUUUUODDDDDDDDDDDUDDDHHHHBHHH)94 USE A (UDUUUUDDDDDDDDDDDDUDDDHHHHHHHR)95 USE A (UUUUUUDDDDDDDDDDDDUDDDHHHHHHHH)96 USE A (UUUDUUUDDDDDDDDDDUDDDDHHHHHHHR)

46

97 USE A (UDUDUUUDDDDDDDDDDUDDDDBHHHHHHH)98 USE A (UUUDUUUDDDDDDDDDDUDDDDHHHHHHHH)99 USE A (UUUUOUUDDDDDDDDDDUDDDDHHHHHHHH)100 USE A (UDUUDUUDDDDDDDDDDUDDDDHHHHHHHH)101 USE A (UUUUDUUDDDDDDDDDDUDDDDHHHHHHHH)102 USE A (UUUUUDUDDDDDDDDDDUDDDDHHHHHHHH)103 USE A (UDUUUDUDDDDDDDDDDUDDDDHHHHHHHH)104 USE A (UUUUUDUDDDDDDDDDDUDDDDHHHHHHHH)105 USE A (UUUUUUDDDDDDDDDDDUDDDDHHHHHHHH)106 USE A (UDUUUUDDDDDDDDDDDUDDDDHHHHHHHH)107 USE A (UUUUUUDDDDDDDDDDDUDDDDHHHHHHHH)108 USE A (UUUDUUUDDDDDDDDDUDDDDDHHHHHHHH)109 USE A (UDUDUUUDDDDDDDDDUDDDDDHHHHHHHH)110 USE A (UUUDUUUDDDDDDDDDUDDDDDHHHHHHHH)111 USE A (UUUUOUUDDDDDDDDDUDDDDDHHHHHHHH)112 USE A (UDUUDUUDDDDDDDDDUDDDDDHHHHHHHH)113 USE A (UUUUOUUDDDDDDDDDUDDDDDHHHHHHHH)114 USE A (UUUUUDUDDDDDDDDDUDDDDDHHHHHHHH)115 USE A (UDUUUDUDDDDDDDDDUDDDDDHHHHHHHH)116 USE A (UUUUUOUDDDDDDDDDUDDDDDHHHHHHHH)117 USE A (UUUUUUDDDDDDDDDDUDDDDDHHHHHHHH)118 USE A (UDUUUUDDDDDDDDDDUDDDDDHHHHHHHH)119 USE A (UUUUUUDDDDDDDDDDUDDDDDHHHHHHHH)120 USE A (UUUDUUUDDDDDDDDUDDDDDDHHHHHHHH)121 USE A (UDUDUUUDDDDDDDDUDDDDDDHHHHHHHH)122 USE A (UUUDUUUDDDDDDDDUDDDDDDHHHHHHHH)123 USE A (UUUUOUUDDDDDDDDUDDDDDDHHHHHHHH)124 USE A (UDUUDUUDDDDDDDDUDDDDDDHHHHHHHH)125 USE A (UUUUDUUDDDDDDDDUDDDDDDHHHHHHHH)126 USE A (UUUUUDUDDDDDDDDUDDDDDDHHHHHHHH)127 USE A (UDUUUDUDDDDDDDDUDDDDDDHHHHHHHH)128 USE A (UUUUUOUDDDDDDDDUDDDDDDHHHHHHHH)129 USE A (UUUUUUDDDDDDDDDUDDDDDDHHHHHHHH)130 USE A (UDUUUUDDDDDDDDDUDDDDDDHHHHHHHH)131 USE A (UUUUUUDDDDDDDDDUDDDDDDHHHHHHHH)132 USE A (UUUDUUUDDDDDDDUDDDDDDDHHHHHHHH)133 USE A (UDUDUUUDDDDDDDUDDDDDDDHHHHHHHH)134 USE A (UUUDUUUDDDDDDDUDDDDDDDHHHHHHHH)135 USE A (UUUUOUUDDDDDDDUDDDDDDDHHHHHHHH)136 USE A (UDUUDUUDDDDDDDUDDDDDDDHHHHHHHH)137 USE A (UUUUDUUDDDDDDDUDDDDDDDHHHHHHHH)138 USE A (UUUUUOUDDDDDDDUDDDDDDDHHHHHHHH)139 USE A (UDUUUDUDDDDDDDUDDDDDDDHHHHHHHH)140 USE A (UUUUUDUDDDDDDDUDDDDDDDHHHHHHHH)141 USE A (UUUUUUDDDDDDDDUDDDDDDDHHHHHHHH)142 USE A (UDUUUUODDDDDDDUDDDDDDDHHHHHHHH)143 USE A (UUUUUUDDDDDDDDUDDDDDDDHHHHHHHH)144 USE A (UUUDUUUDDDDDDUDDDDDDDDHHHHHHHH)145 USE A (UDUDUUUDDDDDDUDDDDDDDDHHHHHHHH)146 USE A (UUUDUUUDDDDDDUDDDDDDDDHHHHHHHH)147 USE A (UUUUDUUDDDDDDUDDDDDDDDHHHHHHHH)148 USE A (UDUUDUUDDDDDDUDDDDDDDDHHHHHHHH)149 USE A (UUUUDUUDDDDDDUDDDDDDDDHHHHHHHH)150 USE A (UUUUUOUDDDDDDUDDDDDDDDHHHHHHHH)151 USE A (UDUUUDUDDDDDDUDDDDDDDDHHHHHHHH)152 USE A (UUUUUOUDDDDDDUDDDDDDDDHHHHHHHH)153 USE A (UUUUUUDDDDDDDUDDDDDDDDHHHHHHHH)154 USE A (UDUUUUDDDDDDDUDDDDDDDDHHHHHHHH)

47

155 USE A (UUUUUUDDDDDDDUDDDDDDDDHHHHHHHH)156 USE A (UUUDUUUDDDDDUDDDDDDDDDHHHHHHHH)157 USE A (UDUDUUUDDDDDUDDDDDDDDDHHHHHHHH)158 USE A (UUUDUUUDDDDDUDDDDDDDDDHHHHHHHH)159 USE A (UUUUDUUDDDDDUDDDDDDDDDHHHHHHHH)160 USE A (UDUUDUUDDDDDUDDDDDDDDDHHHHHHHH)161 USE A (UUUUDUUDDDDDUDDDDDDDDDHHHHHHHH)162 USE A (UUUUUDUDDDDDUDDDDDDDDDHHHHHHHH)163 USE A (UDUUUDUDDDDDUDDDDDDDDDHHHHHHHH)164 USE A (UUUUUDUDDDDDUDDDDDDDDDHHHHHHHH)165 USE A (UUUUUUDDDDDDUDDDDDDDDDHHHHHHHH)166 USE A (u~UUUUDDDDDDUDDDDDDDDDHHHHHHHH)

167 USE A (UUUUUUDDDDDDUDDDDDDDDDHHHHHHHH)168 USE A (UUUDUUUDDDDUDDDDDDDDDDHHHHHHHH)169 USE A (UDUDUUUDDDDUDDDDDDDDDDHHHHHHHH)170 USE A (UUUDUUUDDDDUDDDDDDDDDDHHHHHHHH)171 USE A (UUUUDUUDDDDUDDDDDDDDDDHHHHHHHH)172 USE A (UDUUDUUDDDDUDDDDDDDDDDHHHHHHHH)173 USE A (UUUUDUUDDDDUDDDDDDDDDDHHHHHHHH)174 USE A (UUUUUDUDDDDUDDDDDDDDDDHHHHHHHH)175 USE A (UDUUUDUDDDDUDDDDDDDDDDHHHHHHHH)176 USE A (UUUUUDUDDDDUDDDDDDDDDDHHHHHHHH)177 USE A (UUUUUUDDDDDUDDDDDDDDDDHHHHHHHH)178 USE A (UDUUUUDDDDDUDDDDDDDDDDHHHHHHHH)179 USE A (UUUUUUDDDDDUDDDDDDDDDDHHHHHHHH)180 USE A (UUUDUUUDDDUDDDDDDDDDDDHHHHHHHH)181 USE A (UDUDUUUDDDUDDDDDDDDDDDHHHHHHHH)182 USE A (UUUDUUUDDDUDDDDDDDDDDDHHHHHHHH)183 USE A (UUUUDUUDDDUDDDDDDDDDDDHHHHHHHH)184 USE A (UDUUDUUDDDUDDDDDDDDDDDHHHHHHHH)185 USE A (UUUUDUUDDDUDDDDDDDDDDDHHHHHHHH)186 USE A (UUUUUDUDDDUDDDDDDDDDDDHHHHHHHH)187 USE A (UDUUUDUDDDUDDDDDDDDDDDHHHHHHHH)188 USE A (UUUUUDUDDDUDDDDDDDDDDDHHHHHHHH)189 USE A (UUUUUUDDDDUDDDDDDDDDDDHHHHHHHR)190 USE A (UDUUUUDDDDUDDDDDDDDDDDHHHHHHHH)191 USE A (UUUUUUDDDDUDDDDDDDDDDDHHHHHHHH)192 USE A (UUUDUUUDDUDDDDDDDDDDDDHHHHHHHH)193 USE A (UDUDUUUDDUDDDDDDDDDDDDHHHHHHHH)194 USE A (UUUDUUUDDUDDDDDDDDDDDDHHHHHHHH)195 USE A (UUUUDUUDDUDDDDDDDDDDDDHHHHHHHH)196 USE A (UDUUDUUDDUDDDDDDDDDDDDHHHHHHHH)197 USE A (UUUUDUUDDUDDDDDDDDDDDDHHHHHHHH)198 USE A (UUUUUDUDDUDDDDDDDDDDDDHHHHHHHH)199 USE A (UDUUUDUDDUDDDDDDDDDDDDHHHHHHHH)200 USE A (UUUUUDUDDUDDDDDDDDDDDDHHHHHHHH)201 USE A (UUUUUUDDDUDDDDDDDDDDDDHHHHHHHH)202 USE A (UDUUUUDDDUDDDDDDDDDDDDHHHHHHHH)203 USE A (UUUUUUDDDUDDDDDDDDDDDDHHHHHHHH)204 USE A (UUUDUUUDUDDDDDDDDDDDDDHHHHHHHH)205 USE A (UDUDUUUDUDDDDDDDDDDDDDHHHHHHHH)206 USE A (UUUDUUUDUDDDDDDDDDDDDDHHHHHHHH)207 USE A (UUUUDUUDUDDDDDDDDDDDDDHHHHHHHH)208 USE A (UDUUDUUDUDDDDDDDDDDDDDHHHHHHHH)209 USE A (UUUUDUUDUDDDDDDDDDDDDDHHHHHHHH)210 USE A (UUUUUDUDUDDDDDDDDDDDDDHHHHHHHH)211 USE A (UDUUUDUDUDDDDDDDDDDDDDHHHHHHHH)212 USE A (UUUUUDUDUDDDDDDDDDDDDDHHHHHHHH)

48

213 USE A (UUUUUUDDUDDDDDDDDDDDDDHHHHHHHH)214 USE A (UDUUUUDDUDDDDDDDDDDDDDHHHHHHHH)215 USE A (UUUUUUDDUDDDDDDDDDDDDDHHHHHHHH)216 USE A (UUUDUUUUDDDDDDDDDDDDDDHHHHHHHH)217 USE A (UDUDUUUUDDDDDDDDDDDDDDHHHHHHHH)218 USE A (UUUDUUUUDDDDDDDDDDDDDDHHHHHHHH)219 USE A (UUUUDUUUDDDDDDDOODDDDDHHHHHHHH)220 USE A (UDUUDUUUDDDODDDODDDODDHHHHHHHH)221 USE A (UUUUDUUUDDDDDDDODDDDDDHHHHHHHH)222 USE A (UUUUUDUUDDDDDDDDDDDODDHHHHHHHH)223 USE A (UDUUUDUUDDDDDDOODODODDHHHHHHHH)224 USE A (UUUUUDUUDOODDDDDODDODDBHHHHHHH)225 USE A (UUUUUUDUDDDDDDDDDDDDDDHHHHHHHH)226 USE A (UDUUUUDUDDDDODDDDDDDDDHHHHHHHH)227 USE A (UUUUUUDUDDDDDDDDDDDDDDHHHHHHHH)228 USE A (UUDDDDDUUUUUUUUUUUUUUDDDDDDDDD)229 USE A (DUDDDDDUUUUUUUUUUUUUUDDDDDDDDD)230 USE A (UUDDDDDUUUUUUUUUUUUUUDDDDDDDDD)231 USE A (UUDDODDUUUUUUUUUUUUUDUDDDDDDDD)232 USE A (DUDDDDDUUUUUUUUUUUUUDUDDDDDDDD)233 USE A (UUDDDDDUUUUUUUUUUUUUUUDDDDDDDD)234 USE A (UUDDDDDUUUUUUUUUUUUDUUDDDDDDDD)235 USE A (DUDDDDDUUUUUUUUUUUUDUUDDDDDDDD)236 USE A (UUDDODDUUUUUUUUUUUUDUUDDDDDDDD)237 USE A (UUDDODDUUUUUUUUUUUOUUUDDODDDDD)238 USE A (DUDDODDUUUUUUUUUUUDUUUDDDDDDDD)239 USE A (UUDDDDDUUUUUUUUUUUDUUUDDDDDDDD)240 USE A (UUDDDDDUUUUUUUUUUDUUUUDDDDDDDD)241 USE A (OUDDDDDUUUUUUUUUUDUUUUDDDDDDDD)242 USE A (UUDDDDDUUUUUUUUUUDUUUUDDDDDDDD)243 USE A (UUDDOOOUUUUUUUUUOUUUUUDDDDDDOD)244 USE A (DUDODODUUUUUUUUUOUUUUUDDODODDD)245 USE A (UUDDODDUUUUUUUUUOUUUUUDDODDDDD)246 USE A (UUDDDDDUUUUUUUUOUUUUUUDDODDDDD)247 USE A (DUDDDDDUUUUUUUUDUUUUUUDDODDDDD)248 USE A (UUODDODUUUUUUUUOUUUUUUDDODDDDD)249 USE A (UUDDDODUUUUUUUDUUUUUUUDDODDDDD)250 USE A (DUDDDDDUUUUUUUDUUUUUUUDDODDDOD)251 USE A (UUDDDODUUUUUUUDUUUUUUUDDODDDOD)252 USE A (UUODDDDUUUUUUDUUUUUUUUDDODDDDD)253 USE A (DUDDDDDUUUUUUDUUUUUUUUDDDDDDDD)254 USE A (UUDDDODUUUUUUDUUUUUUUUDDDODDDD)255 USE A (UUDDDODUUUUUDUUUUUUUUUDDDDDDDD)256 USE A (DUDDDODUUUUUOUUUUUUUUUDDDDDDDD)257 USE A (UUDDDDDUUUUUDUUUUUUUUUDDDDDDDD)258 USE A (UUDDDODUUUUDUUUUUUUUUUDDDODDDD)259 USE A (DUDDDODUUUUDUUUUUUUUUUDDDDDDDD)260 USE A (UUDDDDDUUUUDUUUUUUUUUUDDDDDDDD)261 USE A (UUDDDDDUUUDUUUUUUUUUUUDDDDDDDD)262 USE A (DUDDDDDUUUDUUUUUUUUUUUDDDDDDDD)263 USE A (UUDDDDDUUUDUUUUUUUUUUUDDDODDDD)264 USE A (UUDDDODUUDUUUUUUUUUUUUDDDDDDDD)265 USE A (DUDDDODUUDUUUUUUUUUUUUDDDDDDDD)266 USE A (UUDDDDDUUDUUUUUUUUUUUUDDDDDDDD)267 USE A (UUDDDODUDUUUUUUUUUUUUUDDOODDDO)268 USE A (DUDDDDDUDUUUUUUUUUUUUUODDDDDDD)269 USE A (UUDDDDDUDUUUUUUUUUUUUUODDDDDDD)270 USE A (UUDDDDDDUUUUUUUUUUUUUUDDDDDDDD)

49

271 USE A (DUDDDDDDUUUUUUUUUUUUUUDDDDDDDD)272 USE A (UUDDDDDDUUUUUUUUUUUUUUDDDDDDDD)273 USE A (UUDDDDDUUUUUUUUUUUUUUU)274 USE A (DUDDDDDUUUUUUUUUUUUUUU)275 USE A (UUDDDDDUUUUUUUUUUUUUUU)276 USE A (UUUDUUUUUUUUUUUUUUUHHHHHHHH)277 USE A (UDUDUUUUUUUUUUUUUUULLLLLLLL)278 USE A (UUUDUUUUUUUUUUUUUUUHHHHHHHH)279 USE A (UUUUDUUUUUUUUUUUUUUUHHHHHHHH)

280 USE A (UDUUDUUUUUUUUUUUUUUULLLLLLLL)281 USE A (UUUUDUUUUUUUUUUUUUUUHHHHHHHH)282 USE A (lJUUUUDUUUUUUUUUUUUUUUHHHHHHHH)

283 USE A (UDUUUDUUUUUUUUUUUUUUULLLLLLLL)284 USE A (UUUUUDUUUUUUUUUUUUUUUHHHHHHHH)

285 USE A (UUUUUUDUUUUUUUUUUUUUUDHHHHHHHH)286 USE A (UDUUUUDUUUUUUUUUUUUUUDLLLLLLLL)287 USE A (UUUUUUDUUUUUUUUUUUUUUDHHHHHHHH)288 USE A (UUUDUUUUUUUUUUUUUUUUHHHHHHHH)289 USE A (UDUDUUUUUUUUUUUUUUUULLLLLLLL)290 USE A (UUUDUUUUUUUUUUUUUUUUHHHHHHHH)291 USE A (UUUUDUUUUUUUUUUUUUUUDUHHHHHHHH)292 USE A (UDUUDUUUUUUUUUUUUUUUULLLLLLLL)293 USE A (UUUUDUUUUUUUUUUUUUUUUHHHHHHHH)294 USE A (UUUUUDUUUUUUUUUUUUUUDUHHHHHHHH)295 USE A (UDUUUDUUUUUUUUUUUUUUDULLLLLLLL)296 USE A (UUUUUDUUUUUUUUUUUUUUDUHHHHHHHH)297 USE A (UUUUUUDUUUUUUUUUUUUUDUHHHHHHHH)

298 USE A (UDUUUUDUUUUUUUUUUUUUDULLLLLLLL)299 USE A (UUUUUUDUUUUUUUUUUUUUDUHHHHHHHH)300 USE A (UUUDUUUUUUUUUUUUUUUUUHHHHHHHH)301 USE A (UDUDUUUUUUUUUUUUUUUUULLLLLLLL)302 USE A (UUUDUUUUUUUUUUUUUUUUUHHHHHHHH)303 USE A (UUUUDUUUUUUUUUUUUUUDUUHHHHHHHH)

304 USE A (UDUUDUUUUUUUUUUUUUUDUULLLLLLLL)305 USE A (UUUUDUUUUUUUUUUUUUUDUUHHHHHHHH)306 USE A (UUUUUDUUUUUUUUUUUUUDUUHHHHHHHH)307 USE A (UDUUUDUUUUUUUUUUUUUDUULLLLLLLL)308 USE A (UUUUUDUUUUUUUUUUUUUDUUHHHHHHHH)

309 USE A (UUUUUUDUUUUUUUUUUUUDUUHHHHHHHH)310 USE A (UDUUUUDUUUUUUUUUUUUDUULLLLLLLL)311 USE A (UUUUUUDUUUUUUUUUUUUDUUHHHHHHHH)312 USE A (UUUDUUUUUUUUUUUUUUDUUUHHHHHHHH)313 USE A (UDUDUUUUUUUUUUUUUUUUUULLLLLLLL)314 USE A (UUUDUUUUUUUUUUUUUUDUUUHHHHHHHH)315 USE A (UUUUOUUUUUUUUUUUUUDUUUHHHHHHHH)

316 USE A (UDUUDUUUUUUUUUUUUUDUUULLLLLLLL)317 USE A (UUUUDUUUUUUUUUUUUUDUUUHHHHHHHH)318 USE A (UUUUUDUUUUUUUUUUUUDUUUHHHHHHHH)319 USE A (UDUUUDUUUUUUUUUUUUDUUULLLLLLLL)320 USE A (UUUUUDUUUUUUUUUUUUDUUUHHHHHHHH)

321 USE A (UUUUUUDUUUUUUUUUUUDUUUHHHHHHHH)322 USE A (UDUUUUDUUUUUUUUUUUDUUULLLLLLLL)323 USE A (UUUUUUDUUUUUUUUUUUDUUUHHHHHHHH)324 USE A (UUUDUUUUUUUUUUUUUDUUUUHHHHHHHH)325 USE A (UDUDUUUUUUUUUUUUUDUUUULLLLLLLL)326 USE A (UUUDUUUUUUUUUUUUUDUUUUHHHHHHHH)327 USE A (UUUUDUUUUUUUUUUUUDUUUUHHHHHHHH)328 USE A (UDUUDUUUUUUUUUUUUDUUUULLLLLLLL)

50

329 USE A (UUUUDUUUUUUUUUUUUDUUUUHHHHHHHH)330 USE A (UUUUUDUUUUUUUUUUUDUUUUHHHHHHHH)331 USE A (UDUUUDUUUUUUUUUUUDUUUULLLLLLLL)332 USE A (UUUUUDUUUUUUUUUUUDUUUUHHHHHHHH)333 USE A (UUUUUUDUUUUUUUUUUDUUUUHHHHHHHH)334 USE A (UDUUUUDUUUUUUUUUUDUUUULLLLLLLL)335 USE A (UUUUUUDUUUUUUUUUUDUUUUHHHHHHHH)336 USE A (UUUDUUUUUUUUUUUUDUUUUUHHHHHHHH)337 USE A (UDUDUUUUUUUUUUUUDUUUUULLLLLLLL)338 USE A (UUUDUUUUUUUUUUUUDUUUUUHHHHHHHH)339 USE A (UUUUDUUUUUUUUUUUDUUUUUHHHHHHHH)340 USE A (UDUUDUUUUUUUUUUUDUUUUULLLLLLLL)341 USE A (UUUUDUUUUUUUUUUUDUUUUUHHHHHHHH)342 USE A (UUUUUDUUUUUUUUUUDUUUUUHHHHHHHH)

343 USE A (UDUUUDUUUUUUUUUUDUUUUULLLLLLLL)344 USE A (UUUUUDUUUUUUUUUUDUUUUUHHHHHHHH)345 USE A (UUUUUUDUUUUUUUUUDUUUUUHHHHHHHH)346 USE A (UDUUUUDUUUUUUUUUDUUUUULLLLLLLL)347 USE A (UUUUUUDUUUUUUUUUDUUUUUHHHHHHHH)348 USE A (UUUDUUUUUUUUUUUDUUUUUUHHHHHHHH)349 USE A (UDUDUUUUUUUUUUUDUUUUUULLLLLLLL)350 USE A (UUUDUUUUUUUUUUUDUUUUUUHHHHHHHH)351 USE A (UUUUDUUUUUUUUUUDUUUUUUHHHHHHHH)

352 USE A (UDUUDUUUUUUUUUUDUUUUUULLLLLLLL)353 USE A (UUUUDUUUUUUUUUUDUUUUUUHHHHHHHH)354 USE A (UUUUUDUUUUUUUUUDUUUUUUHHHHHHHH)355 USE A (UDUUUDUUUUUUUUUDUUUUUULLLLLLLL)356 USE A (UUUUUDUUUUUUUUUDUUUUUUHHHHHHHH)357 USE A (UUUUUUDUUUUUUUUDUUUUUUHHHHHHHH)358 USE A (UDUUUUDUUUUUUUUDUUUUUULLLLLLLL)359 USE A (UUUUUUDUUUUUUUUDUUUUUUHHHHHHHH)360 USE A (UUUDUUUUUUUUUUDUUUUtiUUHHHHHHH)361 USE A (UDUDUUUUUUUUUUDUUUUUUULLLLLLLL)362 USE A (UUUDUUUUUUUUUUDUUUUUUUHHHHHHHH)363 USE A (UUUUDUUUUUUUUUDUUUUUUUHHHHHHHH)364 USE A (UDUUDUUUUUUUUUDUUUUUUULLLLLLLL)365 USE A (UUUUDUUUUUUUUUDUUUUUUUHHHHHHHH)366 USE A (UUUUUDUUUUUUUUDUUUUUUUHHHHHHHH)367 USE A (UDUUUDUUUUUUUUDUUUUUUULLLLLLLL)368 USE A (UUUUUDUUUUUUUUDUUUUUUUHHHHHHHH)369 USE A (UUUUUUDUUUUUUUDUUUUUUUHHHHHHHH)370 USE A (UDUUUUDUUUUUUUDUUUUUUULLLLLLLL)371 USE A (UUUUUUDUUUUUUUDUUUUUUUHHHHHHHH)372 USE A (UUUDUUUUUUUUUDUUUUUUUUHHHHHHHH)373 USE A ,(UDUDUUUUUUUUUDUUUUUUUULLLLLLLL)374 USE A (UUUDUUUUUUUUUDUUUUUUUUHHHHHHHH)375 USE A (UUUUDUUUUUUUUDUUUUUUUUHHHHHHHH)376 USE A (UDUUDUUUUUUUUDUUUUUUUULLLLLLLL)377 USE A (UUUUDUUUUUUUUDUUUUUUUUHHHHHHHH)378 USE A (UUUUUDUUUUUUUDUUUUUUUUHHHHHHHH)379 USE A (UDUUUDUUUUUUUDUUUUUUUULLLLLLLL)380 USE A (UUUUUDUUUUUUUDUUUUUUUUHHHHHHHH)381 USE A (UUUUUUDUUUUUUDUUUUUUUUHHHHHHHH)382 USE A (UDUUUUDUUUUUUDUUUUUUUULLLLLLLL)383 USE A (UUUUUUDUUUUUUDUUUUUUUUHHHHHHHH)384 USE A (UUUDUUUUUUUUDUUUUUUUUUHHHHHHHH)385 USE A (UDUDUUUUUUUUDUUUUUUUUULLLLLLLL)386 USE A (UUUDUUUUUUUUDUUUUUUUUUHHHHHHHH)

51

387 USE A (UUUUDUUUUUUUDUUUUUUUUUHHHHHHHH)388 USE A (UOUUDUUUUUUUDUUUUUUUUULLLLLLLL)389 USE A (UUUUDUUUUUUUDUUUUUUUUUHHHHHH)390 USE A (UUUUUOUUUUUUDUUUUUUUUUHHHHHHHH)391 USE A (UOUUUDUUUUUUDUUUUUUUUULLLLLLLL)392 USE A (UUUUUOUUUUUUDUUUUUUUUUHHHHHHHH)393 USE A (UUUUUUDUUUUUDUUUUUUUWHHHHHHHH)394 USE A (UOUUUUDUUUUUDUUUUUUUUULLLLLLLL)395 USE A (UUUUUUDUUUUUDUUUUUUUUUHHHHHHHH)396 USE A (UUUOUUUUUUUDUUUUUUUUUUHHHHHHHH)397 USE A (UOUOUUUUUUUDUUUUUUUUUULLLLLLLL)398 USE A (UUUDUUUUUUUDUUUUUUUUUUHHHHH)399 USE A (UUUUDUUUUUUDUUUUUUUUUUHHHHHHHH)400 USE A (UOUUDUUUUUUDUUUUUUUUUULLLLLLLL)401 USE A (UUUUDUUUUUUDUUUUUUUUUUHHHHHHH)402 USE A (UUUUUOUUUUUOUUUUUUUUUUHHHHHHHH)403 USE A (UOUUUDUUUUUOUUUUUUUUUULLLLLLLL)404 USE A (UUUUUOUUUUUOUUUUUUUUUUHHHHHHHH)405 USE A (UUUUUUDUUUUDUUUUUUUUUUHHHHHHHH)406 USE A (UOUUUUDUUUUDUUUUUUUUUULLLLLLLL)407 USE A (UUUUUUDUUUUDUUUUUUUUUUHHHHHHHH)408 USE A (UUUDUUUUUUDUUUUUUUUUUUHHHHHHHH)409 USE A (UOUOUUUUUUDUUUUUUUUUUULLLLLLLL)410 USE A (UUUDUUUUUUDUUUUUUUUUUUHHHHHHHH)411 USE A (UUUUDUUUUUDUUUUUUUUUUUHHHHHH)412 USE A (UOUUDUUUUUDUUUUUUUUUUULLLLLLLL)413 USE A (UUUUDUUUUUOUUUUUUUUUUUHHHHHHHH)414 USE A (UUUUUOUUUUDUUUUUUUUUUUHHHHHHHH)415 USE A (UOUUUDUUUUDUUUUUUUUUUULLLLLLLL)416 USE A (UUUUUOUUUUDUUUUUUUUUUUHHHH)417 USE A (UUUUUUDUUUDUUUUUUUUUUUHHHHHHHH)418 USE A (UOUUUUDUUUDUUUUUUUUUUULLLLLLLL)419 USE A (UUUUUUDUUUDUUUUUUUUUUUHHHHHHHH)420 USE A (UUUDUUUUUOUUUUUUUUUUUUHHHHHHH)421 USE A (UOUOUUUUUOUUUUUUUUUUUULLLLLLLL)422 USE A (UUUDUUUUUOUUUUUUUUUUUUHHHHHHH)423 USE A (UUUUDUUUUDUUUUUUUUUUUUHHH)424 USE A (UOUUDUUUUDUUUUUUUUUUUULLLLLLLL)425 USE A (UUUUDUUUUDUUUUUUUUUUUUHHHHHHH)426 USE A (UUUUUOUUUDUUUUUUUUUUUUHHHHHHHH)427 USE A (UOUUUDUUUDUUUUUUUUUUUULLLLLLLL)428 USE A (UUUUUOUUUDUUUUUUUUUUUUHHHHHHHH)429 USE A (UUUUUUDUUDUUUUUUUUUUUUHHH)430 USE A (UOUUUUDUUDUUUUUUUUUUUULLLLLLLL)431 USE A (UUUUUUDUUDUUUUUUUUUUuumnnnmmI)432 USE A (UUUDUUUUDUUUUUUUUUUUUUHHHHHHHH)433 USE A (UOUOUUUUDUUUUUUUUUUUUULLLLLLLL)434 USE A (UUUDUUUUDUUUUUUUUUUUUUHHHHHHHH)435 USE A (UUUUDUUUDUUUUUUUUUUUUUHHHHHHHH)436 USE A (UOUUDUUUDUUUUUUUUUUUUULLLLLLLL)437 USE A (UUUUDUUUDUUUUUUUUUUUUUHHHHHHHH)438 USE A (UUUUUOUUDUUUUUUUUUUUUUHHHHHHHH)439 USE A (UOUUUDUUDUUUUUUUUUUUUULLLLLLLL)440 USE A (UUUUUOUUDUUUUUUUUUUUUUHHHHHHHH)441 USE A (UUUUUUDUDUUUUUUUUUUUUUHHHH)442 USE A (UOUUUUDUDUUUUUUUUUUUUULLLLLLLL)443 USE A (UUUUUUDUOUUUUUUUUUUUUUHHHHHHHH)444 USE A (UUUOUUUDUUUUUUUUUUUUUUHHH)

52

445 USE A (UDUDUUUDUUUUUUUUUUUUUULLLLLLLL)446 USE A (UUUDUUUDUUUUUUUUUUUUUUHHHHH)447 USE A (UUUUDUUDUUUUUUUUUUUUUUHHHHHHH)448 USE A (UDUUOUUDUUUUUUUUUUUUUULLLLLLLL)449 USE A (UUUUDUUDUUUUUUUUUUUUUUHHHHH)450 USE A (UUUUUDUDUUUUUUUUUUUUUUHHHHHHH)451 USE A (UDUUUDUDUUUUUUUUUUUUUULLLLLLLL)452 USE A (UUUUUDUDUUUUUUUUUUUUUUH)453 USE A (UUUUUUDOUUUUUUUUUUUUUUHHHHHHH)454 USE A (UOUUUUOOUUUUUUUUUUUUUULLLLLLLL)455 USE A (UUUUUUOOUUUUUUUUUUUUUUHHHHH)456 USE A (UUOOOOOOOOOOOOOOOOOOOOOOOOOOUU)457 USE A (OUOOOOOOOOOOOOOOOOOOOOOOOOOOUU)458 USE A (UUOOOOOOOOOOOOODOOOODOOOOOOOUU)459 USE A (UUUDUUUDODDOOOODOODDDOHHHHHHHH)460 USE A (UDUDUUUDOOOOODODDODODDLLLLLLHH)461 USE A (UUUDUUUDDOOOOODDOOOODOHHHHHHHH)462 USE A (UUUUDUUDOOODODDODDDDDDHHHHHHHH)463 USE A (UDUUOUUODOODDDODOOODDOLLLLLLHH)464 USE A (UUUUDUUDDDDDDDDDDDDOODHHHHHHHH)465 USE A (UUUUUDUDOOOODOODOODDDDHHHHHHHH)466 USE A (UDUUUDUODDDDODDDDDDDDDLLLLLLHH)467 USE A (UUUUUDUDDDDDDDDDDDDDDDHHHHHHHH)468 USE A (UUUUUUDDDDDDDDDDDODDDDHHHHHHHH)469 USE A (UDUUUUDOODODOODODDDODDLLLLLLHH)470 USE A (UUUUUUDDDDDDDDDDDODDDDHHHHHHHH)471 USE A (UUOOOODOODODOOOODOOOODDDOUUUOD)472 USE A (OUDDODDODDODOODDDDODDDDDOUUUDD)473 USE A (UUDDODDDDDDDDDDODDDDDDODDUUUOD)474 USE A (UUUDUUUDDDDDDDDDDDDDODHHHHHHHH)475 USE A (UDUDUUUDOOODDOODOOOODDLLLHHHLL)476 USE A (UUUDUUUDOODDODDDDOODDDHHHHHHHH)477 USE A (UUUUDUUDDOODDODODOOOODHHHHHHHH)478 USE A (UDUUDUUODOODDDDDODODDOLLLHHHLL)479 USE A (UUUUOUUDDDDDOODDDDDODDHHHHHHHH)480 USE A (UUUUUOUDDDDDDDDDDOODDDHHHHHHHH)481 USE A (UDUUUDUDOODDDODODDDDDOLLLHHHLL)482 USE A (UUUUUOUDDOODODOOODODDDHHHHHHHH)483 USE A (UUUUUUDOODDDOODODDOOODHHHHHHHH)484 USE A (UOUUUUOOODODOODOOOODDOLLLHHHLL)485 USE A (UUUUUUDDDDDDDDDODOODDDHHHHHHHH)486 USE A (UUDOOOOODODDOOOODDDODDDUUODUOO)487 USE A (DUDDOOODDOOODDDDOOOODOOUUDOUOO)488 USE A (UUDDODODODOOODOOODOOODOUUOOUDO)489 USE A (UUUDUUUDDODDODDOODDDDDHHHHHHHH)490 USE A (UDUOUUUDOOOOOOODOOOOODLHHLLHLL)491 USE A (UUUDUUUDDDOODODDODOOODHHHHHHHH)492 USE A (UUUUDUUODOODOOOOOODOODHHHHHHHH)493 USE A (UDUUDUUDDDDDDDDDDDDDDDLHHLLHLL)494 USE A (UUUUOUUDODODOOOODOOOODHHHHHHHH)495 USE A (UUUUUOUDDDDODDOODDDOODHHHHHHHH)496 USE A (UDUUUDUOOODODOOOODOOOOLHHLLHLL)497 USE A (UUUUUOUOOOOODODODDDODDHHHHHHHH)498 USE A (UUUUUUDDDDOODODDODDOODHHHHHHHH)499 USE A (UDUUUUODDOOODDOOODODOOLHHLLHLL)500 USE A (UUUUUUODOOOOOOOOODOOOOHHHHHHHH)501 USE A (UUDOOOODOOOODOOODDODDOUDUDUODU)502 USE A (DUDDDDOODDDOOOODODODODUOUOUOOU)

53

503 USE A (UUDDDDDDDDDDDDDDDDDDDDUDUDUDDU)504 USE A (UUUOUUUODDDDDDDDDDDDDDHHHHHHHH)505 USE A (UDUDUUUODDDDDDDDDDDDDDHLHLHLLH)506 USE A (UUUOUUUODDDDDDDDDDDDDDHHHHHHHH)507 USE A (UUUUDUUDDDDDDDDDDDDDDDHHHHHHHH)508 USE A (UDUUDUUDDDDDDDDDDDDDDDHLHLHLLH)509 USE A (UUUUDUUDDDDDDDDDDDDDDDHHHHHHHH)510 USE A (UUUUUDUDDDDDDDDDDDDDDDHHHHHHHH)511 USE A (UDUUUOUDDDDDDDDDDDDDDDHLHLHLLH)512 USE A (UUUUUOUDDDDDDDDDDDDDDDHHHHHHHH)513 USE A (UUUUUUDDDDDDDDDDDDDDDDHHHHHHHH)514 USE A (UDUUUUDDDDDDDDDDDDDDDDHLHLHLLH)515 USE A (UUUUUUDDDDDDDDDDDDDDDDHHHHHHHH)516 USE A (UUDDDDDDDDDDDDDDDDDDDDUUDUDDUD)517 USE A (DUDDDDDDDDDDDDDDDDDDDDUUDUDDUD)518 USE A (UUDDDDDDDDDDDDDDDDDDDDUUDUDDUD)519 USE A (UUUOUUUODDDDDDDDDDDDDDHHHHHHHH)520 USE A (UDUDUUUDDDDDDDDDDDDDDDHHLHLLHL)521 USE A (UUUOUUUDDDDDDDDDDDDDDDHHHHHHHH)522 USE A (UUUUDUUDDDDDDDDDDDDDDDHHHHHHHH)523 USE A (UDUUDUUDDDDDDDDDDDDDDDHHLHLLHL)524 USE A (UUUUDUUDDDDDDDDDDDDDDDHHHHHHHH)525 USE A (UUUUUOUDDDDDDDDDDDDDDDHHHHHHHH)526 USE A (UDUUUDUDDDDDDDDDDDDDDDHHLHLLHL)527 USE A (UUUUUDUDDDDDDDDDDDDDDDHHHHHHHH)528 USE A (UUUUUUDDDDDDDDDDDDDDDDHHHHHHHH)529 USE A (UDUUUUDDDDDDDDDDDDDDDDHHLHLLHL)530 USE A (UUUUUUDDDDDDDDDDDDDDDDHHHHHHHH)531 USE A (UUDDUUUODDDDDDDDDDDDDDUUUUUUUU)532 USE A (DUDDUUUODDDDDDDDDDDDDDUUUUUUUU)533 USE A (UUDDUUUODDDDDDDDDDDDDDUUUUUUUU)534 USE A (UUDUDUUDDDDDDDDDDDDDDDDDDDDDDD)535 USE A (DUDUDUUDDDDDDDDDDDDDDDDDDDDDDD)536 USE A (UUDUDUUDDDDDDDDDDDDDDDDDDDDDDD)537 USE A (UUUDUUUDDDDDDDDDDDDDDDHHHHHHHH)538 USE A (UDUDUUUDDDDDDDDDDDDDDDHHHHHHHH)539 USE A (UUUDUUUDDDDDDDDDDDDDDDHHHHHHHH)540 USE A (UUDDUUUDDDDDDDDDDDDDDDUUUUUUUU)541 USE A (DUDDUUUDDDDDDDDDDDDDDDUUUUUUUU)542 USE A (UUDDUUUDDDDDDDDDDDDDDDUUUUUUUU)543 USE A (UUDUUDUDDDDDDDDDDDDDDDDDDDDDDD)544 USE A (DUDUUDUDDDDDDDDDDDDDDDDDDDDDDD)545 USE A (UUDUUDUDDDDDDDDDDDDDDDDDDDDDDD)546 USE A (UUUDUUUDDDDDDDDDDDDDDDHHHHHHHH)547 USE A (UDUDUUUDDDDDDDDDDDDDDDHHHHHHHH)548 USE A (UUUDUUUDDDDDDDDDDDDDDDHHHHHHHH)549 USE A (UUDDUUUDDDDDDDDDDDDDDDUUUUUUUU)550 USE A (DUDDUUUDDDDDDDDDDDDDDDUUUUUUUU)551 USE A (UUODUUUDDDDDDDDDDDDDDDUUUUUUUU)552 USE A (UUDUUUDDDDDDDDDDDDDDDDDDDDDDDD)553 USE A (DUDUUUDDDDDDDDDDDDDDDDDDDDDDDD)554 USE A (UUDUUUDDDDDDDDDDDDDDDDDDDDDDDD)555 USE A (UUUDUUUDDDDDDDDDDDDDDDHHHHHHHH)556 USE A (UDUDUUUDDDDDDDDDDDDDDDHHHHHHHH)557 USE A (UUUDUUUDDDDDDDDDDDDDDDHHHHHHHH)558 USE A (UUDUDUUDDDDDDDDDDDDDDDUUUUUUUU)559 USE A (DUDUDUUDDDDDDDDDDDDDDDUUUUUUUU)560 USE A (UUDUDUUDDDDDDDDDDDDDDDUUUUUUUU)

54

561 USE A (UUDUUDUDDDDDDDDDDDDDDDDDDDDDDD)562 USE A (DUDUUDUDDDDDDDDDDDDDDDDDDDDDDD)563 USE A (UUDUUDUDDDDDDDDDDDDDDDDDDDDDDD)564 USE A (UUUUDUUDDDDDDDDDDDDDDDHHHHHHHH)565 USE A (UDUUDUUDDDDDDDDDDDDDDDHHHHHHHH)566 USE A (UUUUDUUDDDDDDDDDDDDDDDHHHHHHHH)567 USE A (UUDUDUUDDDDDDDDDDDDDDDUUUUUUUU)568 USE A (DUDUDUUDDDDDDDDDDDDDDDUUUUUUUU)569 USE A (UUDUDUUDDDDDDDDDDDDDDDUUUUUUUU)570 USE A (UUDUUUDDDDDDDDDDDDDDDDDDDDDDDD)571 USE A (DUDUUUDDDDDDDDDDDDDDDDDDDDDDDD)572 USE A (UUDUUUDDDDDDDDDDDDDDDDDDDDDDDD)573 USE A (UUUUDUUDDDDDDDDDDDDDDDHHHHHHHH)574 USE A (UDUUDUUDDDDDDDDDDDDDDDHHHHHHHH)575 USE A (UUUUDUUDDDDDDDDDDDDDDDHHHHHHHH)576 USE A (UUDUUDUDDDDDDDDDDDDDDDUUUUUUUU)577 USE A (DUDUUDUDDDDDDDDDDDDDDDUUUUUUUU)578 USE A (UUDUUDUDDDDDDDDDDDDDDDUUUUUUUU)579 USE A (UUDUUUDDDDDDDDDDDDDDDDDDDDDDDD)580 USE A (DUDUUUDDDDDDDDDDDDDDDDDDDDDDDD)581 USE A (UUDUUUDDDDDDDDDDDDDDDDDDDDDDDD)582 USE A (UUUUUDUDDDDDDDDDDDDDDDHHHHHHHH)583 USE A (UDUUUDUDDDDDDDDDDDDDDDHHHHHHHH)584 USE A (UUUUUDUDDDDDDDDDDDDDDDHHHHHHHH)584 USE A (UUUUUUUDDDDDDDDDDDDDDDHHHHHHHH)

END_CONFIGEND_DATA

One of the defect detection application files

SYNTAX_VERSION 1.0DESIGN ALABSX2REVISION UNKNOWNTEST inter

CONFIG conf-lFREQ = 10000SERIAL_CHANNEL TAPl

TIMING = 0DIOS_1 EXTEST

END_CHANNELEND_CONFIG

ACCESS_DESCRIPTIONCONFIG conf-l

USE AEND_CONFIG

END_DESCRIPTION

ACCESS_TABLEMWE AMOE AMGll AMCS4 AMCS3 A

(NNNNNNNN NNNNNNNN NNNNNNNN NNHXHXHXHXHXHXHX HXHXNNHX HXNNNNNN NNNNNNNN)

(NNNNNNNN NNHXHXHX HXHXHXHX LXLXLXLXLXLXLXLX HXHXHXHX HXHXHXHX HXHXHXHX)

TAP1 DIOS_l 14 W 10;TAP1 DIOS_l 16 W 9;TAPl DIOS_l 36 W 60;TAP1 DIOS_2 6 W 31;TAP1 DIOS_2 4 W 17;

55

MC52 A TAP 1 0105_2 2 W 22;MC51 A TAP1 0105_2 0 W 23;MAl4 A TAP 1 0105_2 52 W 15;MA13 A TAP1 0105_2 50 W 38;MAl 2 A TAP 1 D105_2 48 W 39;MAl1 A TAP1 0105_2 46 W 40;MAlO A TAPl 0105_2 44 W 41;MA9 A TAP1 0105_2 42 W 42;MA8 A TAP1 0105_2 40 W 58;MA7 A TAP1 0105_1 34 W 61;MA6 A TAP1 0105_1 32 W 62;MA5 A TAP1 0105_1 30 W 63;MA4 A TAP1 0105_1 28 W 53;MA3 A TAP1 0105_1 26 W 55;MA2 A TAPl 0105_1 24 W 56;MAl A TAPl 0105_1 22 W 57;MAO A TAP 1 0105_1 20 W 8;MD8 A TAP 1 0105_2 22 W 57

A TAPl D105_2 38 R 59;M07 A TAP1 0105_2 20 W 8

A TAP1 0105_2 36 R 60;M06 A TAP 1 0105_2 18 W 9

A TAP1 0105_2 34 R 61;M05 A TAP1 0105_2 16 W 10

A TAP1 0105_2 32 R 62;M04 A TAP1 0105_2 14 W 11

A TAPl 0105_2 30 R 63;M03 A TAP 1 0105_2 12 W 28

A TAP1 0105_2 28 R 53;M02 A TAP 1 0105_2 10 W 29

A TAPl 0105_2 26 R 55;MOl A TAP1 0105_2 8 W 30

A TAPl D105_2 24 R 56;

* A TAPl 0105_2 39 WA TAP 1 D105_2 37 WA TAP1 D105_2 35 WA TAP 1 D105_2 33 WA TAP1 D105_2 31 WA TAP 1 0105_2 29 WA TAPl D105_2 27 WA TAP 1 D105_2 25 W

END_TABLE

DATAU5E_CONF1G conf-l

1 U5E A (UUO OODD DDO DDDD DDDD DDDD UUUU UUUU 0)2 U5E A (DUD DDDD DDD DDOD DDDD ODDD UUUU UUUU D)3 U5E A (UUD DDDD ODD OODD ODDO DDDO UUUU UUUU 0)

4 U5E A (UUU DUUU DDD DDDD ODDO ODDD HHHH HHHH D)5 U5E A (UDU OUUU DDD DDDD DODO DDDD HHHH HHHH D)6 U5E A (UUU DUUU DDD ODDD DDDD DDDD mum HHHH D)

7 U5E A (UUU UOUU DDD DDOD DDDD DDDD HHliH HHHH D)8 U5E A (UDU UDUU DDD DODD DODD ODDD HHHH HHHH D)9 U5E A (UUU UDUU DOD DDOD DDDD ODDD HHHH HHHH D)

56

10 USE A (UUU UUDU DDD DDDD DDDD DDDD HHHH HHHH D)11 USE A (UDU UUDU DDD DDDD DDDD DDDD HHHH HHHH D)12 USE A (UUU UUDU DDD DDDD DDDD DDDD HHHH HHHH D)

13 USE A (UUU UUUD DDD DDDD DDDD DODD HHHH HHHH D)14 USE A (UDU UUUD DDD DDDD DDDD DDDD HHHH HHHH D)15 USE A (UUU UUUD DOD DDDD DODD DODD HHHH HHHH D)

END_CONFIGEND_DATA

D.2 TTL PCB

This board is a demonstration board. The inputs and outputs of the internal chips are controllableby the on board boundary-scan octals. The test vectors are loaded into these boundary-scan chips[4, 5, 25].

The test vectors define the input and output signals from and to the internal chips (the intercon­nection signals). These vectors are sent from the computer [10] to the boundary-scan controller [12](see appendix B, tester 2). The controller sends this information by means of the boundary-scanprotocol to the boundary-scan octals. Hence by sending a test vector the board can be put into acertain operating state.

The used application files, in BTSL format, are listed at the end of this appendix section. Thetest vectors of the interconnect application file have the following layout (position description):

(1..2)(3 ..4)(5 ..6)(7..8)(9..16)(65 ..72)(73..80)

Select channel of both demultiplexers (U12, A and B)Data for each demultiplexer (U12, !lG and !2G)The enable line and the select line (U21, BST_GATE and BST_SEL)The selection line for led 6 and 7 (FBST_1 and FBST_2)The input signals (U1, INO..IN7)The output signals (OUTO..OUT7)The led selection lines (U2l, SELlA/B. SE-2AjB, SEL3A/B, SELAA/B)

For example the following vector will active all LEDs:

SelectUU

Data Mux BST InputUU UU UU UUUUUUUU

OutputDDDDDDDD

SelectionUUUUUUUU

Interconnect application file

SYNTAX_VERSION 1.0DESIGN CLUSTERREVISION UNKNOWNTEST inter

CONFIG conf-1FREQ = 20000SERIAL_CHANNEL TAP1

TIMING = 0/U3 EXTEST

END_CHANNELSERIAL_CHANNEL TAP2

(LLNNNNNNNNXXXXXXXX)

57

TIMING = 0/DIOS_l EXTEST

/U2 EXTEST/Ul £lTEST

END_CHANNELEND_CONFIG

CONFIG conf-2FREQ = 20000SERIAL_CHANNEL TAPl

TIMING = 0/U3 £lTEST

END_CHANNELSERIAL_CHANNEL TAP2

TIMING = 0/DIOS_l EXTEST

/U2 £lTEST/Ul EXTEST

END_CHANNELEND_CONFIG

ACCESS_DESCRIPTIONCONFIG conf-l

USE AEND_CONFIGCONFIG conf-2

USE BEND_CONFIG

END_DESCRIPTION

ACCESS_TABLEBSLA ABBST_B ABBST_Gl ABBST_G2 ABBST_GATE AB

ABBST_SEL AB

ABFBST_l AB

ABFBST_2 AB

ABINO AB

ABINl AB

ABIN2 AB

ABIN3 AB

ABIN4 AB

(HXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHX)

(HXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXLNLNLNLNLNLNLNLN)

(LLNNNNNNNNXXXXXXXX)(LLNNNNNNNNXXXXXXXX)

(HHNNNNNNNNXXXXXXXX)

(HXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHX)

(HXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHX)

(LLNNNNNNNNXXXXXXXX)(LLNNNNNNNNXXXXXXXX)

TAP2 /Ul 7 W 2;TAP2 /Ul 6 W 3;TAP2 /Ul 5 W 4;TAP2 /Ul 4 W 5;TAP1 /U3 10 R 17TAP2 /Ul 2 W 8;TAP1 /U3 11 R 19TAP2 /Ul 3 W 7;TAP1 /U3 9 R 16TAP2 /Ul 1 W 9;TAP1 /U3 8 R 15TAP2 /Ul 0 W 10;TAP2 /DIOS_l 14 B 11TAP2 /Ul 15 R 23;TAP2 /DIOS_l 12 B 28TAP2 /Ul 14 R 22;TAP2 /DIOS_l 10 B 29TAP2 /Ul 13 R 21;TAP2 /DIOS_l 8 B 30TAP2 /Ul 12 R 20;TAP2 /DIOS_l 6 B 31

58

AB TAP2 IU1 11 It 19;INS AB T1P2 10105_1 4 B 17

AB TAP2 IUl 10 It 17;IN6 AB TAP2 /010S_1 2 B 22

AB TAP2 IUl 9 It 16;IN7 AB TAP2 IDIOS_1 0 B 23

AB TAP2 /U1 8 It 15;N$743 AB TAP2 /0105_1 52 B 15;N$744 AB TAP2 /DI05_1 54 B 14:N$745 AB TAP2 /DI05_1 56 B 51;N$746 AB TAP 2 /DI05_1 58 B 49:N$747 AB TAP2 /DI0S_1 60 B 48;N$748 AB TAP2 /DI0S_1 62 B 47;N$753 AB TAP2 /DI05_2 62 B 47;N$754 AB TAP2 /DI0S_2 60 B 48;N$755 AB TAP2 /DI05_2 58 B 49;N$756 AB TAP2 /DIOS_2 56 B 51;N$757 AB TAP2 /0105_2 54 B 14;N$812 AB TAP2 /0105_2 22 B 57;N$813 AB TAP2 /010S_2 32 B 62;N$814 AB TAP2 /0105_2 42 B 42;N$815 AB TAP 2 /010S_2 52 B 15:N$817 AB TAP2 /DI0S_2 18 B 9;N$818 AB TAP2 IDIOS_2 28 B 53;N$819 AB TAP2 /DIOS_2 38 B 59;N$820 AB TAP2 /DI0S_2 48 B 39;N$822 AB TAP2 /DI05_2 24 B 56;N$823 AB TAP2 /D1OS_2 34 B 61;N$824 AB TAP2 /DIOS_2 44 B 41;N$826 AB TAP 2 /D1OS_2 20 B 8-,N$827 AB TAP 2 /DIOS_2 30 B 63;N$828 AB TAP2 /DI0S_2 40 B 58;N$829 AB TAP2 /DIOS_2 50 B 38:N$830 AB TAP2 101OS_2 16 B 10;N$831 AB TAP2 /0105_2 26 B 55;N$832 AB TAP2 /0105_2 36 B 60;N$833 AB TAP2 /01OS_2 46 B 40;N$835 AB TAP2 /010S_1 50 B 38;N$836 AB TAP2 /010S_1 16 B 10;N$837 AB TAP2 /0IOS_1 26 B 55;N$838 AB TAP2 /010S_1 36 B 60;N$839 AB TAP2 /DIOS_1 46 B 40;N$841 AB TAP2 /DIOS_1 22 B 57;N$842 AB TAP2 /DIOS_1 32 B 62;N$843 AB TAP2 /DIOS_l 42 B 42;N$845 AB TAP2 IDI05_1 18 B 9;N$846 AB TAP2 /DIOS_l 28 B 53;N$847 AB TAP2 /DIOS_l 38 B 59;N$848 AB TAP2 /DIOS_l 48 B 39;N$850 AB TAP2 /DIOS_1 24 B 56;N$851 AB TAP2 /DIOS_l 34 B 61;N$852 AB TAP2 /DIOS_1 44 B 41;N$854 AB TAP2 /DIOS_l 20 B 8;N$855 AB TAP2 /DIOS_1 30 B 63;N$856 AB TAP2 /DIOS_1 40 B 58;DurO A TAP1 /U3 7 W 2

A TAP2 /DIOS_2 14 It 11B TAP2 /DIOS_2 14 B 11;

59

oun A TAP1 /U3 6 W 3A TAP2 /DIOS_2 12 R 28B TAP 2 /DIOS_2 12 B 28;

OUT2 A TAP1 /U3 5 W 4A TAP2 /DIOS_2 10 R 29B TAP2 /DIOS_2 10 B 29;

OUT3 A TAP1 /U3 4 W 5A TAP2 /DIOS_2 8 R 30B TAP2 /DIOS_2 8 B 30;

OUT4 A TAPl /U3 3 W 7A TAP2 /DIOS_2 6 R 31B TAP2 /DIOS_2 6 B 31;

OUT5 A TAPl /U3 2 W 8A TAP2 /DIOS_2 4 R 17B TAP2 /D10S_2 4 B 17;

OUTS A TAPl /U3 1 W 9A TAP2 /DIOS_2 2 R 22B TAP2 /DIOS_2 2 B 22;

OUT7 A TAPl /U3 0 'Ii 10A TAP 2 /DIOS_2 0 R. 23B TAP2 /DIOS_2 0 B 23;

SEL_1A AB TAP2 /U2 7 W 2;SEL_1B AB TAP2 /U2 6 W 3;SEL_2A AB TAP2 /U2 5 W 4;SEL_2B AB TAP2 /U2 4 W 5'.SEL_3A AB TAP2 /U2 3 W 7;SEL_3B AB TAP2 /U2 2 W 8;SEL_4A AB TAP2 /U2 1 W 9;SEL3B AB TAP2 /U2 0 'Ii 10;END_TABLE

DATA

! Extended stuck_at_O/stuck_at_l patterns.USE_CONFIG conf-l

001 USE A (11111111111111111111111111111111111111111111111111111111111111111111111111111111)

002 USE A (00000000000000000000000000000000000000000000000000000000000000000000000000000000)

END_CONFIGUSE_CONFIG conf-2

003 USE B (11111111111111111111111111111111111111111111111111111111111111111111111111111111)

004 USE B (00000000000000000000000000000000000000000000000000000000000000000000000000000000)

END_CONFIG

Distributed bridging patterns with complement.USE_CONFIG conf-2

005 USE B (00000000000000000000000000000000000000000001111111111111111111111111111111111111)

END_CONFIGUSE_CONFIG conf-l

006 USE A (00000000000000000000011111111111111111111110000000000000000000001111111111111111)

END_CONFIGUSE_CONFIG conf-2

007 USE B (000000000001111111111000000000001111111111100000000001111111

60

11110000000000011111)END_CONFIGUSE_CONFIG conf-l

008 USE A (00000111111000001111100000011111000001111110000011111000000111110000011111100000)

END_CONFIGUSE_CONFIG conf-2

009 USE B (00011000111001110001100011100111000110001110011100011000111001110001100011100111)

END_CONFIGUSE_CONFIG conf-l

010 USE A (01101001011010010110100101101001011010010110100101101001011010010110100101101001)

END_CONFIGUSE_CONFIG conf-2

011 USE B (00110011001100110011001100110011001100110011001100110011001100110011001100110011)

END_CONFIGUSE_CONFIG conf-l

012 USE A (10101010101010101010101010101010101010101010101010101010101010101010101010101010)

END_CONFIGUSE_CONFIG conf-2

013 USE B (01010101010101010101010101010101010101010101010101010101010101010101010101010101)

END_CONFIGUSE_CONFIG conf-l

014 USE A (11001100110011001100110011001100110011001100110011001100110011001100110011001100)

END_CONFIGUSE_CONFIG conf-2

015 USE B (10010110100101101001011010010110100101101001011010010110100101101001011010010110)

END_CONFIGUSE_CONFIG conf-l

016 USE A (11100111000110001110011100011000111001110001100011100111000110001110011100011000)

END_CONFIGUSE_CONFIG conf-2

017 USE B (11111000000111110000011111100000111110000001111100000111111000001111100000011111)

END_CONFIGUSE_CONFIG conf-l

018 USE A (11111111111000000000011111111111000000000001111111111000000000001111111111100000)

END_CONFIGUSE_CONFIG conf-2

019 USE B (11111111111111111111100000000000000000000001111111111111111111110000000000000000)

END_CONFIGUSE_CONFIG conf-l

020 USE A (11111111111111111111111111111111111111111110000000000000000000000000000000000000)

Open detection application file for open Xl and X6

61

SYNTAX_VERSION 1.0DESIGN CLUSTERREVISION UNKNOWNTEST inter

CONFIG conf-lFREQ = 100SERIAL_CHANNEL TAPl

TIMING = 0/U3 EITEST

END_CHANNELSERIAL_CHANNEL TAP2

TIMING = 0/DIOS_l EXTEST

/U2 EITEST/Ul EITEST

END_CHANNELEND_CONFIG

ACCESS_DESCRIPTIONCONFIG conf-l

USE AEND_CONFIG

END_DESCRIPTION

ACCESS_TABLEBST_A ABST_B ABST_Gl ABST_G2 AlA4 A2A3 AEND_TABLE

DATA

(LLNNNNNNNNHHHHHHHH)

(HXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHIHXHXHXHXHXHXHXHXHXHXHXHXHXHI)

(HXHXHXHXHXHXHXHXHXHXHXHXHXHXHIHXHXHIHXHXHXHXHXHILNLNLNLNLNLNLNLN)

(LLNNNNNNNNXXXXXIXI)(LLNNNNNNNNXIIIIIXI)

TAP2 /Ul 7 W 2;TAP2 /Ul 6 W 3;TAP2 /Ul 5 W 4;TAP2 /Ul 4 W 5;TAP2 /U2 12 R 20;TAP2 /U2 9 R 16:

USE_CONFIG001 USE A002 USE A

END_CONFIG

conf-l(110100)(011011)

Open detection application file for open X4 and X5

SYNTAX_VERSION 1.0DESIGN CLUSTERREVISION UNKNOWNTEST inter

CONFIG conf-lFREQ = 20000SERIAL_CHANNEL TAPl

TIMING = 0/U3 EITEST

END_CHANNEL(LLNNNNNNNNHHHHHHHH)

62

SERIAL_CHANNEL TAP2TIMING = 0IDIOS_l EXTEST

IU2 EXTESTlUi EXTEST

END_CHANNELEND_CONFIG

ACCESS_DESCRIPTIONCONFIG conf-l

USE AEND_CONFIG

END_DESCRIPTION

(HXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHX)

(HXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXHXLNLNLNLNLNLNLNLN)

(LLNNNNNNNNXXXXXXXX)(LLNNNNNNNNXXXXXXXX)

ACCESS_TABLEBST_GATE

FBSLl

DATA

USE_CONFIG000 USE A002 USE A

END_CONFIG

AAAA

conf-l(11)

(00)

TAPl IU3

TAP2 lUiTAP 1 IU3TAP2 lUi

63

10 R 172 W 8;

9 R 161 W 9;

Appendix E

Tables (Ie PSC consumption)

This appendix lists the following DC electrical characteristics for all ICs per tested PCB (see alsothe data-sheets [23, 24, 25, 26, 27, 28]):

Icc Supply current: The current flowing into the Vee supply terminal of the circuit. Input con­ditions are chosen to guarantee worst case operation. (displayed: typical value)

VI £ Input LOW voltage: The range of input voltages recognized by the device as a logic LOW.(displayed: maximum value)

VIH Input HIGH voltage: The range of input voltages recognized by the device as logic HIGH.(displayed: minimum value)

IlL Input LOW current: The current flowing out of an input when a specified LOW level voltageis applied to that input. (displayed: maximum value)

IIH Input HIGH current: The current flowing into an input when a specified HIGH level voltageis applied to that input. (displayed: maximum value)

VOL Output LOW voltage: The maximum guaranteed LOW voltage at an output terminal sinkingthe specified load current 10£. (displayed: maximum value)

VOH Output HIGH voltage: The minimum guaranteed HIGH voltage at an output terminal forthe specified output current IO H and at the minimum Vee values. (displayed: minimumvalue)

10£ Output LOW current: The current flowing into an output which is in the LOW state. (dis­played: maximum value)

IO H Output HIGH current: The current flowing out of an output which is in the HIGH state.(displayed: maximum value)

los Output short-circuit current: The current flowing out of an output which is in the HIGHstate when that output is short-circuit to ground. (displayed: min/max value)

64

E.! CMOS PCB

Table E.! PSC consumption of all ICs on CMOS PCB

Icc 2p,A 2p,A 8pA 8p,A 8pAVlL 0.8V 0.8V 0.8V 0.8V 0.8VV1H 2.2V 2.2V 1.6V 1.6V 1.6VIlL 1.0pA 1.0p,A O.lpA O.lpA O.lpAIlH 1.0p,A 1.0p,A O.lpA O.lpA O.lpAVOL OAV OAV O.3V 0.3V 0.3VVOH 4.5V 4.5V 4.0V 4.0V 4.0VIOL - - - - -IOH - - - - -los . - 25mA min. 25mA min. 25mA min.

~ D43256AC-lOL I D43256AC-12L I 74HCT373 I 74HCT244 I 74HCT138 ~

Remarks:

1. Values marked with the character "." are not specified in the data-sheets.

2. DC symbols and definitions are listed at the begin of this appendix.

E.2 TTL PCB

Table E.2 PSC consumption of all ICs on TTL PCB

Icc 3.6mA 6.8mA 9.7mA 52.0mAVlL O.8V O.8V O.8V O.8VV1H 2.0V 2.0V 2.0V 2.0VIlL OAmA OAmA OAmA LOrnAI lH 20mA 20mA 20mA 20p,AVOL OAV OAV OAV OAVVOH 2.7V 2.7V 2.7V 2.0VIO L 8.0mA 8.0mA 8.0mA 64mAIOH OAmA OAmA OAmA 15mAlos 20mA min. 15mA min. 20mA min. 100mA min.los 100mA max. 100mA max. 100mA max. 225mA max.

~ 74L804 I 74L8139 I 74L8157 I 74BCT8244 ~

Remarks:

1. Values marked with the character "-" are not specified in the data-sheets.

2. DC symbols and definitions are listed at the begin of this appendix.

3. The data-sheets of the 74BCT8244 specify Icc at different conditions. Icc is52mA when all outputs are driven low, 5.5mA when all output are driven highand 2.3mA when all outputs are disabled (tri-state).

65

Appendix F

Tables(measurements/ estimations)

All values displayed in this appendix (tables) are the results of multiple measurements.

F.1 CMOS PCB: Measured PSC, the fault free board

Table F.l Measured PSC (in !-LA) on the fault free PCB (no pull-ups active)

~ Vector rr~---=-=-====::]

~ ~1,W 200 45 220 120 100 1202,W 120 22 120 53 49 783,W 210 58 190 120 100 1204,R 240 140 200 76 75 815,R 90 38 58 60 65 786,R 220 90 200 76 76 79

Notes:

1. The vector 1 and 3 are the same vector, and vector 4 and 6 are also the same.Vectors 1, 2 and 3 represent the write cycle and the vectors 4, 5 and 6 represent theread cycle. The deviation of these current values is ±21 /2f-LA « lOOf-LA) or ±25f-LA(>lOO!-LA). The voltage across the PCB is maintained at 5 Volt throughout allmeasurements.

2. Test 1 is the PSC measurement before measuring the PSC values of the nexttable F.2 (these values were measured directly after the board was powered on).Test 2 is the PSC measurement after the values of that table were measured (fourhours later). The last three measurements were made in sequence with a largewarming up time (approximately three hours) and at least ten minutes betweenmeasurements.

3. The test sequence can be found in appendix D.1.

66

F.2 CMOS PCB: Measured PSC, opens

Table F.2 Measured PSG (in JLA) for opens (no pull-ups active)

Vector Global SHAM1!WE; lOE ADR14 DQ7 lCS DQ7

1,W 240 78 140 40 130 712,W 240 140 28 28 80 953,W 280 86 150 66 170 914,R 320 140 180 140 210 1305,R 250 110 170 40 75 306,R 300 140 150 110 210 110

Notes:

1. The vector 1 and 3 are the same vector, and vector 4 and 6 are also the same.Vectors 1, 2 and 3 represent the write cycle and the vectors 4, 5 and 6 represent theread cycle. The deviation of these current values is ±21hJLA «100JLA) or ±25JLA(> 100JLA). The voltage across the PCB is maintained at 5 Volt throughout allmeasurements.

2. Test 1 and 2 of the previous table F.1 are the PSC measurements, without anydefect, before and after the values in this table were measured, respectively. ThePSC values were measured in sequence: !CS of SHAM1, !WE, !OE, ADR14, DQ7of SRAM1 and last DQ7) without any warming up.

3. The test sequence can be found in appendix D.l.

F.3 CMOS PCB: Measured PSC, signal shorts

Table F.3 Measured PSG (in rnA) for shorts between nets (!=NOT)

OCTAL2 !Cy, Cx 50±1 1h Chip select, CS(x) and CS(y)OCTAL3 !Ay, Ax 50±11 h Address, adr(x) and adr(y)OCTAL4 !Ay, Ax 50±11 h Address, adr(x) and adr(y)OCTAL5 !Dx, Dy 50±11 h Data, all SRAMs in read modeRAMv-w !Dx, Dy 25±11 h Data, short between different SRAMsRAMv-v !Dx, Dy 25±1 1 / 2 Data, other RAMs disabled

~ Chip I Output drivers ~ Current I Remark (x/y) ~

Notes:

1. The PSC values listed in this table are the absolute PSC values. The PSC con­sumption of the fault free board is smaller than 1mA (no pull-up circuitry isactivated).

2. All test vectors gave approximately the same result. The PSC is measured for alloutput drivers per chip.

3. The voltage across the PCB is maintained at 5 Volt throughout all measurements.

4. The test sequence can be found in appendix D.l.

67

F.4 CMOS PCB: Measured PSC, power supply shorts

Table F.4 Measured PSG (in rnA) for power supply shorts

~ Chip I Type ~ Low output on Vee I High output on GND ~

RAMI D43256AC 41±Ph 25±P/2RAM2 D43256AC 40±llh 26±11/2RAM3 D43256AC 40±11/2 25±11/2RAM4 D43256AC 39±11/2 25±11hOCTAL2 74HCT244 70±llh 55±11/2OCTAL3 74HCT244 65±llh 54±llhOCTAL4 74HCT244 65±llh 53±llhOCTAL5 74HCT244 65±11/2 50±11/2OCTAL6 74HCT244 70±llh 54±llh

Notes:

1. The PSC values listed in this table are the absolute PSC values. The PSC con­sumption of the fault free board is smaller than ImA (no pull-up circuitry isactivated).

2. All test vectors gave approximately the same result. The PSC is measured for alloutput drivers per chip.

3. The voltage across the PCB is maintained at 5 Volt throughout all measurements.

4. The test sequence can be found in appendix D.l.

68

F.5 TTL PCB: Estimated PSC, opens and signal shorts

Table F.5 Estimated minimum PSG for opens and signal shortsV~ctOI' F~l.\llt 0 tHllili Silorh

free Xl X4 0 2 XV xl. A13 A10

1 51.2 51.2 51.1 51.2 51.2 51.2 51.2 in.:! 51.2 51.2 51.2 51.2 51.22 250.4 250.4 248.0 240.4 250,4 205.4 205.4 250.4 250.4 25(L4 205.4 250.4 250.43 4S.0 ols.n 47.9 olS.0 4S,U 48.0 48.0 48.n 48.11 48.H 4S.0 4S.0 48.04 200.7 200.7 198.9 199.7 200,1 215.1 215.7 ZOO.? :wn.7 ZOO.7 215.7 ZOO.? ZOO.75 98.7 98.7 9G.9 97.7 98.7 113.7 113.7 98.7 98.7 98.7 113.7 98.7 98.7G 101.0 IOI,!) IOO.! IOO.!) 101.0 11G.9 11G.9 101.0 101.9 lOt.!> 110.9 In}.o IOt.!)7 1G7.8 107.8 1GG.n 1GG.8 1G7.8 182.8 1G7.8 107.8 IG7.8 107.8 182.8 107.8 107.88 173.1 173.1 171.3 173.1 173.1 188.1 173.1 173.1 193.1 273.1 173.1 273.1 273.19 138.3 138.2 138.2 137.3 138.2 138.3 153,3 138.3 138.3 238.3 138.3 138.3 238.3

1<1 151.8 151.8 151.8 150.8 151.8 151.0 100.8 251.8 151.8 251.8 100.8 151.8 151.811 123.3 123.3 121.5 123.3 123,3 123.3 138.3 123.3 143.3 223.3 138.3 123.3 123.312 lrl{).O 149.0 laO.U ISO,II ISO.U 105.0 tOS.n 250.n 15n.u 25U.n HiO,n HiO.O lS0.n13 121.2 121.2 119.4 120.2 121.2 121.2 121.2 121.2 121.2 221.2 130.2 121.2 121.214 149.9 149.8 149.8 148.9 148.9 140.0 240.0 249.0 149.9 244.0 140.9 149.9 140.015 123.2 123.2 121.4 123.3 123.2 123.2 123.2 123.2 143.2 223.2 123.2 123.2 123.210 124.3 124.3 122.5 124.3 124.3 124.3 224.3 124.3 144.3 224.3 124.3 224.3 224.317 1115.0 105.9 105.0 104.0 105.0 105.0 12U.O 105.0 10s.n 205.0 12n.o 105.0 112.n18 82.2 82.1 82.1 82.1 82.1 82.2 82.2 82.2 82.2 82.2 82.2 182.2 82.210 140.1 140.1 140.1 140.1 140.1 140.1 140.1 140.1 140.1 140.1 140.1 140.1 140.120 105.8 105,8 105,8 105.8 105.8 105,8 105,8 105.8 105.8 1DS.8 105.8 105.8 195.8

Notes:

1. The defects XIO, X14, X16 and X17 (see next two tables, note 2) are shorts inthe boundary-scan chain. The defect XIO forces almost all outputs high (lowestPSC state). The level of PSC is defined by the current through the LEDs and thecurrent consumption of U3 (output buffer/led-driver) only. The change in PSCcaused by the defects X14, X16 and X17 are to complex to estimate manually(PSC values depend on previous sta,tes). Furthermore, the boundary-scan chipsdo not comply with the boundary-scan architecture standard [5] with respect tothe states of TDO; TDO never goes in tristate.

2. The defect XlI is not simulated because this fault is not detectable. The increasein current is supplied by the power supply of the tester, hence the PSC observedin the Vee-line does not increase.

3. The absolute deviation of these PSC values is 0.15% of the value plus 0.05mA.The voltage across the PCB is maintained at 5 Volt throughout all measurements.Several manufacturers didn't specify minimum values, hence typical values areused for those estimations. The test sequence can be found in appendix D.2.

Table F.6 Estimated maximum PSG (in mA) for opens and signal shortsVt!ctor Fa-lilt ()J.H:mtll :::iburt ..

fl'~ 1 X4 Xo X, X. X3 X X8 Xv AI. Als A10

1 al,2 51.2 51.1 51.2 51.2 51.2 51.2 51.2 51.2 51.2 51.2 51.2 51.22 251),4 250.4 248.0 249.4 :l5C).4 35n.4 350.4 250.4 250.4 2aO.4 350.4 2aO.4 250.43 48.U 48.0 47.9 48.0 48.U 48.U 4S.n 48.U 4S.0 48.n 48.0 4S.0 48.U4 2nn.7 2t10.7 198.9 199.7 200.7 300.7 300.7 20n.7 2nn.7 200.7 300.7 200.7 200.75 98.7 98.7 90.0 07.7 98.7 198.7 108.7 98.7 98.7 98.7 198.7 08.7 98.70 101.9 IOI.!) IOO.1 lUlL!) 101.9 201.0 201.0 101.0 10}.0 101.0 20}.0 lut.O 101.07 107.8 107.8 10G.n 100.8 107.8 207.8 107.8 IG7.8 107.8 107.8 201.8 107.8 107.88 173.1 173.1 171.3 173.1 173.1 273.1 173.1 173.1 273.1 308.1 173.1 398.1 308.10 138.3 138.2 138.2 137.3 138.2 138.3 238.3 138.3 138.3 3G3.3 138.3 138.3 303.3In 151.8 151.8 151.8 15tL8 151.8 151.0 251.8 370.8 1~1.8 370.8 251.8 151.8 151.811 123.3 123.3 121.5 123.3 123.3 123,3 223.3 123.3 223.3 348.3 223.3 123.3 123.312 laO.O 149.0 15n.n 150.0 150.U 25n.1) 250.0 37&.n 150.0 375,U 150.n 15o.n 150.U13 121.2 121.2 110.4 120,2 121.2 121.2 121.2 121.2 121.2 340.2 221.2 121.2 121.214 140.9 140.8 149.8 148.9 148.9 140.9 374.0 374.9 140.0 374.9 140.9 149.9 149.915 123.2 123.2 121.4 123.3 123.2 123.2 123.2 123.2 223.2 348.2 123.2 123.2 123.210 124.3 124.3 122.S 124.3 124.3 124.3 340.3 124.3 224.3 349.3 124.3 340.3 349.317 10tt.0 105.0 105.0 104.0 105.0 105.0 205.0 105.9 105.0 33n.9 205.0 10S.0 112.n18 82.2 82.1 82.1 82.1 82.1 82.2 82.2 82.2 82.2 82.2 82.2 307.2 82.210 140.1 140.1 140.1 140.1 140.1 140.1 140.1 140.1 140.1 140.1 140.1 140.1 140.120 105.8 105.8 195.8 105.8 105.8 105.8 105.8 195.8 105.8 105.8 1D5.8 105.8 195.8

Note: All notes given at the previous table (minimum PSC estimations) are also truefor this table. Except, the maximum PSC estimations are obtained from maximum ortypical (if the manufacturers didn't specify any maximum values) values.

69

F.6 TTL PCB: Measured PSC, opens and signal shorts

Table F.7 Measured PSG (in rnA) for opens and signal shortsYt:t<.:&or FauJt: Opt:tU.lll ShQrtti{,_ Xl x4 X, XO X2 X3 X X~ x9 xlO A12

1 22.9 22.7 22.1 22.7 22.0 22.0 32.02 lOG. a 107.1 100.8 100.0 100.0 100.3 25(L2 220.4 luo.n 2I8.a3 21.4 20.1 ZO.2 20.t 20.2 20.n 29.04 135.2 132.7 133.3 133.5 133.8 133.7 191.4 188.0 29.0 180.75 50.1 50.3 so.a 50.S ~(}.2 GOA 107.2 107.2 29.7 IOO.S0 49.2 49.3 49.7 49.9 49.3 40.5 lOS.? IOG.n 28.8 105.37 100.0 IOS.S lO8.0 108.3 lO8.8 108.7 105.4 103.4 :W.7 102.48 IOG.n 100.4 lOO.4 lOO.1 lOO.7 IOG.S 102.8 141.2 223.5 77.49 85.0 84.0 85.9 85.G 84.7 84.8 141.0 202.7 20.110 85.0 84.7 85.u 85.5 84.8 84.8 14U.7 208.4 203.1 07.8 140.211 09.8 70.3 70.5 7n.5 7n.4 70.4 12G.n 105.7 189.7 29.7 125.512 94.3 94.4 94.0 94.0 94.0 95.2 153.4 ISO,2 217.7 71.113 TO.2 7(1.1 70.3 70.S Tn.l TO.I 29.7 125.514 94.3 94.3 94.0 94.0 95.1 95.3 151.0 217.5 212.5 71.11~ 77.1l 70.9 77.1 77.2 70.8 77.5 112.2 195.0 29.810 09.4 09.3 GO.5 GO.5 09.3 09.1 120.9 104.'" 189.0 48.417 50.4 GO.n 50.0 OU.2 GO.n 59.0 I1G.2 170.2 29.7 110.018 37.5 37.2 37.3 37.3 37.2 37.2 28.819 95.5 00.2 90.3 90.3 90.0 00.4 20.820 120.0 I30,t 128.2 130.3 130,1) 120.5 100.2

Notes:

1. For clarity, the cells with a PSC value within the PSC range of the fault freeboard (see column two and tree) are marked by a".".

2. Seventeen jumpers are present on the PCB (C.4) which allows the user to insertdifferent types of faults on the board. When a short-jumper is not placed it isinactive. The open-jumper on the other hand is removed to activate the defect.The following table lists the first twelve jumpers with a brief defect description:

Xl Opens the connection between !2Y2 (V12) and V22 pin 13.X2 Bridging fault between !2Yl (V12) and TDO (VI).X3 Bridging fault between !2Y3 (V12) and 2Yl (VI).X4 Opens the BST_GATE between 2Y2 (VI) and !G (V2l) and 2A2 (V3).X5 Opens the BST_SEL between 2Y3 (VI) and !A/B (V2l) and 2A3 (V3).X6 Opens the connection between !lY3 (V12) and lA4 (V2).X7 Bridging fault between nets OVT3 and OVT4.X8 Bridging fault between lY and 2Y (V2l).X9 Bridging fault between 2Y2 and 2Y3 or 2Y3 and 2Y4 (VI).XlO Opens the TEST MODE SELECT (TMS, VI).Xll Bridging fault between nets IN3 and IN4.X12 Bridging fault between !2Y3 (V12) and net INO.

3. The defects XlO, X14, X16 and X17 are shorts in the boundary-scan chain. Thedefect XIO forces almost all outputs high (lowest PSC state). The level of PSCis defined by the current through the LEDs and the current consumption of V3(output buffer/led-driver) only. The change in PSC caused by the defects X14,X16 and X17 are to complex to estimate manually (PSC values depend on previousstates). Furthermore, the boundary-scan chips do not comply with the boundary­scan architecture standard [5) with respect to the states of TDO; TDO never goesin tristate.

4. The defect Xll is not simulated because this fault is not detectable. The increasein current is supplied by the power supply of the tester, hence the PSC observedin the Vee-line does not increase.

5. The absolute deviation of these PSC values is 0.15% of the value plus 0.05mA.The voltage across the PCB is maintained at 5 Volt throughout all measurements.The test sequence can be found in appendix D.2.

70

Table F.8 Measured PSG (in rnA) for opens and signal shorts, continue

Vector Fault Shorts, continuefree X13 X14 X15 X16 X17

1 22.9 22.7 83.9 39.4 56.02 166.5 167.1 148.43 21.4 20.1 80.6 36.9 53.64 135.2 132.7 70.2 86.75 50.1 50.3 101.6 86.76 49.2 49.3 86.2 203.67 109.0 108.5 86.68 106.0 106.4 194.7 161.3 216.2 218.2 117.79 85.6 84.6 144.0 173.4 78.5 78.610 85.0 84.7 201.7 104.311 69.8 70.3 169.0 185.112 94.3 94.4 154.0 110.8 110.713 70.2 70.1 190.0 185.214 94.3 94.3 153.4 110.9 110.815 77.0 76.9 135.5 93.4 70.316 69.4 69.3 159.3 195.2 175.5 76.917 59.4 60.0 119.2 64.9 66.2 66.218 37.5 37.2 128.4 169.1 49.219 95.5 96.2 153.8 170.020 126.6 130.1 229.3 244.2

Notes:

1. For clarity, the cells with a PSC value within the PSC range of the fault freeboard (see column two and tree) are marked by a".".

2. Seventeen jumpers are present on the PCB C.4 which allows the user to insertdifferent types of faults on the board. When a short-jumper is not placed it isinactive. The open-jumper on the other hand is removed to activate the defect.The following table lists the last five jumpers with a brief defect description:

X13 Bridging fault between 2Y4 (U1) and net IN7.X14 Bridging fault between !2YO (U12) and TDO (U1).X15 Bridging fault between 1Y1 (U2) and net OUTO.X16 Bridging fault between TDO of U1 and U2.X17 Bridging fault between TDO of U1 and U3.

3. The defects XlO, X14, X16 and X17 are shorts in the boundary-scan chain. Thedefect X10 forces almost all outputs high (lowest PSC state). The level of PSCis defined by the current through the LEDs and the current consumption of U3(output buffer/led-driver) only. The change in PSC caused by the defects X14,X16 and X17 are to complex to estimate manually (PSC values depend on previousstates). Furthermore, the boundary-scan chips do not comply with the boundary­scan architecture standard [5] with respect to the states of TDO; TDO never goesin tristate.

4. The defect XlI is not simulated because this fault is not detectable. The increasein current is supplied by the power supply of the tester, hence the PSC observedin the Vee-line does not increase.

5. The absolute deviation of these PSC values is 0.15% of the value plus 0.05mA.The voltage across the PCB is maintained at 5 Volt throughout all measurements.The test sequence can be found in appendix D.2.

71

F.7 TTL PCB: Measured PSC, power supply shorts

Table F.9 Measured PSG (in rnA) for power supply shorts

U1 74BCT8244 (430-160) 270±30 (150-17) 133±17U12 74L8139 (220-160) 60±30 (75-17) 58±3U13 74L804 (200-160) 40±30 (130-100) 30±17U2 74BCT8244 (450-160) 290±30 (150-17) 133±17U21 74L8157 (200-160) 40±30 (150-110) 40±30U3 74BCT8244 (450-160) 290±30 (170-20) 150±17

~ Chip I Type ~ Low output on Vee I High output on GND ~

Note: The value between brackets represent the P8C increase (short current - faultfree board current). The voltage across the PCB is maintained at 5 Volt throughoutall measurements.

72

Appendix G

Digital Audio Broadcast (DAB)

Note May 1, 1995

uP

POWER

BLASTER: PM3720

TAP1/2 : PF2130

DIOSI/2 : PF2111

POWER : PM2813

SCOPE : 2430A

DAB2S

Yl

SCOPE

Figure G.!: Simplified measuring schematic diagram

The description of the measuring equipment is given in appendix B.

73

G.! Introduction

The Digital Audio Broadcasting test receiver was developed by the Philips Advanced DevelopmentCenter during the Eureka 147 project. The kernel of the DAB is Philips'JESSI DAB chip-set. Theset consists of FADIC (FFT processing) [20], SIVIC (De-interleaving and Viterbi decoding) [21]and SAA2500/SAA2501 (MPEG Audio layer I & II decoding) [39]. The DAB implementationis split into two printed circuit boards, the digital and analogue PCB. The digital subprint wassubjected to (dynamic) PSC measurements to define the usability of PSCM for complex CMOSassemblies.

G.2 Measurements

(G.l)

Figure G.l shows the measuring diagram [19] used for the PSC measurements. The test vectorsare sent from the vector blaster (see appendix B, tester 3). The blaster sends this informationby means of the boundary-scan protocol to the digital I/O scan module, which consists of twoboundary-scan ICs (DIOSes), and to the PCB. The bidirectional ports of the DIOSes are connectedto the inputs and outputs of the printed circuit board, hence by sending a test vector the boardcan be put in a certain state. Before each test the DIOSes and the board are powered down. Thisis the only way to put the board in test mode [19]. The resistor Rs of 0.150 is used as currentsensor. The following equation is used to calculate the PSC through the PCB (where V. is thevoltage across the sensor):

Vs VsI = R

s= 0.15 ::::: 6.67Vs

Figures G.2 .. G.13 display the dynamic PSC behavior (oscilloscope picture) of twelve tests. Thefigures show (binary) square blocks near the time axes. These blocks represents the duration ofsubtests within each test (the time of the actual subtests). At each subtest the level of the squareblock is toggled (low to high and high to low). In most cases the correlation between the durationof these subtests (blocks) and the level of PSC is high. However, the displayed time resolution,which is low, obscures detail. The PSC behavior before, during and after the subtests were notstable, see figures G.14 and G.15. The negative current value seen in all figures is due to the vectorblaster (always on) which provides power through the boundary-scan interface to the PCB whenthe board and DIOSes are powered down. The distortion shown as a superimposed signal on thePSC is especially due to the influence of the vector blaster (sends EMC and the clock signal TCK[4, 5] is always active: AM signal) and the large number of flat cables (EMC induction) whichconnect the PCB with the test equipment. The description of each test is listed in section G.5.

G.3 Conclusions

The dynamic PSC behavior of the board (dynamic PSCM) ranges between 200 and 750mA. Thevariation in the PSC for identical set of test vectors can vary between 100 and 200mA. From theabove results and the current consumption specs of the DAB digital components (table G.l) canbe noted that direct detection of opens and shorts is not possible, because the variation in PSCfor the fault free board is larger than the PSC change which would be caused by the defects.Also, at the moment of switching to another operating state (new test vector is activated, thenew operating state is engaged) the PSC is not stable, see figures G.14 and G.15. Moreover, theexpectance is that if this board is tested by PSCM at a Manufacturing Environment the externalinfluences will also be large. Hence, the conclusion which can be drawn from these measurementsis that the used setup has the same problems which were accounted at the CMOS measurements

74

(page 10) in this report. Too many distortions were introduced by the test equipment and theenvironment. The following improvements should limit the external influences:

• Use short cables

• Shield the cables

• Shield the test setup

The PSC measurements have not been repeated with these improvements, because the measuringtime was limited. The same conclusions written in the last chapter of this report concerningCMOS assemblies are also true here. The problems stated must be eliminated to make this methodeconomical and practical.

75

G.4 Table (IC PSC consumption)

IIIrr I v I v I I I Vnt I Vn I Inr I In,., Inc::

Table G.! PSG consumption of all IGs on the DABC1 Tf( rr rH f{

OSI" n.8V 2.nv nAV 2.4V .\FAOIC (ASIC) . .\MI'EG

'toomA 1.5V 3.5V S"..A S",A O.5V 4.5V lChuA\

SIYIC (ASIC) .\24C04MLI 2mA 1.5V 3.5V 2",A 2"A nAV 2",A 2",A .\4244.0C)·GoL 2ruA l11J6A 10",A (JAV 2.4V 10pA 10,.. A .\74BCT8244A a2ruA 1l.8Y 2.UV 1.0wA 20pA O.4V 2.nv G4.HruA IS.UluA tOOruA\225ruA7<lHCTll(}O 8"A 1l.8Y loGY U.l",A O.l",A (}.3Y 4.(}Y . 2amA \74HCT(}8D 8"A 1l.8Y loGY 1l.1"A f).IliA O.3V 4.11Y 25rnA\74HCT244D 8"A (}.8Y l.GY O.l",A O.lpA n.3V 4.nv 25wA\14HCT573D 8"A Il.BY l.GY n.l~A (}.l"A 1l.3Y 4.0V . 25mA \74HCT4020 8"A 1l.8Y l.GY O.l",A n.lpA n.3V 4.0V 25mA\GALIGYBB 75ruA n.SV 2.0V O.twA 10",A O,5V 2.4V IO.uInA 3.2rnA 30mA\150mAM27C512 20ruA O.2V 4.8V 10J'A lO,..A n.SY 3.5V l"A l"A ·\10fhuAMAX232A 10ruA U.8V 2.11Y O.4V 3.5V 3.2mA 25wA \ .MCM02U(3CJl5 IG5mA n.sv 2.2V l,..A ,,,A O.4V 2.4V l"A ,,,A .\MSM512!i7ALL 10llJA n.sv 2.2V l"A l"A O.4V 2.4V l,.,A ,,,A .\f>S7C528EBAA 25mA n.sv l.OV SOl' O.5V 2.4V .\ .PCF8[)74T 40",A 1.5V 3.5V 25mA 0.3111 A .\SA5230 110ruA \SCC2692AC 10111 A o.sv 2.oV 20 lAA 20JIIA O.4V 4.5V 75pA 75,..A .\ 10mATDA1543AT SUmA o.4ruA 20,..A \

II Ie

Remarks:

1. The DSP type is the XC56156FE40 and the MPEG type is the SAA2500 (old) orSAA2501 (new).

2. Values marked with the character "-" are not specified in the data-sheets.

3. The DC symbols and definitions (see also data-sheets [27]);

Icc Supply current: The current flowing into the Vee supply terminal of thecircuit. Input conditions are chosen to guarantee worst case operation. (dis­played: typical value)

VlL Input LOW voltage: The range of input voltages recognized by the device asa logic LOW. (displayed: maximum value)

VI H Input HIGH voltage: The range of input voltages recognized by the deviceas logic HIGH. (displayed: minimum value)

II L Input LOW current: The current flowing out of an input when a specifiedLOW level voltage is applied to that input. (displayed: maximum value)

h H Input HIGH current: The current flowing into an input when a specifiedHIGH level voltage is applied to that input. (displayed: maximum value)

VOL Output LOW voltage: The maximum guaranteed LOW voltage at an outputterminal sinking the specified load current 10L . (displayed: maximum value)

VO H Output HIGH voltage: The minimum guaranteed HIGH voltage at an out­put terminal for the specified output current IOH and at the minimum Veevalues. (displayed: minimum value)

IOL Output LOW current: The current flowing into an output which is in theLOW state. (displayed: maximum value)

IOH Output HIGH current: The current flowing out of an output which is in theHIGH state. (displayed: maximum value)

los Output short-circuit current: The current flowing out of an output which isin the HIGH state when that output is short-circuit to ground. (displayed:min/max value)

76

G.5 PSC behavior (oscilloscope pictures)

Interconnect without connectors:

This interconnect test checks the interconnects between the test connectors and the PCB.

Interconnect with connectors:

This interconnect test checks the interconnection between all connectors and the PCB.

Pull-up:

The pull-up test checks the pull-up circuitry.

7014 DRAM SIVIC:

This test checks the DRAM used by the SIVIC.

7015 HCT244 part 1:

This test checks the first LATCH of 7015.

7015 HCT244 part 2:

This test checks the second LATCH of 7015.

7018 HCTOO CA_N:

This test checks the CA..N signal.

7200 HCTOO Reset:

This test checks the reset circuitry.

7011 16V8GAL Clock divider:

This test checks the clock divider.

7000 DSP:

Several tests are done in this DSP-test, more information can be found in [18].

7100 Micro-processor:

Several tests are done in this J.tC-test, more information can be found in (17).

7000/7100 DSP/Micro-processor:

Several test are done in this DSP/ J.tC-test, more information is found in [18, 17].

77

Figure G.2: PSC behavior, interconnect without connects test

78

Figure G.3: PSC behavior, interconnect with connectors test

79

Figure G.4: PSC behavior, Pull-up circuitry test

80

Figure G.5: PSC behavior, 7014 DRAM SIVIC test

81

Figure G.6: PSC behavior, 7015 HCT244 part 1 test

82

Figure G.7: PSC behavior, 7015 HCT244 part 2 test

83

Figure G.8: PSC behavior, 7018 HCTOO CA..N test

84

Figure G.9: PSC behavior, 7200 HCTOO Reset test

85

Figure G.lO: PSC behavior, 7011 16V8GAL Clock divider test

86

Figure G.ll: PSC behavior, 7000 nsp test

87

Figure G.12: PSC behavior, 7100 Micro-processor test

88

Figure G.13: PSC behavior, 7000/7100 nsp/Micro-processor test

89

Figure G.14: PSC behavior, interconnect test at test state activation (first measurement)

90

o

C'l ,.-...e, CZl

E'-'0

E.-....C'l000

en!..-

0......0Q)cc0u......::::J0..c......--s......uCDcc00~

CD~

C0- 0r-- ~ g

(VW) :>Sd

g'"

g- o

'"00o

oNo

ooo

Figure G.15: PSC behavior, interconnect test at test state activation (second measurement)

91

Appendix H

Contact test on assemblies(MCPs)

Note Mar 24, 1995

H.l Problem

The aim of the contact test [14, 15] is to check for the existence of the connection (opens) betweenthe device and its interface to the environment. The theory for this test is based on the voltagedrop across the natural and protection diodes at the device boundary (inputs, outputs and supplypins). In normal operation these diodes are reversed biased and conduct only a very small current,typically in the nA region. If the pin voltage is beyond the normal operation range (i.e. the pinvoltage between VDD and Vss ) then one of the diodes (see figure H.I) will open and clamp the pinvoltage to either VDD or Vss . The maximum forward current of these diodes is typically severalmAo If the proper forward bias current is forced through the diode then the voltage drop will beapproximately 0.6 Volt.

pin __---+------i

Vdd

to internalIe logic

Vss

Figure H.I: Protection diodes on chip I/O

The contact test is usually performed per device (each pin is injected with approximately lOJLAand the voltage drop over the diode is measured, typically between 400 and 700mV). In MCPs(Multi Chip Packages) several (identical) devices are connected to each other by nets. These netsmake it possible to test the contact for all pins (of different devices) which are connected to thesame net simultaneously (parallel testing). This note investigates this possibility and the diagnosiscapabilities.

92

H.2 Theory

I D! CD

a bFigure H.2: Diode model

c

I

............................., V..t. X

R : Rk In~ :.... : """11

: .:- :... '. ::....

L- ..L. ••••••••••••••••••••••••••••••

Figure H.3: Contact test diagram model

The model used for the (pn junction) diode, figure H.2a, is seen in figure H.2b (see also [7J page140). The voltage across the diode is measured static. Therefore, the model can be simplified tofigure H.2c. The resistor T s models the series resistance contributed by the neutral (ohmic) regionson either side of the junction.

The measuring diagram, figure H.4 (next section) can be modeled according to figure H.3. Theresistor R g models the internal resistor of the current supply source and the resistors R1 ..R",. modelthe internal resistors at the device (IC) boundary [27J and the Ts of the diode in question. Thefollowing equations hold,

Therefore,

,see figure H.3 (H.l)

93

(H.2)

This equation can be rewritten to (n-t open connections),

t1+ Lx..R.v: - k=l

x - t

L i.k=l

In case of ideal diodes (all parameters are identical for all diodes):

IRVx =VT+­

t

(H.3)

(HA)

where VT is the forward biased threshold voltage [7].

As noted in the previous section each pin (protection diode) is injected with approximately 10pA.For example, the internal pin resistor of a 74HCT4020 is at least lOOn [27]. If two input pins (bothon the same net) are checked for connection simultaneously, the following holds (ideal, I=20pA,UT=600mV):

Both disconnected

One connected and one disconnected

Vx = very large

(2IlXIOO)

Vx =600 + T mV = 602mV

Both connected Vx = 600 + (~) mV = 601mV2

From this example can be concluded that detection could be very difficult with respect to the smallchange in V", (i.e. one connected and one disconnected versus both connected). Moreover, variationin the voltage drop across the forward biased diodes and the variation in the value of the internalpin resistors can make it even impossible to distinct between connected and disconnected pinswhich are tested on the same net simultaneously. The usability of this method can be proven bymeasuring the forward voltage variation of several protection diodes for several injected currentvalues, see next section. If the difference between the forward voltage variation per diode forconstant injected current and the forward voltage variation per injected current for the samediode is to small, then no distinction can be made between connected and disconnected pins (twoor more pins are tested).

H.3 Measurements and verification

If two or more pins of several devices are connected to each other (that is, on the same net) thenthe injected current must be several times higher than the injected current used to forward biasthe diode of one pin. When one or more of these pins are open (disconnected from the net) thenthe injected current must flow through the rest of the diodes (connected pins). This increasesthe forward voltage across these diodes. So, the prove of the usability of parallel contact testing(multiple open detection) lays in the difference between the variation in the forward voltage perpin (constant inject current) and the variation in the forward voltage per injected current value(the same pin/diode), see previous section. If this difference is to small then no detection anddiagnostic possibilities will exist.

Two arbitrary identical CMOS circuits (HEF4050B [23]) have been selected. The forward voltagedrop across both pin-diodes (see figure H.1) of all pins were measured for several injected currentvalues. The two measuring diagrams (pin-VDD diode and Vss-pin diode) are shown in figure HA­The results of these measurements are displayed at the end of this note (table H.l, ICl, andtable H.2, IC2). From these tables can be concluded that the forward voltage of the diodes ranges

94

Vdd

+'------'-_4_----1 Vss

Measuring diagram

Vss-pin diode

+

VssMeasuring diagram

pin-Vdd diode

Figure H.4: Measuring diagrams

between 450 and 650mV for the current range 10 to 70f-LA. The variation between the forwardvoltage of the diodes per injected current value ranges between 10 to 50mV (the Vss-VDD naturaldiode is not taken into account because this diode is implicit tested by the I/O pin contact tests).

Table H.3 shows the relation between the variation of the forward voltage for all pins (injectedcurrent value constant, column) and the variation of the forward voltage for the different injectedcurrent values (pin constant, row). The similarity between the variation of the forward voltage perpin and the variation per injected current value shows that it is not possible to apply the contacttest parallel, no distinction can be made between connected and disconnected pins on the samenet (no detection capabilities).

H.4 Solution

•............................................................................................................;

Vdd

pIn

Vss

...-...- I

II C····················

--ICI IC2

- I ..-.......-

:.....:

ICn

............. : ................................

Figure H.5: Proposed solution

From the results obtained from the measurements can be concluded that it is possible to checkthe connection between a single device and its interface to the environment, see also [14, 15].However, it is not possible to check the connections on the same net between several devices andtheir interface to the environment (I/O pins) simultaneously. No distinction can be made betweennone or several open connections, hence the detection and diagnosis are not possible. The solution

95

to this problem is to split the positive power supply line, such that each device has its own positivepower supply line. In this way the connect test can be done for each device and pin separately, seefigure R.5. There is one test restrain to this solution: there must exist a natural or a protectiondiode between VDD and the I/O pin for each pin which is to be tested. If there is no natural or aprotection diode then the connection/contact to that pin can not be checked with this method.

H.5 Tables

Table H.I Forward voltage of the protection/natural diodes for several forwardcurrents (10, 20 and 'lOp-A). First test chip: HEF4050B, non-inv buffer.

Pin Pin Voltage diode Voltage diodeNo Description pin-VD D (V) Vss-pin (V)

10 20 70 10 20 70

1 VD D 0.50 0.52 0.552 01 0.54 0.55 0.58 0.55 0.57 0.603 II 0.58 0.60 0.654 02 0.54 0.54 0.57 0.55 0.57 0.605 12 0.58 0.60 0.656 03 0.54 0.54 0.57 0.55 0.56 0.607 13 0.58 0.60 0.658 Vss 0.49 0.50 0.549 14 0.58 0.60 0.6510 04 0.53 0.54 0.57 0.55 0.57 0.6011 15 0.58 0.60 0.6512 05 0.53 0.54 0.58 0.55 0.56 0.6013 n.c.14 16 0.58 0.60 0.6515 06 0.52 0.54 0.58 0.55 0.56 0.6016 n.c.

n Maxlmum voltage ~U variation ~

II between all pins 0.05 0.05 0.04 0.08 0.080.10 II

between all I/O pins 0.02 0.01 0.01 0.03 0.04 0.05

Remarks:

1. The deviation in the current values is ±11hp,A and the deviation in the voltagevalues is ±5mV.

2. There is an input protection diode between the pins and Vss only. Therefor, onlythe results from the Vss-pin diode can be used for the connect test. The diodesof the output are the natural diodes.

96

Table H.2 Forward voltage of the protection/natural diodes for several forwardcurrents (10, 20 and 70/.LA) Second test chip: HEF4050B, non-inv buffer.

Pin Pin Voltage diode Voltage diodeNo Description pin-VDD (V) Vss-pin (V)

10 20 70 10 20 70

1 VDD 0.50 0.52 0.552 01 0.54 0.56 0.59 0.55 0.57 0.603 11 0.58 0.60 0.654 02 0.54 0.56 0.59 0.55 0.57 0.605 12 0.58 0.60 0.656 03 0.54 0.56 0.59 0.55 0.56 0.607 13 0.58 0.60 0.658 Vss 0.50 0.52 0.559 14 0.58 0.60 0.6510 04 0.54 0.56 0.59 0.55 0.57 0.6011 15 0.58 0.60 0.6512 05 0.54 0.56 0.59 0.55 0.56 0.6013 n.c.14 16 0.58 0.60 0.6515 06 0.54 0.56 0.59 0.55 0.56 0.6016 n.c.

n MaxImum voltage ~U variation U

II between all pins 0.04 0.04 0.04 0.08 0.080.10 II

between all I/O pins 0.00 0.00 0.00 0.03 0.04 0.05

Remarks:

1. The deviation in the current values is ±11hILA and the deviation in the voltagevalues is ±5mV.

2. There is an input protection diode between the pins and Vss only. Therefor, onlythe results from the Vss-pin diode can be used for the connect test. The diodesof the output are the natural diodes.

97

Table H.3 Difference between the forward voltage of the protection/natural forseveral forward currents (10, 20 and 70JLA). Both test chips: HEF4050B.

Pin Pin Voltage diode pin-VDD Voltage diode Vss-pin Maximum voltageNo Description of the first chip (V) of the second chip (V) variation (V)

10 20 70 10 20 70 10-20 10-70 20-70

1 VDD 0.50 0.52 0.55 0.50 0.52 0.55 0.02 0.05 0.032 01 0.55 0.57 0.60 0.55 0.57 0.60 0.02 0.05 0.033 I1 0.58 0.60 0.65 0.58 0.60 0.65 0.02 0.07 0.054 02 0.55 0.57 0.60 0.55 0.57 0.60 0.02 0.05 0.035 12 0.58 0.60 0.65 0.58 0.60 0.65 0.02 0.07 0.056 03 0.55 0.56 0.60 0.55 0.56 0.60 0.01 0.05 0.047 13 0.58 0.60 0.65 0.58 0.60 0.65 0.02 0.07 0.058 Vss9 14 0.58 0.60 0.65 0.58 0.60 0.65 0.02 0.07 0.0510 04 0.55 0.57 0.60 0.55 0.57 0.60 0.02 0.05 0.0311 15 0.58 0.60 0.65 0.58 0.60 0.65 0.02 0.07 0.0512 05 0.55 0.56 0.60 0.55 0.56 0.60 0.01 0.05 0.0413 n.c.14 16 0.58 0.60 0.65 0.58 0.60 0.65 0.02 0.07 0.0515 06 0.55 0.56 0.60 0.55 0.56 0.60 0.01 0.05 0.0416 n.c.

II between all pins 0.08 0.08 0.1011

0.08 0.08 0.10 0.02 0.07 0.05

IIbetween all I/O pins 0.03 0.04 0.05 0.03 0.04 0.05 0.02 0.07 0.05

n Maxlmum voltage ~U variation ~

Remarks:

1. The deviation in the current values is ±11hJLA and the deviation in the voltagevalues is ±5mV.

2. There is an input protection diode between the pins and Vss only. Therefor, onlythe results from the Vss-pin diode can be used for the connect test. The diodesof the output are the natural diodes.

3. The results of both (identical) chips are almost equal.

4. The variation between the voltage per pin is almost equal to the variation betweenthe voltage per current value.

98