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Efficient Analytical Efficient Analytical Determination of the SEU-Determination of the SEU-

induced Pulse Shapeinduced Pulse Shape

Rajesh GargRajesh GargSunil P. KhatriSunil P. Khatri

Department of ECEDepartment of ECETexas A&M UniversityTexas A&M UniversityCollege Station, TXCollege Station, TX

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Radiation Particle StrikeRadiation Particle Strike What is a radiation particle strike?What is a radiation particle strike?

Neutron, proton and heavy cosmic ionsNeutron, proton and heavy cosmic ions Ions strike diffusion regionsIons strike diffusion regions Deposit chargeDeposit charge Results in a voltage spikeResults in a voltage spike Can result in a logical error – Can result in a logical error –

Single Event Upset Single Event Upset (SEU) or (SEU) or Soft ErrorsSoft Errors

Radiation particle strike is Radiation particle strike is modeled by a current pulsemodeled by a current pulse asas

wherewhere: Q is the amount of charge deposited: Q is the amount of charge deposited is the collection time constantis the collection time constant is the ion track establishment constantis the ion track establishment constant

)()(

)( //

tt

seu eeQti

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OutlineOutline IntroductionIntroduction Previous WorkPrevious Work ApproachApproach

Classification of Radiation Particle StrikesClassification of Radiation Particle Strikes Our ModelOur Model

Experimental ResultsExperimental Results ConclusionsConclusions

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IntroductionIntroduction Modern VLSI DesignsModern VLSI Designs

Vulnerable to noise effects- crosstalk, SEU, etcVulnerable to noise effects- crosstalk, SEU, etc

Single Event Upsets Single Event Upsets (SEUs) or Soft Errors(SEUs) or Soft Errors Troublesome for both memories and combinational logicTroublesome for both memories and combinational logic Becoming increasingly problematic even for terrestrial Becoming increasingly problematic even for terrestrial

designsdesigns

Applications demand reliable systemsApplications demand reliable systems Need Need to efficiently to efficiently design design radiation tolerant circuitsradiation tolerant circuits Selectively harden Selectively harden sensitive gates in a circuitssensitive gates in a circuits

Gate which significantly contribute to soft error failure rate of Gate which significantly contribute to soft error failure rate of circuitcircuit

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IntroductionIntroduction 3 masking factors determine sensitivity of gates3 masking factors determine sensitivity of gates

Logical, temporal and electrical maskingLogical, temporal and electrical masking Logical and temporal can be obtained Logical and temporal can be obtained without without

electrical simulationselectrical simulations Electrical masking Electrical masking needneed electrical simulations electrical simulations

Depends upon on the electrical properties of all gatesDepends upon on the electrical properties of all gates on sensitized path from gate to primary outputs (POs) on sensitized path from gate to primary outputs (POs)

Important to Important to considerconsider these factors for efficient these factors for efficient circuit hardeningcircuit hardening Need Need efficient analysis efficient analysis andand simulation simulation approachesapproaches

Analyze circuits Analyze circuits earlyearly in design flow in design flow Based on the results of the analysis, we can efficiently Based on the results of the analysis, we can efficiently

achieve required tolerance while minimizing overheadsachieve required tolerance while minimizing overheads

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SEU Simulation and AnalysisSEU Simulation and Analysis Electrical masking effects can be determined by Electrical masking effects can be determined by

SPICE SPICE based simulation of SEU eventsbased simulation of SEU events Most accurate circuit simulation possible Most accurate circuit simulation possible Computationally Computationally expensiveexpensive Too many scenarios required to be simulatedToo many scenarios required to be simulated

Amount of charge dumpedAmount of charge dumped State of circuit inputsState of circuit inputs Need to simulate all nodes in a circuitNeed to simulate all nodes in a circuit

Hence we Hence we needneed an efficient and accurate an efficient and accurate approach to determine the shape of the radiation approach to determine the shape of the radiation induced voltage glitch induced voltage glitch

This is the focus of this talkThis is the focus of this talk

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Previous WorkPrevious Work Device-level simulationDevice-level simulation:: Dodd et. al 1994, etc Dodd et. al 1994, etc

Accurate but very time consumingAccurate but very time consuming Not helpful for circuit hardeningNot helpful for circuit hardening

Logic-level simulation:Logic-level simulation: Cha et. al 1996 Cha et. al 1996 Abstract transient faults by logic-level modelsAbstract transient faults by logic-level models Gate-level timing simulators are usedGate-level timing simulators are used Highly inaccurateHighly inaccurate

Circuit-level simulation:Circuit-level simulation: Intermediate between device and logic level simulationIntermediate between device and logic level simulation However, this is still very time consuming since a large However, this is still very time consuming since a large

number of scenarios need to be modelednumber of scenarios need to be modeled

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Previous WorkPrevious Work Shih et. al 1992Shih et. al 1992 solve transistor non-linear differential solve transistor non-linear differential

equation using infinite power seriesequation using infinite power series Computationally expensiveComputationally expensive

Dahlgren et. al 1995Dahlgren et. al 1995 presented switch level simulator presented switch level simulator Electrical simulations are performed to obtain the pulse width of a voltage Electrical simulations are performed to obtain the pulse width of a voltage

glitch for given R and C values of a gateglitch for given R and C values of a gate Pulse width for other R and C values are obtained using linear relationship Pulse width for other R and C values are obtained using linear relationship

between the obtained pulse width and the newbetween the obtained pulse width and the newR and C valuesR and C values

Cannot be used Cannot be used for different values of for different values of QQ Mohanram 2005Mohanram 2005 reports a closed form model for SEU reports a closed form model for SEU

induced transient simulation for combinational circuitsinduced transient simulation for combinational circuits Linear RC gate model is usedLinear RC gate model is used IgnoresIgnores the contribution of the contribution of in in iiseuseu(t) – w(t) – we found that this results in e found that this results in 40% 40%

root mean square percentage errorroot mean square percentage error in voltage glitch in voltage glitch Both these factors result in Both these factors result in higher inaccuracy. higher inaccuracy. Our approach has a Our approach has a 4.5% error 4.5% error

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ObjectiveObjective Develop an Develop an analytical model analytical model for waveform of a for waveform of a

radiation-induced voltage glitch in combinational radiation-induced voltage glitch in combinational circuitscircuits Closed form analytical expression Closed form analytical expression for the for the pulse shape pulse shape

of voltage glitchof voltage glitch Accurate and efficientAccurate and efficient Applicable to Applicable to

Any logic gate Any logic gate Different gate sizes Different gate sizes Different gate loadingDifferent gate loading

IncorporatesIncorporates the contribution of the the contribution of the time constant time constant Can be Can be easily integrated easily integrated in a design flowin a design flow Can be used with a glitch propagation tool to Can be used with a glitch propagation tool to evaluateevaluate

the effect (at the circuit Primary Outputs) of a radiation the effect (at the circuit Primary Outputs) of a radiation strike at any internal gate strike at any internal gate GG

So we can find (and harden) sensitive gates in a So we can find (and harden) sensitive gates in a designdesign

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Our ApproachOur Approach Consider a radiation particle strike at the output of INV1Consider a radiation particle strike at the output of INV1

Implemented using 65nm PTM with VDD=1VImplemented using 65nm PTM with VDD=1V Radiation strike: Radiation strike: QQ=150fC, =150fC, =150ps & =150ps & =50ps=50ps

Models Radiation Particle Strike M1 in Linear

M2 in Cutoff

M1 in Saturation

M2 in Cutoff

M1 in Saturation

M2 in SaturationM1 and M2 operate in different regions during radiation-induced transients

We estimate the radiation-induced voltage waveform by modeling these regions

INV1 cannot be modeled accurately by a linear RC model (as was done in several previous approaches)

M1 in Saturation

M2 in Saturation

M2’s Drain-Bulk diode is ON

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Classification of Radiation StrikeClassification of Radiation Strike INV1 can operate in INV1 can operate in 4 different cases 4 different cases

depending upon voltage glitch magnitude depending upon voltage glitch magnitude VVGM GM

((=V=Vaa))

Case 1: Case 1: VVGM GM ≥≥ VDD + 0.6V VDD + 0.6V Case 2: VDD+|VCase 2: VDD+|VTPTP| | ≤≤ VVGM GM < VDD + 0.6V< VDD + 0.6V Case 3: 0.5Case 3: 0.5**VDD VDD ≤≤VVGM GM <<VDD+|VVDD+|VTPTP|| Case 4: Case 4: VVGM GM < < 0.50.5**VDDVDD

Different analytical models are applicable to differentDifferent analytical models are applicable to differentcases to compute pulse waveform of the voltage glitchcases to compute pulse waveform of the voltage glitch

Use Case 2 equations to estimate the shape

of voltage glitch

Model OverviewModel OverviewGiven a gate G, its input

state, the gates in the fanoutof G and Q, and

Determine the value of VGM using gate current model for

Vdsat ≤ Va ≤ VDD – V|TP|

If Case==4No voltage glitch

Yes No Use Case 3 equations to estimate the shape

of voltage glitch

Cell library data Iout(Vin,VDS)for VGS=1 and 0, CG and CD

If Case==3

Determine the value of VGM using gate current model for

Va ≥ VDD – V|TP|

Yes

If Case==2YesNoUse Case 1 equations

to estimate the shape of voltage glitch

No

Integrate Equation 1 from

(0, 0) to (Vdsat, T1sat)

with

If VGM > 0.5*VDD then there is a glitch

Load current model of INV with input at VDDLoad current model of INV with input at VDD

Differential equation for radiation induced voltage transient Differential equation for radiation induced voltage transient at output of INV1at output of INV1

(1)(1)

Again integrate Equation 1 with initial condition (Vdsat, T1sat) and with DS

VDS VKKI a 43

Now VGM = Va(TVGM)

If 0.5*VDD ≤ VGM < VDD + |VTP| then Case 3 is applicable otherwise need to resolve between Case 1 and Case 2 13

Obtain TVGM by differentiating Va(t) and

solving dVa(t)/dt = 0

Voltage Glitch Magnitude (Voltage Glitch Magnitude (VVGMGM))

t

Va(t)Green Known

Yellow Unknown

nDSVDS RVI a /

T1sat

Vdsat

Solve for T1sat TVGM

VGM

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Derivation for Case 3 Derivation for Case 3 For Case 3: For Case 3: 0.5*VDD ≤ V0.5*VDD ≤ VGMGM < VDD + |V < VDD + |VTPTP|| PMOS transistor never turns ONPMOS transistor never turns ON Already know voltageAlready know voltage

expressions for time intervalsexpressions for time intervals((00 , ,T1T1satsat) ) and (and (T1T1satsat , ,T2T2satsat))

(1)(1)

t

Va(t) Green Known

Yellow Unknown

T1sat

Vdsat

TVGM

VGM

T2sat

Solve for T2sat

Integrate Equation 1 from

with (Vdsat, T2sat) as initial

condition with nDSVDS RVI a /

Now, the voltage expression is available for t = T2sat to infinity also

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Resolving Between Cases 1 and 2Resolving Between Cases 1 and 2 VVGMGM > VDD + |V > VDD + |VTPTP|| Need to re-compute VNeed to re-compute VGMGM to resolve to resolve

between Cases 1 and 2between Cases 1 and 2 Find Find T1T1PP when when

Va(t) = VDD + V|TP|

t

Va(t)Green Known

Yellow Unknown

T1sat

Vdsat

TVGM

VGM

VDD + |VTP|

T1P

Solve for T1P

Integrate Equation 1 from

with (VDD+V|TP|, T1P) as

initial condition with DSVDS VKKI a 65

Obtain TVGM by differentiating Va(t) and

solving dVa(t)/dt = 0

Now VGM = Va(TVGM)

If VDD + V|TP| ≤ VGM <VDD + 0.6 then Case 2 is applicable otherwise Case 1 is applicable*Details can be found in the paper

Derivation for Case 2Derivation for Case 2 For Case 2: For Case 2: VDD + VVDD + V|TP| |TP| ≤ V≤ VGMGM < VDD + 0.6 < VDD + 0.6 Diode never turns ONDiode never turns ON Already know voltage expressions Already know voltage expressions

for time intervals (for time intervals (00 , ,T1T1satsat),), ((T1T1satsat , ,T1T1PP) and () and (T1T1PP , ,T2T2PP))

Solve for Solve for T2T2PP

Also known for (Also known for (T2T2PP, , T2T2satsat)) Solve for Solve for T2T2satsat

Now integrate Equation 1 with Now integrate Equation 1 with initial condition (initial condition (VVdsatdsat, , T2T2satsat) similar ) similar to Case 3to Case 3

Va(t)

T1sat

Vdsat

TVGM

VGM

VDD + |VTP|

T1P

Green Known

Yellow Unknown

tT2P

Solve for T2P

Integrate Equation 1 from

with (VDD+V|TP|, T1P) as

initial condition with DSVDS VKKI a 43

T2sat

Solve for T2sat

Derivation for Case 1Derivation for Case 1 For Case 1: For Case 1: VVGM GM ≥ VDD + 0.6V ≥ VDD + 0.6V

Diode turns ON and clamps the node voltageDiode turns ON and clamps the node voltageto VDD + 0.6Vto VDD + 0.6V

Derivation is similar to Case 2Derivation is similar to Case 2

For (For (T1T1PP, , T2T2PP) the voltage expression is modified ) the voltage expression is modified to to min(VDD + 0.6, Vmin(VDD + 0.6, Vaa(t))(t))

Voltage expression for other time intervals are Voltage expression for other time intervals are samesame as that of Case 2 as that of Case 2

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Experimental ResultsExperimental Results Implemented our model in Implemented our model in PerlPerl Applied our model to INV, NAND2 and NOR3Applied our model to INV, NAND2 and NOR3

Using 65nm PTM model card with VDD=1VUsing 65nm PTM model card with VDD=1V Characterized each gate for Characterized each gate for IIDSDS, , CCGG and and CCDD

For each of these gates, we applied our modelFor each of these gates, we applied our model For different values of For different values of QQ, , and and

Different gate sizes and loadsDifferent gate sizes and loads Our model is Our model is ~275X faster ~275X faster compared to SPICEcompared to SPICE

Results could be Results could be improvedimproved if implemented in a compiled if implemented in a compiled languagelanguage

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Experimental ResultsExperimental Results

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Experimental ResultsExperimental Results Root mean square percentage (RMSP) error for 3X gates Root mean square percentage (RMSP) error for 3X gates

for for QQ=150fC, =150fC, =150ps and =150ps and = 50ps= 50ps

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Experimental ResultsExperimental Results RMSP error averaged over all possible input states for RMSP error averaged over all possible input states for

different gate sizes for different gate sizes for QQ=150fC, =150fC, =150ps and =150ps and = 50ps= 50ps

Average RMSP error of our model is Average RMSP error of our model is 4.5%4.5% Much lower than Much lower than 40% error 40% error of the model by Mohanram 2005of the model by Mohanram 2005

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ConclusionConclusion We presented an analytical model to We presented an analytical model to estimate the estimate the

shape shape of the radiation-induced voltage glitchof the radiation-induced voltage glitch Can be used with glitch propagation tools to estimate Can be used with glitch propagation tools to estimate

the voltage glitch at POsthe voltage glitch at POs Based on this, sensitive gates can be identified and Based on this, sensitive gates can be identified and

hardened to improve the radiation tolerance of the hardened to improve the radiation tolerance of the designdesign

This can be done early in the design cycleThis can be done early in the design cycle Our model is Our model is accurateaccurate and and efficientefficient

RMSP error is 5% RMSP error is 5% compared to SPICEcompared to SPICE Our method is Our method is 275X faster 275X faster than SPICEthan SPICE

Our model gains accuracyOur model gains accuracy By using the load current model (and avoiding a linear By using the load current model (and avoiding a linear

RC model for the gate)RC model for the gate) By including the contribution of By including the contribution of

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Thank YouThank You