Microelectronics Reliability xxx (2015) xxx–xxx

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Microelectronics Reliability

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Effect of source and drain asymmetry on hot carrier degradation in verticalnanowire MOSFETs

Jae Hoon Lee a, Jin-Woo Han b, Chong Gun Yu a, Jong Tae Park a,⁎a Department of Electronics Engineering, Incheon National University, #119 Academi-Ro Yoonsu-Gu, Incheon 406-772, South Koreab NASA Ames Research Center, Moffett Field, CA 94035, USA

⁎ Corresponding author.E-mail address: jtpark@incheon.ac.kr (J.T. Park).

http://dx.doi.org/10.1016/j.microrel.2015.06.0620026-2714/© 2015 Published by Elsevier Ltd.

Please cite this article as: J.H. Lee, et al., Effecelectronics Reliability (2015), http://dx.doi.o

a b s t r a c t

a r t i c l e i n f o

Article history:Received 19 May 2015Received in revised form 18 June 2015Accepted 18 June 2015Available online xxxx

Keywords:Vertical MOSFETHot carrier degradationAsymmetry source/drain

Effects of source and drain (S/D) asymmetry on hot carrier degradation in vertical nanowire MOSFETs have beeninvestigated with different nanowire radiuses. The S/D asymmetry causes different degree of hot carrier degra-dations between forward and reverse stresses. The actual stress voltage applied to the channel as a result of par-asitic resistance and gate to junction overlap length is attributed to the cause of the asymmetric degradation. Thenarrower nanowire also suffers from worse hot carrier effects due to current crowding and geometric effects.

© 2015 Published by Elsevier Ltd.

1. Introduction

Due to the excellent short channel effect immunity and theimproved device performances, silicon nanowire MOSFET is gener-ally considered as one of the most promising candidates for nextgeneration CMOS technology [1–3]. There are two nanowiredevices based on nanowire orientation: namely, lateral type andvertical or pillar type. As well known, a vertical MOSFET isolatesthe pillar body from the substrate and has much smaller footprintthan the lateral one [4,5]. Since the vertical MOSFETs have advan-tages of occupying lowest silicon area and high device density,recently they have received with considerable attention for appli-cation of nonvolatile memory and stacked surrounding gate mem-ory [6,7]. However, due to two different ion implantation to form abottom source and a top drain region, a vertical MOSFET has differ-ent source and drain resistances (RS and RD), which results in theasymmetric characteristics. The device performances and reliabili-ty including, drive current, transconductance, cut-off frequency,and hot carrier degradation, depend on the source and drain resis-tance [8,9]. Therefore, it is of interest to investigate the effect of ex-trinsic asymmetry on hot carrier degradation in vertical MOSFETs.In previous work [10], the effects of graded channel doping profilesin vertical MOSFET and gate-drain/source overlap effects in asym-metric MOSFET on the hot carrier degradation have been reported.There has so far no experimental study to understand the effectsof extrinsic asymmetry on hot carrier degradation in verticalMOSFETs.

t of source and drain asymmrg/10.1016/j.microrel.2015.06

In this work, we investigated the hot carrier degradation in thevertical nanowire MOSFET under forward and reverse stress conditionsand with different nanowire radius (RW).

2. Transistor details

Vertical nanowire MOSFETs fabricated on p-type bulk wafer werestudied. Phosphorus (1 MeV/5E14 cm-2) was implanted vertically at7 tilt to form the source. Boron (120 KeV/8E13 cm-2) was implantedfor p-channel and arsenide (80 KeV/3E15 cm-2) and phosphorus (50KeV/5E14 cm-2) were co-implanted vertically at 7 tilt to form thedrain. Arsenide was introduced to form an abrupt junction neardrain for increasing hot carrier injection in the flash memory. Sincea high energy arsenide implant to the source causes damage intothe crystal, phosphorus was implanted to form the source and alow energy arsenide implant was selectively conducted to form thedrain. After activation of the dopants, Si etching was carried toform vertical pillars. The exposed Si pillars with a height of 450 nmwere obtained after deposition and planarization of high densityplasma SiO2. Tunneling oxide of 5 nm, Si3N4 of 6 nm and blockingoxide of 8 nm were grown and deposited, sequentially. The metalof Ti/TiN/W (20/10/150 nm) was deposited for the gate electrodeand patterned to form vertical MOSFET. Fig. 1(a) and (b) show aschematic view and doping concentration profile along the channellength of tested vertical MOSFET. A SEM image in Fig. 1(c) shows aconical shape of pillar in vertical MOSFET. The tested device showsasymmetric doping concentration profile in the source and drainand result, lead to the different RS and RD. Since there is no highenergy/high current implant equipment, the maximum dose of thehigh energy equipment is limited by the tool itself. If the multiple

etry on hot carrier degradation in vertical nanowire MOSFETs, Micro-.062

Fig. 1. Schematic view (a) and doping profile along the channel length (b) of testedvertical MOSFET.

Fig. 3. GIDL current characteristics of RW = 565 nm in the forward and the reversemeasurement.

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implants are repeated to increase doping concentration of thesource, the significant crystal damage is introduced. Therefore,asymmetrical doping concentration of source and drain for the verti-cal transistor is usual. The test devices also have the lightly dopeddrain extension and the Gaussian doping concentration profile inthe channel region. The gate length was 250 nm and RW rangedfrom 85 nm to 565 nm. In order to characterize hot carrier degrada-tion, we used stress VDS and stress VGS -VTH were 4.0 V and 4.0 V,respectively.

3. Results and discussion

The asymmetric characteristics of vertical MOSFET were ob-served from the measured transfer curve at VDS = 0.1 V as shownin Fig. 2 by S/D swapping. The ON current in the forward measure-ment is larger than that in the reverse measurement at the sameVGS. In case of vertical MOSFET where RS tends to be larger thanRD, ON-current in the reverse measurement is expected to be largerthan that in the forward measurement due to the source side seriesresistance. However, the contradictory result is observed. The firstreason is the high injection of electrons from the source to thechannel in the forward measurement. Since the doping concentra-tion of the source is lower than that of the drain, the potential bar-rier in forward is lower than that in reverse. As result, the electronscan easily be injected from the source into the channel region. The

Fig. 2. A plot of the transfer curves of RW = 125 nm in the forward and the reversemeasurements.

Please cite this article as: J.H. Lee, et al., Effect of source and drain asymmelectronics Reliability (2015), http://dx.doi.org/10.1016/j.microrel.2015.06

larger OFF leakage current in the forward measurement than thatin the reverse measurement supports the higher thermionic injec-tion due to the low potential barrier. The second reason is less-overlap region formed between the gate and the drain due to thegate recess below the drain junction. The less-overlap at the drainregion is verified from that the larger GIDL (Gate Induced DrainLeakage) current in the reverse measurement than that in theforward measurement as shown in Fig. 3. The less-overlap at thedrain region was not intentionally made, but it may be formed bythe process. As the vertical gate length is not readily controlled,we did not pay much effort to align the junction and the edge ofthe gate. A conical shape of a pillar inherited from the processmay be the third reason for the increased ON current in the forwardmeasurement.

In order to investigate the asymmetry of the source and the drain onhot carrier degradation, the measured output characteristics underforward and reverse stress conditions were shown in Fig. 4. The deviceswere stressed at VDS = 4.0 V and VGS -VTH = 4.0 V for 60 min. Thedevice degradation is more severe in forward stress than in reversestress. The reasons will be discussed in the last section.

Fig. 5 shows a plot of hot carrier induced drain current degradationin saturation region (ΔIDS/IDS) as a function of RWunder forward and re-verse stress. The devices were stressed at VDS = 4.0 V and VGS -VTH =4.0 V for 60 min. It is worth to noting that the device degradationunder both forward and reverse stress conditions is increased as RW de-creases. According to the previous report [11,12], hot carrier degrada-tion in multiple gate MOSFETs has been shown either decrease orincrease with decreasing fin width. It has also been reported that hotcarrier degradation has been increased for narrow diameter devices ingate all around twin silicon nanowire field effect transistor due to theincreased vertical electric field at nanowire surface [13].

Fig. 4. Output characteristics before and after forward and the reverse stress.

etry on hot carrier degradation in vertical nanowire MOSFETs, Micro-.062

Fig. 5. A plot of ΔIDS/IDS as a function of RW.

Fig. 7. IDS, RS and RD as a function of RW.

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In order to investigate the cause of ΔIDS/IDS with different stressmodes and RW, the actual stress biases that effective to the intrinsicpart of the devices have been calculated from the extraction of seriesresistances, RS and RD. It has been known that the device degradationdepends more on RS than RD [8]. To explore further the effect of theasymmetric characteristics of RS and RD on hot carrier degradation, weshould extract RS and RD separately. In this work, the Avalanche HotSource Method (AHSM) has been used to extract RS and RD separately[14]. Since the characterizations of AHSM were performed on otherdevices, the stress induced damages under the measurement of AHSMcould be avoided in hot carrier characterization. The measurementswere made in more than 3 samples in each size device, and the valueswere averaged. The deviations of RS and RD for each device were lessthan 4%.

Fig. 6 shows a plot of RD extraction of RW = 245 nm using AHSM inthe forwardmeasurement. Since RS and RD become almost independenton VGS at high VDS, we can assume that RS and RD are independent of VGS

Fig. 6. RD extraction using AHSM in the forward mode measurement.

Please cite this article as: J.H. Lee, et al., Effect of source and drain asymmelectronics Reliability (2015), http://dx.doi.org/10.1016/j.microrel.2015.06

at the stress condition of VDS = 4.5 V. Using AHSM, the extracted RD ofRW = 245 nm measurement is 794 Ω. The extracted RS and RD withdifferent RW have been plotted in Fig. 7. RS is larger than RD becausethe doping concentration of the source is less than that of the drain.As the nanowire is narrowed, RS and RD and their difference are in-creased. The drain current increases in both forward and reverse mea-surements as RW increases.

In order to investigate the dependence of asymmetry of device struc-ture and RW onΔIDS/IDS, the actual voltages stressed to the intrinsic partof the device with different RW have been calculated using followingequations

VGS: int ¼ VGS−RS � IDSVDS: int ¼ VDS− RS þ RDð Þ � IDS:

Fig. 8 shows a plot of effective stress voltage of VGS.int -VTH andVDS.int under both forward and reverse stress conditions as a functionof RW. The effective stress voltages of VGS.int -VTH and VDS.int underreverse condition are larger than those under forward stress condition.Although the channel field at the less-overlap lightly doped drain regiondecreases under forward stress, this result provides the answer to thequestion why the hot carrier degradation is more significant under thereverse stress condition than under forward stress condition. It isremarkable to note that VGS.int -VTH and VDS.int are independent ofRW. Therefore, from the extracted actual stress voltages we can't solelyexplain why hot carrier degradation becomes more significant as RW

decreases.Currently there is an interesting report on a simple geometric effect

explaining that the gate oxide captures more effectively the scatteredhot carriers for narrower fin devices [15]. To investigate further thecause of increased hot carrier degradationwithdecreasingRW, the effect

Fig. 8. Actual voltages stressed to the intrinsic part of transistor under both forward andreverse stresses.

etry on hot carrier degradation in vertical nanowire MOSFETs, Micro-.062

Fig. 9. Drain current density as a function of RW.

Fig. 10. Correlation between ΔIDS/IDS and S/V.

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of nanowire surface area on the device degradation has been explored.Fig. 9 shows the normalized drain current by nanowire surface areawith different RW. The increase of IDS/S with decreasing RW may beattributed to the current crowding effect. About 5% variation of draincurrent was observed due to the variation of process and RW. A plot ofΔIDS/IDS and the surface-to-volume ratio of nanowires (S/V) have beenplotted in Fig. 10. It is remarkable to note that there is some correlationbetween ΔIDS/IDS and S/V curves. Therefore, we can conclude that thedevice with the larger surface area can collect the more hot carriersand a result, the device degradation is more significant as previousreport [15].

Finally, we can speculate from hot carrier effects as a function of RW

that the programming speed of flashmemorywill be fasterwith smallerRW in a vertical MOSFET with SONOS gate stack. However, when a highVGS and VDS are used for reading the state “0”, SONO gate stack close to

Please cite this article as: J.H. Lee, et al., Effect of source and drain asymmelectronics Reliability (2015), http://dx.doi.org/10.1016/j.microrel.2015.06

the drain is trapped by hot electrons. This leads to a degradation of thesense margin of flash memory, especially for small RW devices.

4. Conclusion

An asymmetric hot carrier effect in vertical MOSFET was investigat-ed. The reverse mode stress was found to result in more severe hotcarrier degradation than the forward mode stress. This phenomenon isexplained by the actual stress voltage applied to the channel due tothe S/D asymmetric doping concentration and conical shape of pillar.The more significant hot carrier degradation with decreasing the nano-wire radius may be attributed to the current crowding and geometriceffects.

Acknowledgment

This work was supported by the Incheon National UniversityResearch Grant in 2015.

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