Introduction From Diode to Transistor Two terminals to three
terminals Use of the voltage between two terminals to control the
current flowing in the third terminal Two types of Transistors
MOSFETs: metal oxide semiconductor field effect transistors
(chapter 4) BJT: bipolar junction transistor (chapter 5) Topics
Physical structure and operations Terminal characteristics Circuit
models Basic circuit applications: amplifier and logic inverter
4
Slide 5
Metal-Oxide- Semiconductor (MOS) Field- Effect Transistors
(MOSFETs) MOSFET Most important component in modern digital
integrated circuits Used in microprocessors Used in computer memory
5
Slide 6
4.1 Device Structure and Physical Operation ( Physical
structure of the enhancement-type NMOS transistor) 6 perspective
view cross-section Typically L = 0.1 to 3 m, W = 0.2 to 100 m, and
the thickness of the oxide layer (t ox ) is in the range of 2 to 50
nm.
Slide 7
4.1 Device Structure and Physical Operation 4.1.1 Device
Structure Source (S) connects to Body (B), Drain (D) is at a
positive voltage relative to S, two pn junctions are cut off
Substrate: no effect on device operation 3 terminals device Source
and drain can be interchanged 7
Slide 8
4.1.4 Applying a Small VDS 8 An NMOS transistor with v GS (gate
voltage) > V t (threshold voltage)and with a small v DS applied.
The device acts as a resistance whose value is determined by v GS.
Specifically, the channel conductance is proportional to v GS V t
and thus i D is proportional to ( v GS V t ) v DS. Note that the
depletion region is not shown (for simplicity).
Slide 9
4.1.4 Applying a Small VDS (Cont.) 9 The i D (drain current) v
DS (drain voltage) characteristics of the MOSFET in the above slide
when the voltage applied between drain and source, v DS, (drain
source) is kept small. The device operates as a linear resistor
whose value is controlled by v GS (gate source).
Slide 10
4.1.5 Operation as V DS I s Increased 10 Operation of the
enhancement NMOS transistor as v DS is increased. The induced
channel acquires a tapered shape, and its resistance increases as v
DS is increased. Here, v GS is kept constant at a value > V
t.
Slide 11
4.1.6 Derivation of the I D V DS relationship 11 The drain
current i D versus the drain-to-source voltage v DS for an
enhancement-type NMOS transistor operated with v GS > V t.
Slide 12
4.1.8 Complementary MOS or CMOS 12 Cross-section of a CMOS
integrated circuit. Note that the PMOS transistor is formed in a
separate n-type region, known as an n well. Another arrangement is
also possible in which an n-type body is used and the n device is
formed in a p well.
Slide 13
13 Symbols for enhancement-type MOSFETs
Slide 14
4.2 Current-Voltage Characteristics 4.2.1 Circuit Symbol 14 (a)
Circuit symbol for the n-channel enhancement-type MOSFET. (b)
Modified circuit symbol with an arrowhead on the source terminal to
distinguish it from the drain and to indicate device polarity
(i.e., n channel). (c) Simplified circuit symbol to be used when
the source is connected to the body or when the effect of the body
on device operation is unimportant.
Slide 15
4.2.2 The I D v DS Characteristics There are three distinct
regions of operation: The cut-off region The triode region The
saturation region 15
Slide 16
4.2.2 The I D v DS Characteristics (Cont.) 16 (a) An n-channel
enhancement-type MOSFET with v GS and v DS applied and with the
normal directions of current flow indicated. (b) The i D v DS
characteristics for a device with k n (W/L) = 1.0 mA/V 2.
Slide 17
4.2.2 The I D v DS Characteristics (Cont.) 17 Cut off
region
Slide 18
4.2.2 The I D v DS Characteristics (Cont.) 18 Triode region The
N-channel enhancement-type MOSFET Operates in the triode region
when v GS is greater than V i and the drain voltage is lower than
the gate voltage by at least V t.
Slide 19
Triode Region Example 19
Slide 20
Triode Region Example (Cont.) 20
Slide 21
Problem 4.7c&d 21
Slide 22
Problem 4.7c&d (Cont.) 22 ox for silicon = 3.45x10 -11
Slide 23
4.2.2 The I D v DS Characteristics (Cont.) 23 Saturation region
The N-channel enhancement-type MOSFET Operates in the saturation
region when v GS is greater than V i and the drain voltage does not
fall below the gate voltage by more than V t.
Slide 24
Saturation Region Example 24
Slide 25
4.2.2 The I D v DS Characteristics (Cont.) 25 Saturation region
The i D v GS characteristic for an enhancement-type NMOS transistor
in saturation (V t = 1 V, k n W/L = 1.0 mA/V 2 ).
Slide 26
4.2.2 The I D v DS Characteristics (Cont.) 26 Large-signal
equivalent-circuit model of an n-channel MOSFET operating in the
saturation region
Slide 27
4.2.3 Finite Output Resistance in Saturation 27 IDEAL: a change
v DS causes zero change in I D, which means infinite output
resistance Increasing v DS beyond v DSsat causes the channel
pinch-off point to move slightly away from the drain, thus reducing
the effective channel length (by L).
Slide 28
4.2.3 Finite Output Resistance in Saturation 28 Large-signal
equivalent circuit model of the n-channel MOSFET in saturation,
incorporating the output resistance r o. The output resistance
models the linear dependence of i D on v DS and is given by Eq.
(4.22). Eq. 4.22Eq. 4.24
Slide 29
4.3 MOSFET Circuit At DC 29
Slide 30
Example 4.2 30 Design the circuit of Fig. 4.20 so that the
transistor operates at I D =0.4mA and V D =+0.5V. The NMOS
transistor has V t =0.7V, n C ox =100 A/V 2, L = 1 m, and W=32 m.
Neglect the channel- length modulation effect (i.e. assume that
=0). RD= ?, RS = ?
Slide 31
Example 4.2 (Cont.) 31
Slide 32
Example 4.2 (Cont.) 32
Slide 33
Another Design Example 33 Figure 1
Slide 34
Example 4.4 34 Design the circuit in Fig. 4.22 to establish a
drain voltage of 0.1 V. What is the effective resistance between
drain and source at this operating point? Let Vt=1 V,
knW/L=1mA/V2.
Slide 35
Example 4.4 (Cont.) 35
Slide 36
Example 4.4 (Cont.) 36
Slide 37
Another Design Example 37 Figure 2 Assume saturation
Slide 38
Figure (c) 38 V 5 = -10 - ( - (2.5x10 3 )(2x10 -3 )) = - 10 + 5
= -5 V I D = 2 = ()(1)(V ov ) 2 ) (V ov ) 2 = 4 V ov = 2, However,
V ov = -2 V since pmos circuit V GS = V t + V ov = -2 -2 = - 4 Thus
V s = 4 V = V 4 Assume saturation
Slide 39
Figure (d) 39 I D = 2 = ()(1)(V ov ) 2 ) (V ov ) 2 = 4 V ov =
2, However, V ov = -2 V since pmos circuit V GS = V t + V ov = -2
-2 = - 4, V s = 4 V 6 = 10 4 = 6 V V 7 = 6 4 = 2 V
Slide 40
4.4 The MOSFET As An Amplifier and As A Switch 40
Slide 41
4.4.1 Large-signal Operation The Transfer Characteristic 41
Basic structure of the common-source amplifier Graphical
construction to determine the transfer characteristic of the
amplifier in (a). Common Source Amplifier (CS) To determine the
voltage transfer characteristic between v I and v O V I = v GS V O
= v DS = V DD - R D i D Graphically and analytically v DS = V DD -R
D i D i D = (V DD -v DS )/R D
Slide 42
4.4.2 Graphical Derivation of the Transfer Characteristic 42
Transfer characteristic showing operation as an amplifier biased at
point Q.
Slide 43
4.4.3 Operation As Switch 43
Slide 44
4.4.4 Operation as a Linear Amplifier 44 Two load lines and
corresponding bias points. Bias point Q 1 does not leave sufficient
room for positive signal swing at the drain (too close to V DD ).
Bias point Q 2 is too close to the boundary of the triode region
and might not allow for sufficient negative signal swing.
Slide 45
4.4.5 Analytical Expressions for the Transfer Characteristic 45
Cutoff-Region Segment, XA v I < V t, and v O = V DD
Slide 46
4.4.5 Analytical Expressions for the Transfer Characteristic
(Cont.) 46 Saturation-Region Segment, AQB A v = - 2 (V DD V OQ ) /
V OV = - (2V RD ) / V OV
Slide 47
Example 47
Slide 48
Example (Cont.) 48 A v = - 2 (V DD V OQ ) / V OV = - (2V RD ) /
V OV
Slide 49
4.4.5 Analytical Expressions for the Transfer Characteristic
(Cont.) 49 Triode-Region Segment, BC
Slide 50
4.5 Biasing In MOS Amplifier Circuits 50
Slide 51
4.5.1 Biasing by Fixing V GS 51 Most straightforward Device
dependent Temperature dependent The use of fixed bias (constant V
GS ) can result in a large variability in the value of I D. Devices
1 and 2 represent extremes among units of the same type.
Variability
Slide 52
4.5.2 Biasing by Fixing VG and Connecting a Resistance in the
Source 52 Reduced Variability Biasing using a fixed voltage at the
gate, VG, and a resistance in the source lead, RS: (a)basic
arrangement; (b)reduced variability in ID;
Slide 53
4.5.2 Biasing by Fixing VG and Connecting a Resistance in the
Source (Cont.) 53 Biasing using a fixed voltage at the gate, VG,
and a resistance in the source lead, RS: (c) practical
implementation using a single supply; (d) coupling of a signal
source to the gate using a capacitor CC1; (e) practical
implementation using two supplies.
Slide 54
Example 54 6 Bias current does not change
Slide 55
Example 55
Slide 56
4.5.3 Biasing Using a Drain-to-Gate Feedback Resistor 56
Biasing the MOSFET using a large drain-to-gate feedback resistance,
R G.
Slide 57
Problem 4.64b 57
Slide 58
4.5.4 Biasing Using a Constant-Current Source 58 Biasing the
MOSFET using a constant-current source I. Implementation of the
constant- current source I using a current mirror.
Slide 59
4.5.4 Biasing Using a Constant-Current Source (Cont.) 59
Slide 60
4.6 Small-Signal Operation And Models 60
Slide 61
4.6.1 The DC Bias Point 61 Set v gs to zero Conceptual circuit
utilized to study the operation of the MOSFET as a small-signal
amplifier.
Slide 62
4.6.2 The Signal Current in the Drain Terminal 62 Conceptual
circuit utilized to study the operation of the MOSFET as a
small-signal amplifier. VOVO i D = the instantaneous drain current
I D = the DC Bias Current To reduce nonlinear distortion, the input
signal should be kept small so that:
Slide 63
4.6.3 The Voltage Gain 63 Conceptual circuit utilized to study
the operation of the MOSFET as a small-signal amplifier.
Slide 64
4.6.4 Separating the DC Analysis and the Signal Analysis 64
Conceptual circuit utilized to study the operation of the MOSFET as
a small-signal amplifier.
Slide 65
4.6.5 Small Signal Equivalent-Circuit Models 65 neglecting the
dependence of i D on v DS in saturation (the channel- length
modulation effect) including the effect of channel- length
modulation, modeled by output resistance r o = |V A | /I D. V A =
1/ (where = the channel-length modulation effect) r 0 = 10K to
1000K
Slide 66
4.6.6 The Transconductance g m 66 In contrast, g m for a
bipolar junction transistor (BJT) is proportional to I D and is
independent of the physical size And geometry of the device.
Slide 67
Example 67
Slide 68
Example a 68 I D = (1/2) x 1 x (5 1) 2 2I D = 4 2 = 16 I D = 8
mA
Slide 69
Example b 69 G m = 1 x (5 1) = 4 mA/V
Slide 70
Example c 70 A V = - 4mA x 4K = -16 V/V
Slide 71
Example d 71 output resistance r o = |V A | /I D V A = 1/
(where = the channel-length modulation effect) r O = 1 / (0.01 x
8mA) = 1 / 0.08mA = 12.5 K A V = - 4mA x (4K || 12.5K) = - 3.03
V/V
Slide 72
4.6.7 The T Equivalent-Circuit Model 72 Development of the T
equivalent-circuit model for the MOSFET. For simplicity, r o has
been omitted but can be added between D and S in the T model of
(d).
Slide 73
4.6.7 The T Equivalent-Circuit Model (cont.) 73 The T model of
the MOSFET augmented with the drain-to-source resistance r o. An
alternative representation of the T model.
Slide 74
4.6.9 Summary Small Signal Parameters Transconductance: Output
Resistance: Small Signal Equivalent Circuit Models 74 Hybrid- model
T models
Slide 75
4.7 Single-Stage MOS Amplifiers 75
Slide 76
4.7.1 The Basic Structure 76 Basic structure of the circuit
used to realize single-stage discrete-circuit MOS amplifier
configurations
Slide 77
4.7.2 Characterizing Amplifiers 77
Slide 78
4.7.2 Characterizing Amplifiers (cont.) 78
Slide 79
4.7.2 Characterizing Amplifiers (cont.) 79
Slide 80
4.7.3 The Common-Source (CS) Amplifier 80
Slide 81
4.7.3 The Common-Source (CS) Amplifier (cont.) 81
Slide 82
4.7.3 The Common-Source (CS) Amplifier (cont.) 82
Slide 83
4.7.4 The Common-Source Amplifier with a Source Resistance 83
Common-source amplifier with a resistance R S in the source lead.
Small-signal equivalent circuit with r o neglected.
Slide 84
4.7.4 The Common-Source Amplifier with a Source Resistance
84
Slide 85
Problem 77 85
Slide 86
Problem 77a 86 a)V G = 15 x (5/15) = 5 V V S = 3I D = V GS = 5
- 3I D I D = (1/2)(2)(5 - 3I D - 1) 2 0 = 16 -25I D + 9I D 2 I D =
1 mA V GS = 5 - 3I D = 2 V V D = 15 (7.5K x 1mA) = 7.5 V
Slide 87
Problem 77b 87 G m = 2 I D / V OV = (2 x 1) /(2 1) = 2 mA r O =
V A / I D = 100/1mA = 100K
Slide 88
Problem 77c 88
Slide 89
Problem 77d 89 x x
Slide 90
4.7.5 The Common-Gate (CG) Amplifier 90
Slide 91
4.7.5 The Common-Gate (CG) Amplifier (cont.) 91
Slide 92
4.7.6 The Common-Drain (CD) or Source- Follower Amplifier
92
Slide 93
4.7.6 The Common-Drain (CD) or Source- Follower Amplifier
(cont.) 93
