Effect of Annealing Ambient on Structural and Electrical Properties

of Ge Metal-Oxide-Semiconductor Capacitors

with Pt Gate Electrode and HfO2 Gate Dielectric

S. V. Jagadeesh Chandra1, Myung-Il Jeong1, Yun-Chang Park2,Jong-Won Yoon3 and Chel-Jong Choi1;4;*

1School of Semiconductor and Chemical Engineering, Semiconductor Physics Research Center (SPRC),Chonbuk National University, Jeonju 561-756, Korea2Measurement and Analysis Division, National Nanofab Center (NNFC), Daejeon 305-343, Korea3Department of Advanced Materials Science and Engineering, Dankook University, Cheongan 330-714, Korea4Department of BIN Fusion Technology, Chonbuk National University, Jeonju 561-756, Korea

We fabricated Ge metal-oxide-semiconductor (MOS) devices with Pt/HfO2 gate stacks and investigated the effect of thermal treatment ontheir structural and electrical properties in oxygen (O2) and forming gas (FG) environments. The annealing ambient dependency of the structuraland electrical properties of Ge MOS devices was directly compared to that of Si MOS devices. For both Ge and Si MOS devices, the thermaltreatment process led to a decrease in accumulation capacitance regardless of the annealing ambient. The interfacial layer (IL) at the HfO2/Gestack was much thinner than the HfO2/Si stack. O2 annealing resulted in the improvement of the HfO2 interfacial quality of Ge and Si MOSdevices, although the improvement of the Ge devices was greater than that of the Si devices. FG annealing was much more effective in thereduction of interface state density (Dit) in Si devices than in Ge devices. A negligible IL at a HfO2/Ge stack could be a main cause of degradedelectrical performance of a Ge device with FG annealing. [doi:10.2320/matertrans.M2010324]

(Received September 16, 2010; Accepted October 22, 2010; Published December 8, 2010)

Keywords: metal-oxide-semiconductor (MOS), germanium, silicon, HfO2, annealing, interfacial layer, density of interface state

1. Introduction

Extensive studies have been conducted on high dielectricconstant (high-k) materials as possible replacements forconventional SiO2 gate dielectric material in complementarymetal-oxide-semiconductor (CMOS) devices, which requirean equivalent oxide thickness (EOT) of below �1 nm.Among various high-k materials, HfO2 has been identifiedas a promising candidate to meet the scaling requirementsstated in the International Technology Roadmap for Semi-conductors.1) There is a need for alternate channel materialsthat can enhance channel mobility beyond the physical limitsof Si-based CMOS devices without sacrificing the produc-tivity required by semiconductor device manufacturers.Recently, Ge has received considerable attention as apromising CMOS-compatible channel material because ofits higher intrinsic carrier mobility of hole and electron overSi.2–4) The benefits of employing high-k gate dielectrics onGe include a thin interfacial layer (IL) between the high-kmaterial and the Ge, and the possibility of hiding theimperfect properties of native oxide in capacitance scal-ing.5,6) This implies that there are many chances for us tochallenge the integration of a Ge channel and high-k gatedielectric with a negligible effect on low-permittivity IL.Many studies in this area have been performed over the lastdecade. Until now, researchers have focused on the simpledeposition of high-k material on chemically cleaned Ge,various substrate pre-depositional treatments, and post-deposition annealing for various ambient conditions. Forexample, Kamata et al.7) and Chen et al.8) reported no IL at

ZrO2/Ge and TiLaO/Ge interfaces, respectively. Sun et al.9)

noted various Ge-related defects in the electrical properties ofa HfO2/Ge stack, including flatband voltage (VFB) instabilitywith large hysteresis and high leakage currents due to oxygenvacancy and interstitial sites in Ge, respectively. A thermally-evaporated HfO2 layer, which was deposited directly on Gesubstrates, showed low leakage current characteristics andpoor interface quality with low accumulation capacitancevalues upon N2 annealing.

10) Wu et al.11) and Zhang et al.12)

observed severe Ge incorporation into HfO2 occurring duringthermal annealing due to a haphazard IL between the HfO2

and Ge. Chen et al.13) described degraded electrical proper-ties on Ge substrates with different high-k gate dielectricssuch as HfO2 and Al2O3 without an intentional IL afterannealing in a forming gas (FG) ambient at �500�C, due todirect contact between the high-k material and the Ge.Oshima et al.14) observed higher leakage currents in FG-annealed devices at 370�C than in as-grown devices whenHfO2 was deposited directly on a chemically cleaned Gesubstrate. Cheng et al.15) experimentally observed that theout-diffusion of Ge during thermal treatment in NH3 ambientled to degraded leakage current characteristics. In contrast,Gao et al.16) demonstrated highly reliable electrical prop-erties such as low leakage currents and excellent C-Vcharacteristics with an AlN IL between the HfO2 gatedielectric and Ge substrate, rather than Ge-surface nitrida-tion, due to the high thermal stability of the AlN IL. Maedaet al.17) obtained good interfacial quality with a low interfacestate density (Dit) level of 1:8� 1011 cm�2eV�1 for HfO2

deposited on Ge3N4/Ge stacks. In this study, we investigatedthe effect of O2 and FG annealing on the electrical structuralproperties of Ge metal-oxide-semiconductor (MOS) devices*Corresponding author, E-mail: cjchoi@chonbuk.ac.kr

Materials Transactions, Vol. 52, No. 1 (2011) pp. 118 to 123#2011 The Japan Institute of Metals EXPRESS REGULAR ARTICLE

with Pt/HfO2 gate stacks, and demonstrated their comparisonwith Si MOS devices. We show that O2 annealing is effectivein the improvement of HfO2 interfacial quality withnegligible frequency dispersion, as shown by the capaci-tance-voltage (C-V) curves of Ge MOS devices. We alsoshow that FG-annealed Ge MOS devices exhibited degrada-tion in electrical performance (such as high Dit and leakagecurrent levels) due to the absence of an IL between the HfO2

gate dielectric and Ge substrate.

2. Experimental Procedures

MOS capacitors were fabricated on p-type Ge (100) waferswith doping concentrations of 2� 1018 cm�3. After remov-ing the native Ge oxide by dipping the sample in a diluted HFsolution (1 : 50) for 1min, HfO2 films with a thickness of6 nm were deposited on the wafers using the atomic layerdeposition (ALD) process by means of sequential pulses ofHfCl4 and H2O sources at a wafer temperature of 300�C. Fora gate electrode, 50 nm-thick Pt films were sputter-depositedat room temperature, followed by patterning with thedimensions of 300� 300 mm2 using lift-off lithography.Then, post-metallization annealing was carried out at500�C for 30min in O2 and FG (H2: 5% and N2: 95%)environments. For comparison, Pt/HfO2 gate stacks wereformed on p-type Si (100) wafers with a doping concentrationof 5� 1015 cm�3 using the same fabrication conditions. Forconvenience, the MOS devices fabricated on Ge and Siwafers are hereafter referred to as ‘‘Ge devices’’ and ‘‘Sidevices’’, respectively. The microstructures of the fabricateddevices were examined using a field emission transmissionelectron microscope (FETEM, Tecnai G2 F30 S-Twin) atNational Nanofab Center (NNFC). C-V and conductance-voltage (G-V) characteristics were measured at 100KHzusing a precision LCR meter (HP4284A). Current-voltage(I-V) characteristics were determined using a precisionsemiconductor parameter analyzer (Agilent 4156C).

3. Results and Discussion

Figure 1 shows the C-V and G-V characteristics of the Geand Si devices. For both devices, the thermal treatmentprocess led to a decrease in accumulation capacitance.However, the decrease in the accumulation capacitance of theO2-annealed Ge-device was insignificant compared to theO2-annealed Si-device. This result could be associated with arelatively large increase in the thickness of the IL beneath theHfO2 in Si devices, which will be described subsequently. Anoticeable bump in the C-V curves in the depletion region isclearly visible for the Ge and Si devices without thermaltreatments. This could be related to HfO2 interfacial quality,such as Dit related to Si or Ge dangling bonds at thesubstrate/gate dielectric interface.18) However, after the O2

annealing process, the bump in the C-V curve of the Gedevice (Fig. 1(a)) almost disappeared, whereas the Si device(Fig. 1(b)) showed a small bump. This implies that O2

annealing is not particularly effective in improving theinterface quality of an HfO2/Si stack. Furthermore, the FG-annealed Ge device exhibited a strange C-V plot, showing arapid decrease in accumulation capacitance. This could be

due to the presence of large leakage currents caused by directcontact between the HfO2 gate dielectric and Ge substratewithout any separation, which will be discussed subsequent-ly. In contrast, the FG-annealed Si device showed a preciseC-V plot without any bump in the depletion region, resultingin an improvement in the interface quality of the HfO2/Sistack. This was also confirmed through G-V measurementsof the Ge and Si devices before and after annealing in O2

and FG environments, as shown in Figs. 1(c) and 1(d). Forboth Ge and Si devices, annealing in an O2 environmentdemonstrated a dramatic decrease in the maximum values ofconductance near VFB, suggesting a reduction of the Dit level.The Dit values of O2-annealed Ge and Si devices, extractedfrom the G-V characteristics at 10 kHz (not shown here) assuggested by Yang et al.,19) were measured to be�1:5� 1012

and �2:9� 1012 cm�2eV�1, respectively. The value of theDit level in the O2-annealed Si devices was nearly two timeshigher than that of the O2-annealed Ge devices. This impliesthat O2 annealing played a more effective role in thepassivation of Ge dangling bonds than in the passivation of Sidangling bonds. In meticulous, the dominant interface (Pb)centers at the HfO2/Ge stack were physically removed by O2

annealing, resulting in the reduction of the Dit level.20) In

addition, the presence of excessive diffused oxygen species atthe SiO2/Si interface could depassivate the interface (Pbo)centers and produced additional interface traps in the Sidevices.21,22) Moreover, we note that the FG-annealed Gedevice shows a significant peak (see inset of Fig. 1(c)),whereas the same was disappeared in the FG-annealedSi device (Fig. 1(d)). This indicates that FG annealing isineffective in the passivation of Ge dangling bonds at agate dielectric/Ge interface caused by containing a similarnegative charge on Ge dangling bonds and interstitialhydrogen in the Ge.23) However, Si dangling bonds werepassivated more effectively at an HfO2/Si interface byforming Si-H bonds during FG annealing.24) For example,it is not possible to determine the Dit level in FG-annealedGe devices due to strange C-V behavior, whereas the Dit

value in FG-annealed Si devices was calculated to be 4:1�1011 cm�2eV�1.

Figure 2 shows frequency dispersion in the C-V curvesmeasured at a multiple high frequency range. We note thatfrequency dispersion in the accumulation region of the O2-annealed Ge devices is negligible (Fig. 2(a)), whereas severefrequency dispersion is shown in the C-V plots of the FG-annealed Ge devices (Fig. 2(b)). In particular, thermallytreated Si devices exhibited low frequency dispersionirrespective of the annealing ambient. It has been previouslyreported that defects in the dielectric layer and/or Dit couldbe primary sources of frequency dispersion.25–27) However,considering that the Dit level in FG-annealed Si devices isapproximately one order of magnitude lower than that of O2-annealed Ge devices, the imperfection of HfO2 gate dielectricmaterial such as oxygen vacancies is believed to be a maincause of the annealing ambient dependency of frequencydispersion in the C-V curves in present devices. Thus, O2

annealing suppresses the formation of oxygen vacancies inthe HfO2 layer due to the oxygen-enriched region duringthermal treatment. However, annealing in an FG environmentmay not reduce oxygen vacancies in the HfO2 layer due to

Effect of Annealing Ambient on Structural and Electrical Properties of Ge Metal-Oxide-Semiconductor Capacitors 119

a lack of sufficient oxygen in the surroundings, leading tofrequency dispersion.

Figure 3 shows cross-sectional high-resolution electronmicroscope (HREM) images taken from the Ge and Sidevices before and after thermal treatments. The thicknessof the as-deposited HfO2 films on the Ge and Si substrateswas measured to be 6 nm (Figs. 3(a) and 3(d)). However,the thickness of the HfO2 in Ge devices increased up to�6:5 nm after the O2 and FG annealing processes (Figs. 3(b)and 3(c)). No such variations were monitored in the HfO2

thickness in the Si devices regardless of the annealingambient (Figs. 3(e) and 3(f)). It is unclear whether there wasan increase in the HfO2 thickness for the thermally-treatedGe devices. However, this could be associated with theformation of HfGeOx driven by significant diffusion of Geinto HfO2.

28) Namely, the diffusion of substrate atoms intoHfO2 from the interface of the HfO2/substrate led to thevolumetric expansion of the HfO2 layer.

29) Such an increasein HfO2 thickness seems to be a main cause for the small

decrease in the accumulation capacitance value of O2-annealed Ge devices, even for a thin IL, compared to as-deposited Ge devices. Thus, the thickness of the IL betweenthe HfO2 and Ge was changed by annealing in O2 and FGenvironments due to the nonuniform oxidation behavior ofthe Ge.11,30) For Ge devices, thermal treatment resulted ina reduction in the thickness of the IL. For example, thethicknesses of the IL in as-deposited and O2-annealed Gedevices were measured to be 0.6 and 0.4 nm, respectively.However, the IL thickness in the FG-annealed Ge device wasalmost negligible. Such a reduction of IL thickness in Gedevices during thermal treatment could be associated withthe easy decomposition of GeO2 into volatile GeO, and thedesorption of GeO at low temperatures (�450�C).7) Insuffi-cient oxygen in the vicinity during thermal treatment couldbe responsible for the negligible IL thickness in FG-annealedGe devices, implying direct contact between the HfO2 andGe. Moreover, despite the natural characteristics of Ge oxide,a supply of sufficient oxygen in the HfO2/Ge interface allows

Fig. 1 C-V characteristics of (a) Ge and (b) Si devices before and after annealing in O2 and FG environments at 500�C. G-V

characteristics of (c) Ge and (d) Si devices before and after annealing in O2 and FG environments at 500�C.

120 S. V. J. Chandra, M.-I. Jeong, Y.-C. Park, J.-W. Yoon and C.-J. Choi

Fig. 2 C-V curves measured at multiple frequencies for Ge devices after (a) O2 and (b) FG annealing at 500�C, and for Si devices after

(c) O2 and (d) FG annealing at 500�C.

Fig. 3 HREM images taken from Ge devices (a) before and after (b) O2 and (c) FG annealing at 500�C and from Si devices (d) before and

after (e) O2 and (f) FG annealing at 500�C.

Effect of Annealing Ambient on Structural and Electrical Properties of Ge Metal-Oxide-Semiconductor Capacitors 121

the presence of a thin IL in the O2-annealed Ge device, whichscreens the HfO2 from the Ge substrate. In contrast, Sidevices show pronounced ILs with thickness of 1.0, 2.1,and 1.8 nm for as-deposited, O2-annealed, and FG-annealeddevices, respectively. It has been reported that uponannealing at temperatures above �780�C, SiO2 decomposesfollowed by transformation into volatile SiO.31) This impliesthat for Si devices, annealing at 500�C leads to enhanced ILthickness.

Figure 4 shows I-V characteristics of Ge and Si devicesafter O2 and FG annealing. The open and closed symbolsrepresent Ge and Si devices, respectively. For the O2-annealed Ge device, the leakage current density measuredat a gate bias of 1V was found to be �3� 10�8 Acm�2.However, we note that the FG-annealed Ge device showedseverely degraded I-V characteristics. For example, theleakage current density of the FG-annealed Ge deviceincreased significantly, up to �0:9� 101 Acm�2 at a gatebias of 1V. Such an extremely high leakage current densitycould be associated with direct contact between the HfO2 andGe substrate as shown in Fig. 3(c). Similar behavior wasobserved by Abe et al.,32) who showed that dipoles at theHfO2/Si interface caused by direct contact between HfO2

and Si led to high leakage currents (on the order of �10�1 to100 Acm�2). Thus, the existence of an IL between the HfO2

and substrate is required to reliably attain low leakagecurrents. This is clearly confirmed by the I-V characteristicsof the Si devices with thermal treatments in O2 and FGenvironments. For example, the leakage current densities ofO2 and FG-annealed Si devices with relatively thick ILs weremeasured to be �3� 10�9 and �4� 10�9 Acm�2, respec-tively.

4. Conclusion

We investigated the effects of the O2 and FG annealingambient on the structural and electrical properties of Ge

devices, and showed a comparison with Si devices. Thereduction in the accumulation capacitance of O2-annealed Gedevices was relatively insignificant when compared to O2-annealed Si devices due to the insignificant variations in ILthickness at the HfO2/Ge stack. The interface quality of O2-annealed Ge devices was improved with a possible passiva-tion of the interface centers at the HfO2/Ge stack. On theother hand, FG-annealed Ge devices exhibited the severedegradation of HfO2 interface quality due to the similarcharge on Ge dangling bonds and interstitial hydrogen in Ge.O2-annealed Ge devices showed relatively insignificantfrequency dispersion compared to O2-annealed and FG-annealed Si devices. This could be attributed in part to thereduction of Dit, and to the apparent suppression of oxygenvacancies in the HfO2 layer. A negligible IL between theHfO2 and Ge led to the degradation of electrical performancein FG-annealed Ge devices caused by the formation ofdipoles at the HfO2/Ge interface. However, O2 annealingproduced low leakage currents, which is comparable to thethermally-treated Si devices. Therefore, we suggest that O2

annealing produces reliable electrical properties such asnegligible frequency dispersion, low Dit, and an acceptableleakage current level without an intentional interfacial layeron the Ge substrate.

Acknowledgement

This work was financially supported by the ‘‘SupportProgram for the Advancement of National Research Facili-ties and Equipments (NFEC-2007-11-048017)’’ of the Min-istry of Education, Science and Technology, Republic ofKorea, and was partially supported by the ‘‘IT R&D program(KI002083, Next-Generation Substrate Technology for HighPerformance Semiconductor Devices)’’ of the Ministry ofKnowledge Economy, Republic of Korea.

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