1 1 1 University of Michigan 1 1

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EECS 598: Integrating Emerging Technologies with Computer Architecture

Lecture 4: Memory Technologies

Instructor: Ron Dreslinski

Winter 2016

2 2 2 University of Michigan

Traditional Memory Choices §  Flip-Flops

§  SRAM

§  DRAM

§  FLASH

§  Hard-Disk Drive (HDD)

§ Magnetic Tape

3 3 3 University of Michigan

Group Discussion – Memory System Review §  Break into groups and discuss the traditional memory technologies and how they

relate to these factors: §  Can it be used in synthesis+P&R? §  Can it be integrated onto the processor die? §  Relative speed to other technologies? §  Relative density to other technologies? § What purpose does it serve in the system (memory, cache, paged-device, etc.)? §  Is the data retained when powered off?

§ Memory Devices: §  Flip-Flops §  SRAM §  DRAM §  FLASH §  Hard-Disk Drive (HDD) § Magnetic Tape

NON-MOSFET BASED MEMORY Alex Rodriguez-Triana Terence Frederick April 21, 2008

OUTLINE

¢ MOSFET Based RAM Memory �  DRAM, SRAM, FLASH

¢ Problems with MOSFET Memory �  Scaling

¢ Alternative Memory �  MRAM �  FeRAM �  PCRAM

¢ Summary

HISTORY OF MOSFET MEMORY

¢ Concept goes back to the 1960s ¢ People were speculative

�  BJT was more advanced and faster �  Leakage current

¢ They were attractive �  Simple Processing �  Layout Advantages

¢  Leads to high-density integrated circuits

HISTORY OF MOSFET MEMORY

¢ SRAM were proposed �  six MOSFET’s per cell

¢ SRAM began to be used in the mid-70s

¢ DRAM patented in 1968 �  1 MOSFET, 1 Capacitor

¢ First commercial DRAM �  1971 by Intel

DYNAMIC RAM

¢ Most common type of RAM memory ¢ Arranged in a square array

�  one capacitor and transistor per cell

¢ Stores one bit per cell �  Recharging/Refreshing : capacitors lose their charge

¢ Rows: Word Lines ¢ Columns: Bit Lines

ADVANTAGES/DISADVANTAGES OF DRAM

¢ Advantages �  Cost �  Small

¢  1T & 1C vs. 6T for SRAM

�  Number of Read/Write Cycles ¢  > 10^15

¢ Disadvantages �  Slow

¢  Need to refresh

�  Volatile ¢  Data is lost when memory is not powered

STATIC RAM

¢ Memory cell uses flip-flop to store bit ¢ Requires 6 transistors

�  Each bit is stored on 4 transistors that form two inverters �  Two other transistors control the access to a cell during read and write

operations

¢ This storage cell has two stable states �  0 and 1

ADVANTAGES/DISADVANTAGES OF SRAM

¢ Advantages �  Performance better than DRAM

¢  Faster ¢  Less Power Hungry

�  Number of Read/Write Cycles ¢  > 10^15

¢ Disadvantages �  Cost

¢  More than DRAM

�  Volatile ¢  Data is lost when memory is not powered

FLASH MEMORY

¢  Invented by Dr. Fujio Masuoka at Toshiba in 1984 ¢ Stores information in an array of memory cells made from floating-

gate transistors ¢ Single-Level Cell Devices - each cell stores only one bit

ADVANTAGES/DISADVANTAGES OF FLASH

¢ Advantages �  Cost �  Non-Volatile

¢  Does not lose information when the power is off

�  Low Power �  Fast Erase

¢  Large blocks rather than one word at a time

¢ Disadvantages �  Number of Read/Write Cycles

¢  ~ 10^6

�  Slow Write ¢  Entire block must be read, word updated, then entire block written back

FUTURE OF MOSFET MEMORY

¢ Current memory technologies are nearing the end ¢ Main issue with MOSFET RAMs

�  Scalability

¢ Designers put more components onto each chip �  Width of the smallest features is shrinking

¢  130 nm in 2000 to 45 nm today

¢ Existing memory technologies will be good for several more generations �  Unlikely to make the transition to 22 nm (scheduled for 2011) or 16 nm

(2018)

¢ New types of technologies �  MRAM, FeRAM, PCRAM

MOSFET SCALING

¢ Late 1990s �  Scaling resulted in great improvement in MOSFET circuit operation

¢ Reasons for smaller MOSFETs �  Same functionality in a smaller area �  Reduces cost per chip

¢  Smaller ICs allow for more chips on a wafer ¢  Fab costs for wafer are relatively fixed

MOSFET SCALING

¢ Problems when scaling too small �  Slower chip speed

¢  Greater delay due to interconnects

�  Operational problems ¢  Higher sub-threshold, increased gate-oxide and junction leakage, lower

transconductance, heat production, and process variation

�  Simulation ¢  Difficult to predict what the final device will look like ¢  Modeling of physical processes ¢  Microscopic variations in structure due to the probabilistic nature of atomic

processes require statistical predictions

ALTERNATIVE TECHNOLOGIES

¢ Magnetic RAM (MRAM)

¢ Ferroelectric RAM (FeRAM)

¢ Phase Change RAM (PCRAM)

MAGNETORESISTIVE RAM

¢ Under development since the 1990s ¢ Data is stored by magnetic storage elements

�  Formed from two ferromagnetic plates

¢ Plates can hold a magnetic field �  Polarization doesn’t leak away with time like charge �  Less wear since switching states doesn’t involve movement of electron or

atoms

¢ One plates is a permanent magnet �  Set to a certain polarity �  Second plate’s field will change to match that of an external field

¢ A memory device is built from a grid of "cells"

4MB MRAM

¢  1st commercial available MRAM ¢ Based on 1T and 1 magnetic tunnel junction ¢  Isolates read and write path ¢ Separates programming components from the sense circuit

�  Improved performance

READ AND WRITE OF MRAM

¢ Read �  Current is passed

through the bit �  resistance of the

bit is sensed

¢ Write �  Current is passed through

the programming lines �  Induced magnetic field is created at

the junction, which the writable plate picks up

MRAM

¢ Cell works in a toggling mode �  Same direction

¢  Low resistance state (0)

�  Opposite direction ¢  High resistance state (1)

MRAM IN EMBEDDED SYSTEMS

¢  Inserted late in the SC fabrication process ¢ Low temperature

�  Compatible with CMOS processing

¢ Consolidate multiple MRAM into one �  highly reliable NVRAM �  Less complexity �  High performance RD/WR

ADVANTAGES/DISADVANTAGES OF MRAM ¢ Advantages

�  Non-volatile ¢  Does not require programming sequences or block erasing

�  Very fast RD/WR and unlimited endurance �  Simple device Architecture and easy software development

¢  Due to easy write and overwrite

¢ Disadvantages �  Scalability of magnetic domain?

¢  Might have the same problems as a transistor

�  Disturbance of neighboring cells when put close together ¢  Leads to false writes

�  High power needed to write

Ferroelectric RAM

¢ Borrows concepts from DRAM �  most popular design follows the 1T1C design concept �  similar/same write process

¢  write accomplished by applying charge that is stored in capacitor

¢ Similarity to Floating Gate Design �  1T design

¢ Also reminiscent of MRAM �  focuses on ferroelectric properties, whereas MRAM techniques often focus

on ferromagnetic properties �  both characteristics take form of hysteresis loop

Structure

¢  1T type �  Similar to normal transistor �  Identical to floating gate design

where floating gate is ferroelectric material

¢  1T1C type �  ferroelectric material serves ONLY

as capacitor

Advantages/Disadvantages of FeRAM

¢ Advantages �  lower power usage �  faster write speed �  greater number of rewrites �  already being mass-produced

¢ Disadvantages �  still more research to be done on reliability (i.e. high NRE cost) �  only applicable to a small niche

“Study of Phase Change Random Access Memory (PCRAM) at the Nano-Scale”

by R. Zhao, L.P. Shi, W.J. Wang, H.X. Yang, H.K. Lee, K.G. Lim, E.G. Yeo, E.K. Chua and T.C. Chong

Introduction

¢ RAM based on floating-gate design (i.e. Flash memory) will soon meet physical limitations �  interpoly tunneling �  intercell crosstalk

¢ Flash memory is the most prevalent non-volatile memory on the market �  a viable option must be found soon

¢  PCRAM may be that option

Fabrication/Design

¢  “Bybrid” process used to etch the layers �  Electronic Beam Lithography (EBL) �  Optical Lithography

¢  Electrodes made of TiW ¢  Dielectric is common SiO2 ¢  Phase Change material is Ge2Sb5Te2

¢  Feature size refers to contact between PC and bottom electrode

How it Works

¢ Unique Phase Change material has two states �  Crystalline state has low resistance and represents a stored ‘1’ �  Amorphous state has high resistance and represents a stored ‘0’

¢ To change bit from 1 to 0 (i.e. RESET), a relatively high voltage is applied for a short time such that the compound melts but is not able to recrystallize

¢ To change bit from 0 to 1 (i.e. SET), a lower voltage is applied for a longer time so that compound can crystallize

Advantages/Disadvantages of PCRAM

¢ Advantages �  great scalability �  fast for both reads and writes �  low current required to program

¢ Disadvantages �  as of yet, only in the research phase �  still limited read/write accesses (108)

Memory Device Technology

• Background on 3 type of NVM (STT, PCM, ReRAM)

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Comparison of emerging memory technologies Jeffrey Vetter, ORNL

Robert Schreiber, HP Labs Trevor Mudge, University of Michigan

Yuan Xie, Penn State University

SRAM DRAM eDRAM 2D NAND Flash

3D NAND Flash

PCRAM STTRAM

2D ReRAM 3D ReRAM

Data Retention N N N Y Y Y Y Y Y

Cell Size (F2) 50-200 4-6 19-26 2-5 <1 4-10 8-40 4 <1

Minimum F demonstrated (nm) 14 25 22 16 64 20 28 27 24

Read Time (ns) < 1 30 5 104 104 10-50 3-10 10-50 10-50

Write Time (ns) < 1 50 5 105 105 100-300 3-10 10-50 10-50

Number of Rewrites 1016 1016 1016 104-105 104-105 108-1010 1015 108-1012 108-1012

Read Power Low Low Low High High Low Medium Medium Medium

Write Power Low Low Low High High High Medium Medium Medium

Power (other than R/W) Leakage Refresh Refresh None None None None Sneak Sneak

Maturity

http://ft.ornl.gov/trac/blackcomb

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The memristor: 4th fundamental two terminal circuit element

Predicted 1971 Leon Chua U.C. Berkeley

Reduced to practice 2008 R. Stanley Williams

HP Laboratories

MEMRISTOR dφ = M dq

1971 Chua

Ohm 1827

1831 Faraday

Von Kleist 1745

RESISTOR dv = R di

CAPACITOR dq = C dv

INDUCTOR dφ = L di

i

v

q

φ

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Memristor - First Glance

•  The memristor is built on a Metal-Insulator-Metal (MIM) structure. •  Memristor can be switched between High Resistance State (HRS)

and Low Resistance State (LRS) by applying an external voltage across the cell.

•  Current, voltage relationship is non-linear

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Memristor Cell

Memristor switching device with low non-linearity

Selector with high non-linearity

Combination of a selector in series with memristor device

Ideally we want the memristor IV curve to be highly non-linear

Memristor

Selector

Memristor Cell

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Accessing Traditional Memory

•  2D grid of cells with a dedicated access switch in each cell

•  Easier to read/write to a cell

•  Low density but high read margin

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Traditional Memory vs. Memristor Crossbar

Cells being read or written

Row select signal to read or write a

row

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Traditional Memory vs. Memristor Crossbar

Access transistor isolates unnecessary

signal - But it increases cost

Cells being read or written

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Crossbar Memristor array

•  No access transistor à a dense crossbar array with a cell size of 4F2 •  You can lay transistors and circuits below the array

•  Maximum use of silicon area

Selected Cell

Half Selected Cell

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Memristor Operation

Row select signal to read or write a

row

Vdd/2 Vdd/2 Vdd/2 Vdd/2 Vdd/2 Vdd/2 Vdd/2

Vdd

Vdd/2

Vdd/2

Vdd/2

Vdd/2

0

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Memristor Operation

Half Selected Cells Leak Current

Vdd/2 Vdd/2 Vdd/2 Vdd/2 Vdd/2 Vdd/2 Vdd/2

Vdd

Vdd/2

Vdd/2

Vdd/2

Vdd/2

0

Non-linearity (Kr) helps reduce leakage current Kr = ILSR(@VSET) / ILSR(@VSET/2)

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Memristor Operation

Unselected cells shown in light blue will also get impacted

Vdd/2 Vdd/2 Vdd/2 Vdd/2 Vdd/2 Vdd/2 Vdd/2

Vdd

Vdd/2

Vdd/2

Vdd/2

Vdd/2

0

Non-linearity (Kr) helps reduce leakage current Kr = ILSR(@VSET) / ILSR(@VSET/2)

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Complex Tradeoffs in Crossbar

Enough voltage drop (for switching)

Avoid write disturbance

Enough ∆I (noise margin)

Write

Read V/2? V/3? Floating?

?

I? V

Array size

>1 bit?

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Complex Tradeoffs in Designing Memristor Crossbar

Enough voltage drop (for switching)

Avoid write disturbance

Enough ∆I (noise margin)

V/2?

V/3?

Floating?

?

I? V

selected cell

•  Design decisions are not obvious

•  What is the optimal array dimensions?

•  What is the right driving voltage?

•  What is the biasing voltage?

•  Tradeoff in writing/reading single bit vs.

multiple bits per array

Depending upon the delay/energy/area constraints, we can tune the array accordingly

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ReRAM/Memristor Microarchitecture and Design Space Exploarion

•  Design of Cross-point Metal-oxide ReRAM Emphasizing Reliability and Cost.", Dimin Niu, Cong Xu, Naveen Muralimanohar, Norm Jouppi, Yuan Xie, ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2013.

•  Understanding the Tradeoffs in MLC ReRAM Memory Design, Cong Xu, Dimin Niu, Naveen Muralimanohar, Norm Jouppi, Yuan Xie, Design Automation Conference (DAC), 2013.

TOWARDS AN EARLY DESIGN SPACE EXPLORATION TOOL SET FOR STT-RAM DESIGN

Philip Asare and Ben Melton

STT-RAM Overview: Advantages

¨  Everything volatile currently has ¤ High speed (SRAM) ¤ Density (DRAM)

¨  AND Everything non-volatile presents ¤ Non-volatility ¤  Low Power (Flash) ¤  Reliability (Hard-drive)

¨  On its own ¤ CMOS-compatible ¤ Good scalability potential (over tradition MRAM)

¨  Potential for use as universal memory

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STT-RAM Overview: Challenges

¨  Device-Level ¤  Tunneling Magneto-Resistance Ratio (TMR) ¤  Fabrication Issues

¨  Circuit-Level ¤ Current-sensing ¤ Variation

n  cell strength: reading difficulty n  sense amp: offset (especially at smaller nodes)

¤  Stochastic nature of MTJ ¨  Architecture-Level

¤  Read-write asymmetry in energy and delay ¤  Periphery components may dominate

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Understanding STT-RAM: Structures

Storage Element*

MTJ Resistance Characteristics*

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Bit Cell and Column

Array

* A. Nigam et al., “Delivering on the Promise of Universal Memory for Spin Torque Transfer RAM (STT-RAM)” International Symposium on Low-Power Electronics and Design (ISLPED), August 2011

Understanding STT-RAM: Read 51

(1)

(2) (1)

(1)  Decode address à select word (2)  Turn on sense amp à pre-charge BL (3)  Disable precharge à evaluate/read data (4)  Turn off sense amp (1)

(2)

(1) X

X X

(3) (4)

(2)

Understanding STT-RAM: Write 52

(1)

(1)

(1)  Decode address à select word (2)  Charge BL or SL to write (depends on value) (3)  Disable write transistors

(1)

(2) or X

(2)

(3)

(3)

X or (2)

(2) or X X or (2)