EE457Homework 18(not too long

Due:Instructor: G. Puvvada

in the wooden box outside EEB243

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The material which was not tested in the midterm is very importantfor the final exam. The final exam is supposed to be comprehensive.However, I will be less emphasizing topics such as CPU Performance(chapter #2) on the final.

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Part I (on CLAs)------------

Refer to you class notes. In this course, count "the' delay of anexclusive-OR gate- as two gate-delays. This is based on the SOP(sum of products) expression of s = {(a'). (b) + (a). (b')}implementation of the XOR gate which requires two AND gates inthe first level followed by an OR gate in the second level.We are not counting inverters as a level of gates. The actualVLSI design of an XOR gate does not use this SOP expressionand the delay may be less than 2 gate delay.

1.1 (a) Refer to the 16-bit adder on page 4-19 and calculate delayof the adder design. Is it 5 or 7 or 9 gate-delays? Explainhow you arrived at your answer.

(b) If you take four of these 16-bit adders and builda 64-bit adder using an additional level of carry-lookaheadlogic, what would be the delay of such a design.

(c) What would be the complexity of gates needed in the SOPimplementation of the carry-lookahead logic which canreceive eight pairs of p's and g's and also a carry-in (cO)and produce cl-c8? By complexity of gates, we ~ean thehighest fan-in (number of input pins) warranted for theAND gates and the highest fan-in warranted for the OR gatesto implement the design in 2-level AND-OR logic usingSOP (sum of products) expressions.

2 Refer to page 4-29 showing a tree of OR gates.Consider the evaluation of

B = A63 + A62 + . . . . . . + Al + ADUse 4-input OR gates only. What is the delay (in gate-delays)if you arrange OR gates in a linear cascade? What would bethe delay if you arrange in a tree fashion? You do not haveto draw any of the two arrangements.

Part II Question IV.1 from Final Summer 1993Part III Question 1 from Final Summer 1995Part IV Question 1 from Final Fall 1995 <== CANCELLEDPart V Question 1 from Final Spring 2000Part V1 Question 1.1 from Final Fall 2001======================================================:

(:;ii\~IV. Sot 5..-'1-+'),. :. f~ points) ~-+g+8+ i ': 2.4 ~\".

Page I ~/7 8&457 r~ Su'93

@\~3)EE457

Final Exam (40%)Summer 1995 Instructor: G. Puvvada

Date: Aug. 1, '95 Tues. GFS106Time: 3:30-5:45 PMName:

SSN: Total points: q 5( ~O 11::15 = perfect score)

1 ( G+6 , 'J points) 15mi"--

Unsigned and signed numbers:

1~1 Design a 4-bit comparator to compare two UNSIGNED numbers A (A3 A2 AlAD) and B (B3 82 BI BO) using a 4-bit adder-subtractor given below andadditional logic as needed.Hint Consider the overflow in unsigned subtraction as you would do inSL TU instruction implementation.

- -'3 A1. A\ ;. '."..8';:..&. ., ,,_.

- ~4~p-..-

8.$

8,(J AoA\8183, A~ 82.. A2.

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'Z.fl,

~~~ 11:

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CP

~b~ r-~ ,...LI..

11-. -i

--~]¥"'.". c. .t L~ ie.'.,t ~.

Cc.

A<B. A.>BfA B

EE457 Final Summer 95 /7

I.;il\~!)1.2 Design a 4-bit comparator to compare two SIGNED numbers X (X3 X2 Xl

XO) and Y (Y3 Y2 Yl YO) using a 4-bit adder-subtractor given below andadditional logic as needed.Hint: Consider the overflow in signed subtraction as you would do inSL T instruction implementation.

~4.~A\A3 A')..

8~..: \1B:~".. r'.'.BI.;.

'l'~ h

~,------.

E£ -f

"1"r..,;.-,

A"CB fA~B IA>&I

1().EE~7 Final Swnme: 95 - .,2' /7

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Spring 2000 EE4S7 Insttuctor: G. PuvvadaFinal Exam (40%) Date: May 8,2000 MondaySGM124

Name: Time: 2:00-~ P:.f- 4 : , 0 ~t.1

SSN: Totalnints: '"~- ---~--- - "--- (1O, score)

6+ ICot ~ 2D (Smt~1. ( points)

Basic computer arithmetic (c.rry-Look-Ah8d adder, inaementer, and d~enter design>:

1.1 An inaementer is a special case of an adder adding the constant 1 (ONE).Instead of using a full CLA adder for inaementation, a simplified inaementercan be designed as shown below. The ONE to be added can be conveyed at theCO ( carry-in) input. However we would like to consider CO as a variable.

Note: 5i = (Ai XOR Bi ) XOR Ci = (Ai XOR 0 ) XOR Ci = Ai XOR CiPi = Ai OR Bi = Ai OR 0 = Aigi = Ai AND Bi =AiANDO =0Ci = 1 if some earlier adder (FA) generates a carry and all

intermediate adders (F As) co-operate and propagate, the same.Since 8i is zero here, the Ci can only be true if there is acarry-in (CO) and all intermediate Pi are true.

1:N;;=::aii;,lii=i!~:~~ L A 2- A I A 0

a t ~ Iffice C C~ Pt Ps Ps

I ~I Sf

-~s"-

Vcc

lJj~op3 c3 p2 c2 p1 01 pO

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tt)

u

'I~

u

'.,..

tJ I p I New CLL INcl -

1.1.1 Write the boolean equations for Cl, C2, C3 produced by the NBW_CLL_INC.

1.1.2 What is the gate delay of the 4-bit incrementer. Note: Count an XORasa 2-gate delay device.

State how you arrived at the value.

EE457 Mnal Spring 2{XX) - 1 / ~

@Copyrlght Pwv8da 2000

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1.2 Similar to an incrementer, a decrementer is a special case of an adder adding theconstant -1 (MINUS ONE). In 2's complement 4-bit signed number system, aminus one is represented as 1111 (all ones). Design a simplified (area efficient,speed efficient) decrementer by simplifying a CLA adder adding 1111. Do notassume that the CO is a zero; treat it as a variable.

Note: Si = (Ai XOR Bi) XOR Ci = (Ai XOR 1 ) XOR Ci = Ai' XOR Ci = Ai XNOR Ci

Pi = Ai OR Bi = Ai OR 1 =

gi = Ai AND Hi = Ai AND 1 =

Ci = 1 if some earlier adder (FA) generates a carry and all

intermediate adders (F As) co-operate and propagate.Since all Pi are here, the Ci can be true if

1°A.A 2..

S3

:.c~~S1,..

0

u~92 c2 g1 c1 gO JcO

cO

-- rNew CLL DECI --

g3 c3

, I~

U

, ,c..a

U

II-

u

G:.

C:-, 1.2.1 Write boolean equations for C1, C2, C3, and for the group generate G produced\~~;J by the NBW_CLL_DEC in the above space.

1.2.2 Consider a 64-bit decrementer using three levels of the above CLL.

1.2.2.1 Number of NEW CLL DEC needed:- -1.2.2.2 Number of NEW BIT-CELL DEC needed:- -

I~-;\ 1.2.2.3 Delay of the 64-bit decrementer in gates:\~:.J Note: Count an XOR or an XNOR as a 2-gate delay device.

~1.2.2.4 The 64-bit decrementer is good to decrement

(unsigned numbers only / signed 2'5 oompL numbers only / both unsigned and signed)EE457 Final Spring 2OOJ - 2 / 1-

@Copyrt9ht Puvvada 2000

INAW Rit.~AII nEcl. ,,~

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rFall 2001 Instrfgctor: Gandhi Puvvada&~: 12/ 14/2001, FridayTke: 2:05 - 4:35PM THH

,

Total points: '0 5Perfect score: CIS I {OS

EE457Final Exam (35 Oft) ) _.J rc.to ~ bOC) k 1 Qjo UQ Y\C \(.~Name:

Student ill:

1 ( points) t S min.g q,( I--

Ripple carry adder (RCA), Carry Look-Ahead adder (CLA), delays:

1.1

~Delay of the 2-bit RCA (design #1 on the right)is gate delays.Delay of the 2-bit CLA (design #2 on the right) is

gate delays.

Delay of a 4-bit RCA isDelay of a 4-bit CLA is

gate delays.gate delays

Delay of the first 8-bit adder (design #3 below) isgates.

Delay of the second 8-bit adder (design #4 below) isgates.

EE451 Final Ewn - Pall 2001 1/12@Copyright2001 Gandhi Puvvada