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EE365 Adv. Digital Circuit Design Clarkson University Lecture #1 Course Outline Number Systems. Syllabus. No mid-course exams (only final exam) Design Problems heavily weighted Optional homeworks Quizzes (every few days) correspond to HWs Textbook: does everyone have it? - PowerPoint PPT Presentation
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EE365Adv. Digital Circuit Design
Clarkson University
Lecture #1
Course Outline
Number Systems
• No mid-course exams (only final exam)
• Design Problems heavily weighted
• Optional homeworks
• Quizzes (every few days) correspond to HWs
• Textbook: does everyone have it?
• Office Hours: where/when
• Contact information (phone, e-mail, AIM)
Rissacher EE365
Syllabus
Lect #1
www.clarkson.edu/class/ee365• Schedule
• Notes (suggest printing before class)
• Handouts
• Class Location (some will be in computer lab)
• Links
Rissacher EE365
Course Website
Lect #1
• Interrupt me at anytime for questions
• Discussions encouraged
• Grade not based on attendance
• Feel free to excuse yourself at any time (e.g., if you’re falling asleep go stretch your legs and buy a mountain dew, or leave after quiz is over)
• Bring scrap paper: I may give in-class practice problems
Rissacher EE365
Lecture Structure
Lect #1
• Heavily weighted
• May take some time, start early & use the weekends
• Will have at least one in-class help session for each project.
• Each project will require you to hand in files on floppy or CD (your choice)… make sure you have a supply before the first project is due
Rissacher EE365
Projects
Lect #1
General Topics:• Basic Logic Review
• Logic Laws/Theorems/Methods
• VHDL
• Transistor-Level Logic Implementation
• Electrical Behavior (timing, hazards, etc.)
• MSI Devices (Gates, Encoders, MUXs, registers, etc.)
• Sequential Logic
• LSI/VLSI Devices (memory, CPLDs, FPGAs)
Rissacher EE365
Overview
Lect #1
Will be covered later today
Rissacher EE365
Number Systems & Math
Lect #1
• DeMorgan’s Law, Sum of Products, Product of Sums
• Minterm, Maxterm
• Karnaugh Maps
• Commutativity, Associativity, etc.
Rissacher EE365
Logic Laws & Methods
Lect #1
Rissacher EE365
VHDL
Lect #1
entity and2 isport ( a, b : in bit; y : out bit );
end and2;
architecture basic of and2 isbegin
and2_behavior : processbegin
y <= a and b after 2 ns;wait on a, b;
end process and2_behavior;end basic;
Rissacher EE365
Transistor-Level Logic Implementation
Lect #1
Rissacher EE365
Electrical Behavior
Lect #1
• Propagation Delay
• Fan-In, Fan-Out
• Timing Hazards
• etc
Rissacher EE365
MSI Devices
Lect #1
74x541
D0 Y0...
D7 Y7
G1G2
74x541
D0 Y0...
D7 Y7
G1G2
74x541
D0 Y0...
D7 Y7
G1G2
74x541
D0 Y0...
D7 Y7
G1G2
8
G Y0 Y1A Y2B Y3
1/2 of74x139
A0A1
data 0data 3 data 2 data 1
Encoders, Decoders, Multiplexers, Registers, PLDs, Comparators, Adders, Subtractors, ALUs, etc.
Rissacher EE365
Sequential Logic
Lect #1
Rissacher EE365
LSI/VLSI Devices
Lect #1
• ROMs
• SRAM
• DRAM
• CPLDs
• FPGAs
Rissacher EE365Lect #1
Number Systems
• Binary
• Hex
• Octal
• Addition/Subtraction
•Negative Numbers
Rissacher EE365Lect #1
Number Systems
2n 10n 8n 16n
Where n is the bit #, or decimal place
Rissacher EE365Lect #1
Binary Addition
Rissacher EE365Lect #1
Binary Subtraction
Rissacher EE365Lect #1
Negative Binary Numbers
• Signed-Magnitude
• Two’s Complement
Rissacher EE365Lect #1
Signed-Magnitude
• MSB represents the sign
• Other bits represent the value
• 01010101 = +85
• 11010101 = -85
Rissacher EE365Lect #1
Two’s Complement
• MSB represents the sign
• Other bits represent the value if positive
• Complement + 1 of other bits represents the value if negative
• creates a continuous number line so that if we start with most negative number and count up, we see that each successive number can be obtained
• e.g., 17 = 00010001, complement = 11101110 + 1 = 11101111 = -17
Rissacher EE365Lect #1
Two’s Complement Addition/Subtraction
+3 0011
+ +4 0100
+7 0111
+4 0100
+ -7 1001
-3 1101
• Ignore carry bits into MSB
• For subtraction, simply negate one of the numbers
Rissacher EE365Lect #1
Binary Multiplication/Division
• Very similar to the multiplication and long division methods that we learned in elementary school
Rissacher EE365Lect #1
Binary Multiplication
• Multiplication is achieved by adding a list of shifted multiplicands according to the digits of the multiplier
• Un-signed example:
Rissacher EE365Lect #1
Binary Multiplication• Instead of listing all shifted multiplicands before adding, we can add each shifted multiplicand to a partial product (move convenient in a digital system):
Rissacher EE365Lect #1
Two’s Complement Multiplication• A sequence of two’s-complement additions is similar except for the last step where the shifted multiplicand (corresponding to the MSB) must be negated:
Rissacher EE365Lect #1
Binary Division• Use long division, shift and subtract (shown below)
• Direct two’s complement method not discussed here, but sign can be handled by negating the quotient if the dividend and divisor had different signs
Rissacher EE365Lect #1
Next Time
• Logic Theorems
• Sum-of-Products vs. Product-of-Sums
• Minterms/Maxterms
• Logic Function Representations
Rissacher EE365Lect #1
Homework• E-mail me your contact information and preferred methods of reaching you
• Please include e-mail, phone, messenger names, etc.
• my address: [email protected]